Senior Fitness - Exercise and Nutrition for Aging Men and Women
FREE Article Feed for your website.
Home Ownership Magazine
Party Planning Information
Article Marketing Resources
Bio-Medical Research Article Database
Informative Articles on Life, Love and Happiness
Tutorials on Business to Writing
Famous Quotes from Famous People
Song Lyric Information
New US Patent Information
Comprehensive List of Content by Category
Online Auctions and Shopping Related Articles
Article Search
Most Recent Articles
Title: Elastomer composition for cross-linked olefin elastomer foam
Patent Number: 7,189,764 Issued on 03/13/2007 to Sueda,   et al.

Title: Method for electrophoretically immersion-enameling substrates that have edges
Patent Number: 6,736,950 Issued on 05/18/2004 to Klein,   et al.

Title: Hair care compositions and improved hair quality
Patent Number: 6,740,317 Issued on 05/25/2004 to Cho,   et al.

Title: Creating a power distribution arrangement with tapered metal wires for a physical design
Patent Number: 7,185,305 Issued on 02/27/2007 to Rodman

Title: System and method for VLSI CAD design
Patent Number: 7,185,304 Issued on 02/27/2007 to Suto,   et al.

Title: Rapid development in a distributed application environment
Patent Number: 7,107,279 Issued on 09/12/2006 to Pociu

Title: Freestanding reactive multilayer foils
Patent Number: 6,736,942 Issued on 05/18/2004 to Weihs,   et al.

Title: Multicolor imaging using multiphoton photochemical processes
Patent Number: 7,026,103 Issued on 04/11/2006 to DeVoe,   et al.

Title: Method and apparatus for peeling a lens sheet from a forming mold therefor
Patent Number: 6,740,265 Issued on 05/25/2004 to Matsumoto,   et al.

Title: Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
Patent Number: 6,730,391 Issued on 05/04/2004 to Saijo,   et al.

Title: Semiconductor device having a ferroelectric capacitor and fabrication process thereof
Patent Number: 6,740,533 Issued on 05/25/2004 to Takamatsu,   et al.

Title: Stacked card connector having two rows of terminals extending out of a bottom surface of the connector at a side opposite to an insert port
Patent Number: 6,736,672 Issued on 05/18/2004 to Tsai

Title: Mask repattern process
Patent Number: 6,750,548 Issued on 06/15/2004 to Farnworth

Title: Variable two part DC-jack
Patent Number: 6,736,649 Issued on 05/18/2004 to Fahllund

Title: Cable organizing and securing device
Patent Number: 6,736,669 Issued on 05/18/2004 to Martin,   et al.

Title: Devices with a bendable tip for medical procedures
Patent Number: 6,743,239 Issued on 06/01/2004 to Kuehn,   et al.

Title: Electro-optic displays, and components for use therein
Patent Number: 7,190,008 Issued on 03/13/2007 to Amundson,   et al.

Title: Bus bandwidth consumption profiler
Patent Number: 6,735,653 Issued on 05/11/2004 to O Mathuna,   et al.

Title: Method and apparatus for fault tolerant and flexible test signature generator
Patent Number: 6,738,939 Issued on 05/18/2004 to Udawatta,   et al.

Title: Root cause analysis of server system performance degradations
Patent Number: 6,738,933 Issued on 05/18/2004 to Fraenkel,   et al.

Title: Electrical load disconnection detecting apparatus
Patent Number: 6,737,868 Issued on 05/18/2004 to Takagi

Title: Method of making installation zone for ceramic doll eye and structure thereof
Patent Number: 6,740,278 Issued on 05/25/2004 to Chang

Title: Electrical connector
Patent Number: 6,736,651 Issued on 05/18/2004 to Ho

Title: Charge storage devices with overlapping, folded electrodes
Patent Number: 6,740,447 Issued on 05/25/2004 to Keshishian

Title: Methods, systems and apparatus for providing urgent public information
Patent Number: 7,194,249 Issued on 03/20/2007 to Phillips,   et al.

Title: Parallel bit correlator
Patent Number: 6,738,794 Issued on 05/18/2004 to Stein,   et al.

Title: Electrochemical cell with carbonaceous material and molybdenum carbide as anode
Patent Number: 6,740,453 Issued on 05/25/2004 to Hossain,   et al.

Title: Ink composition for ink jet recording, ink jet recording method, composition for color toner, and composition for color filter
Patent Number: 6,739,715 Issued on 05/25/2004 to Harada,   et al.

Title: Control valve
Patent Number: 6,705,586 Issued on 03/16/2004 to Williges

Title: Device for transmitting electric current between two components of a steering device for motor vehicles
Patent Number: 6,736,657 Issued on 05/18/2004 to Bonn

Title: Automated scanning method for pathology samples
Patent Number: 7,133,543 Issued on 11/07/2006 to Verwoerd,   et al.

Title: Phase shift circuit and phase shifter
Patent Number: 7,167,064 Issued on 01/23/2007 to Miyaguchi,   et al.

Title: Reformable convex adapter for ostomy appliance
Patent Number: 6,740,067 Issued on 05/25/2004 to Leise, Jr.,   et al.

Title: Light emitting diode
Patent Number: 6,774,404 Issued on 08/10/2004 to Imai

Title: Surge suppressor
Patent Number: 7,193,830 Issued on 03/20/2007 to Fournier,   et al.

Title: Wiper arm shaped as an aerodynamic deflector
Patent Number: 6,739,018 Issued on 05/25/2004 to Jallet,   et al.

Title: Integrated circuit with design for testability and method for designing the same
Patent Number: 6,735,730 Issued on 05/11/2004 to Fujiwara,   et al.

Title: Speech platform architecture
Patent Number: 7,174,294 Issued on 02/06/2007 to Schmid,   et al.

Title: High-speed output transconductance amplifier capable of operating at different voltage levels
Patent Number: 6,741,130 Issued on 05/25/2004 to Wey,   et al.

Title: System using home gateway to analyze information received in an email message for controlling devices connected in a home network
Patent Number: 6,738,820 Issued on 05/18/2004 to Hilt

Title: Testing method and configurations for multi-ejector system
Patent Number: 6,740,530 Issued on 05/25/2004 to Bruce,   et al.

Title: Coated fuel cell electrodes
Patent Number: 6,740,445 Issued on 05/25/2004 to Grot

Title: Method for optimizing a cell layout using parameterizable cells and cell configuration data
Patent Number: 6,735,742 Issued on 05/11/2004 to Hatsch,   et al.

Title: System and method for enabling graphic applications in an interactive programming model
Patent Number: 6,738,817 Issued on 05/18/2004 to Chen,   et al.

Title: Method and apparatus for automatically provisioning data circuits
Patent Number: 6,738,825 Issued on 05/18/2004 to Bortolotto,   et al.

Title: Method and system for detecting defects
Patent Number: 6,735,745 Issued on 05/11/2004 to Sarig

Title: Method system, and program for dynamic resource linking when copies are maintained at different storage locations
Patent Number: 6,735,741 Issued on 05/11/2004 to Pannu

Title: Method and architecture for monitoring the health of servers across data networks
Patent Number: 6,738,811 Issued on 05/18/2004 to Liang

Title: Method and apparatus for performing extraction using a model trained with bayesian inference
Patent Number: 6,735,748 Issued on 05/11/2004 to Teig,   et al.

Title: Polyester fiber
Patent Number: 6,740,402 Issued on 05/25/2004 to Tsukamoto

Title: Processor capable of executing packed shift operations
Patent Number: 6,738,793 Issued on 05/18/2004 to Lin,   et al.

Title: Method and apparatus for organizing and accessing electronic messages in a telecommunications system
Patent Number: 6,738,800 Issued on 05/18/2004 to Aquilon,   et al.

Title: Adaptive mechanism for optimally accessing data based upon data access characteristics
Patent Number: 7,185,314 Issued on 02/27/2007 to Yellin

Title: Prosthetic repair fabric with erosion resistant edge
Patent Number: 6,736,854 Issued on 05/18/2004 to Vadurro,   et al.

Title: Memory devices and methods for use therewith
Patent Number: 6,738,883 Issued on 05/18/2004 to March,   et al.

Title: Electrical card connector
Patent Number: 6,736,656 Issued on 05/18/2004 to Yu

Title: Memory management of data buffers incorporating hierarchical victim selection
Patent Number: 6,738,866 Issued on 05/18/2004 to Ting

Title: Traction bandage
Patent Number: 6,736,855 Issued on 05/18/2004 to Bertels

Title: Method and system of deploying an application between computers
Patent Number: 6,738,806 Issued on 05/18/2004 to Maryka,   et al.

Title: System for selecting desired entry information from directory information stored in directory server and using entry information for external application and external service
Patent Number: 6,738,776 Issued on 05/18/2004 to Kanameda

Title: Color filter substrate and method for making the same, electro-optical device and method for making the same, and electronic apparatus
Patent Number: 6,740,457 Issued on 05/25/2004 to Takizawa

Title: Repair and maintenance support system and a car corresponding to the system
Patent Number: 6,735,504 Issued on 05/11/2004 to Katagishi,   et al.

Title: Circuit for receiving an AC coupled broadband signal
Patent Number: 6,741,140 Issued on 05/25/2004 to Jamal,   et al.

Title: Mobile telephone comprising a detachable connector between its body and its battery pack
Patent Number: 6,738,648 Issued on 05/18/2004 to Delacourte

Title: Use of enable bits to control execution of selected instructions
Patent Number: 6,738,892 Issued on 05/18/2004 to Coon,   et al.

Title: Dynamically configurable generic container
Patent Number: 6,738,783 Issued on 05/18/2004 to Melli,   et al.

Title: Method for benchmarking standardized data element values of agricultural operations through an internet accessible central database and user interface
Patent Number: 6,738,774 Issued on 05/18/2004 to Uthe,   et al.

Title: Compound-type energy generation system
Patent Number: 6,740,439 Issued on 05/25/2004 to Ban,   et al.

Title: Self-timed transmission system and method for processing multiple data sets
Patent Number: 6,738,795 Issued on 05/18/2004 to Colon-Bonet

Title: Data package including synchronization data
Patent Number: 6,738,789 Issued on 05/18/2004 to Multer,   et al.

Title: System and method for tracking records in a distributed computing system
Patent Number: 6,738,797 Issued on 05/18/2004 to Martin

Title: Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations
Patent Number: 6,738,893 Issued on 05/18/2004 to Rozas

Title: Method for varying an image processing path based on image emphasis and appeal
Patent Number: 6,738,494 Issued on 05/18/2004 to Savakis,   et al.

Title: Reducing signaling traffic with multicasting in a wireless communication network
Patent Number: 6,738,639 Issued on 05/18/2004 to Gosselin

Title: Method and apparatus for providing downlink power control in radio communication systems employing virtual cells
Patent Number: 6,735,451 Issued on 05/11/2004 to Jarleholm,   et al.

Method of manufacturing a semiconductor device Number:6,893,503 from the United States Patent and Trademark Office (PTO) owispatent

Home    Author Login    Submit Article    Article Search    Add Your Link    Edit Your Link    Contact Us    Advertising    Disclaimer

   

 
Web LinkGrinder.com

Top Breaking News
     Greek, Cypriot Leaders Resume Unification Talks in Nicosia by Nathan Morley
     Indonesia Tobacco Sales Grow, Raising Health Fears
     South Korea Allows Top Defector to Travel Overseas by VOA News

Title: Method of manufacturing a semiconductor device

Abstract: A method of producing a semiconductor device which removes catalyst elements from a silicon-containing semiconductor film while maintaining the advantage of low temperature process is provided. The method comprises the steps of: forming an amorphous semiconductor film containing silicon on a glass substrate to crystallize it by using a catalyst element; selectively introducing into the amorphous semiconductor film an impurity belonging to Group 15 to form gettering regions and regions to be gettered; and causing the catalyst element in the silicon film to move to the gettering regions by heat treatment. Through the gettering process, the crystalline silicon film can be obtained in which the concentration of nickel contained therein is sufficiently reduced.

Patent Number: 6,893,503 Issued on 05/17/2005 to Ohnuma,   et al.


Inventors: Ohnuma; Hideto (Kanagawa, JP); Yamazaki; Shunpei (Tokyo, JP); Nakajima; Setsuo (Kanagawa, JP); Ohtani; Hisashi (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Atsugi, JP)
Appl. No.: 050182
Filed: March 26, 1998

Foreign Application Priority Data

Mar 27, 1997[JP]9-094607

Current U.S. Class: 117/94; 117/95; 117/97; 117/101; 117/102; 117/106
Intern'l Class: C30B 025/04
Field of Search: 117/94,106,95,97,101,102


References Cited [Referenced By]

U.S. Patent Documents
5244819Sep., 1993Yue.
5403772Apr., 1995Zhang et al.
5426064Jun., 1995Zhang et al.
5481121Jan., 1996Zhang et al.
5488000Jan., 1996Zhang et al.
5492843Feb., 1996Adachi et al.
5501989Mar., 1996Takayama et al.
5508533Apr., 1996Takemura.
5529937Jun., 1996Zhang et al.
5534716Jul., 1996Takemura.
5543352Aug., 1996Ohtani et al.
5563426Oct., 1996Zhang et al.
5569610Oct., 1996Zhang et al.
5569936Oct., 1996Zhang et al.
5580792Dec., 1996Zhang et al.
5585291Dec., 1996Ohtani et al.
5589694Dec., 1996Takayama et al.
5595923Jan., 1997Zhang et al.
5595944Jan., 1997Zhang et al.
5604360Feb., 1997Zhang et al.
5605846Feb., 1997Ohtani et al.
5606179Feb., 1997Yamazaki et al.
5608232Mar., 1997Yamazaki et al.
5612250Mar., 1997Ohtani et al.
5614426Mar., 1997Funada et al.
5614733Mar., 1997Zhang et al.
5616506Apr., 1997Takemura.
5620910Apr., 1997Teramoto.
5621224Apr., 1997Yamazaki et al.
5624851Apr., 1997Takayama et al.
5637515Jun., 1997Takemura.
5639698Jun., 1997Yamazaki et al.
5643826Jul., 1997Ohtani et al.
5646424Jul., 1997Zhang et al.
5654203Aug., 1997Ohtani et al.
5656825Aug., 1997Kusumoto et al.
5663077Sep., 1997Adachi et al.
5677549Oct., 1997Takayama et al.
5696386Dec., 1997Yamazaki.
5696388Dec., 1997Funada et al.
5700333Dec., 1997Yamazaki et al.
5705829Jan., 1998Miyanaga et al.
5712191Jan., 1998Nakajima et al.
5744822Apr., 1998Takayama et al.
5744824Apr., 1998Kousai et al.
5756364May., 1998Tanaka et al.
5766977Jun., 1998Yamazaki.
5773327Jun., 1998Yamazaki et al.
5773846Jun., 1998Zhang et al.
5773847Jun., 1998Hayakawa.
5783468Jul., 1998Zhang et al.
5795795Aug., 1998Kousai et al.
5808321Sep., 1998Mitanaga et al.
5811327Sep., 1998Funai et al.
5814540Sep., 1998Takemura et al.
5818076Oct., 1998Zhang et al.
5821138Oct., 1998Yamazaki et al.
5824573Oct., 1998Zhang et al.
5824574Oct., 1998Yamazaki et al.
5830784Nov., 1998Zhang et al.
5837619Nov., 1998Adachi et al.
5840118Nov., 1998Yamazaki.
5843225Dec., 1998Takayama et al.
5843833Dec., 1998Ohtani et al.
5851862Dec., 1998Ohtani et al.
5858823Jan., 1999Yamazaki et al.
5869362Feb., 1999Ohtani.
5869363Feb., 1999Yamazaki et al.
5879977Mar., 1999Zhang et al.
5882960Mar., 1999Zhang et al.
5886366Mar., 1999Yamazaki et al.
5888857Mar., 1999Zhang et al.
5888858Mar., 1999Yamazaki et al.
5895933Apr., 1999Zhang et al.
5897347Apr., 1999Yamazaki et al.
5904770May., 1999Ohtani et al.
5915174Jun., 1999Yamazaki et al.
5923962Jul., 1999Ohtani et al.
5923997Jul., 1999Mitanaga et al.
5929464Jul., 1999Yamazaki et al.
5932893Aug., 1999Miyanaga et al.
5937282Aug., 1999Nakajima et al.
5940690Aug., 1999Kusumoto et al.
5942768Aug., 1999Zhang.
5946560Aug., 1999Uochi et al.
5949115Sep., 1999Yamazaki et al.
5953597Sep., 1999Kusumoto et al.
5956579Sep., 1999Yamazaki et al.
5961743Oct., 1999Yamazaki et al.
6251712Jun., 2001Tanaka et al.
6355509Mar., 2002Yamazaki.
Foreign Patent Documents
5-109737Apr., 1993JP.
08-330602Dec., 1996JP.
08-340127Dec., 1996JP.
09-045616Feb., 1997JP.

Primary Examiner: Kunemund; Robert
Attorney, Agent or Firm: Fish & Richardson P.C.

Claims



1. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a direction parallel to the insulating surface; and

patterning the crystallized semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film;

forming an active layer of the thin film transistor using the crystalline semiconductor island;

wherein the second heat treatment is performed in a temperature range not exceeding a glass transition point of the substrate.

2. A method according to claim 1, wherein the crystalline semiconductor film has grain boundaries.

3. A method according to claim 1, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

4. A method according to claim 1, wherein the substrate is a glass substrate.

5. A method according to claim 1, wherein the second heat treatment is furnace annealing.

6. A method according to claim 1, wherein the amorphous semiconductor film comprises germanium.

7. A method according to claim 1, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

8. A method according to claim 1, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

9. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

selectively providing a first portion of the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film, so that a crystallization proceeds from the first portion in a lateral direction to the insulating surface;

introducing an impurity element belonging to Group 15 into a second portion of the crystalline semiconductor film by using a mask while a third portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the second and third portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the third portion is moved to the second portion in a lateral direction to the insulating surface; and

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the third portion thereby removing the second portion of the crystalline semiconductor film;

forming an active layer of the thin film transistor using the crystalline semiconductor island;

wherein the second heat treatment is performed in a temperature range not exceeding a glass transition point of the substrate.

10. A method according to claim 9, wherein the crystalline semiconductor film has grain boundaries.

11. A method according to claim 9, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

12. A method according to claim 9, wherein the substrate is a glass substrate.

13. A method according to claim 9, wherein the second heat treatment is furnace annealing.

14. A method according to claim 9, wherein the amorphous semiconductor film comprises germanium.

15. A method according to claim 9, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

16. A method according to claim 9, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

17. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film;

irradiating a laser light or an intense light to the crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask after the irradiating step, while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a lateral direction to the insulating surface;

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film;

forming an active layer of the thin film transistor using the crystalline semiconductor island;

wherein the second heat treatment is performed in a temperature range not exceeding a glass transition point of the substrate.

18. A method according to claim 17, wherein the crystalline semiconductor film has grain boundaries.

19. A method according to claim 17, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

20. A method according to claim 17, wherein the substrate is a glass substrate.

21. A method according to claim 17, wherein the second heat treatment is furnace annealing.

22. A method according to claim 17, wherein the amorphous semiconductor film comprises germanium.

23. A method according to claim 17, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

24. A method according to claim 17, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

25. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

selectively providing a first portion of the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film, so that a crystallization proceeds from the first portion of the amorphous semiconductor film in a lateral direction to the insulating surface;

irradiating a laser light or an intense light to the crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a second portion of the crystalline semiconductor film by using a mask after the irradiating step, while a third portion of the crystalline semiconductor film below the mask is not introduced with the impurity element;

wherein the second and third portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the third portion is moved to the second portion in a lateral direction to the insulating surface;

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the third portion thereby removing the second portion of the crystalline semiconductor film;

forming an active layer of the thin film transistor using the crystalline semiconductor island;

wherein the second heat treatment is performed in the temperature range not exceeding a glass transition point of the substrate.

26. A method according to claim 25, wherein the crystalline semiconductor film has grain boundaries.

27. A method according to claim 25, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

28. A method according to claim 25, wherein the substrate is a glass substrate.

29. A method according to claim 25, wherein the second heat treatment is furnace annealing.

30. A method according to claim 25, wherein amorphous semiconductor film comprises germanium.

31. A method according to claim 25, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

32. A method according to claim 25, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

33. A method according to claim 1, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

34. A method according to claim 8, wherein a dose of said phosphorous (P) is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

35. A method according to claim 8, wherein a concentration of said phosphorous is a digit higher than a concentration of said element which promotes crystallization.

36. A method according to claim 9, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

37. A method according to claim 16, wherein a dose of said phosphorous is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

38. A method according to claim 16, wherein a concentration of said phosphorous is a digit higher than a concentration of said element which promotes crystallization.

39. A method according to claim 17, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

40. A method according to claim 24, wherein a dose of said phosphorous is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

41. A method according to claim 24, wherein a concentration of said phosphorus is a digit higher than a concentration of said element which promotes crystallization.

42. A method according to claim 25, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

43. A method according to claim 32, wherein a dose of said phosphorous is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

44. A method according to claim 32, wherein a concentration of said phosphorous is a digit higher than a concentration of said element which promotes crystallization.

45. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a lateral direction to the insulating surface;

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film;

forming a gate insulating film over the crystalline semiconductor island;

forming at least one gate electrode comprising a metal on the gate insulating film;

doping an impurity element into at least a second portion of the crystalline semiconductor island to form a lightly doped drain region; and

forming at least a source region and a drain region by doping an impurity element into third portions of the crystalline semiconductor island;

wherein the second heat treatment is performed in a temperature range not exceeding a glass transition point of the substrate.

46. A method according to claim 45, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

47. A method according to claim 45, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

48. A method according to claim 45, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

49. A method according to claim 45, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

50. A method according to claim 48, wherein a dose of said phosphorus is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

51. A method according to claim 48, wherein a concentration of said phosphorous is a digit higher than a concentration of said element which promotes crystallization.

52. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film comprising silicon over a substrate having an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

crystallizing the amorphous semiconductor film by a first heat treatment to form a crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a lateral direction to the insulating surface;

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film;

forming a gate insulating film over the crystalline semiconductor island;

forming at least one gate electrode comprising a metal on the gate insulating film;

doping an impurity element into at least a second portion of the crystalline semiconductor island to form a lightly doped drain region;

forming at least a source region and a drain region by doping an impurity element into third portions of the crystalline semiconductor island;

forming an interlayer insulating film comprising silicon over the gate electrode;

forming an interlayer insulating film comprising an organic resin film over the interlayer insulating film; and

forming a pixel electrode that is electrically connected to the source region or drain region through a contact hole over the interlayer film;

wherein the second heat treatment is performed in a temperature range not exceeding a glass transition point of the substrate.

53. A method according to claim 52, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

54. A method according to claim 52, wherein the amorphous semiconductor film comprises germanium.

55. A method according to claim 52, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

56. A method according to claim 52, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

57. A method according to claim 52, wherein said step of introducing the impurity element belonging to Group 15 is performed by plasma doping.

58. A method according to claim 56, wherein a dose of said phosphorous is set in a range from 1×1013 ions/cm2 to 5×1014 ions/cm2.

59. A method according to claim 56, wherein a concentration of said phosphorous is a digit higher than a concentration of said element which promotes crystallization.

60. A method according to claim 45, wherein the amorphous semiconductor film comprises germanium.

61. A method according to claim 1, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

62. A method according to claim 9, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

63. A method according to claim 17, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

64. A method according to claim 25, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

65. A method according to claim 45, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

66. A method according to claim 52, wherein the element in the crystalline semiconductor island after the second heat treatment has a concentration in a range of 1×1018 atoms/cm3 or lower.

67. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film on an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

performing a first heat treatment to crystallize the amorphous semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the first portion is moved to the second portion in a direction parallel to the insulating surface;

patterning the crystallized semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film; and

forming an active layer of the thin film transistor using the crystalline semiconductor island.

68. A method according to claim 67, herein the crystalline inductor film has grain boundaries.

69. A method according to claim 67, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

70. A method according to claim 67, wherein the second heat treatment is furnace annealing.

71. A method according to claim 67, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

72. A method according to claim 67, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

73. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film on an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

performing a first heat treatment to crystallize the amorphous semiconductor;

irradiating a laser light or an intense light to the crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask after the irradiating step, while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a lateral direction to the insulating surface;

patterning the crystalline semiconductor film to form a crystalline semiconductor island in the second portion thereby removing the first portion of the crystalline semiconductor film; and

forming an active layer of the thin film transistor using the crystalline semiconductor island.

74. A method according to claim 73, wherein the crystalline semiconductor film has grain boundaries.

75. A method according to claim 73, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

76. A method according to claim 73, wherein the second heat treatment is furnace annealing.

77. A method according to claim 73, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

78. A method according to claim 73, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

79. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film on an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

performing a first heat treatment to crystallize the amorphous semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a direction parallel to the insulating surface;

forming a crystalline semiconductor island by removing the first portion and a part of the second portion; and

forming an active layer of the thin film transistor using the crystalline semiconductor island.

80. A method according to claim 79, wherein the crystalline semiconductor film has grain boundaries.

81. A method according to claim 79, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

82. A method according to claim 79, wherein the second heat treatment is furnace annealing.

83. A method according to claim 79, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

84. A method according to claim 79, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

85. A method of manufacturing a semiconductor device including at least a thin film transistor, said method comprising the steps of:

forming an amorphous semiconductor film on an insulating surface;

providing the amorphous semiconductor film with an element which promotes crystallization of the amorphous semiconductor film;

performing a first heat treatment to crystallize the amorphous semiconductor;

irradiating a laser light or an intense light to the crystalline semiconductor film;

introducing an impurity element belonging to Group 15 into a first portion of the crystalline semiconductor film by using a mask after the irradiating step, while a second portion of the crystalline semiconductor film below the mask is not provided with the impurity element;

wherein the first and second portions of the crystalline semiconductor film are in contact with the insulating surface over the substrate;

performing a second heat treatment for gettering so that the element contained in the second portion is moved to the first portion in a lateral direction to the insulating surface;

forming a crystalline semiconductor island by removing the first portion and a part of the second portion; and

forming an active layer of the thin film transistor using the crystalline semiconductor island.

86. A method according to claim 85, wherein the crystalline semiconductor film has grain boundaries.

87. A method according to claim 85, wherein the second heat treatment is performed in the temperature range from 500 to 700° C.

88. A method according to claim 85, wherein the second heat treatment is furnace annealing.

89. A method according to claim 85, wherein the element which promotes crystallization is at least one element selected from the group of elements consisting of Ni, Co, Fe, Pd, Pt, Cu and Au.

90. A method according to claim 85, wherein the impurity element belonging to Group 15 is at least one element selected from the group of elements consisting of P, N, As, Sb, and Bi.

91. A method according to claim 1, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

92. A method according to claim 9, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

93. A method according to claim 17, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

94. A method according to claim 25, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

95. A method according to claim 45, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

96. A method according to claim 52, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

97. A method according to claim 67, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

98. A method according to claim 73, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

99. A method according to claim 79, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.

100. A method according to claim 85, wherein the element which promotes crystallization is provided with the amorphous semiconductor layer by introducing into the amorphous semiconductor film or applying a layer containing the element to the amorphous semiconductor film.
Description


Free Web Sudoku Puzzles.
Solve with your browser.
9   8     3   6  
          1   7  
  6         5    
  5 2   1   6    
      4   2      
    7   6   4 9  
    3         2  
  9   1          
  1   7     3   4
What is it?



Add Your Site · Terms Of Service · Privacy Policy


DISCLAIMER
Linkgrinder is a free service that searches the Internet and indexes all files found so that you may search quickly and easily for shared files. These files are created and made available individually by users whose identity we are not aware of and who we have no control over. In essence we function like a search engine tool; these files ARE NOT STORED OR SERVED BY OUR NETWORK. We are not responsible for any materials obtained by using our service. We do not monitor any of the contents of these files. These files may contain viruses, illegal materials, materials inappropriate for minors, offensive files and the like. BY USING OUR SERVICE, YOU ASSUME FULL RESPONSIBILITY FOR DOWNLOADING THESE MATERIALS AND WILL INDEMNIFY US FOR ANY DAMAGES THAT MAY BE INCURRED.

For More Specific Information VIEW OUR TERMS OF SERVICE.

Thank you and Enjoy!