Multi-mode graphics address remapping table for an accelerated graphics port device Number:6,750,870 from the United States Patent and Trademark Office (PTO) owispatent A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page. The size of the GART table entries is selectively dependent on the addressing capability of the AGP bus device and the amount of system memory allocated to the AGP bus device.<H accelerated, remapping, Multi, mode, grap, 6750870.html, Patent, pto, 6750870

Title: Multi-mode graphics address remapping table for an accelerated graphics port device

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page. The size of the GART table entries is selectively dependent on the addressing capability of the AGP bus device and the amount of system memory allocated to the AGP bus device.

Patent Number: 6,750,870 Issued on 06/15/2004 to Olarig

Inventors: Olarig; Sompong P. (Pleasanton, CA)
Assignee: Hewlett-Packard Development Company, L.P. (Houston, TX)

Appl. No.: 09/730,948

Filed: December 6, 2000

Current U.S. Class: 345/531 ; 345/520

Current International Class: G06F 12/10 (20060101)

Field of Search: 711/206,154,2 345/532,520,519,568,522,543,544,531,547,537 710/3,107,306

References Cited [Referenced By]

U.S. Patent Documents


5999198	December 1999	Horan et al.

Primary Examiner: Bella; Matthew C.
Assistant Examiner: Singh; Dalip K.

Claims

What is claimed is:

1. A computer system, comprising: a system processor to generate graphics data; a system memory operably coupled to the system processor, the system memory comprising a plurality of addressable storage locations, wherein the graphics data are stored in some of the plurality of addressable storage locations in the system memory; a graphics controller to generate video display data from the graphics data for display on a video display; a core logic chipset operably coupled to the system processor, to the system memory, and to the graphics controller; and a graphics address remapping table (GART) comprising a plurality of GART entries, each of the plurality of GART entries comprising an address pointer to a corresponding addressable storage location of the graphics data in the system memory, wherein each of the plurality of GART entries comprises a plurality of bits, wherein the number of the plurality of bits of each of the plurality of GART entries is based on an addressing capability of the graphics controller, and wherein the core logic chipset uses the plurality of GART entries for remapping the graphics data into an graphics device address space for use by the graphics controller in generating the video display data.

2. The system as recited in claim 1, wherein the number of the plurality of bits of each of the plurality of GART entries is 64 bits.

3. The system as recited in claim 1, wherein the number of the plurality of bits is correlative to an amount of the system memory allocated to the graphics controller.

4. The system as recited in claim 1, wherein the number of the plurality of bits is dependent on selection of an addressing mode for the GART.

5. The system as recited in claim 1, wherein the core logic chip set is operably coupled to the system processor via a system bus, to the system memory via a memory bus, and to the graphics controller via a graphics bus.

6. The system as recited in claim 5, wherein the graphics bus comprises an accelerated graphics port (AGP) bus.

7. The system as recited in claim 1, wherein the plurality of addressable storage locations comprise a plurality of pages in the system memory.

8. The system as recited in claim 7, wherein the plurality of pages of graphics data are stored in the system memory in a non-contiguous and random order.

9. The system as recited in claim 1, wherein a first number of most significant bits of the plurality of bits corresponding to each of the plurality of GART entries comprises the address pointer, wherein the address pointer comprises a base address of the corresponding one of the plurality of addressable storage locations of graphics data.

10. The system as recited in claim 9, wherein a second number of least significant bits of the plurality of bits comprises a plurality of feature flags for the corresponding one of the plurality of addressable storage locations of graphics data, the plurality of feature flags for customizing the corresponding graphics data.

11. The system as recited in claim 1, wherein the plurality of GART entries are stored in the system memory.

12. The system as recited in claim 1, wherein the plurality of GART entries are stored in a plurality of pages of GART entries in the system memory.

13. The system as recited in claim 12, wherein the plurality of pages of GART entries are stored in the system memory in a non-contiguous and random order.

14. The system as recited in claim 13, comprising a GART directory comprising a plurality of directory entries, each of the plurality of directory entries comprising an address pointer to a corresponding one of the plurality of pages of GART entries, wherein the core logic chipset uses the plurality of directory entries for locating the plurality of pages of GART entries in the system memory.

15. The system as recited in claim 1, wherein the core logic chipset comprises at least one integrated circuit.

16. The system as recited in claim 15, wherein the at least one integrated circuit core logic chipset comprises at least one application specific integrated circuit.

17. The system as recited in claim 15, wherein the at least one integrated circuit core logic chipset comprises at least one programmable logic array integrated circuit.

18. The system as recited in claim 1, comprising a video display operably coupled to the graphics controller.

19. A core logic chipset for connecting a computer processor and a system memory to a graphics bus, the core logic chipset comprising: a memory interface and control logic configured to connect to a system memory; a processor interface configured to connect to at least one processor; and a graphics data and control logic configured to connect to a graphics device, the graphics data and control logic in communication with the memory interface and control logic and the processor interface, wherein, the graphics data and control logic is configured to use a graphics address remapping table (GART) having a plurality of GART entries, each of the plurality of GART entries comprising a plurality of bits, the plurality of bits of each of the plurality of GART entries comprising an address pointer to a corresponding one of a plurality of pages of graphics data in the system memory, wherein the number of the plurality of bits of each of the plurality of GART entries is dependent on an addressing parameter.

20. The core logic chipset as recited in claim 19, wherein the addressing parameter comprises the size of the system memory allocated to the graphics device.

21. The core logic chipset as recited in claim 19, wherein the addressing parameter comprises the addressing capability supported by the graphics device.

22. The core logic chipset as recited in claim 19, wherein the addressing parameter comprises a selected addressing mode.

23. The core logic chipset as recited in claim 19, wherein the plurality of bits of each of the plurality of GART entries comprises a plurality of feature flags for customizing the corresponding one of the plurality of pages of graphics data.

24. The core logic chipset as recited in claim 19, wherein the graphics data and control logic is configured to connect to a graphics bus having the graphics device connected thereto.

25. The core logic chipset as recited in claim 24, wherein the graphics bus comprises an accelerated graphics port (AGP) bus.

26. The core logic chipset as recited in claim 25, comprising: the processor interface configured to connect the at least one processor to a peripheral component interconnect (PCI) bus; and a PCI-to-PCI interface adapted for connecting the PCI bus to the AGP bus, wherein PCI transactions are transferred between the PCI bus and the AGP bus.

27. The core logic chipset as recited in claim 26, wherein the PCI bus comprises a PCI-X bus.

28. The core logic chipset as recited in claim 19, wherein the graphics device comprises an accelerated graphics port (AGP) controller.

29. A method of creating a graphics address remapping table (GART) for use in a computing system comprising a system memory for storing graphics data, and a graphics controller for generating video display data from the graphics data for display on a video display, the method comprising: determining an available amount of system memory, the system memory comprising a plurality of addressable storage locations for storing graphics data; determining a size of at least a portion of the available amount of system memory to allocate to the graphics controller; determining an addressing capability of the graphics controller; and creating a GART to map the plurality of addressable storage locations in the system memory to a graphics address space for use by the graphics controller, the GART comprising a plurality of GART entries, each of the plurality of GART entries corresponding to one of the plurality of addressable storage locations for storing graphics data, each of the plurality of GART entries comprising a plurality of bits, wherein the number of the plurality of bits of each of the plurality of GART entries is dependent on at least one of the size of the available system memory to allocate to the graphics controller and the addressing capability of the graphics controller.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), video graphics processor(s), random access memory and input-output peripherals together, and more particularly, to a multi-mode graphics address remapping table (GART) used with an accelerated graphics port device.

2. Description of the Related Art

Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be stand-alone workstations (high end individual personal computers), desk-top personal computers, portable lap-top computers and the like, or they may be linked together in a network by a "network server" which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail ("E-mail"), document databases, video teleconferencing, white boarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks ("LAN") and wide area networks ("WAN").

A significant part of the ever increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit ("CPU"). The peripheral devices' data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the "Peripheral Component Interconnect" or "PCI." A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; PCI BIOS Specification, revision 2.1, and Engineering Change Notice ("ECN") entitled "Addition of `New Capabilities` Structure," dated May 20, 1996; and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0, dated Sep. 22, 1999, the disclosures of which are hereby incorporated by reference. These PCI specifications and ECN are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.

A computer system has a plurality of information (data and address) buses, such as a host bus, a memory bus, at least one high speed expansion local bus such as the PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor(s) of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor(s) communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.

Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the "PENTIUM" and "PENTIUM PRO" (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Cyrix, IBM, Digital Equipment Corp., and Motorola.

These sophisticated microprocessors have, in turn, made possible running complex application programs using advanced three dimensional ("3-D") graphics for computer aided drafting and manufacturing, engineering simulations, games and the like. Increasingly complex 3-D graphics require higher speed access to ever larger amounts of graphics data stored in memory. This memory may be part of the video graphics processor system, but, preferably, would be best (lowest cost) if part of the main computer system memory. Intel Corporation has proposed a low cost but improved 3-D graphics standard called the "Accelerated Graphics Port" (AGP) initiative. With AGP 3-D, graphics data, in particular textures, may be shifted out of the graphics controller local memory to computer system memory. The computer system memory is lower in cost than the graphics controller local memory and is more easily adapted for a multitude of other uses besides storing graphics data.

The proposed Intel AGP 3-D graphics standard defines a high speed data pipeline, or "AGP bus," between the graphics controller and system memory. This AGP bus has sufficient bandwidth for the graphics controller to retrieve textures from system memory without materially affecting computer system performance for other non-graphics operations. The Intel 3-D graphics standard is a specification which provides signal, protocol, electrical, and mechanical specifications for the AGP bus and devices attached thereto. This specification is entitled "Accelerated Graphics Port Interface Specification Revision 1.0," dated Jul. 31, 1996, ("AGP1.0") the disclosure of which is hereby incorporated by reference. Enhancements to the AGP1.0 Specification are included in the "Accelerated Graphics Port Interface Specification Revision 2.0," dated May 4, 1998 ("AGP2.0"), the disclosure of which is hereby incorporated by reference. Both the AGP1.0 and AGP2.0 Specifications are available from Intel Corporation, Santa Clara, Calif.

The AGP1.0 interface specification uses the 66 MHz PCI (Revision 2.1) specification as an operational baseline, with three performance enhancements to the PCI specification which are used to optimize the AGP1.0 Specification for high performance 3-D graphics applications. These enhancements are: 1) pipelined memory read and write operations, 2) demultiplexing of address and data on the AGP bus by use of sideband signals, and 3) data transfer rates of 133 MHz for data throughput in excess of 500 megabytes per second ("MB/s"). The remaining AGP1.0 Specification does not modify the PCI specification, but rather provides a range of graphics-oriented performance enhancements for use by 3-D graphics hardware and software designers. The AGP1.0 Specification is neither meant to replace nor diminish full use of the PCI standard in the computer system. The AGP1.0 Specification creates an independent and additional high speed local bus for use by 3-D graphics devices such as a graphics controller, wherein the other input-output ("I/O") devices of the computer system may remain on any combination of the PCI, SCSI, EISA and ISA buses. The AGP1.0 Specification supports only 32-bit memory addressing.

The AGP2.0 Specification supports 64-bit memory addressing, which is beneficial for addressing memory sizes allocated to the AGP device that are larger than 2 GB. The AGP2.0 Specification also includes several other enhancements. For example, the AGP2.0 Specification supports 1) 4.times. transfer mode with low (1.5V voltage electrical signals that allows four data transfers per 66 MHz clock cycle, providing data throughput of up to 1 GB/second; 2) five additional sideband signals; 3) a fast write protocol; 4) new input/output buffers; and 5) new mechanical connectors.

Regardless of the version of the AGP specification, to functionally enable the AGP 3-D graphics bus, new computer system hardware and software are required. This requires new computer system core logic designed to function as a host bus/memory bus/PCI bus to AGP bus bridge meeting the AGP1.0 or AGP2.0 Specifications, and new Read Only Memory Basic Input Output System ("ROM BIOS") and Application Programming Interface ("API") software to make the AGP dependent hardware functional in the computer system. The computer system core logic must still meet the PCI and/or PCI-X standards referenced above and facilitate interfacing the PCI bus(es) to the remainder of the computer system. In addition, new AGP compatible device cards must be designed to properly interface, mechanically and electrically, with the AGP bus connector.

A major performance/cost enhancement using AGP in a computer system is accomplished by shifting texture data structures from local graphics memory to main memory. Textures are ideally suited for this shift for several reasons. Textures are generally read-only, and therefore problems of access ordering and coherency are less likely to occur. Shifting of textures serves to balance the bandwidth load between system memory and local graphics memory, since a well-cached host processor has much lower memory bandwidth requirements than does a 3-D rendering machine; texture access comprises perhaps the single largest component of rendering memory bandwidth, so avoiding loading or caching textures in local graphics memory saves not only this component of local memory bandwidth, but also the bandwidth necessary to load the texture store in the first place, and, further, this data must pass through main memory anyway as it is loaded from a mass store device. Texture size is dependent upon application quality rather than on display resolution, and therefore may require the greatest increase in memory as software applications become more advanced. Texture data is not persistent and may reside in the computer system memory only for the duration of the software application, so any system memory spent on texture storage can be returned to the free memory heap when the application concludes (unlike a graphic controller's local frame buffer which may remain in persistent use). For these reasons, shifting texture data from local graphics memory to main memory significantly reduces computer system costs when implementing 3-D graphics.

Generally, in a computer system memory architecture the graphics controller's physical address space resides above the top of system memory. The graphics controller uses this physical address space to access its local memory which holds information required to generate a graphics screen. In the AGP system, information still resides in the graphics controller's local memory (textures, alpha, z-buffer, etc.), but some data which previously resided in this local memory is moved to system memory (primarily textures, but also command lists, etc.). The address space employed by the graphics controller to access these textures becomes virtual, meaning that the physical memory corresponding to this address space doesn't actually exist above the top of memory. In reality, each of these virtual addresses corresponds to a physical address in system memory. The graphics controller sees this virtual address space, referenced hereinafter as "AGP device address space," as one contiguous block of memory, but the corresponding physical memory addresses may be allocated in 4 kilobyte ("KB"), non-contiguous pages throughout the computer system physical memory.

There are two primary AGP usage models for 3D rendering that have to do with how data are partitioned and accessed, and the resultant interface data flow characteristics. In the "DMA" model, the primary graphics memory is a local memory referred to as local frame buffer and is associated with the AGP graphics controller or "video accelerator." 3D structures are stored in system memory, but are not used (or "executed") directly from this memory; rather they are copied to primary (local) memory, to which the rendering engine's address generator (of the AGP graphics controller) makes references thereto. This implies that the traffic on the AGP bus tends to be long, sequential transfers, serving the purpose of bulk data transport from system memory to primary graphics (local) memory. This sort of access model is amenable to a linked list of physical addresses provided by software (similar to operation of a disk or network I/O device), and is generally not sensitive to a non-contiguous view of the memory space.

In the "execute" model, the video accelerator uses both the local memory and the system memory as primary graphics memory. From the accelerator's perspective, the two memory systems are logically equivalent; any data structure may be allocated in either memory, with performance optimization as the only criteria for selection. In general, structures in system memory space are not copied into the local memory prior to use by the video accelerator, but are "executed" in place. This implies that the traffic on the AGP bus tends to be short, random accesses, which are not amenable to an access model based on software resolved lists of physical addresses. Since the accelerator generates direct references into system memory, a contiguous view of that space is essential. But, since system memory is dynamically allocated in, for example, random 4,096 byte blocks of the memory, hereinafter 4 kilobyte ("KB") pages, the "execute" model provides an address mapping mechanism that maps the random 4 KB pages into a single contiguous address space.

The AGP Specification supports both the "DMA" and "execute" models. However, since a primary motivation of the AGP is to reduce growth pressure on the graphics controller's local memory (including local frame buffer memory), the "execute" model is preferred. Consistent with this preference, the AGP Specification requires a virtual-to-physical address re-mapping mechanism which ensures the graphics accelerator (AGP master) will have a contiguous view of graphics data structures dynamically allocated in the system memory. This address re-mapping applies only to a single, programmable range of the system physical address space and is common to all system agents. Addresses falling in this range are re-mapped to non-contiguous pages of physical system memory. All addresses not in this range are passed through without modification, and map directly to main system memory, or to device specific ranges, such as a PCI device's physical memory. Re-mapping is accomplished via a "Graphics Address Remapping Table" ("GART table") which is set up and maintained by a GART miniport driver software, and used by the core logic chipset to perform the re-mapping. In order to avoid compatibility issues and allow future implementation flexibility, this mechanism is specified at a software (API) level. In other words, the actual GART table format may be abstracted to the API by a hardware abstraction layer ("HAL") or mini-port driver that is provided with the core logic chipset. While this API does not constrain the future partitioning of re-mapping hardware, the re-mapping function will typically be implemented in the core logic chipset.

The contiguous AGP graphics controller's device addresses are mapped (translated) into corresponding physical addresses that reside in the computer system physical memory by using the GART table which may also reside in physical memory. The GART table is used by the core logic chipset to remap AGP device addresses that can originate from either the AGP, host, or PCI buses. The GART table is managed by a software program called a "GART miniport driver." The GART miniport driver provides GART services for the computer software operating system.

What is needed to more fully and efficiently utilize the computer system and its physical memory when implementing AGP 3-D graphics requiring GART table translations is a system, method and apparatus for customizing the properties of each page of system memory associated with the GART table.

In light of the greater memory needs of increasingly complex applications, a GART table that implements greater than 32-bit addressing is desirable. The particular configuration of the GART table, including the number of bits used for addressing, would be dependent on the capabilities of the AGP device and the amount of system memory available for allocation to the AGP device.

SUMMARY OF THE INVENTION

Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.

In accordance with one aspect of the present invention, there is provided a computer system comprising a system processor to execute software instructions and generate graphics data, a system memory comprising a plurality of addressable storage locations in which the software instructions and the graphics data are stored, a graphics controller to generate video display data from the graphics data, and a core logic chipset coupled to the system processor, the system memory, and the graphics controller. The system further comprises a graphics address remapping table (GART) comprising a plurality of GART entries. Each of the GART entries comprises an address pointer to a corresponding addressable storage location of graphics data in the system memory. The core logic chipset uses the GART entries to remap the graphics data into a graphics device address space for use by the graphics controller in generating the video display data. Each GART entry comprises a plurality of bits, wherein the number of the bits of each entry is based on an addressing capability of the graphics controller.

In accordance with another embodiment, a core logic chipset for connecting a processor and a system memory to an accelerated graphics port (AGP) bus comprises a memory interface and control logic configured to connect to the system memory; a processor interface configured to connect to a processor; and an AGP data and control logic configured to connect to an AGP bus having an AGP device connected thereto. The AGP data and control logic is configured to use a GART comprising a plurality of GART entries, each of the plurality of GART entries comprising a plurality of bits, wherein the number of the bits of each GART entry is dependent on an addressing parameter.

In accordance with yet another embodiment of the invention, a method of creating a GART is provided. The method comprises determining an available amount of system memory, determining an amount of the available system memory to allocate to a graphics controller, and determining an addressing capability of the graphics controller. The method further comprises creating a GART to map a plurality of addressable storage locations in the system memory to a graphics address space for use by the graphics controller. The GART comprises a plurality of GART entries, each of which corresponds to one of the plurality of addressable storage locations. Each GART entry further comprises a plurality of bits, the number of which is dependent on at least one of the size of the available system memory to allocate to the graphics controller and the addressing capability of the graphics controller.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIGS. 1 and 1A are a schematic block diagram of a prior art computer system;

FIGS. 2 and 2A area schematic block diagram of a computer system according to the present invention;

FIG. 3 is a schematic functional block diagram of an embodiment of the present invention according to the computer system illustrated in FIGS. 2 and 2A;

FIGS. 4, 5 and 6 are schematic diagrams of a computer system memory map, a GART table in the computer system memory and a GART table entry, respectively according to the present invention;

FIG. 7 is a schematic diagram of a memory map of an AGP single-level address translation;

FIG. 8 is a schematic diagram of a memory map of an AGP two-level address translation;

FIG. 9 is a schematic functional block diagram of the AGP single-level address translation according to FIG. 7;

FIG. 10 is a table of bits required for page offset in a single-level translation;

FIG. 11 is a schematic flow diagram of single-level address remapping;

FIG. 12A is a schematic functional block diagram of the AGP two-level address translation according to FIG. 8;

FIG. 12B is a table of bits required for directory and page offset in a two-level translation;

FIGS. 12C and 12D are a schematic flow diagram of two-level address remapping;

FIGS. 13 and 13A are a schematic diagram of a memory map of the GART table, according to the present invention;

FIGS. 14 and 14A are a schematic diagram of a memory map of entries in a GART directory, a page of GART table entries and an AGP memory, according to the present invention;

FIG. 15 is a table of maximum GART table size versus size of AGP memory;

FIG. 16 is a schematic functional block diagram of the AGP logical architecture;

FIG. 17A is a schematic table of registers according to the AGP functional block diagram of FIG. 16 and an embodiment of the present invention;

FIGS. 17B, 17Ba and 17C are tables of a functional description of the bits used in the AGP registers of FIG. 17A, according to the present invention;

FIGS. 18A and 18Aa are a schematic table of registers according to the AGP functional block diagram of FIG. 16 and an embodiment of the present invention;

FIGS. 18B-18Ma are tables of a functional description of the bits used in the AGP registers of FIGS. 18A and 18Aa, according to the present invention;

FIG. 19A is a schematic table of memory-mapped registers according to the AGP functional block diagram of FIG. 16 and an embodiment of the present invention;

FIGS. 19B-19N are tables of functional descriptions of the bits used in the AGP registers of FIG. 19A, according to the present invention;

FIG. 20 is a schematic memory map of caching GART table entries, according to an embodiment of the present invention;

FIG. 21 is a schematic memory map of prefetching GART table entries, according to an embodiment of the present invention;

FIG. 22A is a schematic table of AGP graphics controller configuration registers according to the AGP functional block diagram of FIG. 16 and an embodiment of the present invention;

FIGS. 22B-22E are tables of functional descriptions of the bits used in the AGP registers of FIG. 16A, according to the present invention;

FIG. 23 is a table of best, typical, and worst case latencies for AGP, according to the present invention;

FIG. 24 is a schematic functional block diagram of the AGP software architecture;

FIGS. 25A-25F are tables of software services provided by the GART miniport driver;

FIGS. 26A and 26B are tables of software services available to the GART miniport driverl

FIG. 27 is a schematic functional block diagram of the AGP single-level address translation in the compatible mode;

FIG. 28 is a table of bits used for page offset in a single-level address translation in the compatible mode;

FIG. 29 is a schematic functional block diagram of the AGP two-level address translation in the compatible mode; and

FIG. 30 is a table of bits used for directory and page offset in a two-level translation in the compatible mode.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

The present invention provides a core logic chipset in a computer system which is capable of implementing a bridge between host processor and memory buses, an AGP bus adapted for an AGP device(s), and a PCI bus adapted for PCI devices. The AGP device may be a graphics controller which utilizes graphical data such as textures by addressing a contiguous virtual address space, hereinafter "AGP device address space," that is translated from non-contiguous memory pages located in the computer system physical memory by the core logic chipset. The core logic chipset utilizes a "Graphics Address Remapping Table" ("GART table") which may reside in a physical memory of the computer system, such as system random access memory, and may be controlled by the core logic chipset software driver(s). The function of the GART table is to remap virtual addresses referenced by the AGP device to the physical addresses of the graphics information located in the computer system physical memory. Each entry of the GART table describes a first byte address location for a page of physical memory. The page of physical memory may be 4,096 bytes (4 KB) in size. A GART table entry comprises a memory address translation pointer and software controllable feature flags (see FIGS. 13 and 13A). These feature flags may be used to customize the associated page of physical memory. API software and miniport drivers may write to and/or read from these feature flags.

For illustrative purposes, preferred embodiments of the present invention are described hereinafter for computer systems utilizing the Intel x86 microprocessor architecture and certain terms and references will be specific to those processor platforms. AGP and PCI are interface standards, however, that are hardware independent and may be utilized with any host computer designed for these interface standards. It will be appreciated by those skilled in the art of computer systems that the present invention may be adapted and applied to any computer platform utilizing the AGP and PCI interface standards.

The PCI specifications referenced above are readily available and are hereby incorporated by reference. The AGP Specifications as referenced above and incorporated herein by reference are ready available from Intel Corporation. Further definition and enhancement of the AGP1.0 Specification is more fully defined in "Compaq's Supplement to the `Accelerated Graphics Port Interface Specification Version 1.0`," Revision 0.8, dated Apr. 1, 1997, and is hereby incorporated by reference.

Referring now to the drawings, the details of preferred embodiments of the present invention are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. Referring now to FIGS. 2 and 2A, a schematic block diagram of a computer system utilizing the present invention is illustrated. A computer system is generally indicated by the numeral 200 and comprises a central processing unit(s) ("CPU") 102, core logic 204, system random access memory ("RAM") 106, a video graphics controller 210, a local frame buffer 208, a video display 112, a PCI/SCSI bus adapter 114, a PCI/EISA/ISA bridge 116, and a PCI/IDE controller 118. Single or multilevel cache memory (not illustrated) may also be included in the computer system 200 according to the current art of microprocessor computer systems. The CPU 102 may be a plurality of CPUs 102 in a symmetric or asymmetric multi-processor configuration.

The CPU(s) 102 is connected to the core logic 204 through a host bus 103. The system RAM 106 is connected to the core logic 204 through a memory bus 105. The video graphics controller(s) 210 is connected to the core logic 204 through an AGP bus 207. The PCI/SCSI bus adapter 114, PCI/EISA/ISA bridge 116, and PCI/IDE controller 118 are connected to the core logic 204 through a primary PCI bus 109. Also connected to the PCI bus 109 are a network interface card ("NIC") 122 and a PCI/PCI bridge 124. Some of the PCI devices such as the NIC 122 and PCI/PCI bridge 124 may plug into PCI connectors on the computer system 200 motherboard (not illustrated).

Hard disk 130 and tape drive 132 are connected to the PCI/SCSI bus adapter 114 through a SCSI bus 111. The NIC 122 is connected to a local area network 119. The PCI/EISA/ISA bridge 116 connects over an EISA/ISA bus 113 to a ROM BIOS 140, non-volatile random access memory (NVRAM) 142, modem 120, and input-output controller 126. The modem 120 connects to a telephone line 121. The input-output controller 126 interfaces with a keyboard 146, real time clock (RTC) 144, mouse 148, floppy disk drive ("FDD") 150, and serial/parallel ports 152, 154. The EISA/ISA bus 113 is a slower information bus than the PCI bus 109, but it costs less to interface with the EISA/ISA bus 113.

Referring now to FIG. 3, a schematic functional block diagram of the core logic 204 of FIGS. 2 and 2A, according to the present invention, is illustrated. The core logic 204 functionally comprises CPU host bus interface and queues 302, memory interface and control 304, host/PCI bridge 306, AGP logic 318, and PCI/PCI bridge 320. The AGP logic 318 comprises AGP arbiter 316, GART cache 322, AGP data and control 310, and AGP request/reply queues 312. The CPU host bus interface and queues 302 connect to the host bus 103 and include interface logic for all data, address and control signals associated with the CPU(s) 102 of the computer system 200. Multiple CPUs 102 and cache memory associated therewith (not illustrated) are contemplated and within the scope of the present invention.

The CPU host bus interface and queues 302 interfaces with the host/PCI bridge 306 and memory interface and control 304 over a core logic bus 311. The CPU host bus interface and queues 302 interfaces with the AGP logic 318 over the core logic bus 311. The memory interface and control 304 interfaces with the AGP logic 318 over a core logic bus 309. An advantage of having separate buses 309 and 311 is that concurrent bus operations may be performed thereover. For example, video data stored in system RAM 106, connected to the bus 105, may be transferring to the video graphics controller 210 (AGP device) on the AGP bus 207 while the CPU 102 on the host bus 103 is accessing an independent PCI device (i.e., NIC 122) on the PCI bus 109.

The host bus interface and queues 302 allows the CPU 102 to pipeline cycles and schedule snoop accesses. The memory interface and control 304 generates the control and timing signals for the computer system RAM 106 which may be synchronous dynamic RAM and the like. The memory interface and control 304 has an arbiter (not illustrated) which selects among memory accesses for CPU writes, CPU reads, PCI writes, PCI reads, AGP reads, AGP writes, and dynamic memory refresh Arbitration may be pipelined into a current memory cycle, which ensures that the next memory address is available on the memory bus 105 before the current memory cycle is complete. This results in minimum delay, if any, between memory cycles. The memory interface and control 304 also is capable of reading ahead on PCI master reads when a PCI master issues a read multiple command, as more fully described in the PCI Specification.

The host/PCI bridge 306 controls the interface to the PCI bus 109. When the CPU 102 accesses the PCI bus 109, the host/PCI bridge 306 operates as a PCI master. When a PCI device is a master on the PCI bus 109, the host/PCI bridge 306 operates as a PCI slave. The host/PCI bridge 306 contains base address registers for PCI device targets on its PCI bus 109 (not illustrated).

The AGP data and control 310, AGP arbiter 316, and AGP request/reply queues 312 interface to the AGP bus 207 and also have signal, power and ground connections (not illustrated) for implementation of signals defined in the AGP and PCI Specifications. The AGP bus 207 is adapted to connect to an AGP device(s) and/or an AGP connector(s) (not illustrated). The GART cache 322 is used to store GART table entries for reordering and retrieving random non-contiguous AGP pages 412 (FIG. 4) in the computer system memory 106 to contiguous AGP device address space 406 for use by the graphics controller 210.

The PCI/PCI bridge 320 is connected between the PCI bus 109 and the AGP bus 207. The PCI/PCI bridge 320 allows existing enumeration code in the computer system BIOS 140 to recognize and handle AGP compliant devices, such as the video graphics controller 210, residing on the AGP bus 207. The PCI/PCI bridge 320, for example, may be used in configuring the control and status registers of the AGP graphics controller 210 or the AGP logic 318 by bus enumeration during POST, both being connected to the AGP bus 207, as more fully described herein below.

The following description which references FIGS. 4-26B is provided for a particular embodiment based on the AGP1.0 and PCI Specifications which support 32-bit memory addressing only. In alternative embodiment shall be described below with reference to FIGS. 27-30, which contemplates greater than 32-bit memory address (e.g., 64-bit addressing). It should be understood, however, that many aspects of a system which support 32-bit addressing carry over to a system which supports greater than 32-bit memory addressing. Indeed, any differences in many of the components (e.g., registers, etc.) of the 32-bit addressing system described below may be readily ascertained with reference to the AGP2.0 and PCI-X Specifications. It should be understood that such components are described herein to facilitate the understanding of a system that implements the invention and that differences in the arrangement and structure of such components to support addressing greater than 32 bits is contemplated by the invention.

Referring now to FIGS. 4, 5, and 6 (also see FIGS. 13 and 13A), schematic diagrams of a computer system memory map, a GART table in the computer system memory, and a GART table entry are illustrated. A logical memory map of the computer system memory 106 is generally indicated by the numeral 402, the graphics controller physical address space by the numeral 404, and the AGP device address space (virtual memory) by the numeral 406. The computer system 200 may address up to 4 gigabytes ("GB") of memory with a 32 bit address, however, some of this 4 GB of memory address space may be used for local memory associated with various devices such as the AGP video graphics controller's 210 memory which may include the local frame buffer 208, texture cache, alpha buffers, Z-buffers, etc., all being addressed within the graphics controller physical address space 404. In addition, according to the present invention, some of the memory address space 402 is used for the AGP device address space 406. In FIG. 4, the bottom (lowest address) of the computer system memory 106 is represented by the numeral 408 and the top (highest address) is represented by the numeral 410. In between the bottom 408 and the top 410 are various blocks or "pages" of AGP memory represented by the numeral 412. Each page 412 has a contiguous set of memory addresses.

In the present invention, some of these AGP memory pages (indicated by 412a, 412b and 412c) are used to store AGP information, such as textures, lists and the like, and at least one page (indicated by 414) is used to store entries in the GART table 414. The GART table 414 comprises a plurality of entries 418 (FIG. 5). Enough GART table entries 418 are stored to represent all of the associated AGP device address space 406 being used in the computer system 200. Each GART table entry 418 represents the base address 416 of the respective page 412 of the AGP memory. Another memory page may also be used to store a GART directory (not illustrated). The GART directory is used for two-level address remapping as more fully described herein below. Each GART table entry 418 stores 32 binary bits of information (FIG. 6). The GART table 414 is used to remap AGP device address space 406 to addresses of the pages 412, by using the upper bits (31:12) to store a base address 416 for each of the corresponding 4 KB pages 412. The lower 12 bits of the AGP device address 406 is the same as the lower 12 bits of the address of the page 412, as more fully described hereinbelow. See also FIGS. 9 and 12A and the specification relating thereto. Thus the lower 12 bits (11:0), when using a 4 KB size page 412 addressed by each GART table entry 418, are free for other uses besides addressing AGP texture data. For other memory page sizes, different numbers of bits are available in the GART table entry 418 for the other uses and are contemplated herein.

The embodiment of the present invention contemplates using the lower unused bits of each GART table entry 418 to customize its associated referenced page 412. For example, the page 412 in the physical memory 106 may contain 4,096 bytes (4 KB) of data such as textures, command lists and the like. Each GART table entry 418 may comprise four eight bit bytes for a total of 32 bits of binary information. If the twenty most significant bits 426 (31:12) (FIG. 6) in the GART table entry 418 are used for the base address 416 of the corresponding 4 KB page 412, the twelve least significant bits (11:0) are available for use by the systems designer in defining and/or customizing certain features and attributes associated with the memory page 412. These least significant bits are hereinafter referred to as "feature bits" or "feature flags." For example: a present bit 420 may indicate whether a page 414 whose base address 416 is referenced by the GART table entry 418 (bits 31:12) has been reserved by the GART miniport driver. A link bit 422 may indicate whether the next GART table entry 418 is associated with the current GART table entry 418. A dirty bit 424 may indicate whether the page 412 has been modified. Many other combinations of these feature bits may be utilized and are contemplated herein for the present invention. These feature bits (11:0) are typically managed by the GART miniport driver, but may be accessed by any other device driver of the computer system (i.e., ROM BIOS, etc.) because the GART table 414, typically, is located in the computer system memory 106. Thus, any number of features and attributes may be associated with each page 412 and the page's features and attributes are easily and quickly determined by reading the feature bits of the associated GART table entry 418. Just as easily, the page's features and attributes may be changed for each page 412 by writing to the lower bits of the associated GART table entries 418 located in the main computer system memory 106. Thus, any system software may easily and quickly determine the features and attributes of any AGP page 412 stored in the memory 106 by simply reading from and/or writing to the feature bits of the associated GART table entry 418.

AGP1.0 and AGP2.0 Specifications

The Intel AGP1.0 and AGP2.0 Specifications provide signal, protocol, electrical, and mechanical specifications for the AGP bus. However, further design must be implemented before a fully function computer system with AGP capabilities is realized. As noted above, for ease of reference, the following disclosure defines the implementation specific parts of an AGP interface according to the present invention with reference in particular to the AGP1.0 Specification. It is intended that the following disclosure also be extended to an AGP interface which follows the AGP2.0 Specification with appropriate changes as dictated therein. The following disclosure includes the GART table, buffer depths, latencies, registers, and driver functionality and interfaces.

Moving textures and other information required by the graphics controller, such as command lists, out of the local frame buffer into system memory creates a problem: the presently implemented prior art computer system architecture, illustrated in FIGS. 1 and 1A, cannot support the bandwidth requirements of tomorrow's 3-D graphics enhanced applications. The standard PCI bus 109 (33 MHz, 32 bit) bandwidth is 132 MB/s peak and 50 MB/s typical. Microsoft Corporation estimates that future graphics applications will require in excess of 200 MB/s. This means that the PCI bus 109 in the computer system architecture illustrated in FIGS. 1 and 1A will likely starve the graphics controller 110 as well as other PCI devices (122, 124, 114, 116 and 118) also trying to access the PCI bus 109.

AGP Architecture

To remedy this situation, Intel developed the AGP architecture illustrated in FIGS. 2 and 2A and 3. In the Intel AGP architecture, a graphics controller 210 is removed from the existing PCI bus 109 and placed on a higher bandwidth AGP bus 207. This AGP bus 207 has a peak bandwidth of 532 megabytes per second ("MB/s"). The bandwidth bottleneck now exists in the core logic chipset 204 and the memory bus 105, which have to handle requests from the host bus 103, the PCI bus 109, and the AGP bus 207 (FIGS. 2 and 2A), as well as memory 106 refreshing by the memory interface and control 304. However, with the introduction of faster memory 106 and highly integrated, faster chipsets, this problem becomes manageable.

Understanding the necessity for the Graphics Address Remapping Table ("GART table") requires a full understanding of the AGP addressing scheme. Referring now to FIGS. 7 and 8, schematic memory maps of an AGP single-level address translation and an AGP two-level address translation, respectively, are illustrated. In the prior art computer system architecture illustrated in FIGS. 1 and 1A, the graphics controller's physical address space resides above the top 410 of system memory 106. The graphics controller 110 used this physical address space for the local frame buffer 108, texture cache, alpha buffers, Z-buffers, etc. In the AGP system, information still resides in the graphics controller memory (alpha, z-buffer, local frame buffer 108, etc.), but some data which previously resided in the prior art local frame buffer 108 is moved to system memory 106 (primarily textures, but also command lists, etc.). The address space employed by the graphics controller 210 to access these textures becomes virtual, meaning that the physical memory corresponding to this address space doesn't actually exist above the top of memory. In reality, each of these virtual addresses correspond to a physical address in the system memory 106. The graphics controller 210 addresses this virtual address space, referenced hereinabove and hereinafter as "AGP device address space" as one contiguous block of memory 406, but the corresponding physical addresses are allocated in 4 KB, non-contiguous pages 412 throughout the computer system memory 106.

A system, method and apparatus is needed to remap the graphics controller's contiguous, AGP device addresses into their corresponding physical addresses that reside in the system memory 106. This is the function of the GART table. The GART table resides in the physical memory 106 (FIGS. 1 and 1A), and is used by the core logic chipset 204 to remap AGP device addresses that can originate from either the AGP bus 207, host bus 103, or PCI bus(es) 109. The GART table is managed by a GART miniport driver. In the present invention, the GART table implementation supports two options for remapping AGP addresses: single-level address translation and two-level address translation. Further, as will be discussed in the alternative embodiment described below with respect to FIGS. 27-30, the GART table may be configured in any of multiple modes, including a standard mode which supports 32-bit memory addressing and a compatible mode which supports greater that 32-bit memory addressing based on the capability of the AGP device and the amount of available system memory.

Single-Level GART Table Translation

A single-level address translation may improve overall AGP performance by reducing the number of GART table entry lookups required by the chipset. Single-level means that the chipset need only perform one GART table lookup to get the physical address of the desired page (table.fwdarw.page). This is possible because the GART table is allocated by the operating system into one single, contiguous block of uncachable memory. Allocation of this memory is typically performed early in the initialization process to ensure that contiguous memory is available. However, defragmentation of the computer system memory to obtain the necessary contiguous memory space at any time during operation of the computer system is contemplated herein.

In a computer system using single-level address translation and 32-bit addressing, the AGP device addresses used by the graphics controller can be viewed as consisting of three parts as illustrated in FIG. 9: the base address of device address space (bits 31:x), the page offset into AGP device address space (bits x:12), and the offset into the 4 KB page (bits 11:0). Note that the page offset into AGP device address space can also be used as an entry index into the GART table. Also note that the number of bits comprising the page offset into AGP device address space depends upon the size of virtual (and physical) memory allocated to AGP. For instance, it takes 13 bits to represent all of the pages in a system with 32 MB of AGP memory. The table of FIG. 10 illustrates the number of bits required to represent each 4 KB page in AGP memory versus the size of the AGP memory.

System memory requires an address with the format illustrated in FIG. 9. This address consists of the base address of the 4 KB page (bits 31:12) and the offset into the 4 KB page (bits 11:0). The base address of each 4 KB page is information required by the GART table to remap corresponding device addresses. The offset into the 4 KB page is the same offset that exists in the AGP device address.

Referring now to FIG. 11, a schematic flow diagram for converting device addresses into physical addresses in a single-level address translation is illustrated. The base address of AGP device address space, along with the size of AGP memory can optionally be used by the chipset to determine if the address in the request falls within AGP device address space before remapping occurs. To remap the address, the page offset from the AGP base address is multiplied by the size of a single GART table entry (4) and added to the base address of the GART table. This provides the physical address of the required GART table entry. This entry is retrieved from the GART table, which resides in system memory. Within this GART table entry is the base address of the desired 4 KB page; a page which resides somewhere in system memory. Adding the offset into the 4 KB page to this base address yields the required physical address. Note that the offset into the 4 KB page in virtual AGP memory (bits 11:0) is equivalent to the offset into the 4 KB page in physical (system) memory.

Two-Level GART Table Translation

Two-level address translation requires two GART table lookups to remap an AGP device address to a physical address in memory (directory.fwdarw.page.fwdarw.table). The first lookup reads the GART directory entry from system memory. The GART directory entry contains the physical address of a corresponding page of GART table entries, also residing in physical memory. A second lookup is required to retrieve the appropriate GART table entry which then points to the base address of the desired 4 KB page of AGP data in the computer system physical memory.

In some designs, two-level address translation may be preferred over the single-level address translation because it is not necessary for the GART directory and 4 KB pages comprising the GART table to be contiguous. The operating system may be more likely to successfully allocate physical memory for the GART table using two-level address translation since a large block of contiguous memory is not needed. Dynamic allocation of the GART table using either single-level or two-level address translation is contemplated in the present invention.

In a system using two-level address translation and 32-bit addressing, the device addresses used by the graphics controller can be viewed as consisting of four parts as illustrated in FIG. 12A: the base address of AGP device address space (bits 31:x), the directory offset into AGP device address space (bits x:22), the page offset into a table entry (bits 21:12), and the offset into the 4 KB page (bits 11:0). Note that the number of bits comprising the directory offset into AGP device address space depends upon the size of AGP device address space. For instance, it takes 6 bits to represent all of the GART directory entries (64) in a system with 256 MB of AGP memory. Since each GART directory entry corresponds to 4 MB of address space (i.e. 1024 pages), each page offset can be addressed using 10 bits. The table of FIG. 12B illustrates the number of bits required to represent the GART directory and page in AGP memory versus the size of AGP memory.

Referring now to FIGS. 12C and 12D, a schematic flow diagram for converting device addresses into physical addresses in a two-level address translation is illustrated. The base address of AGP device address space (bits 31:x), along with the size of AGP memory can optionally be used by the chipset 204 to determine if the address in the request falls within AGP device address space before remapping occurs. To remap the address, the directory offset (bits x:22) is multiplied by the size of a single GART directory entry (4 bytes) and added to the base address of the GART directory (a.k.a.--base address of 4 KB page containing the directory). This provides the physical address of the required GART directory entry. The GART directory entry is retrieved from physical memory, and within this GART directory entry is the physical address to the base of the 4 KB page holding the GART table entry corresponding to the request. To get the GART table entry, the page offset (bits 21:12) is multiplied by the size of a single GART table entry (4 bytes) and added to the base address of the retrieved page of the GART table. This GART table entry is then fetched from memory, and within this GART table entry is the base address of the desired 4 KB page of AGP graphics data, The AGP graphics data page resides in system memory. Adding the offset into the AGP data 4 KB page (bits 11:0) base address yields the required physical address. Note that the offset into the 4 KB page in AGP device address space (bits 11:0) is equivalent to the offset into the AGP data 4 KB page in physical (syst