Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping Number:6,803,299 from the United States Patent and Trademark Office (PTO) owispatent

Title: Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Abstract: An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Patent Number: 6,803,299 Issued on 10/12/2004 to Eitan

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Inventors:	Eitan; Boaz (Ra'anana, IL)
Assignee:	Saifun Semiconductors Ltd. (Netanya, IL)
Appl. No.:	10/412,317
Filed:	April 14, 2003

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	939570	Aug., 2001	6566699
	211981	Dec., 1998	6552387
	902890	Jul., 1997

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Current U.S. Class:	438/593 ; 257/296; 257/315; 257/E21.21; 257/E29.309; 438/261; 438/591
Field of Search:	257/296,315,324 438/261,591,593 365/185.09,185.18,185.24,185.29

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Primary Examiner: Nelms; David
Assistant Examiner: Nguyen; Dao H.
Attorney, Agent or Firm: Eitan, Pearl, Latzer & Cohen Zedek, LLP

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Parent Case Text

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CROSS REFERENCE

This application is a continuation of U.S. application Ser. No. 09/939,570 filed Aug. 28, 2001 now U.S. Pat. No. 6,566,699, which is a continuation of U.S. application Ser. No. 09/211,981 filed Dec. 14, 1998, now U.S. Pat. No. 6,552,387 which is a divisional of Ser. No. 08/902,890 filed Jul. 30, 1997 now abandoned. All of which are hereby incorporated by reference.

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Claims

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What is claimed is:

1. A method of operating a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer, the method comprising: programming said cell in a first direction to have a minimum width charge trapping region within said charge trapping layer; and reading said cell with a minimum voltage on said gate in a second direction opposite to said first direction.

2. The method of claim 1, further comprising erasing said cell such that said cell does not enter deep depletion.

3. The method of claim 1, wherein said step of programming further comprises: applying a first programming voltage to a drain of said cell; applying a second programming voltage to said gate; and grounding source of said cell separated from said drain by a channel, wherein said first programming voltage is substantially lower than said second programming voltage.

4. The method of claim 3, wherein the step of reading further comprises: applying a first read voltage to said source; applying a second read voltage to said gate; grounding said drain; and subsequently sensing current through said memory cell from said source to said drain.

5. The method of claim 1, wherein said step of reading further comprises: applying a first read voltage to a source of said cell; applying a second read voltage to said gate; grounding a drain of said cell; and subsequently sensing current through said memory cell from said source to said drain.

6. The method according to claim 5, wherein said read voltage applied to said gate during said step of reading said cell is not lower than the voltage sufficient to generate an inversion in said channel whereby the unprogrammed state can be sensed.

7. The method of claim 6, and wherein said read voltage applied to said gate during said step of reading said cell is limiting the voltage across a region of said channel beneath said trapped charge region to be lower than the voltage applied to said source during reading of said cell.

8. the method according to claim 5, wherein said read voltage applied to said gate during said step of reading said cell is limiting the voltage across a region of said channel beneath said trapped charge region to be lower than the voltage applied to said source during reading of said cell.

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Description

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FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices and more particularly to flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomenon of hot electron injection to trap charge within a trapping dielectric material within the gate.

BACKGROUND OF THE INVENTION

Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.

Semiconductor ROM devices, however, suffer from the disadvantage of not being electrically programmable memory devices. The programming of a ROM occurs during one of the steps of manufacture using special masks containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacture. In addition, because ROM devices are programmed during manufacture, the time delay before the finished product is available could be six weeks or more. The advantage, however, of using ROM for data storage is the low cost per device. However, the penalty is the inability to change the data once the ROM has been manufactured. If mistakes in the data programming are found they are typically very costly to correct. Any ROM inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used. In addition, extensive time delays are incurred because new masks must first be generated from scratch and the entire manufacturing process repeated, at least from the ROM programming mask step. Also, the cost savings in the use of ROM memories only exist if large quantities of the ROM are produced.

Moving to EPROM semiconductor devices eliminates the necessity of mask programming the data but the complexity of the process increases drastically. In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices. An advantage of EPROMs is that they are electrically programmed, but for erasing, EPROMs require exposure to ultraviolet (UV) light. EPROM dice are placed in packages with windows transparent to UV light to allow each die to be exposed for erasing, which must be performed before the device can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.

Semiconductor EEPROM devices also involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. The disadvantage of flash EEPROM is that it is very difficult and expensive to manufacture and produce.

The widespread use of EEPROM semiconductor memory has prompted much research focusing on constructing better memory cells. Active areas of research have focused on developing a memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times, shorter erase times and smaller physical dimensions. One such area of research involves a