Non-volatile memory and method with multi-stream updating Number:7,412,560 from the United States Patent and Trademark Office (PTO) owispatent In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead.<H updating, volatile, Non, volatile, me, 7412560.html, Patent, pto, 7412560

Title: Non-volatile memory and method with multi-stream updating

Abstract: In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead.

Patent Number: 7,412,560 Issued on 08/12/2008 to Smith, et al.

Inventors: Smith; Peter John (Eskbank, GB), Gorobets; Sergey Anatolievich (Edinburgh, GB), Bennett; Alan David (Edinburgh, GB)
Assignee: Sandisk Corporation (Milpitas, CA)

Appl. No.: 11/191,686

Filed: July 27, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
11016285	Dec., 2004	7315916

Current U.S. Class: 711/103

Current International Class: G06F 12/00 (20060101)

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Primary Examiner: Nguyen; Hiep T.
Attorney, Agent or Firm: Davis Wright Tremaine LLP

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 11/016,285, filed on Dec. 16, 2004.

Claims

It is claimed:

1. A method of recording data units from a host comprising: providing first and second nonvolatile storages; receiving a host write command that indicates the data units to be written; setting up either the first or second storage for recording depending on whether or not a predetermined condition is satisfied based on the data units to be written; sending the data units to the storage being set up as the data units are received from the host; and recording the data units to the set up storage when the predetermined condition is confirmed based on the data units received, otherwise setting up the second storage if not already set up, and recording the data units received to the second storage.

2. A method as in claim 1, wherein said setting up includes addressing the selected storage.

3. A method as in claim 1, wherein said sending the data units to the storage includes sending the data units to a set of data latches for programming the selected storage.

4. A method as in claim 1, further comprising: organizing the data into data units having a predetermined order; and organizing the first and second nonvolatile storages into pages, each page for programming together multiple data units having predetermined page offsets; and wherein: said predetermined condition is when one of the data units has a page-end offset; and said recording the data to the first storage includes recording to a page of the first storage said page-end data unit and any preceding data units in the page.

5. A method as in claim 4, wherein each of the first and second storages is for storing a block of memory units that are erasable together.

6. A method as in claim 4, wherein: said data from the host is update data for a group of data units; said first storage is for storing said update data; and said second storage is for buffering said update data before being transferred to the first storage.

7. A method as in claim 4, further comprising: organizing the data into data units having a predetermined order; and organizing the first and second nonvolatile storages into pages, each page for programming together multiple data units having predetermined page offsets.

8. A method as in claim 7, wherein each page is once-programmable after an erase.

9. A method as in claim 7, wherein: said recording data to the second storage includes recording to a page thereof at least one index of the data stored in the second storage.

10. A method as in claim 9, wherein said at least one index of the data stored in the second storage is recorded to a location of said page having a page-end offset.

11. A method as in claim 7, wherein: said recording data to the second storage includes recording to a page thereof at least one index of the data stored in the first and second storages.

12. A method as in claim 11, wherein said at least one index of the data stored in the first and second storages is recorded to a location of said page having a page-end offset.

13. A method as in claim 7, wherein: said recording data to the second storage includes recording to a page thereof a pointer pointing to the next recording location of the first storage.

14. A method as in claim 13, wherein said pointer is recorded to a location of a page having said page-end offset.

15. A method as in any one of claims 1-14, wherein the first and second nonvolatile storages are constituted from memory cells that individually store one bit of data.

16. A method as in any one of claims 1-14, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.

17. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; a controller for controlling operations of said blocks; first and second blocks, each for recording data from a host; a buffer for receiving the data from the host; and said controller setting up either the first or second storage for recording depending on whether or not a predetermined condition is satisfied based on the data units to be written; and sending the data units to the storage being set up as the data units are received from the host; and recording the data units to the set up storage when the predetermined condition is confirmed based on the data units received, otherwise setting up the second storage if not already set up, and recording the data units received to the second storage.

18. A nonvolatile memory as in claim 17, wherein said nonvolatile memory is in the form of a removable memory card.

19. A nonvolatile memory as in claim 17, wherein: said data from the host is update data for a group of data units; said first block is for storing said update data; and said second block is for buffering said update data before being transferred to the first block.

20. A nonvolatile memory as in claim 17, wherein: the data is organized into data units having a predetermined order; and said first and second blocks are organized into pages, each page for programming together multiple data units having predetermined page offsets.

21. A nonvolatile memory as in claim 20, wherein each page is once-programmable after an erase.

22. A nonvolatile memory as in claim 17, wherein: said predetermined condition is when one of the received data units has a page-end offset; and said controller controlling recording the data to said first block includes recording to a page of said first block said page-end data unit and any preceding data units in the page.

23. A nonvolatile memory as in claim 17, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the second storage.

24. A nonvolatile memory as in claim 23, wherein said at least one index of the data stored in the second storage is recorded to a location of said page having a page-end offset.

25. A nonvolatile memory as in claim 17, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the first and second storages.

26. A nonvolatile memory as in claim 25, wherein said at least one index of the data stored in the first and second storages is recorded to a location of said page having a page-end offset.

27. A nonvolatile memory as in claim 17, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof a pointer pointing to the next recording location of the first storage.

28. A nonvolatile memory as in claim 27, wherein said pointer is recorded to a location of a page having said page-end offset.

29. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; a controller for controlling operations of said blocks; first and second blocks, each for sequentially recording data from a host; a buffer for receiving the data from the host; and means for controlling either recording of the data to said first block when a predetermined condition is satisfied, or recording of the data to said second block when the predetermined condition is not satisfied.

30. A nonvolatile memory as in any one of claims 17-29, wherein the first and second nonvolatile storages are constituted from memory cells that individually store one bit of data.

31. A nonvolatile memory as in any one of claims 17-29, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.

32. A method of recording data from a host comprising: providing first and second nonvolatile storages; receiving the data from the host; loading the data as it is being received to a set of data latches for programming the first storage and to a set of data latches for programming the second storage; addressing either the first or second storage depending on whether or not a predetermined condition is satisfied based on the data received; and recording the data to the addressed storage from its set of data latches.

33. A method as in claim 32, wherein said set of data latches for programming the first storage is identical to that for programming the second storage.

34. A method as in claim 32, further comprising: organizing the data into data units having a predetermined order; and organizing the first and second nonvolatile storages into pages, each page for programming together multiple data units having predetermined page offsets; and wherein: said predetermined condition is when one of the data units has a page-end offset; and said recording the data to the first storage includes recording to a page of the first storage said page-end data unit and any preceding data units in the page.

35. A method as in claim 34, wherein each of the first and second storages is for storing a block of memory units that are erasable together.

36. A method as in claim 34, wherein: said data from the host is update data for a group of data units; said first storage is for storing said update data; and said second storage is for buffering said update data before being transferred to the first storage.

37. A method as in claim 34, further comprising: organizing the data into data units having a predetermined order; and organizing the first and second nonvolatile storages into pages, each page for programming together multiple data units having predetermined page offsets.

38. A method as in claim 37, wherein each page is once-programmable after an erase.

39. A method as in claim 37, wherein: said recording data to the second storage includes recording to a page thereof at least one index of the data stored in the second storage.

40. A method as in claim 39, wherein said at least one index of the data stored in the second storage is recorded to a location of said page having a page-end offset.

41. A method as in claim 37, wherein: said recording data to the second storage includes recording to a page thereof at least one index of the data stored in the first and second storages.

42. A method as in claim 41, wherein said at least one index of the data stored in the first and second storages is recorded to a location of said page having a page-end offset.

43. A method as in claim 37, wherein: said recording data to the second storage includes recording to a page thereof a pointer pointing to the next recording location of the first storage.

44. A method as in claim 43, wherein said pointer is recorded to a location of a page having said page-end offset.

45. A method as in any one of claims 32-44, wherein the first and second nonvolatile storages are constituted from memory cells that individually store one bit of data.

46. A method as in any one of claims 32-44, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.

47. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; a controller for controlling operations of said blocks; first and second blocks, each for recording data from a host; a buffer for receiving the data from the host; and said controller controlling loading the data as it is being received to a set of data latches for programming the first storage and to a set of data latches for programming the second storage; addressing either the first or second storage depending on whether or not a predetermined condition is satisfied based on the data received; and programming the data to the addressed storage from its set of data latches.

48. A nonvolatile memory as in claim 47, wherein said nonvolatile memory is in the form of a removable memory card.

49. A nonvolatile memory as in claim 47, wherein: said data from the host is update data for a group of data units; said first block is for storing said update data; and said second block is for buffering said update data before being transferred to the first block.

50. A nonvolatile memory as in claim 47, wherein: the data is organized into data units having a predetermined order; and said first and second blocks are organized into pages, each page for programming together multiple data units having predetermined page offsets.

51. A nonvolatile memory as in claim 49, wherein each page is once-programmable after an erase.

52. A nonvolatile memory as in claim 47, wherein: said predetermined condition is when one of the received data units has a page-end offset; and said controller controlling recording the data to said first block includes recording to a page of said first block said page-end data unit and any preceding data units in the page.

53. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the second storage.

54. A nonvolatile memory as in claim 52, wherein said at least one index of the data stored in the second storage is recorded to a location of said page having a page-end offset.

55. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the first and second storages.

56. A nonvolatile memory as in claim 54, wherein said at least one index of the data stored in the first and second storages is recorded to a location of said page having a page-end offset.

57. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof a pointer pointing to the next recording location of the first storage.

58. A nonvolatile memory as in claim 56, wherein said pointer is recorded to a location of a page having said page-end offset.

59. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; first and second blocks, each for sequentially recording data from a host; a buffer for receiving the data from the host; and means for loading the data as it is being received to a set of data latches for programming the first storage and to a set of data latches for programming the second storage; means for addressing either the first or second storage depending on whether or not a predetermined condition is satisfied based on the data received; and means for recording the data to the addressed storage from its set of data latches.

60. A nonvolatile memory as in any one of claims 47-59, wherein the first and second nonvolatile storages are constituted from memory cells that individually store one bit of data.

61. A nonvolatile memory as in any one of claims 47-59, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.

Description

BACKGROUND OF THE INVENTION

This invention relates generally to the operation of non-volatile flash memory systems, and, more specifically, to more efficient methods of programming data within a non-volatile flash memory.

There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is removably connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Some of the commercially available cards are CompactFlash.TM. (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. In some systems, a removable card does not include a controller and the host controls operation of the memory array in the card. Examples of this type of memory system include Smart Media cards and xD cards. Thus, control of the memory array may be achieved by software on a controller in the card or by control software in the host. Besides the memory card implementation, this type of memory can alternatively be embedded into the memory card implementation, this type of memory can alternatively be embedded into various types of host systems. In both removable and embedded applications, host data may be stored in the memory array according to a storage scheme implemented by memory control software.

Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762. These patents, along with all other patents and patent applications referenced in this application are hereby incorporated by reference in their entirety.

The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, and 6,522,580.

The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements and are described in United States patent application publication no. 2003/0109093 of Harari et al.

As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned United States patent application publication no. 2003/0109093. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528, which patents, along with all patents and patent applications cited in this application, are hereby incorporated by reference in their entirety.

Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together (an erase block). That is, the erase block is the erase unit, a minimum number of cells that are simultaneously erasable. Each erase block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the erase block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each erase block, and each page stores one or just a few host sectors of data.

In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.

To further efficiently manage the memory, erase blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one erase block from each plane. Use of the metablock is described in U.S. Pat. No. 6,763,424. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all erase blocks of a metablock are erased together. A metablock may be programmed in a unit of a metapage that comprises one page from each erase block in a metablock. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within erase blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page. In a memory system using metablocks, the metablock may be the effective minimum unit of erase of the memory array. Thus, the minimum unit of erase (a block) may be either an erase block or a metablock depending on the memory architecture. The term "block" may refer to either an erase block or a metablock depending on the architecture. Similarly, the term "page" may refer to the minimum unit of programming of the memory system. This may be a page within a single erase block or may be a metapage that extends across several erase blocks depending on the architecture of the memory system.

Data stored in a metablock are often updated, the likelihood of updates increases as the data capacity of the metablock increases. Updated sectors of one metablock are normally written to another metablock. The unchanged sectors are usually also copied from the original to the new metablock, as part of the same programming operation, to consolidate the data. Alternatively, the unchanged data may remain in the original metablock until later consolidation with the updated data into a single metablock again. Operations to consolidate current data to a new block and erase a block containing only obsolete data are generally referred to as "garbage collection" operations.

It is common to operate large block or metablock systems with some extra blocks maintained in an erased block pool. When one or more pages of data less than the capacity of a block are being updated, it is typical to write the updated pages to an erased block from the pool and then copy data of the unchanged pages from the original block to erase pool block. Variations of this technique are described in aforementioned U.S. Pat. No. 6,763,424. Over time, as a result of host data files being re-written and updated, many blocks can end up with a relatively few number of its pages containing valid data and remaining pages containing data that is no longer current. In order to be able to efficiently use the data storage capacity of the array, logically related data pages of valid data are from time-to-time gathered together from fragments among multiple blocks and consolidated together into a fewer number of blocks. This process is commonly termed "garbage collection."

In some memory systems, the physical memory cells are also grouped into two or more zones. A zone may be any partitioned subset of the physical memory or memory system into which a specified range of logical block addresses is mapped. For example, a memory system capable of storing 64 Megabytes of data may be partitioned into four zones that store 16 Megabytes of data per zone. The range of logical block addresses is then also divided into four groups, one group being assigned to the physical blocks of each of the four zones. Logical block addresses are constrained, in a typical implementation, such that the data of each are never written outside of a single physical zone into which the logical block addresses are mapped. In a memory cell array divided into planes (sub-arrays), which each have their own addressing, programming and reading circuits, each zone preferably includes blocks from multiple planes, typically the same number of blocks from each of the planes. Zones are primarily used to simplify address management such as logical to physical translation, resulting in smaller translation tables, less RAM memory needed to hold these tables, and faster access times to address the currently active region of memory, but because of their restrictive nature can result in less than optimum wear leveling.

Individual flash EEPROM cells store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as V.sub.T) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window is commonly divided into a number of ranges, one for each of the two or more storage states of the memory cell. These ranges are separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels do shift as a result of charge disturbing programming, reading or erasing operations performed in neighboring or other related memory cells, pages or blocks. Error correcting codes (ECCs) are therefore typically calculated by the controller and stored along with the host data being programmed and used during reading to verify the data and perform some level of data correction if necessary. Also, shifting charge levels can be restored back to the centers of their state ranges from time-to-time, before disturbing operations cause them to shift completely out of their defined ranges and thus cause erroneous data to be read. This process, termed data refresh or scrub, is described in U.S. Pat. Nos. 5,532,962 and 5,909,449.

In some memory arrays, a page may consist of a portion of an erase block that can hold multiple sectors of data. Once the page has been written, no further writing may be possible without corrupting the data that is already written. For memory arrays using such a system, a page may be defined by a set of memory cells that are connected to the same word line. Such memory arrays may be inefficiently programmed where data is received in amounts that are less than the size of a page. For example, where data is received one sector at a time, just one sector may be programmed to a page. No additional data may be programmed to the page without risk of corrupting the sector of data that is already saved there. Sometimes a series of single sectors may be received with some delay between them. In this case, each sector is written to a separate page of the memory array. Thus, the sectors are stored in a way that is inefficient in how it uses space in the memory array. Where multi-level logic is used, memory cells are particularly sensitive to the effects of later programming of nearby cells. In addition, programming of multi-level cells is generally done by programming a group of cells with a first page of data and later programming the cells with a second page of data. The programming of the second page of data may cause corruption of the first page of data in some cases. Hence, there is a need for a more efficient way to store data in a memory array that has a multi-sector page when the memory array receives data in amounts that are less than a page. There is also a need for a way to prevent corruption of data of a first page during programming of a subsequent page when programming a group of multi-level cells.

SUMMARY

In a memory array having a block as the unit of erase, one or more blocks may be designated as scratch pad blocks and may be used to improve performance of the memory system. A scratch pad block may operate as a buffer so that data is written to the scratch pad block with a low degree of parallelism and then copied to another location within the memory array with a high degree of parallelism. Data may be accumulated in the scratch pad block until it may be more efficiently written to another location. In memories having multi-sector pages, sectors may be accumulated until a full page may be written using the maximum parallelism of the system. In multi-level cell memories, a lower page may be stored in a scratch pad block until the upper page is available so that the upper and lower pages are stored together.

The degree of parallelism of a particular program operation is proportional to the number of bits of data that are programmed together. Thus, programming a large amount of data together is considered a write with high parallelism, while programming a small amount of data together is considered low parallelism. Where parallelism of less than a page is used, space in the memory array may be wasted and this wasted space means that garbage collection must be performed more often thus adversely affecting the efficiency of the memory system. Sometimes, small amounts of data must be stored in the memory system. By writing these small writes in one location, a scratch pad block, and later writing them together with higher parallelism to another location, the efficiency of the memory system may be improved.

In a memory system having a minimum unit of program of a page that consists of multiple sectors of data, a method of storing data that are received in amounts that are less than one page is disclosed. A block designated as a scratch pad block is used to store received sectors until a complete page may be written to the flash memory array. A first sector is stored in a first page of the scratch pad block. Subsequently received sectors may be stored in additional pages of the scratch pad block. Individually received sectors or groups of sectors are saved in a new page of the scratch pad block when they are received. Previously stored sectors from other pages in the scratch pad block may be copied to the latest page along with the new data. Thus, sectors of data are accumulated in the scratch pad block as long as there is less than a full page of new data in a page of the scratch pad block. Sectors are written to the scratch pad block with a lower degree of parallelism than the maximum available parallelism for the block. Sectors may be updated while stored in the scratch pad block. When a new sector of data is received that results in a full page of data being available for programming, the new sector and the sectors previously stored in the scratch pad block may be programmed together to the same page in another block of the memory array. This page is fully populated with data and is written with the maximum available parallelism. The data stored in the scratch pad block may then be marked as obsolete and may be erased at a convenient time. Thus, space in the flash memory is more efficiently used and the frequency of garbage collection operations is reduced.

In memories having multi-level cells, a scratch pad block may store a page of data that is also written to an active block. The stored page may be kept in the scratch pad block until another page of data is received so that the two pages of data may be written together to their destination in an active block. They may be written as an upper and lower page together using a high degree of parallelism and with a lower risk of corrupting data than if they were written separately. The scratch pad block may also be used to retain a copy of a previously programmed lower page during programming of the associated upper page so that if there is a loss of power, the data in the lower page may be recovered from the scratch pad block.

A scratch pad block may allow temporary storage of data that is to be written to another location. Data may be stored in a scratch pad block during updating of sectors of data of a block. Where a page within a block contains sectors of data from different files, the page is updated when either block is updated. It may require more than one block to store the updated data from the two files using conventional methods because two copies of the multi-file page may be needed. Using a scratch pad block allows part of the page from one file to be stored until the remainder of the page (from the other file) is available. Then, the complete updated page is programmed to its destination using maximum parallelism.

A scratch pad block may contain sectors of unrelated data. Both host data sectors and control data sectors may be stored in a scratch pad block. Both host data sectors and control data sectors may be stored in the same page within a scratch pad block. Sectors from two different files or from logically remote portions of the same file may be stored in the same page of a scratch pad block. This may allow programming of the scratch pad block with maximum parallelism so that high speed is maintained as data is received. Where data is received at a low speed, the additional space in a page may be o