Title: Nonvolatile memory device with multi-bit memory cells having plural side gates
Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.
Patent Number: 6,936,888 Issued on 08/30/2005 to Katayama, et al.
| Inventors:
|
Katayama; Kozo (Kokubunji, JP);
Kamigaki; Yoshiaki (Takamatsu, JP);
Minami; Shinichi (Kodaira, JP)
|
| Assignee:
|
Renesas Technology Corp. (Tokyo, JP)
|
| Appl. No.:
|
676158 |
| Filed:
|
October 2, 2003 |
Foreign Application Priority Data
| Nov 29, 2000[JP] | 2000-362667 |
| Current U.S. Class: |
257/320; 257/316; 257/317; 257/319 |
| Intern'l Class: |
H01L 029/78.8; H01L 029/76 |
| Field of Search: |
257/315,316,317,318,319,320
|
References Cited [Referenced By]
U.S. Patent Documents
| 4099196 | Jul., 1978 | Simko.
| |
| 5768192 | Jun., 1998 | Eitan.
| |
| 6025627 | Feb., 2000 | Forbes et al.
| |
| 6174758 | Jan., 2001 | Nachumovsky.
| |
| 6272050 | Aug., 2001 | Cunningham et al.
| |
| 6291855 | Sep., 2001 | Chang et al.
| |
| 6388293 | May., 2002 | Ogura et al.
| |
| 6504207 | Jan., 2003 | Chen et al.
| |
| 6838320 | Jan., 2005 | Tokunaga et al.
| |
| Foreign Patent Documents |
| 2001/-156275 | Jun., 2001 | JP.
| |
Primary Examiner: Ngô ; Ngân V.
Attorney, Agent or Firm: Miles & Stockbridge PC
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of application Ser. No. 09/988,725 filed
Nov. 20, 2001 now U.S. Pat. No. 6,653,685.
Claims
1. A semiconductor apparatus comprising:
a nonvolatile memory; and
a central processing unit;
wherein said nonvolatile memory has a plurality of memory cells;
wherein each said memory cell is a multi-bit memory cell including:
a memory gate formed over a first semiconductor region with a first insulating
film and a second insulating film interposed therebetween, a plurality of data
bits being stored in the memory cell by trapping electrons at one or more of a
plurality of selectable portions of said second insulating film beneath said memory
gate;
a first switch gate formed over said first semiconductor region to a first side
of said memory gate with a third insulating film;
a second switch gate formed over the first semiconductor region to a second side
of said memory gate with a fourth insulating film, wherein said second side is
opposite said first side across said memory gate; and
a second semiconductor region and a third semiconductor region respectively formed
adjacent to opposite sides of said first semiconductor region; and
wherein said first nonvolatile memory is capable of storing a program and data;
and
wherein said central processing unit executes said program read from said first
nonvolatile memory.
2. A semiconductor apparatus according to claim 1, further comprising a random
access memory,
wherein said random access memory is used for a work memory for said central
processing unit.
3. A semiconductor apparatus according to claim 2,
wherein said central processing unit controls to access to said nonvolatile memory.
4. A semiconductor apparatus according to claim 3, wherein said nonvolatile memory
is capable of rewriting data stored therein.
5. A semiconductor apparatus according to claim 4, further comprising a second
nonvolatile memory,
wherein said central processing unit controls to access to said second nonvolatile
memory.
6. A semiconductor apparatus according to claim 4, further comprising a communication
circuit and an antenna,
wherein said communication circuit couples to said antenna, and
wherein said communication circuit is capable of communication by electromagnetic
induction.
7. A semiconductor apparatus according to claim 1,
wherein each said memory cell is capable of storing data by trapping electrons
in said memory gate thereof to change a threshold voltage.
8. A semiconductor apparatus comprising:
a nonvolatile memory, which is capable of storing a program and data; and
a central processing unit, which executes said program read from said nonvolatile
memory,
wherein said nonvolatile memory has a plurality of memory cells,
wherein each said memory cell is a multi-bit memory cell including:
a memory gate formed over a first semiconductor region with a first insulating
film and a second insulating film interposed therebetween;
a first switch gate formed over said first semiconductor region with a third
insulating film and by a first side of said memory gate;
a second switch gate formed over said first semiconductor region with a fourth
insulating film and by a second side of said memory gate, wherein said second side
is opposite said first side across said memory gate,
a second semiconductor region and a third semiconductor region respectively formed
adjacent to opposite sides of said first semiconductor region; and
wherein in a first programming operation, an electron is supplied from said third
semiconductor region, moves through said first semiconductor region under said
first switch gate, and is injected into a first area of said second insulating
film near said first switch gate, and
wherein in a second programming operation, an electron is supplied from said
second semiconductor region, moves through said first semiconductor region under
said second switch gate, and is injected into a second area of said second insulating
film near said second switch gate.
9. A semiconductor apparatus according to claim 8, further comprising a random
access memory,
wherein said random access memory is used for a work memory for said central
processing unit.
10. A semiconductor apparatus according to claim 9,
wherein said central processing unit controls to access to said nonvolatile memory.
11. A semiconductor apparatus according to claim 10, wherein said nonvolatile
memory is capable of rewriting data stored therein.
12. A semiconductor apparatus according to claim 11, further comprising a second
nonvolatile memory,
wherein said central processing unit controls to access to said second nonvolatile
memory.
13. A semiconductor apparatus according to claim 11, further comprising a communication
circuit and an antenna,
wherein said communication circuit couples to said antenna, and
wherein said communication circuit is capable of communication by electromagnetic
induction.
14. A semiconductor apparatus according to claim 8,
wherein each said memory cell is capable of storing data by trapping electrons
in said second insulating film thereof to change a threshold voltage.
15. A semiconductor apparatus according to claim 8,
wherein said central processing unit is adapted to control access to said nonvolatile memory.
Description
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having nonvolatile memory
cells of multi-storage forms, wherein a structure called "a so-called MNOS (Metal
Nitride Oxide Semiconductor)" or "MONOS (Metal Oxide Nitride Oxide Semiconductor)"
is configured as a base, and electrons are trapped in nitride near the interface
between nitride and oxide at physically different positions, thereby making it
possible to perform the storage of multi-valued information, an IC card using the
semiconductor device, and a method for manufacturing such a semiconductor device.
The present invention also relates to, for example, a technology effective for
application to a microcomputer for an IC card provided with a nonvolatile memory
of a multi-storage form on an on-chip basis.
A nonvolatile memory cell having a MONOS structure has been described in U.S.
Pat.
No. 5,768,192. According to this, as illustrated in FIGS.
45(A) and
45(B),
a gate oxide film
1 and a gate nitride film
2 are laminated on a
semiconductor region, and a memory gate electrode
3, which constitutes a
word line, is provided thereon. Further, signal electrodes
4 and
5
either of which serves as a source or drain electrode, are formed in the semiconductor
region placed under the memory gate electrode. The present nonvolatile memory cell
is capable of trapping electrons in the gate nitride film
2 near the interface
with the gate oxide film
1 at physically different positions, thereby performing
the storage of multi-valued information. The injection of electrons in nitride
is carried out according to channel hot electron injection. When one attempts to
inject hot electrons into the right end of the gate nitride
2 as shown in
FIG.
45(A), the left signal electrode
5 is used as a source (source
(W)), and the right signal electrode
4 is used as a drain (drain (W)). Further,
a drain current is caused to flow so that the direction indicated by arrow W takes
the direction of motion of electrons. Thus, the electrons in a channel are accelerated
under a high electric field near the drain and thereby brought into hot electrons,
followed by injection into the drain end of the gate nitride film
2. When
it is desired to inject hot electrons into the left end of the gate nitride film
2 as shown in FIG.
45(B), the right signal electrode
4 is
used as a source (source (W)) and the left signal electrode
5 is used as
a drain (drain (W)), and electrons are moved in the direction indicated by arrow W.
When information stored at the right end of the gate nitride film
2 is
read as shown in FIG.
45(A), the right signal electrode
4 is used
as a source (source (R)) and the left signal electrode
5 is used as a drain
(drain (R)), and the memory gate electrode
3 may be set to a select level.
Since a depletion layer of a MOS transistor expands into the drain side, the switch
state of the memory cell greatly depends on the state of a threshold voltage on
the source side. Thus, when information stored at the left end of the gate nitride
film
2 is read as shown in FIG.
45(B), the left signal nitride
5
and the right signal electrode
4 are respectively used as a source (source
(R)) and a drain (drain (R)) so that the sources and drains are set contrary to
FIG.
45(A), and the memory gate electrode
3 may be set to a select
level. If an erase state in which the threshold voltage is lower than the gate
select level, is taken, then electrons flow in the direction indicated by arrow R.
A plan view of one memory cell is illustrated in FIG.
45(C). F means a
minimum
processed size. FIG.
46(A) illustrates voltage-applied states necessary
for an erase (e.g., electron discharge) operation based on word-line units, FIG.
46(B) illustrates voltage-applied states necessary for an erase operation
based on a memory array batch, FIG.
46(C) illustrates voltage-applied states
necessary for writing (e.g., injection of electrons), and FIG.
46(D) illustrates
voltage-applied states necessary for reading, respectively. In FIGS.
46(A)
through
46(D), portions indicated by elliptical circles affixed to the memory
cells respectively means regions intended for writing, erasing and reading.
SUMMARY OF THE INVENTION
The prior art is not capable of performing writing in plural bit units. Namely,
upon the write operation as illustrated in FIG. 46(C), a bit line 6
is supplied with 3V and a word line 7 is supplied with 6V to carry out hot
electron injection. However, if an attempt to carry out byte writing, for example
is made, then a write blocking or inhibition voltage of 6V must be applied to the
corresponding bit line with respect to a write inhibition bit. In doing so, a large
electric field occurs between the bit line and a word line write-unselected at
0V and hence writing is effected on an undesired bit. Since the channel hot-electron
injection system is adopted, a write current will increase. Upon the read operation
as shown in FIG. 46(D) as well, it is necessary to set a source line for
an adjacent memory cell which shares the use of a bit line 6 between a memory
cell selected for the read operation and the adjacent memory cell, to floating
(F). There is a possibility that the read operation based on such a virtual ground
system will be susceptible to the unbalance of parasitic capacity of the source
line brought to the floating and the read operation will be unstable.
As one for solving some of the problems, there is known the preceding application
(Unexamined Patent Publication No. 2001-156275, U.S. Serial or application Ser.
No. 09/660,923) filed by the present applicant. In a nonvolatile memory cell shown
in the present application, as illustrated in FIG. 47(A), a gate oxide film
11 and a gate nitride film 12 are laminated on a semiconductor region,
and a memory gate electrode 13, which constitutes a word line, is formed
thereon. Further, switch gate electrodes 16 and 17 are formed over
the semiconductor region on both sides of the memory gate electrode 13 with
gate oxide films 14 and 15 interposed therebetween. Signal electrodes
18 and 19 either of which serves as a source or drain electrode,
are formed in the semiconductor region lying in the neighborhood below the respective
switch gate electrodes 16 and 17. Since the present memory cell is
added with the switch gate electrodes 16 and 17, a cell size increases
correspondingly as illustrated in FIG. 47(B). Erasing effected on the memory
cell is carried out by applying an electric field between the word line (memory
gate electrode) and a substrate and drawing electrons into the substrate as illustrated
in FIG. 48(A). Writing is carried out by a source side hot-electron injection
system. Namely, as illustrated in FIG. 48(B), a word line 20 for
a write-selected memory cell is set to a high potential to allow a channel current
to flow through the memory cell via an on-state switch gate electrode 16,
whereby an electric field is formed between a memory gate electrode 13,
and a substrate and a source electrode 18. Thus, when the electrons from
the signal electrode 18 used as a source electrode pass through a channel
narrowed down by the switch gate electrode 16, they are accelerated and
set high in energy. They are further accelerated under a high electric field between
the memory gate electrode and the substrate, followed by trapping into the gate
nitride film 12 on the signal electrode 18 side used as the source
electrode. Since the writing is carried out according to electron source side injection,
the source/drain at reading may be the same as at writing. As shown in FIG. 48(C),
a signal electrode 19 may be used as a drain and a signal line 21
may be used as a bit line. W in FIG. 47(A) means the direction of injection
of electrons at writing, R means the direction of motion of electrons at a read
operation, and E means the direction of transfer of electrons at erasure. Incidentally,
when the electrons are injected into the gate nitride film 12 on the signal
electrode 19 side although not shown in the drawing and thereby stored information
is read, voltage conditions may be varied so that the source and drain are changed
or reversed.
According to the memory cell structure of FIG. 47, since the switch gate
electrodes 16 and 17 are provided, the separation of the corresponding
memory cell from its adjacent memory cell sharing the use of the source line/bit
line is allowed and the source line for the adjacent memory cell may not be set
to the floating upon writing or reading. Since the writing is carried out according
to the source side hot-electron injection, a write current can also be reduced.
However, the present inventors could find out the following points as a
result of further discussions about the memory cell structure. Firstly, rewriting
based on plural bit units like byte rewriting cannot be implemented. Namely, a
bit line 6 and a word line 7 are respectively supplied with 3V and
6V upon a write operation as illustrated in FIG. 48(B) to perform source
side electron injection. However, if an attempt to carry out byte writing, for
example is made, then a write blocking or inhibition voltage 6V must be applied
to the bit line with respect to a write inhibition bit, and a switch gate electrode
which accepts it, must be controlled to a voltage higher than 6V. In doing so,
a large electric field occurs between the bit line and a word line write-unselected
at 0V, and hence electrons are undesirably injected or discharged with respect
to each write-unselected memory cell. Secondly, in the source side electron injection
system, electrons from the source side are injected into an insulating film like
silicon oxide between a switch gate electrode and a gate nitride film, so that
erase/write characteristics are degraded. Thirdly, it has been clearly found out
that even the source side electron injection system increase in current consumption
as compared with tunnel writing and needs further low power consumption upon application
to an IC card or the like supplied with power in non-contact form. Fourthly, it
has been clearly found out by the present inventors that because of a configuration
using switch gate electrodes, the above memory cell increases in area as compared
with each memory cell employed in the channel hot electron injection system, and
there is need to provide new means for reducing a chip occupied area as a whole
in terms of the layout of each memory cell and a well structure or the like.
An object of the present invention is to implement rewriting based on plural
bit
units like byte rewriting with respect to a memory using memory cells of multi-storage forms.
Another object of the present invention is to prevent electrons delivered
from a source side from being injected into an insulating film between each of
switch gate electrode and a gate nitride film and improve rewrite resistance characteristics.
A further object of the present invention is to reduce a write current produced
from a source side of a memory cell of a multi-storage form.
A still further object of the present invention is to provide a semiconductor
device
like a microcomputer or a data processor most suitable for mounting to a non-contact
IC card in terms of the consumption of power by an on-chip memory cell of a multi-storage form.
Further, the present invention aims to provide a method capable of relatively
easily manufacturing a memory cell of a multi-storage form, which is capable of
performing the byte rewriting and is excellent in rewrite resistance characteristics.
The above, other objects, and novel features of the present invention will become
apparent from the description of the present specification and the accompanying drawings;
Summaries of typical ones of the inventions disclosed in the present application
will be described in brief as follows:
[1] <
In the nonvolatile memory cell, the storage of information therein is carried
out based on the difference in threshold voltage as viewed from the memory gate
electrode according to the amount of carriers, e.g., electrons captured by the
second gate insulating film, and the injection of the electrons is allowed according
to the source side injection system. For instance, erasing for the nonvolatile
memory cell is carried out by applying an electric field between the memory gate
electrode and the first semiconductor region to thereby draw electrons from the
second gate insulating film to the first semiconductor region. For example, writing
is carried out according to the source side injection system. The memory gate electrode
is brought to a high potential to allow a channel current to flow into the memory
cell through the on-state switch gate electrode, whereby an electric field is formed
between the memory gate electrode and the first semiconductor region and signal
electrode used as the source. Thus, when the electrons from the signal electrode
used as the source electrode pass through a channel narrowed down by the switch
gate electrode, they are accelerated and increase in energy. Further, they are
accelerated under a high electric field lying between the memory gate electrode
and the first semiconductor region, whereby they are obtained by the second insulating
film on the signal electrode used as the source electrode.
According to the memory cell structure, since the writing is carried out
according to the source side injection, a write current can also be reduced.
In particular, the memory cell structure is adopted wherein the memory gate electrode
and the switch gate electrodes are arranged in parallel in the same direction.
Therefore, even if a write voltage is applied to the memory gate electrode common
for the plurality of memory cells which use the memory gate electrode and switch
gate electrodes in common, write and write blocking voltage states can be applied
to the respective memory cells through their inherent first and second signal electrodes.
If at this time, the switch gate electrodes of memory cells intended for write
non-selection, each having the memory gate electrode and switch gate electrodes
different from each memory cell intended for writing are respectively brought to
a cut-off state, then the application of an undesired high electric field to the
second gate insulating film for each memory cell for write non-selection can be
blocked. Accordingly, writing can be carried out in units of plural memory cells
like byte units.
Types of the storage of the information by the nonvolatile memory cell will
be described. The single nonvolatile memory cell stores 2-bit information therein
according to a first state (first write state) in which carriers, e.g., electrons
are captured on the first switch gate electrode side of the second gate insulating
film, a second state (first erase state) in which the electrons captured in the
first state are reduced, a third state (second write state) in which electrons
are captured on the second switch gate electrode side of the second gate insulating
film, or a fourth state (second erase state) in which the electrons captured in
the third state are reduced.
Since the threshold voltage of a MOS type transistor is principally placed
under the influence of an electrical charge injected into the source side, the
source/drain is changed with respect to each memory cell of the multi-storage form
to perform a read operation, whereby 2-bit stored information can be obtained from
one nonvolatile memory cell back and forth. This can be carried out in the following
manner specifically. When a potential at the second signal electrode selected by
the second switch gate electrode is set higher than a potential at the first signal
electrode selected by the first switch gate electrode, the nonvolatile memory cell
can read 1-bit storage information placed in the first or second state. When a
potential at the first signal electrode selected by the first switch gate electrode
is set higher than a potential at the second signal electrode selected by the second
switch gate electrode, the nonvolatile memory cell can read 1-bit storage information
placed in the third or fourth state.
[2] <
A pair of the nonvolatile memory cells which is adjacent to the first direction
and shares the use of the memory gate electrode, may adopt a configuration wherein
either one of the first and second signal electrodes is used in common and the
others thereof are individualized, and the first and second signal electrodes are
connected to their corresponding first and second signal wirings. Thus, the number
of the signal wirings can be reduced. Further, this contributes to a reduction
in chip occupied area of a memory cell array.
[3] <m,
30n) in divided form, and each of the nonvolatile memory cells is
caused to discharge electrons from the second gate insulating film to the corresponding
well region according to the difference in potential between the well region and
the memory gate electrode. Thus, electron emission like erasing for the memory
cell can be carried out in well region units. If erasing is allowed in well units,
then an erase operation is allowed for each byte according to well separation made
for each byte. However, when the divided number of well regions increases, well
separation regions relatively increase, so that a chip occupied area of a memory
cell array increases.
In order to enable the erasing in small number of bit units even if the divided
number of well regions is reduced, electrons may be emitted from the second gate
insulating film to the first semiconductor region according to the difference in
potential between the first or second signal electrode selected by the first or
second switch gate electrode and the first semiconductor region. Thus, the erase
operation can be carried out in a minimum unit corresponding to the first or second
signal electrode.
In order to enable the erasing with the memory gate electrode as a minimum unit,
electrons may be emitted from the second(insulating film to the memory gate electrode
according to the difference in potential between the corresponding signal electrode
selected by the first or second switch gate electrode and the memory gate electrode.
[4] <
[5] <
[6] <
If such a semiconductor device is used as a microcomputer for an IC card, the
IC card can comprise the semiconductor device, and a card interface terminal connected
to the external interface circuit of the semiconductor device, all of which being
provided on a card substrate. In the case of a non-contact IC card, an antenna
is provided on the card substrate. For example, the transfer of power by an ac
magnetic field and communications based on electromagnetic induction can be done
in non-contact form. Alternatively, both the power transfer and the information
communications may be carried out by the electromagnetic induction. Only the power
transmission may be carried out in non-contact form.
[7] <
The first manufacturing method includes (a) a step of forming a first conductivity
type (p-type) first semiconductor region (30) on a main surface of a semiconductor
substrate, (b) a step of forming a first insulating film and a second insulating
film on the main surface of the semiconductor substrate on the first semiconductor
region in order, (c) a step of forming a first conductor element (memory gate electrode)
having a first width as viewed in a first direction of the main surface of the
semiconductor substrate and a second width as viewed in a second direction substantially
orthogonal to the first direction, on the second insulating film, (d) a step of
introducing a first impurity (p type: B) of the first conductivity type into the
first semiconductor region below the first conductor element as viewed in the first
direction to selectively form second semiconductor regions (high-concentration
impurity regions 60), (e) a step of forming a third insulating film on side
walls of the first conductor element as viewed in the first direction, (f) a step
of forming second and third conductor elements (switch gate electrodes) respectively
having a third width as viewed in the first direction and a fourth width as viewed
in the second direction at both ends of the first conductor element as viewed in
the first direction with the third insulating film interposed therebeween, and
(g) a step of introducing a second impurity of a second conductivity type (n-type)
opposite to the first conductivity type as viewed in the first direction to form
a third semiconductor region (source/drain) within the first semiconductor region
on the sides opposite to the first conductor element, of the second and third conductor elements.
The second semiconductor region forming step further includes a step of introducing
a third impurity (n-type: As) of the second conductivity type into the first semiconductor
region at both ends of the first conductor element. The third impurity may be ion-implanted
at a first angle to the main surface of the semiconductor substrate, the first
impurity may be ion-implanted at a second angle to the main surface of the semiconductor
substrate, and the first angle may be set larger than the second angle. Thus, even
if the second semiconductor regions used as the high-concentration impurity regions
formed of the first impurity protrude outside from both ends in the first direction,
of the first conductor element, the impurity concentration of the overflowing or
protruded portion can be modified later, whereby the second semiconductor regions
can be fabricated with high accuracy.
The second width of the first conductor element may be set greater than the first
width, the fourth width of the second conductor element may be set greater than
the third width, and the first and second conductor elements may extend in the
second direction. Thus, the fabricated memory cells can be rewritten in plural
bit units like the byte units as described above.
The first insulating film may comprise silicon oxide, and the second insulating
film may comprise silicon nitride.
The second manufacturing method includes (a) a step of forming a first conductivity
type (p-type) first semiconductor region (30) on a main surface of a semiconductor
substrate, (b) a step of forming two first conductor elements (switch gate electrodes)
having a first width as viewed in a first direction of the main surface of the
semiconductor substrate and a second width as viewed in a second direction substantially
orthogonal to the first direction, on the first semiconductor region with a predetermined
interval interposed therebetween, (c) a step of forming a first insulating film
on side walls of the first conductor element in a region between the first conductor
elements, (d) a step of introducing a first impurity (p-type: B) of the first conductivity
type within the first semiconductor region in the region lying between the first
conductor elements and interposed by the first insulating film formed on the side
walls of the first conductor element in order to form a second semiconductor region
(high-concentration impurity region 80) therewithin, (e) a step of forming
a second insulating film and a third insulating film over the surface of the semiconductor
substrate in the region between the first conductor elements, (f) a step of forming
a second conductor element (memory gate electrode) having a third width as viewed
in the first direction and a fourth width as viewed in the second direction, on
the third insulating film, and (g) a step of introducing a second impurity (n-type)
of a second conductivity type opposite to the first conductivity type as viewed
in the first direction to form a third semiconductor region (source/drain) within
the first semiconductor region on the side opposite to the second conductor element,
of the first conductor element.
In the second manufacturing method, the first insulating film forming step may
include a step of depositing an insulating film on the semiconductor substrate,
and a step of subjecting the insulating film to anisotropic etching and selectively
leaving the insulating film on the side walls of the first conductor element.
The second conductor element may be formed on the side walls of the first conductor
element with the third insulating film interposed therebetween. The second insulating
film may comprise silicon oxide, and the third insulating film may comprise silicon nitride.
The second width of the first conductor element may be set greater than the first
width, the fourth width of the second conductor element may be set greater than
the third width, and the first and second conductor elements may extend in the
second direction. Each of the memory cells fabricated in this way is capable of
performing batch writing or the like in plural bit units like the byte units as
described above.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(A) and 1(B) are vertical cross-sectional views illustrating
a nonvolatile memory cell according to the present invention;
FIG. 2 is a plan layout diagram of the nonvolatile memory cell shown in FIG. 1;
FIG. 3 is a plan layout diagram of a memory cell array in which a memory cell
layout represented in a minimum unit in FIG. 2 is developed plural times;
FIG. 4 is a cross-sectional view taken along line A-A′ of FIG. 3;
FIG. 5 is a cross-sectional view taken along line B-B′ of FIG. 3;
FIG. 6 is a circuit diagram illustrating a circuit configuration corresponding
to layout patterns shown in FIG. 3 together with a voltage-applied state for an
erase operation;
FIG. 7 is a circuit diagram illustrating a case in which data is written into
the source side on the switch gate 36 side, as a voltage-applied state necessary
for a write operation in the circuit configuration shown in FIG. 6;
FIG. 8 is a circuit diagram illustrating a case in which data is written into
the source side on the switch gate 37 side, as a voltage-applied state necessary
for a write operation in the circuit configuration shown in FIG. 6;
FIG. 9 is a circuit diagram illustrating a case in which information stored
in the source side on the switch gate 30 side is read, as a voltage-applied
state necessary for a read operation in the circuit configuration shown in FIG. 6;
FIG. 10 is a circuit diagram illustrating a case in which information stored
in the source side on the switch gate 37 side is read, as a voltage-applied
state necessary for a read operation in the circuit configuration shown in FIG. 6;
FIG. 11 is a circuit diagram illustrates write and read minimum unit circuits
in byte units and illustrating modes of connections of sense amplifiers and write
amplifiers at the assumption of write and read operations (cycle 1) with
respect to the source sides of FIGS. 7 and 9;
FIG. 12 is a circuit diagram illustrating write and read minimum unit circuits
in byte units and illustrating modes of connections of sense amplifiers and write
amplifiers at the assumption of write and read operations (cycle 2) with
respect to the source sides of FIGS. 8 and 10;
FIG. 13 is a timing chart for describing erase, write and read operations under
the circuit configurations shown in FIGS. 11 and 12;
FIG. 14 is a cross-sectional view illustrating a structure of another nonvolatile
memory cell of a multi-storage form according to a source side injection system;
FIG. 15 is a configuration diagram of a plan layout in which two nonvolatile
memory cells each having the sectional structure of FIG. 14 are configured as a
minimum unit;
FIG. 16 is a cross-sectional view illustrating a memory cell structure having
a high-concentration impurity region at a channel portion, as a further nonvolatile
memory cell of a multi-storage form according to a source side injection system;
FIG. 17 is an energy band diagram showing sectional portions taken along line
a-a′, b-b′ and c-c′ of FIG. 16;
FIG. 18 is a vertical cross-sectional view illustrating one process of a method
for manufacturing a semiconductor device having the memory cell illustrated in
FIG. 16;
FIG. 19 is a vertical cross-sectional view illustrating a next process of the
method for manufacturing the semiconductor device having the memory cell illustrated
in FIG. 16;
FIG. 20 is a vertical cross-sectional view illustrating a further next process
of the method for manufacturing the semiconductor device having the memory cell
illustrated in FIG. 16;.
FIG. 21 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 16;
FIG. 22 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 16;
FIG. 23 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 16;
FIG. 24 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 16;
FIG. 25 is a cross-sectional view illustrating a memory cell structure having
a high-concentration impurity region at a channel portion, as a still further nonvolatile
memory cell of a multi-storage form according to a source side injection system;
FIG. 26 is a vertical cross-sectional view illustrating one process of a method
for manufacturing a semiconductor device having the memory cell illustrated in
FIG. 25;
FIG. 27 is a vertical cross-sectional view illustrating a next process of the
method for manufacturing the semiconductor device having the memory cell illustrated
in FIG. 25;
FIG. 28 is a vertical cross-sectional view illustrating a further next process
of the method for manufacturing the semiconductor device having the memory cell
illustrated in FIG. 25;
FIG. 29 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 25;
FIG. 30 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 25;
FIG. 31 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 25;
FIG. 32 is a vertical cross-sectional view illustrating a still further next
process of the method for manufacturing the semiconductor device having the memory
cell illustrated in FIG. 25;
FIG. 33 is a circuit diagram showing another example of the erasure;
FIG. 34 is a circuit diagram illustrating a further example of the erasure;
FIG. 35 is a cross-sectional view of a longitudinally-cut structure of one signal
electrode employed in a memory cell array where the erasures shown in FIGS. 33
and 34 are carried out;
FIG. 36 is a cross-sectional view of a longitudinally-cut structure of the other
signal electrode employed in the memory cell array where the erasures shown in
FIGS. 33 and 34 are executed;
FIG. 37 is a plan view showing another example of the plan layout with respect
to the minimum unit shown in FIG. 2;
FIG. 38 is a circuit diagram illustrating a read minimum unit circuit corresponding
to the plan layout shown in FIG. 37;
FIG. 39 is a timing chart illustrating erase, write and read operations employed
in a circuit configuration shown in FIG. 38;
FIG. 40 is a schematic block diagram of a nonvolatile memory to which each nonvolatile
memory cell of the multi-storage form is applied;
FIG. 41 is a schematic block diagram showing one example of a microcomputer
in which the nonvolatile memory typified in FIG. 40 is built;
FIG. 42 is a schematic block diagram showing another example of the microcomputer
having incorporated the nonvolatile memory typified in FIG. 40 therein;
FIG. 43 is a schematic plan view illustrating a contact IC card to which the
microcomputer shown in FIG. 41 or 42 is applied;
FIG. 44 is a schematic plan view illustrating a non-contact IC card to which
the microcomputer illustrated in FIG. 41 or 42 is applied;
FIGS. 45(A) to 45(C) are diagrams for describing a structure
of a nonvolatile memory cell of a multi-storage form having a conventional MONOS structure;
FIGS. 46(A) to 46(D) are circuit diagrams illustrating voltage-applied
states at erase, write and read operations for the memory cell shown in FIG. 45;
FIGS. 47(A) and 47(B) are explanatory views schematically showing
a structure of a multi-storage type nonvolatile memory cell of a source side injection
form, which has been discussed by the present inventors according to the preceding
application done by the present applicant; and
FIGS. 48(A) to 48(C) are circuit diagrams illustrating voltage-applied
states at erase, write read operations for the memory cell shown in FIG. 47.
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will hereinafter be described
in detail with reference to the accompanying drawing.
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A vertical cross-sectional view of a nonvolatile memory cell according to the
present
invention is illustrated in FIG. 1. A plan layout of the nonvolatile memory cell
is illustrated in FIG. 2. FIG. 1 is a cross-sectional view taken along line
A-A′ of FIG. 2 and shows two types of states (A) and (B) different
in the position of electron injection by a source side injection system. The nonvolatile
memory cell shown in the same drawing is capable of storing 2-bit information according
to injected positions of electrons from the source side in singular form.
In the nonvolatile memory cell illustrated in FIG. 1, a gate oxide film 31
and a gate nitride film 32 are laminated over a semiconductor region, e.g.,
a p-type well region 30, and a memory gate electrode (memory gate) 33,
which constitutes a word line, is formed thereon. Switch gate electrodes (side
gates) 36 and 37, which constitute switch control lines, are respectively
formed over the semiconductor regions placed on both sides of the memory gate electrode
33 with the gate oxide films 34 and 35 interposed therebetween.
Signal electrodes 38 and 39, either of which serves as a source or
drain electrode, are formed within the semiconductor regions lying in the neighborhood
below the switch gates 36 and 37. An interlayer insulating film 40
is interposed between the gate nitride film 32 and memory gate electrode
33 and the switch gate electrodes 36 and 37.
Erasing for the nonvolatile memory cell is carried out by, for example, applying
an electric field between the memory gate electrode 33 and the well region
30 to thereby draw electrons into the well region 30. Writing is
carried out according to a source side hot electron injecting system. In FIG. 1(A)
by way of example, the memory gate electrode 33 is brought to a high potential
to allow a channel current to flow into the memory cell through the on-state switch
gate electrode 36, whereby an electric field is formed between the memory
gate electrode 33 and the well region 30 and source electrode 38.
Thus, when the electrons from the signal electrode 38 used as the source
electrode pass through a channel narrowed down by the switch gate electrode 36,
they are accelerated and increase in energy. Further, they are accelerated under
a high electric field lying between the memory gate electrode 33 and the
well region 30, whereby they are obtained from the signal electrode 38
side used as the source electrode so as to reach the gate nitride film 32.
Since the writing is performed according to the injection of the electrons from
the source side, the source and drain at reading may be the same as at writing,
the signal electrode 39 may be configured as the drain, and the signal electrode
38 may be configured as the source. FIG. 1(A) assumes a case in which
the electrons are injected into the left side of the silicon nitride film, and
FIG. 1(B) assumes a case in which the electrons are injected into the right
side of the silicon nitride film. In the drawing, W means the direction of injection
of the electrons at a write operation, and R means the direction of motion of the
electrons at a read operation.
When the nonvolatile memory cell shown in FIG. 1 is manufactured, a field oxide
film 41 is first formed on a silicon substrate and thereafter a gate oxide
film 31 is formed in a memory cell region. Further, a gate nitride film
32 formed of silicon nitride is formed on the gate oxide film 31.
Polysilicon corresponding to a first layer is processed to form a memory gate electrode
(word line) 33 on the gate nitride film 32. After the gate oxide
film 31 and gate nitride film 32 corresponding to exposed portions
are removed, gate oxide films 34 and 35 and interlayer insulating
film 40 used for switch gate electrodes are formed. Thereafter, polysilicon
corresponding to a second layer is deposited to thereby form the switch gate electrodes
36 and 37 in parallel with the memory gate electrode (word line)
33. Ions are injected into the silicon substrate with the memory gate electrode
33 and the switch gate electrodes 36 and 37 as masks to thereby
form signal electrodes 38 and 39 either of which is formed as a source
or drain electrode. Thereafter, an interlayer insulating film is deposited over
the entire surface and contact holes 42 are defined therein. Further, a
metal such as aluminum or the like is deposited to form data lines 43, 44
and 45 used as signal wirings.
The plan layout of FIG. 2 is shown with the two nonvolatile memory cells MC provided
from side to side as minimum units. One signal electrode 38 is commonly
used in both the memory cells MC and connected to the data line 44. The
other signal electrodes 39 are individualized according to the two memory
cells MC and respectively connected to the discrete data lines 43 and 45.
As is apparent from FIG. 2, the memory gate electrodes 33 and the switch
gate electrodes 36 and 37 extend in the direction substantially orthogonal
to the data lines.
A configuration in which the memory cell layout corresponding to the minimum
unit
shown in FIG. 2 is set to plural times, is illustrated in FIG. 3. Since
the memory cell layout corresponding to the minimum unit of FIG. 2 is equivalent
to a 4-bit one-word configuration, FIG. 3 results in a configuration wherein circuit
blocks corresponding to 8-bit-based 4 words are disposed as two pairs. The memory
gate electrodes 33 adjacent to one another in the transverse direction are
connected to one another to constitute the word lines, and the switch gate electrodes
36 and 37 adjacent to one another in the transverse direction are
connected to one another to constitute switch control lines.
As shown in FIGS. 2 and 3, the adoption of the configuration in which one signal
electrode 38 is commonly used for an adjacent pair of the nonvolatile memory
cells MC using the memory gate electrode 33 in common, and the other signal
electrodes 39 are individualized with respect to the nonvolatile memory
cells MC and connected to their corresponding data lines 43, 44 and
45, allows a reduction in the number of the data lines and a reduction in
chip occupied area of a memory cell array.
FIG. 4 shows a cross-section taken along line A-A′ of FIG. 3, and FIG.
5 illustrates a cross-section taken along line B-B′ of FIG. 3, respectively.
In the configurations shown in FIGS. 4 and 5, p-type well regions (Pwell) 30
are formed every 8 bits per word, and an n-type well region (Nwell) 48 separates
between the two.
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FIG. 6 shows a circuit configuration corresponding to the layout patterns shown
in FIG. 3 and illustrates voltage-applied states for an erase operation
in particular. For the convenience of description herein, the extended memory gate
electrodes 33 are added with suffixes of h, i, j and k so as to be represented
as word lines 33h through 33k. The extended switch
gate electrodes 36 and 37 are respectively represented as switch
control lines 36h, 37h through 36k and
37k, and the extended data lines 43, 44 and 45
are respectively represented as data lines 43h, 44h,
45h through 43k, 44k and 45k.
Similarly, the p-type well regions 30 are respectively marked with suffixes
m and n so as to be represented as p-type well regions 30m and 30n.
The erase operation can be carried out every well regions 30m and
30n in units of word lines 33h through 33k.
In FIG. 6, source side regions added with elliptic marks, of the nonvolatile memory
cell are intended for erasing. For example, a positive high voltage Vpp (6V) is
applied to all the data lines 43h, 44h, 45h
through 43k, 44k and 45k, the word
lines 33h, 33j and 33k lying in non-erasure
rows, and the well region 30m intended for erasing, and a negative
voltage -Vpw (-3V) is applied to the word line 33i intended for erasure
and the well region 30n for non-erasure. 0V is applied to the switch
control lines (side gates) 36i and 37i lying in the
erasure rows, and a Vpp′>Vpp+Vth of (7.5V) is applied to both side
gates 36h, 37h, 36j, 37j,
36k and 37k lying in the non-erasure, rows. Here, Vth
means the threshold voltage of a side gate transistor which comprises the switch
gate electrodes 36 and 37.
Thus, a potential difference (9V) of Vpp+Vpw is applied between the
memory gate electrode 33 of each of memory cells having byt
