Nonvolatile semiconductor memory device Number:6,798,698 from the United States Patent and Trademark Office (PTO) owispatent A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.<H semiconductor, Nonvolatile, Nonvolatile, sem, 6798698.html, Patent, pto, 6798698

Title: Nonvolatile semiconductor memory device

Abstract: A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Patent Number: 6,798,698 Issued on 09/28/2004 to Tanaka, et al.

Inventors: Tanaka; Tomoharu (Yokohama, JP), Nakamura; Hiroshi (Kawasaki, JP), Takeuchi; Ken (Tokyo, JP), Shirota; Riichiro (Fujisawa, JP), Arai; Fumitaka (Kawasaki, JP), Fujimura; Susumu (Kawaskai, JP)
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)

Appl. No.: 10/377,674

Filed: March 4, 2003

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
187285	Jul., 2002	6549464
767152	Jan., 2001	6434055
599397	Jun., 2000	6208560
078137	May., 1998	6134140

Foreign Application Priority Data


May 14, 1997 [JP]			9-124493
Aug 21, 1997 [JP]			9-224922
Dec 11, 1997 [JP]			9-340971
Apr 15, 1998 [JP]			10-104652

Current U.S. Class: 365/185.22 ; 365/185.17; 365/185.19

Field of Search: 365/185.03,185.11,185.17,185.22,185.29,185.19

References Cited [Referenced By]

U.S. Patent Documents


5172338	December 1992	Mehrotra et al.
5570315	October 1996	Tanaka et al.
5576992	November 1996	Mehrad
5627784	May 1997	Roohparvar
5652719	July 1997	Tanaka et al.
5805501	September 1998	Shiau et al.
5870334	February 1999	Hemink et al.

Foreign Patent Documents


03-130995	Jun., 1991	JP
05-182482	Jul., 1993	JP
05-314783	Nov., 1993	JP
06-028875	Feb., 1994	JP
06-124595	May., 1994	JP
06-290591	Oct., 1994	JP
07-169286	Jul., 1995	JP
08-007584	Jan., 1996	JP
08-045284	Feb., 1996	JP
08-063982	Mar., 1996	JP
08-106793	Apr., 1996	JP

Other References

Tae-Sung et al., "A 3.3V 128 Mb Mlti-level NAND Flash Memory for Mass Storage Applications"; IISSC Digest of Technical Papers; Feb. 1996; pp. 32-33. .
U.S. patent application Ser. No. 08/527,725 (now abandoned), filed Sep. 13, 1995..

Primary Examiner: Le; Vu A.
Attorney, Agent or Firm: Banner & Witcoff, Ltd.

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of prior application Ser. No. 10/187,285, filed Jul. 2, 2002, now U.S. Pat. No. 6,549,464 which is a continuation of prior application Ser. No. 09/767,152, filed Jan. 23, 2001 (now U.S. Pat. No. 6,434,055), which is a divisional of prior application Ser. No. 09/599,397, filed Jun. 22, 2000 (now U.S. Pat. No. 6,208,560), which is a divisional of prior application Ser. No. 09/078,137, filed May 14, 1998 (now U.S. Pat. No. 6,134,140), which is based on and claims priority to Japanese Patent Application No. 9-124493, filed May 14, 1997, Japanese Patent Application No. 9-224922, filed Aug. 21, 1997, Japanese Patent Application No. 9-340971, filed Dec. 11, 1997, and Japanese Patent Application No. 10-104652, filed Apr. 15, 1998, the contents of which are incorporated herein by reference.

Claims

What is claimed is:

1. A non-volatile semiconductor memory card comprising: an electrically erasable and programmable non-volatile semiconductor memory device; a controller unit configured to control the memory device; and a terminal configured to connect the memory device to an external device, wherein the memory device comprises: a NAND cell unit comprising a plurality of memory cells connected in series; an erase circuit for applying an erase voltage to all memory cells of said NAND cell unit to erase data from all memory cells of said NAND cell unit; a soft-programming circuit for applying a soft-program voltage to all memory cells of said NAND cell unit, the soft-program voltage having a polarity opposite to a polarity of the erase voltage; and a programming circuit for applying a program voltage to any selected one of the memory cells, applying a first voltage to at least one of two memory cells adjacent to said any selected one of the memory cells, and applying a second voltage to the remaining memory cells of said NAND cell unit, thereby to program data into said any selected one of the memory cells.

2. The non-volatile semiconductor memory card according to claim 1, wherein said programming circuit applies the first voltage to two of said memory cells adjacent to said any selected one of the memory cells.

3. The non-volatile semiconductor memory card according to claim 1, wherein said soft-programming circuit applies the soft-program voltage to all the memory cells after said erase circuit has erased data from all memory cells of said NAND cell unit, and said programming circuit programs the memory cells after said soft-programming circuit has applied the soft-program voltage to all the memory cells.

4. The non-volatile semiconductor memory card according to claim 1, wherein the soft-program voltage is lower than the program voltage.

5. The non-volatile semiconductor memory card according to claim 1, further comprising an erase-verification circuit for determining whether data has been erased from all the memory cells of said NAND cell unit and controlling threshold voltages within a predetermined range after said soft-programming circuit has applied the soft-program voltage to all the memory cells, and in which said programming circuit programs data into said any selected one of the memory cells after said soft-programming circuit and said erase-verification circuit have performed a soft-program operation and an erase verification operation.

6. The non-volatile semiconductor memory card according to claim 5, further comprising a control circuit for causing said soft-programming circuit and said erase-verification circuit to repeat the soft-program operation and the erase verification operation, an d for causing said soft-programming circuit to terminate the soft-program operation when at least one of the memory cells of said NAND cell unit has a threshold voltage forced out of the predetermined range.

7. The non-volatile semiconductor memory card according to claim 6, wherein said control circuit causes said erase circuit to erase data again from all memory cells of said NAND cell unit when the soft-program operation and the erase verification operation have not repeated a predetermined number of times and when at least one of the memory cells of said NAND cell unit is forced out of the predetermined range.

8. The non-volatile semiconductor memory card according to claim 1, wherein the program voltage is higher than the first and second voltages, and the second voltage is higher than the first voltage.

9. The non-volatile semiconductor memory card according to claim 8, wherein the first voltage is 0V.

10. A non-volatile semiconductor memory card comprising: an electrically erasable and programmable non-volatile semiconductor memory-device; a controller unit configured to control the memory device; and a terminal configured to connect the memory device to an external device, wherein the memory device comprises: a memory cell array comprising memory cells arranged in rows and columns, each having a control gate; a programming circuit for programming data into any selected one of said memory cells by applying a program voltage to the control gate of the selected memory cell; an erasing circuit for erasing data from said memory cells by applying an erase voltage opposite in polarity to the program voltage; a soft-programming circuit for applying a soft-program voltage to said memory cells after said erasing circuit has erased data from said memory cells, thereby setting said memory cells into a desirable erased state; a verification read circuit for determining whether said memory cells have been set into the desirable erased state after said soft-programming circuit has soft-programmed said memory cells; and an erased-state determining circuit for causing said soft-programming circuit to terminate a soft-program operation upon determining from an output of said verification read circuit that at least two of said memory cells have a threshold voltage which has reached a predetermined value.

11. The non-volatile semiconductor memory card according to claim 10, wherein said memory cell array includes a plurality of data input/output lines divided into m units, and said erased-state determining circuit comprises circuits for detecting erased states of said memory cells based on the data input/output lines of each unit and causing said soft-programming circuit to terminate the soft-program operation, upon determining that at least one of said memory cells connected to the data input/output lines of any unit has a threshold voltage which has reached the predetermined value.

12. The non-volatile semiconductor memory card according to claim 10, wherein said memory cell array includes a plurality of word lines divided into m units, and said erased-state determining circuit comprises circuits for detecting erased states of said memory cells based on the word lines of each unit and causing said soft-programming circuit to terminate the soft-program operation, upon determining that at least one of said memory cells connected to the word lines of any unit has a threshold voltage which has reached the predetermined value.

13. The non-volatile semiconductor memory card according to claim 10, wherein the non-volatile semiconductor memory cells of said memory cell array form NAND cell units, each comprising a plurality of memory cells connected in series, and said programming circuit applies a first voltage lower than the program voltage to the control gate of at least one of two memory cells adjacent to any selected one of the memory cells of each NAND cell unit, and applies a second voltage between the program voltage and the first voltage, to the remaining memory cells of each NAND cell unit, thereby to program data into said any selected one of the memory cells.

14. The non-volatile semiconductor memory card according to claim 10, further comprising a memory circuit for storing data output from said verification read circuit, and in which said erased-state determining circuit comprises a scan-detection circuit for monitoring the data stored in said memory circuit and counting the memory cells which have a threshold voltage which has reached the predetermined value.

15. The non-volatile semiconductor memory card according to claim 14, further comprising a control circuit for repeatedly causing said soft-programming circuit to perform the soft-program operation, said verification read circuit to perform a verification read operation and said scan-detection circuit to perform a memory-cell counting operation, and for causing said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation when said scan-detection circuit counts at least two memory cells having a threshold voltage which has reached the predetermined value.

16. The non-volatile semiconductor memory card according to claim 15, wherein said control circuit causes said verification read circuit to perform the verification read operation by applying a margin voltage to a word line of each NAND cell unit after said soft-programming circuit has finished performing the soft-program operation, causes said scan-detection circuit to perform the memory-cell counting operation, and causes said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation, when said scan-detection circuit detects that all memory cells of each NAND cell unit have a threshold voltage equal to or lower than a predetermined threshold voltage, the predetermined threshold voltage being higher than the predetermined value.

17. A non-volatile semiconductor memory card comprising: an electrically erasable and programmable non-volatile semiconductor memory device; a controller unit configured to control the memory device; and a terminal configured to connect the memory device to an external device, wherein the memory device comprises: at least three memory cells, each having a control gate; a programming circuit configured to program data into any selected one of said memory cells by applying a program voltage to the control gate of the selected memory cell; an erasing circuit configured to erase data from all of said memory cells by simultaneously applying an erase voltage opposite in polarity to the program voltage to all of said memory cells, thereby setting all of said memory cells into an erased state; a soft-programming circuit configured to simultaneously apply a soft-program voltage having the same polarity as the program voltage to the control gates of all said memory cells in order to adjust the erased state of said memory cells; a verification read circuit configured to determine whether threshold voltages of at least two of said memory cells have entered a given range and configured to output a termination signal if it is determined that the threshold voltages of at least two of said memory cells have entered the given range; and an erased-state determining circuit configured to cause said soft-programming circuit to terminate applying the soft program voltage in response to the termination signal.

18. The non-volatile semiconductor memory card according to claim 17, wherein said soft-programming circuit soft-programs said memory cells after said erasing circuit has erased data from said memory cells, and said verification read circuit performs a determination operation after said soft-programming circuit has soft-programmed said memory cells.

19. The non-volatile semiconductor memory card according to claim 17, wherein said memory cell array includes a plurality of data input/output lines divided into m units, and said erased-state determining circuit comprises circuits configured to detect erased states of said memory cells based on the data input/output lines of each unit and configured to cause said soft-programming circuit to terminate a soft-program operation, upon determining that at least one of said memory cells connected to the data input/output lines of any unit has a threshold voltage which has entered the given range.

20. The non-volatile semiconductor memory card according to claim 17, wherein said memory cell array includes a plurality of word lines divided into m units, and said erased-state determining circuit comprises circuits configured to detect erased states of said memory cells based on the word lines of each unit and configured to cause said soft-programming circuit to terminate a soft-program operation, upon determining that at least one of said memory cells connected to the word lines of any unit has a threshold voltage which has entered the given range.

21. The non-volatile semiconductor memory card according to claim 17, wherein the non-volatile semiconductor memory cells of said memory cell array form NAND cell units, each comprising a plurality of memory cells connected in series, and said programming circuit is configured to apply a first voltage lower than the program voltage to the control gate of at least one of two memory cells adjacent to any selected one of the memory cells of each NAND cell unit, and is configured to apply a second voltage between the program voltage and the first voltage, to the remaining memory cells of each NAND cell unit, thereby to program data into said any selected one of the memory cells.

22. The non-volatile semiconductor memory card according to claim 21, further comprising a memory circuit for storing data output from said verification read circuit, and in which said erased-state determining circuit comprises a scan-detection circuit configured to monitor the data stored in said memory circuit and configured to count the memory cells which have a threshold voltage which has entered the given range.

23. The non-volatile semiconductor memory card according to claim 22, further comprising a control circuit configured to repeatedly cause said soft-programming circuit to perform a soft-program operation, said verification read circuit to perform a verification read operation and said scan-detection circuit to perform a memory-cell counting operation, and configured to cause said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation when said scan-detection circuit counts at least two memory cells having a threshold voltage which has entered the given range.

24. The non-volatile semiconductor memory card according to claim 23, wherein said control circuit causes said verification read circuit to perform the verification read operation by applying a margin voltage to a word line of each NAND cell unit after said soft-programming circuit has finished performing the soft-program operation, causes said scan-detection circuit to perform the memory-cell counting operation, and causes said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation, when said scan-detection circuit detects that all memory cells of each NAND cell unit have a threshold voltage equal to or lower than a predetermined threshold voltage, the predetermined threshold voltage being higher than a predetermined value.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a nonvolatile semiconductor memory device, more particularly to an EEPROM (Electrically Erasable and Programmable Read-Only Memory).

As an example of a memory cell of EEPROM known as a flash memory, there is a memory cell having an MOSFET structure, which comprises a floating gate and a control gate. The floating gate (i.e., charge storage layer) is provided on a semiconductor substrate, and the control gate is provided on the charge storage layer. The memory cell stores a 1-bit data which is either "0" or "1", depending on the amount of electric charge accumulated in the floating gate.

Another type of a memory cell is known, which is designed for use in a flash memory having a large storage capacity. This memory cell can store multi-bit data. A four-value memory cell, for example, can store "0", "1", "2" and "3" by accumulating, respectively, four different amounts of charge in the floating gate.

How a four-value memory cell stores multi-bit data will be explained below.

A four-value memory cell assumes a neutral state when its floating gate accumulates no electric charge. A condition in which a more positive charge is accumulated than the neutral state is an erased state, storing data "0". More specifically, a high voltage of about 20V is applied to the substrate, setting the control gate at 0V, whereby erasing the data, i.e., storing data "0". The threshold voltage of the four-value memory cell may differ from the design value. If so, the voltage applied to the substrate may be too high, and the floating gate may accumulate an excessively large positive charge and the memory cell is, so to speak, "over-erased." In the four-value memory cell which has been over-erased, the charge accumulated in the floating gate would not change to a predetermined negative level even if an ordinary programming pulse voltage is applied to the memory cell. In this case, data, particularly "0" cannot be programmed into the four-value memory cell.

The four-value memory cell stores data "1" when the floating gate accumulates a first negative charge. The memory cell stores data "2" when the floating gate accumulates a second negative charge greater than the first. The memory cell stores data "3" when the floating gate accumulates a third negative charge greater than the second negative charge.

To program data into the four-value memory cell, the program operation, the substrate, source and drain are set at 0V and a high voltage (about 20V) is applied to the control gate. When the floating gate accumulates the first negative charge, data "1" is programmed into the memory cell. When the floating gate accumulates the second negative charge, data "2" is programmed into the memory cell. When the floating gate accumulates the third negative charge, data "3" is programmed into the memory cell. When the substrate, the source, drain and channel are set at a positive potential and the control gate is applied with the high voltage (about 20V), while the substrate remains at 0V, the floating gate holds the accumulated charge. In this case, data "0" is programmed into the memory cell.

The four-value memory cell can thus store four values "0", "1", "2" and "3".

A NAND-type memory cell unit is known, which is designed to increase the storage capacity of a flash memory. The NAND-type memory cell unit comprises a plurality of memory cells and two selection transistors. The memory cells are connected in series, forming a series circuit. The first selection transistor connects one end of the series circuit to a bit line. The second selection transistor connects the other end of the series circuit to the common source line of the memory cells.

To program "0" into a selected one of the memory cells of the NAND-type memory cell unit, the bit line and the gate of the first selection transistor are set at the power-supply voltage VCC (e.g., 3V), the control gate of the selected memory cell is set at 20V, the control gates of the two memory cells adjacent to the selected memory cell are set at 0V, and the control gate of any other memory cells is set at 11V.

In this case, the voltage applied from the bit line via the first selection transistor to the channel of the memory cell at one end of the series circuit is equal to or lower than the power-supply voltage VCC. Once the first selection transistor is turned off, however, the channel voltage rises due to the electrostatic capacitive coupling between the control gate and channel of the memory cell.

The two memory cells adjacent to the selected memory cell are thereby turned off, too. If the coupling ratio is 50%, the channel potential of the selected memory cell will be 10V, as is obtained by simple calculation. The channel potential of any memory cell not selected will be 5.5V.

When the channel potential of any memory cell not selected is 5.5V, the two memory cells adjacent to the selected memory cell will be turned off if their threshold voltage is equal to or higher than -5.5V. In other words, these memory cells must have a threshold voltage equal to or higher than -5.5V in order to program "0" into the selected memory cell.

To program "1", "2" or "3" into any selected memory cell of the NAND-type memory cell unit, the bit line is set at 0V. Program verification is performed on the selected memory cell. If a memory cell is found into which the data is not completely programmed, the program operation is effected again on that memory cell.

The threshold voltage of any memory cell is thereby controlled with high precision. The program operation on the NAND-type memory cell unit ends when all the memory cells are verified. Time periods of one cycle for programming "1", "2", and "3" are set to the same period. Therefore, data "2" and "3" are programmed by controlling the number of cycles for programming. That is, the program operation is effected once to program data "1", twice to program data "2", and thrice to program data "3".

Hence, data "1" is programmed into a memory cell that should store "1" when the program operation is carried out for the first time. Then, data "2" is programmed into a memory cell that should store "2", and thereafter data "3" is programmed into a memory cell that should store "3."

There is known another method of programming data into flash memories. In this method, the bit line voltage is changed in accordance with the value of the data to be programmed, whereby "1", "2" and "3" are written at the same speed, or within the same time period.

The method cannot be used to program data into a NAND-type memory cell unit of the type described above. If the method is so used, however, a voltage higher than 0V of the bit line voltage cannot be transferred to the selected memory cell, if the control gate of the selected memory cell is set at 0V. This is because both memory cells adjacent to the selected memory cell have a threshold voltage which is almost 0V.

The floating gate of a multi-value memory cell must accumulate a larger electric charge to program data into the memory cell than the amount of charge the floating gate of a binary memory cell needs to accumulate to program data. The greater the charge the floating gate accumulates, the higher the rate at which the floating gate is discharged due to a self electromagnetic field. Hence, multi-value memory cells can hold data, but for a shorter time than binary memory cell.

In the conventional nonvolatile memory device having multi-value memory cells, the channel voltage of the selected memory cell at the time of "0" programming rises sufficiently since the channel potential is isolated from the channel voltage any other memory cells. However, when the selected memory cell is over-erased, its threshold voltage decreases excessively and both memory cells adjacent to the selected memory cell cannot be turned off. Consequently, the channel potential of the selected memory cell fails to increase sufficiently, making it impossible to program data "0" into the selected memory cell. It should be noted that the memory cell is over-erased if the erase operation has been performed many times or if an excessively high data-erasing voltage is applied.

Further, the pulse width of a programming pulse which indicates a time period of one cycle of program operation is constant irrespective of the program operations for "1", "2" and "3". Therefore, the programming speed for programming "1", "2" and "3" cannot be made equal. Stated another way, time periods of one cycle for programming "1", "2" and "3" are set to the same period and data "2" and "3" are written by controlling the number of cycles for programming. Therefore, the programming pulse must be applied at short intervals, and much time is required to rewrite data in the memory.

Further, each multi-value memory cell can hold data, but for a shorter time than a binary memory cell.

BRIEF SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which the voltage applied to a selected memory cell is low enough to program data "0" reliably into the selected memory cell even if the selected memory cell has been over-erased.

Another object of the invention is to provide a nonvolatile semiconductor memory device in which multi-value data can be programmed into the memory cells at high speed.

Still another object of this invention is to provide a nonvolatile semiconductor memory system in which each memory cell can hold multi-value data for a long time and which can achieve reliable storage of multi-value data.

(1) According to a first aspect of the present invention, there is provided a nonvolatile semi-conductor memory device comprising a NAND cell unit comprising a plurality of memory cells connected in series; an erase circuit for applying an erase voltage to all memory cells of the NAND cell unit, thereby to erase data from all memory cells of the NAND cell unit; a soft-programming circuit for applying a soft-program voltage to all memory cells of the NAND cell unit, the soft-program voltage being of a polarity opposite to the polarity of the erase voltage; and a programming circuit for applying a program voltage to any selected one of the memory cells, applying a first voltage to at least one of two memory cells adjacent to the any selected one of the memory cells, and applying a second voltage to the remaining memory cells of the NAND cell unit, thereby to program data into the any selected one of the memory cells.

(2) According to a second aspect of the present invention, there is provided a memory device according to the first aspect, in which the programming circuit for applying the first voltage to both of the two memory cells adjacent to the any selected one of the memory cells.

(3) According to a third aspect of the present invention, there is provided a memory device according to the first aspect, in which the soft-programming circuit applies the soft-program voltage to all the memory cells after the erasing circuit has erased data from all memory cells of the NAND cell unit, and the programming circuit programs the memory cells after the soft-programming circuit has applied the soft-program voltage to all the memory cells.

(4) According to a fourth aspect of the present invention, there is provided a memory device according to the first aspect, in which the soft-program voltage is lower than the program voltage.

(5) According to a fifth aspect of the present invention, there is provided a memory device according to the first aspect, which further comprises an erase-verification circuit for determining whether data has been erased from all the memory cells of the NAND cell unit and have threshold voltages controlled within a predetermined range after the soft-programming circuit has applied the soft-program voltage to all the memory cells, and in which the programming circuit programs data into the any selected one of the memory cells after the soft-programming circuit and the erase-verification circuit have performed a soft-program operation and an erase verification operation.

(6) According to a sixth aspect of the present invention, there is provided a memory device according to the fifth aspect, further comprising a control circuit for causing the soft-programming circuit and the erase-verification circuit to repeat the soft-program operation and the erase verification operation, and for causing the soft-programming circuit to terminate the soft-program operation when at least one of the memory cells of the NAND cell unit has a threshold voltage forced out of the predetermined range.

(7) According to a seventh aspect of the present invention, there is provided a memory device according to the sixth aspect, in which the control circuit causes the erasing circuit to erase data again from all memory cells of the NAND cell unit when the soft-program operation and the erase verification operation have not repeated a predetermined number of times and when at least one of the memory cells of the NAND cell unit is forced out of the predetermined range.

(8) According to an eighth aspect of the present invention, there is provided a memory device according to the first aspect, in which the program voltage is higher than the first and second voltages, and the second voltage is higher than the first voltage.

(9) According to a ninth aspect of the present invention, there is provided a memory device according to the eighth aspect, in which the first voltage is 0V.

(10) According to a tenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and a data-programming circuit for performing a program operation in which program pulses are applied to the plurality of nonvolatile semiconductor memory cells to program n-value data into the plurality of nonvolatile semiconductor memory cells, performing a program verification operation in which it is determined whether or not the n-value data has been programmed into the plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of the program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into corresponding memory cell.

(11) According to an eleventh aspect of the present invention, there is provided a memory device according to the tenth aspect, in which each program pulse is removed from corresponding memory cell after the program verification operation in which it has been determined that n-value data has been programmed into the corresponding memory cell.

(12) According to a twelfth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the program operation is terminated when it is determined in the program verification operation that all of n-value data have been programmed into the plurality of nonvolatile semiconductor memory cells.

(13) According to a thirteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the program operation and the program verification operation are terminated after a limited number of cycles.

(14) According to a fourteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the plurality of nonvolatile semiconductor memory cells are connected to one word line.

(15) According to a fifteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the plurality of memory cells are respectively included in corresponding NAND cell units, each NAND cell unit comprising a predetermined number of nonvolatile semiconductor memory cells connected in series, and in the program operation, the data-programming circuit applies a first voltage to at least one of the two memory cells adjacent to the selected memory cells to be programmed and a second voltage to the remaining memory cells.

(16) According to a sixteenth aspect of the present invention, there is provided a memory device according to the fifteenth aspect, in which voltages of the program pulses are higher than the first and second voltages, and the second voltage is higher than the first voltage.

(17) According to a seventeenth aspect of the present invention, there is provided a memory device according to the sixteenth aspect, in which the first voltage is 0V.

(18) According to an eighteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array comprising memory cells arranged in rows and columns, each having a control gate; a programming circuit for programming data into any selected one of the memory cells by applying a program voltage to the control gate of the selected memory cell; an erasing circuit for erasing data from the memory cells by applying an erase voltage opposite in polarity to the program voltage; a soft-programming circuit for applying a soft-program voltage to the memory cells, thereby setting the memory cells into a desirable erased state; a verification read circuit for determining whether the memory cells have been set into the desirable erased state; and an erased-state determining circuit for causing the soft-programming circuit to terminate the soft-program operation upon determining from an output of the verification read circuit that at least two of the memory cells have a threshold voltage which has reached a predetermined value.

(19) According to a nineteenth aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the soft-programming circuit soft-programs the memory cells after the erasing circuit has erased data from the memory cells, and the verification read circuit performs a determination operation after the soft-programming circuit has soft-programmed the memory cells.

(20) According to a twentieth aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the memory cell array includes a plurality of data input/output lines divided into m units (m.gtoreq.2), and the erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the data input/output lines of each unit and causing the soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the data input/output lines of any unit has a threshold voltage which has reached the predetermined value.

(21) According to a twenty-first aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the memory cell array includes a plurality of word lines divided into m units (m.gtoreq.2), and the erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the word lines of each unit and causing the soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the word lines of any unit has a threshold voltage which has reached the predetermined value.

(22) According to a twenty-second aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the nonvolatile semiconductor memory cells of the memory cell array form NAND cell units, each comprising a plurality of memory cells connected in series, and the programming circuit applies a first voltage lower than the program voltage to the control gate of at least one of two memory cells adjacent to any selected one of the memory cells of each NAND cell unit, and applies a second voltage between the program voltage and the first voltage, to the remaining memory cells of each NAND cell unit, thereby to program data into the any selected one of the memory cells.

(23) According to a twenty-third aspect of the present invention, there is provided a memory device according to the twenty-second aspect, which further comprises a memory circuit for storing data output from the verification read circuit, and in which the erased-state determining circuit comprises a scan-detection circuit for monitoring the data stored in the memory circuit and counting the memory cells which have a threshold voltage which has reached the predetermined value.

(24) According to a twenty-fourth aspect of the present invention, there is provided a memory device according to the twenty-third aspect, further comprising a control circuit for repeatedly causing the soft-programming circuit to perform a soft-program operation, the verification read circuit to perform a verification read operation and the scan-detection circuit to perform a memory-cell counting operation, and for causing the soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation when the scan-detection circuit counts at least two memory cells having a threshold voltage which has reached the predetermined value.

(25) According to a twenty-fifth aspect of the present invention, there is provided a memory device according to the twenty-fourth aspect, in which the control circuit causes the verification read circuit to perform the verification read operation by applying a margin voltage to the word line of each NAND cell unit after the soft-programming circuit has finished performing the soft-program operation, causes the scan-detection circuit to perform the memory-cell counting operation, and causes the soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation, when the scan-detection circuit detects that all memory cells of each NAND cell unit have a threshold voltage equal to or lower than a predetermined threshold voltage, the predetermined threshold voltage being higher than the predetermined value.

(26) According to a twenty-sixth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell section including at least one memory cell and having first and second ends; a first signal line connected to the first end of the memory cell section; a second signal line connected to the second end of the memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; and an over-erase detecting circuit for detecting whether the memory cell is over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line, and the reading circuit detects the first read potential.

(27) According to a twenty-seventh aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, further comprising a soft-programming circuit for performing soft-program operation on the memory cell when the over-erase detecting circuit detects that the memory cell has been over-erased.

(28) According to a twenty-eighth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a first memory cell section including at least one memory cell; a second memory cell section including at least one memory cell; a first signal line connected to a first end of the first memory cell section; a second signal line connected to a second end of the first memory cell section; a third signal line connected to a first end of the second memory cell section; a fourth signal line connected to a second end of the second memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; and an over-erase detecting circuit for detecting whether the memory cell is over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line and applying a second reference potential to the third signal line, and the reading circuit detects the first read potential.

(29) According to a twenty-ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a first memory cell section including at least one memory cell; a second memory cell section including at least one memory cell; a first signal line connected to a first end of the first memory cell section; a second signal line connected to a second end of the first memory cell section; a third signal line connected to a first end of the second memory cell section; a fourth signal line connected to a second end of the second memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; an over-erase detecting circuit for detecting whether the memory cell is over-erased; and a soft-programming circuit for performing a soft-program operation on the memory cell when the over-erase detecting circuit detects that the memory cell has been over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line and applying a second reference potential to the third signal line, and the reading circuit detects the first read potential.

(30) According to a thirtieth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node, and a capacitor connected at one end to the first node and at the other end to the second node, and the potential applied to the second node is changed when the sense amplifier detects the potential of the first node.

(31) According to a thirty-first aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node, and a capacitor connected at one end to the first node and at the other end to the second node, the potential applied to the second node is changed when the sense amplifier detects the potential of the first node, the over-erase detecting circuit applies the first reference potential to the second signal line to detect whether the memory cell has been over-erased, the first read potential output to the first signal line is transferred through the first switch to the first node as a second read potential, and the potential of the first node is changed to a third read potential different from the second read potential, by changing potential of the second node.

(32) According to a thirty-second aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first and third lines are bit lines.

(33) According to a thirty-third aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first line is a bit line, and the third line is a bit line adjacent to the first line.

(34) According to a thirty-fourth aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the second and fourth lines are source lines.

(35) According to a thirty-fifth aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first and second reference potentials are of approximately the same value.

(36) According to a thirty-sixth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the first reference potential is a power-supply voltage.

(37) According to a thirty-seventh aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the memory cell section includes a NAND cell unit comprising a plurality of memory cells connected in series.

(38) According to a thirty-eighth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which when the over-erase detecting circuit applies the first reference potential to the second signal line, a first over-erase detection word-line potential is applied to the gate of any selected memory cell and a second over-erase detection word-line potential is applied to the gates of the memory cells connected in series to the any selected memory cell, thereby the first read potential is output to the first signal line.

(39) According to a thirty-ninth aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the first and second over-erase detection word-line potentials are of approximately the same value.

(40) According to a fortieth aspect of the present invention, there is provided a memory device according to the thirty-eight aspect, in which the first and second over-erase detection word-line potentials are of different values.

(41) According to a forty-first aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the first over-erase detection word-line potential is 0V.

(42) According to a forty-second aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the second over-erase detection word-line potential is a power-supply voltage.

(43) According to a forty-third aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell section including a NAND cell unit comprising a plurality of memory cells connected in series; an erasing circuit for erasing data stored in the memory cells; and an over-erase detecting circuit for detecting whether the memory cells are over-erased.

(44) According to a forty-fourth aspect of the present invention, there is provided a memory device according to the forty-third aspect, further comprising a soft-programming circuit for performing a soft-program operation on any one of the memory cells that has been over-erased.

(45) According to a forty-fifth aspect of the present invention, there is provided a memory device according to the forty-third aspect, which further comprises a first signal line connected to one end of the NAND cell unit, a second signal line connected to the other end of the NAND cell unit, and a reading circuit connected to the first signal line, for reading the memory cells, and in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node and a capacitor connected at one end to the first node and at the other end to the second node, and the second node is changed, when the sense amplifier detects the potential of the first node.

(46) According to a forty-sixth aspect of the present invention, there is provided a memory device according to the forty-fifth aspect, further comprising a transistor which includes a gate connected to an output terminal of the sense amplifier and which detects that the second sense amplifier stores the data that has been erased from one of the memory cells.

(47) According to a forty-seventh aspect of the present invention, there is provided a memory device comprising a first signal line connected to one end of a unit of memory cells; a second signal line connected to the other end of the unit of memory cells; and a reading circuit connected to the first signal line, for reading the memory cells, and wherein the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node and a capacitor connected at one end to the first node and at the other end to the second node, and the second node is changed, when the sense amplifier detects the potential of the first node.

(48) According to a forty-eighth aspect of the present invention, there is provided a memory device according to the forty-seventh aspect, in which a potential of the second signal line is set to a potential higher than a potential of the first signal line during a reading operation.

(49) According to a forty-ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory system comprising an electrically programmable nonvolatile semiconductor memory device; and a controller for controlling the nonvolatile semiconductor memory device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.

(50) According to a fiftieth aspect of the present invention, there is provided a memory system according to the forty-ninth aspect, in which the nonvolatile semiconductor memory device comprises a multi-value memory device.

(51) According to a fifty-first aspect of the present invention, there is provided a memory system according to the forty-ninth aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.

(52) According to a fifty-second aspect of the present invention, there is provided a memory system comprising an electrically programmable nonvolatile semiconductor memory device; a controller for controlling the nonvolatile semiconductor memory; a battery for supplying power to the controller when external power supplies are unavailable; and a terminal for receiving and supplying signals and power from and to an external device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.

(53) According to a fifty-third aspect of the present invention, there is provided a memory system comprising an electrically programmable nonvolatile semiconductor memory device; a controller for controlling the nonvolatile semiconductor memory device; a battery for supplying power to the controller when external power supplies are unavailable; a timer for storing data representing a time when data is programmed into the nonvolatile semiconductor memory; a terminal for receiving and supplying signals and power from and to an external device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.

(54) According to a fifty-fourth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the nonvolatile semiconductor memory device comprises a multi-value memory device.

(55) According to a fifty-fifth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.

(56) According to a fifty-sixth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, further comprising an indicator for indicating that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device, when the controller determines that the predetermined time has elapsed.

(57) According to a fifty-seventh aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the battery is a chargeable one and is charged while power is supplied from an external power supply.

(58) According to a fifty-eighth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller stops supply of power to the nonvolatile semiconductor memory device while no power is being supplied from an external power supply.

(59) According to a fifty-ninth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device, and stops supply of power to the nonvolatile semiconductor memory device while no power is being supplied from an external power supply and while the controller is not refreshing the data.

Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.

The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which:

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing the memory cell array and data memories according to the first embodiment;

FIGS. 3A and 3B are diagrams showing a memory cell and a selection transistor according to the first embodiment;

FIG. 4 is a sectional view illustrating a NAND-type cell unit according to the first embodiment;

FIG. 5 is a circuit diagram of the data memory shown in FIG. 2;

FIG. 6 is a circuit diagram of the clocked inverter shown in FIG. 5;

FIG. 7 is a circuit diagram of the word line controller shown in FIG. 1;

FIG. 8 is a timing chart explaining the read operation in the first embodiment;

FIG. 9 is a timing chart explaining how the word line controller operates during the read operation in the first embodiment;

FIG. 10 is a timing chart explaining the program operation in the first embodiment;

FIG. 11 is a timing chart explaining how the word line controller operates during the program operation in the first embodiment;

FIG. 12 is a timing chart explaining how program verification is achieved in the first embodiment;

FIG. 13 is a timing chart explaining how the word line controller operates during the program verification operation in the first embodiment;

FIG. 14 is a flow chart representing the programming algorithm in the first embodiment;

FIG. 15 is a timing chart explaining the erase operation in the first embodiment;

FIG. 16 is a timing chart explaining the soft-program operation in the first embodiment;

FIG. 17 is a timing chart explaining how erase verification is achieved in the first embodiment;

FIG. 18 is a timing chart explaining how the word line controller operates during the erase verification operation in the first embodiment;

FIG. 19 is a flow chart representing the erase algorithm in the first embodiment;

FIG. 20 is a b