Optimized cache structure for multi-texturing Number:7,069,387 from the United States Patent and Trademark Office (PTO) owispatent

Title: Optimized cache structure for multi-texturing

Abstract: A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.

Patent Number: 7,069,387 Issued on 06/27/2006 to Emberling

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Inventors:	Emberling; Brian D. (San Mateo, CA)
Assignee:	Sun Microsystems, Inc. (Santa Clara, CA)
Appl. No.:	403515
Filed:	March 31, 2003

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Current U.S. Class:	711/129 ; 345/535; 345/582; 711/158; 711/3
Current International Class:	G06F 12/00 (20060101)
Field of Search:	711/122,106,137,3 345/535,536

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References Cited [Referenced By]

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U.S. Patent Documents

	6629188		September 2003		Minkin et al.
	6636227		October 2003		Rivard et al.
	6750872		June 2004		Hong et al.
	2003/0063092		April 2003		Margittai et al.
	2003/0177320		September 2003		Sah et al.

Other References

m38316420at0 512 mb ddr sdram modlue data sheet, Samsung Apr. 2000. cited by examiner.

Primary Examiner: Padmanabhan; Mano
Assistant Examiner: Doan; Duc T
Attorney, Agent or Firm: Meyertons Hood Kivlin Kowert & Goetzel, P.C. Hood; Jeffrey C.

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Claims

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I claim:

1. A graphics system comprising: a texture memory operable to store a plurality of texture maps; and a texture cache memory coupled to the texture memory; wherein the texture cache memory is operable to store selected portions of one or more of the texture maps; wherein for each primitive, there are one or more active texture layers corresponding to active texture maps in the texture memory; wherein the texture cache memory is operable to be divided into a commensurate number of cache partitions for each primitive during system operations; and wherein each cache partition corresponds to a respective one of the one or more active texture maps.

2. The graphics system of claim 1, wherein each cache partition is operable to function as a direct mapped cache for its corresponding active texture map.

3. The graphics system of claim 1, wherein each cache partition is operable to function as an associative cache for the texture data comprised in the cache partition's corresponding active texture map.

4. The graphics system of claim 1, wherein the texture cache memory comprises a plurality of cache tags; wherein each cache tag comprises a reference to one of the plurality of cache partitions; and wherein each cache tag further comprises a reference indicating the active texture map corresponding to the partition.

5. The graphics system of claim 1, wherein the graphics system is operable to process pixels or samples corresponding to the primitive for each of the active texture layers for the primitive.

6. The graphics system of claim 1, wherein each active texture map corresponds to a different active layer of texture and each partition of the texture cache memory stores texels from a different active texture map.

7. The graphics system of claim 1, wherein a plurality of layers of texture are applied to a pixel or a sample by blending texel values determined for each layer, and wherein texel values for each layer are determined from a set of texels read from a corresponding partition of the texture cache memory.

8. The graphics system of claim 1, wherein each partition is allocated a dynamically variable portion of the texture cache memory.

9. The graphics system of claim 1, wherein the number of partitions equals the number of active texture layers.

10. A method, the method comprising: storing a plurality of texture maps in a texture memory; identifying for each primitive one or more active texture layers; and dividing a texture cache memory into a number of cache partitions commensurate with the number of active texture layers; wherein each partition is associated with a different one of the one or more active texture layers; and wherein each partition of the texture cache memory is used to store texels from a corresponding active texture map in the texture memory.

11. The method of claim 10, wherein each cache partition operates as a direct mapped cache for its corresponding active texture map.

12. The method of claim 10, further comprising: operating each cache partition as an associative cache for the texture data comprised in the cache partition's corresponding active texture map.

13. The method of claim 10, wherein the texture cache memory comprises a plurality of cache tags; and wherein each cache tag identifires the texture data in the corresponding cache partition.

14. The method off claim 13, further comprising updating each cache tag for each new primitive to identify the texture data in the corresponding cache partition.

15. The method of claim 10, wherein the number of partitions equals the number of active texture layers.

16. The method of claim 10, wherein each partition is allocated a dynamically variable portion of the texture cache memory.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the field of memory interface design and, more particularly, to cache design in a graphics system

2. Description of the Related Art

A computer system typically relies upon its graphics system for producing visual output on the computer screen or display device. Early graphics systems were only responsible for taking what the processor produced as output and displaying that output on the screen. In essence, they acted as simple translators or interfaces. Modern graphics systems, however, incorporate graphics processors with a great deal of processing power. They now act more like coprocessors rather than simple translators. This change is due to the recent increase in both the complexity and amount of data being sent to the display device. For example, modern computer displays have many more pixels, greater color depth, and are able to display images that are more complex with higher refresh rates than earlier models. Similarly, the images displayed are now more complex and may involve advanced techniques such as anti-aliasing and texture mapping.

Since graphics systems typically perform only a limited set of functions, they may be customized and therefore far more efficient at graphics operations than the computer's general-purpose central processor. While early graphics systems were limited to performing two-dimensional (2D) graphics, their functionality has increased to support three-dimensional (3D) wire-frame graphics, 3D solids, and now includes support for three-dimensional (3D) graphics with textures and special effects such as advanced shading, fogging, alpha-blending, and specular highlighting.

With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. One example of a memory sub-system defining the upper limit of overall system performance may be the texture buffer of a graphics system. Certain graphics applications such as 3D modeling, virtual reality viewers, and video games may call for the application of an image to a geometric primitive in lieu of a procedurally generated pattern, gradient or solid color. In these applications, geometric primitives carry additional mapping data (e.g., a UV, or UVQ map), which describes how the non-procedural data is to be applied to the primitive. To implement this type of function, a graphics system may employ a texture buffer to store two dimensional image data representative of texture patterns, "environment" maps, "bump" maps, and other types of non-procedural data.

During the rendering process, the mapping data associated with a primitive may be used to interpolate texture map addresses for each pixel in the primitive. The texture map addresses may then be used to retrieve the portion of non-procedural image data in the texture buffer to be applied to the primitive. In some cases (e.g., photo-realistic rendering) a fetch from the texture buffer may result in a neighborhood or tile of texture pixels or texels to be retrieved from the texture buffer and spatially filtered to produce a single texel. In these cases, four or more texels may be retrieved for each displayed pixel, placing a high level of demand on the texture buffer. Thus, poor performance of the texture buffer is capable of affecting a cascading degradation through the graphics system, stalling the render pipeline, and increasing the render or refresh times of displayed images.

In other words, accesses of graphics data, such as texture map data, must be performed very quickly. Therefore, one goal of a graphics system is to improve the speed and efficiency of memory accesses of texture maps from a texture memory. One common method is to use a texture memory cache to improve the speed of accesses of texture maps from the texture memory. The design of texture memory systems, including texture cache memory systems, plays a significant role in the implementation of new generation graphics systems.

Often, one texture memory cache is used to store multiple texture maps. Typically during multitexturing--that is, when applying more than one texture map to an object--many different areas of memory are being accessed in rapid succession. The resulting stream of widely varying addresses may cause the texture memory cache to thrash, unless it is a fully associative cache, which is generally very expensive to implement. In other words, if different texture maps reside in different areas of a single unified texture memory cache (direct-mapped or partially associative), then two texture maps may be assigned to the same cache line. Every time the two texture maps are accessed in succession, one after the other, the cache line will have to be flushed and reloaded, which is very inefficient and degrades the overall performance of the graphics system. Another possible solution in addition of a fully associative cache, which as mentioned above is generally very expensive to implement, is to permanently divide the cache into a set number of partitions. This would however be impractical, as it would degrade performance of the cache during non-multitexturing operations.

Therefore, new texture cache memory systems and methods are desired to improve texture access performance. More generally, improved cache memory systems are desired in various different applications, including graphics applications.

SUMMARY

One embodiment of the present invention comprises a method for optimizing a cache memory used for multitexturing in a graphics system. An exemplary graphics system may comprise the cache memory coupled to a system memory. One or more requesters may be coupled to the cache memory. In one embodiment, the system memory is a texture memory and the cache memory is a texture cache.

The method may comprise storing texture maps in the texture memory, where each texture map may comprise a set of texture data. When processing a primitive, such as a triangle, all texture maps associated with the primitive may be identified as active texture maps, and the texture cache may be divided into a number of partitions equaling the number of identified active texture maps. In one embodiment, each texture cache partition corresponds to a respective single active texture map, and is operated as a direct-mapped cache for the respective single active texture map. Each texture cache partition may also be operated as an associative cache for the set of texture data comprised in the texture cache partition's corresponding respective single active texture map. In one embodiment, the texture cache memory includes a set of texture cache tags, with each texture cache tag referencing one of the texture cache partitions. Each texture cache tag may be updated, after the texture cache has been divided into partitions, to include a respective partition reference indicating which respective single active texture map corresponds to which texture cache partition.

By operating the texture cache as described above, a need for a fully associative texture cache to avoid thrashing may be averted. Instead, thrashing may be minimized through isolating the texture maps from each other by allocating a single texture cache partition to a single texture map. In other words, a single texture cache partition may operate as a direct-mapped cache corresponding to a single texture map. At the same time, the single texture cache partition may be used as an associative cache for caching texture data corresponding to the single texture map. The texture cache may be dynamically reconfigured for each primitive that accesses a particular set of texture maps. Furthermore, no cache storage is wasted as texture cache partitions may only be reserved for active texture maps.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

FIG. 1 illustrates one set of embodiments of a graphics accelerator configured to perform graphical computations;

FIG. 2 illustrates one set of embodiments of a parallel rendering engine;

FIG. 3 illustrates an array of spatial bins each populated with a set of sample positions in a two-dimension virtual screen space;

FIG. 4 illustrates one set of embodiments of a rendering methodology which may be used to generate samples in response to received stream of graphics data;

FIG. 5 illustrates a set of candidate bins which intersect a particular triangle;

FIG. 6 illustrates the identification of sample positions in the candidate bins which fall interior to the triangle;

FIG. 7 illustrates the computation of a red sample component based on a spatial interpolation of the red components at the vertices of the containing triangle;

FIG. 8 illustrates an array of virtual pixel positions distributed in the virtual screen space and superimposed on top of the array of spatial bins;

FIG. 9 illustrates the computation of a pixel at a virtual pixel position (denoted by the plus marker) according to one set of embodiments;

FIG. 10 illustrates a set of columns in the spatial bin array, wherein the K.sup.th column defines the subset of memory bins (from the sample buffer) which are used by a corresponding filtering unit FU(K) of the filtering engine;

FIG. 11 illustrates one set of embodiments of filtering engine 600;

FIG. 12 illustrates one embodiment of a computation of pixels at successive filter center (i.e. virtual pixel centers) across a bin column;

FIG. 13 illustrates one set of embodiments of a rendering pipeline comprising a media processor and a rendering unit;

FIG. 14 illustrates one embodiment of graphics accelerator 100; and

FIG. 15 illustrates another embodiment of graphics accelerator 100.

FIG. 16 illustrates a conceptual diagram of the operation of a texture mapping pipeline according to one embodiment of the invention;

FIG. 17 illustrates a more detailed diagram of one embodiment of the texture mapping pipeline of FIG. 16, emphasizing the texture cache memory;

FIG. 18 illustrates an exemplary primitive and associated samples, demonstrating the concepts of texel reuse and cache size;

FIG. 19 illustrates in more detail a cache memory structure for the texture mapping pipeline of FIG. 17, implemented in accordance with one set of embodiments of the current invention;

FIG. 20 illustrates a flowchart of a method for operating a cache memory, implemented in accordance with one set of embodiments of the current invention;

FIG. 21 illustrates part of a method for cache-miss prediction and merging with burst reads from memory, implemented in accordance with one set of embodiments of the current invention; and

FIG. 22 illustrates part of a method for cache optimization during multitexturing, implemented in accordance with one set of embodiments of the current invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. Note, the headings are for organizational purposes only and are not meant to be used to limit or interpret the description or claims. Furthermore, note that the word "may" is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not a mandatory sense (i.e., must)." The term "include", and derivations thereof, mean "including, but not limited to". The term "connected" means "directly or indirectly connected", and the term "coupled" means "directly or indirectly connected".

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As used herein, "burst length" is used to refer to a number that indicates how many consecutive data bus transfers may be performed in response to a single bus transfer request sent by a host system. For example, if a burst length is four and a memory read operation is performed, there may be four consecutive sets of data transferred on the data bus in response to a single read signal pulse sent by a host system. The size of a set of data for a single transfer over a data bus is typically commensurate with the size of the data bus. Common burst lengths for a DDR SDRAM may include the values of two, four or eight.

According to prior art, a read operation for a DDR SDRAM may be performed as follows. A DDR SDRAM may receive a Read request through a set of control signals from a requester. A predetermined number of clock cycles after having received the Read request, the DDR SDRAM sends a predetermined number of consecutive strobe signal (DQS) pulses back to the host system. The predetermined number of clock cycles may be referred to as "CAS latency", where CAS stands for "Column Address Strobe". The number of consecutive DQS pulses may be commensurate with one half the value of a predetermined burst length for the read operation. The DDR SDRAM also sends a predetermined number of sets of data to the requestor, where the number may be commensurate with the value of the predetermined burst length for the read operation.

FIG. 1 illustrates one set of embodiments of a graphics accelerator 100 configured to perform graphics computations (especially 3D graphics computations). Graphics accelerator 100 may include a control unit 200, a rendering engine 300, a scheduling network 400, a sample buffer 500, a lower route network 550, and a filtering engine 600.

The rendering engine 300 may include a set of N.sub.PL rendering pipelines as suggested by FIG. 2, where N.sub.PL is a positive integer. The rendering pipelines, denoted as RP(0) through RP (N.sub.PL-1), are configured to operate in parallel. For example, in one embodiment, N.sub.PL equals four. In another embodiment, N.sub.PL=8.

The control unit 200 receives a stream of graphics data from an external source (e.g. from the system memory of a host computer), and controls the distribution of the graphics data to the rendering pipelines. The control unit 200 may divide the graphics data stream into N.sub.PL substreams, which flow to the N.sub.PL rendering pipelines respectively. The control unit 200 may implement an automatic load-balancing scheme so the host application need not concern itself with load balancing among the multiple rendering pipelines.

The stream of graphics data received by the control unit 200 may correspond to a frame of a 3D animation. The frame may include a number of 3D objects. Each object may be described by a set of primitives such as polygons (e.g. triangles), lines, polylines, dots, etc. Thus, the graphics data stream may contain information defining a set of primitives.

Polygons are naturally described in terms of their vertices. Thus, the graphics data stream may include a stream of vertex instructions. A vertex instruction may specify a position vector (X,Y,Z) for a vertex. The vertex instruction may also include one or more of a color vector, a normal vector and a vector of texture coordinates. The vertex instructions may also include connectivity information, which allows the rendering engine 300 to assemble the vertices into polygons (e.g. triangles).

Each rendering pipeline RP(K) of the rendering engine 300 may receive a corresponding stream of graphics data from the control unit 200, and performs rendering computations on the primitives defined by the graphics data stream. The rendering computations generate samples, which are written into sample buffer 500 through the scheduling network 400.

The filtering engine 600 is configured to read samples from the sample buffer 500, to perform a filtering operation on the samples resulting in the generation of a video pixel stream, and, to convert the video pixel stream into an analog video signal. The analog video signal may be supplied to one or more video output ports for display on one or more display devices (such as computer monitors, projectors, head-mounted displays and televisions).

Furthermore, the graphics system 100 may be configured to generate up to N.sub.D independent video pixel streams denoted VPS(0), VPS(1), . . . , VPS(N.sub.D-1), where N.sub.D is a positive integer. Thus, a set of host applications (running on a host computer) may send N.sub.D graphics data streams denoted GDS(0), GDS(1), . . . , GDS(N.sub.D-1) to the graphics system 100. The rendering engine 300 may perform rendering computations on each graphics data stream GDS(I), for I=0, 1, 2, . . . , N.sub.D-1, resulting in sample updates to a corresponding region SBR(I) of the sample buffer 500. The filtering engine 600 may operate on the samples from each sample buffer region SBR(I) to generate the corresponding video pixel stream VPS(I). The filtering engine 600 may convert each video pixel stream VPS(I) into a corresponding analog video signal AVS(I). The N.sub.D analog video signals may be supplied to a set of video output ports for display on a corresponding set of display devices. In one embodiment, N.sub.D equals two. In another embodiment, N.sub.D equals four.

The filtering engine 600 may send sample data requests to the scheduling network 400 through a request bus 650. In response to the sample data requests, scheduling network 400 may assert control signals, which invoke the transfer of the requested samples (or groups of samples) to the filtering engine 600.

In various embodiments, the sample buffer 500 includes a plurality of memory units, and the filtering engine 600 includes a plurality of filtering units. The filtering units interface may interface with the lower router network 550 to provide data select signals. The lower route network 550 may use the data select signals to steer data from the memory units to the filtering units.

The control unit 200 may couple to the filtering engine 600 through a communication bus 700, which includes an outgoing segment 700A and a return segment 700B. The outgoing segment 700A may be used to download parameters (e.g. lookup table values) to the filtering engine 600. The return segment 700B may be used as a readback path for the video pixels generated by filtering engine 600. Video pixels transferred to control unit 200 through the return segment 700B may be forwarded to system memory (i.e. the system memory of a host computer), or perhaps, to memory (e.g. texture memory) residing on graphics system 100 or on another graphics accelerator.

The control unit 200 may include direct memory access (DMA) circuitry. The DMA circuitry may be used to facilitate (a) the transfer of graphics data from system memory to the control unit 200, and/or, (b) the transfer of video pixels (received from the filtering engine 600 through the return segment 700B) to any of various destinations (such as the system memory of the host computer).

The rendering pipelines of the rendering engine 300 may compute samples for the primitives defined by the received graphics data stream(s). The computation of samples may be organized according to an array of spatial bins as suggested by FIG. 3. The array of spatial bins defines a rectangular window in a virtual screen space. The spatial bin array may have dimension M.sub.B.times.N.sub.B, i.e., may comprise M.sub.B bins horizontally and N.sub.B bins vertically.

Each spatial bin may be populated with a number of sample positions. Sample positions are denoted as small circles. Each sample position may be defined by a horizontal offset and a vertical offset with respect to the origin of the bin in which it resides. The origin of a bin may be at its top-left comer. Note that any of a variety of other positions on the boundary or in the interior of a bin may serve as its origin. A sample may be computed at each of the sample positions. A sample may include a color vector, and other values such as z depth and transparency (i.e. an alpha value).

The sample buffer 500 may organize the storage of samples according to memory bins. Each memory bin corresponds to one of the spatial bins, and stores the samples for the sample positions in a corresponding spatial bin.

If a rendering pipeline RP(k) determines that a spatial bin intersects with a given primitive (e.g. triangle), the rendering pipeline may: (a) generate N.sub.s/b sample positions in the spatial bin; (b) determine which of the N.sub.s/b sample positions reside interior to the primitive; (c) compute a sample for each of the interior sample positions, and (d) forward the computed samples to the scheduling network 400 for transfer to the sample buffer 500. The computation of a sample at a given sample position may involve computing sample components such as red, green, blue, z, and alpha at the sample position. Each sample component may be computed based on a spatial interpolation of the corresponding components at the vertices of the primitive. For example, a sample's red component may be computed based on a spatial interpolation of the red components at the vertices of the primitive.

In addition, if the primitive is to be textured, one or more texture values may be computed for the intersecting bin. The final color components of a sample may be determined by combining the sample's interpolated color components and the one or more texture values.

Each rendering pipeline RP(K) may include dedicated circuitry for determining if a spatial bin intersects a given primitive, for performing steps (a), (b) and (c), for computing the one or more texture values, and for applying the one or more texture values to the samples.

Each rendering pipeline RP(K) may include programmable registers for the bin array size parameters M.sub.B and N.sub.B and the sample density parameter N.sub.s/b. In one embodiment, N.sub.s/b may take values in the range from 1 to 16 inclusive.

Sample Rendering Methodology

FIG. 4 illustrates one set of embodiments of a rendering process implemented by each rendering pipeline RP(K) of the N.sub.PL rendering pipelines.

In step 710, rendering pipeline RP(K) receives a stream of graphics data from the control unit 200 (e.g. stores the graphics data in an input buffer).

The graphics data may have been compressed according to any of a variety of data compression and/or geometry compression techniques. Thus, the rendering pipeline RP(K) may decompress the graphics data to recover a stream of vertices.

In step 720, the rendering pipeline RP(K) may perform a modeling transformation on the stream of vertices. The modeling transformation serves to inject objects into a world coordinate system. The modeling transformation may also include the transformation of any normal vectors associated with the stream vertices. The matrix used to perform the modeling transformation is dynamically programmable by host software.

In step 725, rendering engine 300 may subject the stream vertices to a lighting computation. Lighting intensity values (e.g. color intensity values) may be computed for the vertices of polygonal primitives based on one or more of the following: (1) the vertex normals; (2) the position and orientation of a virtual camera in the world coordinate system; (3) the intensity, position, orientation and type-classification of light sources; and (4) the material properties of the polygonal primitives such as their intrinsic color values, ambient, diffuse, and/or specular reflection coefficients. The vertex normals (or changes in normals from one vertex to the next) may be provided as part of the graphics data stream. The rendering pipeline RP(K) may implement any of a wide variety of lighting models. The position and orientation of the virtual camera are dynamically adjustable. Furthermore, the intensity, position, orientation and type-classification of light sources are dynamically adjustable.

It is noted that separate virtual camera positions may be maintained for the viewer's left and right eyes in order to support stereo video. For example, rendering pipeline RP(K) may alternate between the left camera position and the right camera position from one animation frame to the next.

In step 730, the rendering pipeline RP(K) may perform a camera transformation on the vertices of the primitive. The camera transformation may be interpreted as providing the coordinates of the vertices with respect to a camera coordinate system, which is rigidly bound to the virtual camera in the world space. Thus, the camera transformation may require updating whenever the camera position and/or orientation change. The virtual camera position and/or orientation may be controlled by user actions such as manipulations of an input device (such as a joystick, data glove, mouse, light pen, and/or keyboard). In some embodiments, the virtual camera position and/or orientation may be controlled based on measurements of a user's head position and/or orientation and/or eye orientation(s).

In step 735, the rendering pipeline RP(K) may perform a homogenous perspective transformation to map primitives from the camera coordinate system into a clipping space, which is more convenient for a subsequent clipping computation. In some embodiments, steps 730 and 735 may be combined into a single transformation.

In step 737, rendering pipeline RP(K) may assemble the vertices to form primitives such as triangles, lines, etc.

In step 740, rendering pipeline RP(K) may perform a clipping computation on each primitive. In clipping space, the vertices of primitives may be represented as 4-tuples (X,Y,Z,W). In some embodiments, the clipping computation may be implemented by performing a series of inequality tests as follows: T1=(-W.ltoreq.X) T2=(X.ltoreq.W) T3=(-W.ltoreq.Y) T4=(Y.ltoreq.W) T5=(-W.ltoreq.Z) T6=(Z.ltoreq.0) If all the test flags are true, a vertex resides inside the canonical view volume. If any of the test flags are false, the vertex is outside the canonical view volume. An edge between vertices A and B is inside the canonical view volume if both vertices are inside the canonical view volume. An edge can be trivially rejected if the expression Tk(A) OR Tk(B) is false for any k in the range from one to six. Otherwise, the edge requires testing to determine if it partially intersects the canonical view volume, and if so, to determine the points of intersection of the edge with the clipping planes. A primitive may thus be cut down to one or more interior sub-primitives (i.e. subprimitives that lie inside the canonical view volume). The rendering pipeline RP(K) may compute color intensity values for the new vertices generated by clipping.

Note that the example given above for performing the clipping computation is not meant to be limiting. Other methods may be used for performing the clipping computation.

In step 745, rendering pipeline RP(K) may perform a perspective divide computation on the homogenous post-clipping vertices (X,Y,Z,W) according to the relations x=X/W y=Y/W z=Z/W After the perspective divide, the x and y coordinates of each vertex (x,y,z) may reside in a viewport rectangle, for example, a viewport square defined by the inequalities -1.ltoreq.x.ltoreq.1 and -1.ltoreq.y.ltoreq.1.

In step 750, the rendering pipeline RP(K) may perform a render scale transformation on the post-clipping primitives. The render scale transformation may operate on the x and y coordinates of vertices, and may have the effect of mapping the viewport square in perspective-divided space onto (or into) the spatial bin array in virtual screen space, i.e., onto (or into) a rectangle whose width equals the array horizontal bin resolution M.sub.B and whose height equals the array vertical bin resolution N.sub.B. Let X.sub.v and Y.sub.v denote the horizontal and vertical coordinate respectively in the virtual screen space.

In step 755, the rendering pipeline RP(K) may identify spatial bins which geometrically intersect with the post-scaling primitive as suggested by FIG. 5. Bins in this subset are referred to as "candidate" bins or "intersecting" bins. It is noted that values M.sub.B=8 and N.sub.B=5 for the dimensions of the spatial bin array have been chosen for sake of illustration, and are much smaller than would typically be used in most applications of graphics system 100.

In step 760, the rendering pipeline RP(K) performs a "sample fill" operation on candidate bins identified in step 755 as suggested by FIG. 6. In the sample fill operation, the rendering pipeline RP(K) populates candidate bins with sample positions, identifies which of the sample positions reside interior to the primitive, and computes sample values (such as red, green, blue, z and alpha) at each of the interior sample positions. The rendering pipeline RP(K) may include a plurality of sample fill units to parallelize the sample fill computation. For example, two sample fill units may perform the sample fill operation in parallel on two candidate bins respectively. (This N=2 example generalizes to any number of parallel sample fill units). In FIG. 6, interior sample positions are denoted as small black dots, and exterior sample positions are denoted as small circles.

The rendering pipeline RP(K) may compute the color components (r,g,b) for each interior sample position in a candidate bin based on a spatial interpolation of the corresponding vertex color components as suggested by FIG. 7. FIG. 7 suggests a linear interpolation of a red intensity value r.sub.s for a sample position inside the triangle defined by the vertices V1, V2, and V3 in virtual screen space (i.e. the horizontal plane of the figure). The red color intensity is shown as the up-down coordinate. Each vertex Vk has a corresponding red intensity value r.sub.k. Similar interpolations may be performed to determine green, blue, z and alpha values.

In step 765, rendering pipeline RP(K) may compute a vector of texture values for each candidate bin. The rendering pipeline RP(K) may couple to a corresponding texture memory TM(K). The texture memory TM(K) may be used to store one or more layers of texture information. Rendering pipeline RP(K) may use texture coordinates associated with a candidate bin to read texels from the texture memory TM(K). The texels may be filtered to generate the vector of texture values. The rendering pipeline RP(K) may include a plurality of texture filtering units to parallelize the computation of texture values for one or more candidate bins.

The rendering pipeline RP(K) may include a sample fill pipeline which implements step 760 and a texture pipeline which implements step 765. The sample fill pipeline and the texture pipeline may be configured for parallel operation. The sample fill pipeline may perform the sample fill operations on one or more candidate bins while the texture fill pipeline computes the texture values for the one or more candidate bins.

In step 770, the rendering pipeline RP(K) may apply the one or more texture values corresponding to each candidate bin to the color vectors of the interior samples in the candidate bin. Any of a variety of methods may be used to apply the texture values to the sample color vectors.

In step 775, the rendering pipeline RP(K) may forward the computed samples to the scheduling network 400 for storage in the sample buffer 500.

The sample buffer 500 may be configured to support double-buffered operation. The sample buffer may be logically partitioned into two buffer segments A and B. The rendering engine 300 may write into buffer segment A while the filtering engine 600 reads from buffer segment B. At the end of a frame of animation, a host application (running on a host computer) may assert a buffer swap command. In response to the buffer swap command, control of buffer segment A may be transferred to the filtering engine 600, and control of buffer segment B may be transferred to rendering engine 300. Thus, the rendering engine 300 may start writing samples into buffer segment B, and the filtering engine 600 may start reading samples from buffer segment A.

It is noted that usage of the term "double-buffered" does not necessarily imply that all components of samples are double-buffered in the sample buffer 500. For example, sample color may be double-buffered while other components such as z depth may be single-buffered.

In some embodiments, the sample buffer 500 may be triple-buffered or N-fold buffered, where N is greater than two.

Filtration of Samples to Determine Pixels

Filtering engine 600 may access samples from a buffer segment (A or B) of the sample buffer 500, and generate video pixels from the samples. Each buffer segment of sample buffer 500 may be configured to store an M.sub.B.times.N.sub.B array of bins. Each bin may store N.sub.s/b samples. The values M.sub.B, N.sub.B and N.sub.s/b are programmable parameters.

As suggested by FIG. 8, filtering engine 600 may scan through virtual screen space in raster fashion generating virtual pixel positions denoted by the small plus markers, and generating a video pixel at each of the virtual pixel positions based on the samples (small circles) in the neighborhood of the virtual pixel position. The virtual pixel positions are also referred to herein as filter centers (or kernel centers) since the video pixels are computed by means of a filtering of samples. The virtual pixel positions form an array with horizontal displacement .DELTA.X between successive virtual pixel positions in a row and vertical displacement .DELTA.Y between successive rows. The first virtual pixel position in the first row is controlled by a start position (X.sub.start,Y.sub.start). The horizontal displacement .DELTA.X, vertical displacement .DELTA.Y and the start coordinates X.sub.start and Y.sub.start are programmable parameters.

FIG. 8 illustrates a virtual pixel position at the center of each bin. However, this arrangement of the virtual pixel positions (at the centers of render pixels) is a special case. More generally, the horizontal displacement .DELTA.x and vertical displacement .DELTA.y may be assigned values greater than or less than one. Furthermore, the start position (X.sub.start,Y.sub.start) is not constrained to lie at the center of a spatial bin. Thus, the vertical resolution N.sub.P of the array of virtual pixel centers may be different from N.sub.B, and the horizontal resolution M.sub.P of the array of virtual pixel centers may be different from M.sub.B.

The filtering engine 600 may compute a video pixel at a particular virtual pixel position as suggested by FIG. 9. The filtering engine 600 may compute the video pixel based on a filtration of the samples falling within a support region centered on (or defined by) the virtual pixel position. Each sample S falling within the support region may be assigned a filter coefficient C.sub.S based on the sample's position (or some function of the sample's radial distance) with respect to the virtual pixel position.

Each of the color components of the video pixel may be determined by computing a weighted sum of the corresponding sample color components for the samples falling inside the filter support region. For example, the filtering engine 600 may compute an initial red value r.sub.P for the video pixel P according to the expression r.sub.P=.SIGMA.C.sub.Sr.sub.S, where the summation ranges over each sample S in the filter support region, and where r.sub.S is the red sample value of the sample S. In other words, the filtering engine 600 may multiply the red component of each sample S in the filter support region by the corresponding filter coefficient C.sub.S, and add up the products. Similar weighted summations may be performed to determine an initial green value g.sub.P, an initial blue value b.sub.P, and optionally, an initial alpha value .alpha..sub.P for the video pixel P based on the corresponding components of the samples.

Furthermore, the filtering engine 600 may compute a normalization value E by adding up the filter coefficients C.sub.S for the samples S in the bin neighborhood, i.e., E=.SIGMA.C.sub.S. The initial pixel values may then be multiplied by the reciprocal of E (or equivalently, divided by E) to determine normalized pixel values: R.sub.P=(1/E)*r.sub.P G.sub.P=(1/E)*g.sub.P B.sub.P=(1/E)*b.sub.P A.sub.P=(1/E)*.alpha..sub.P.

In one set of embodiments, the filter coefficient C.sub.S for each sample S in the filter support region may be determined by a table lookup. For example, a radially symmetric filter may be realized by a filter coefficient table, which is addressed by a function of a sample's radial distance with respect to the virtual pixel center. The filter support for a radially symmetric filter may be a circular disk as suggested by the example of FIG. 9. The support of a filter is the region in virtual screen space on which the filter is defined. The terms "filter" and "kernel" are used as synonyms herein. Let R.sub.f denote the radius of the circular support disk.

The filtering engine 600 may examine each sample S in a neighborhood of bins containing the filter support region. The bin neighborhood may be a rectangle (or square) of bins. For example, in one embodiment the bin neighborhood is a 5.times.5 array of bins centered on the bin which contains the virtual pixel position.

The filtering engine 600 may compute the square radius (D.sub.S).sup.2 of each sample position (X.sub.S,Y.sub.S) in the bin neighborhood with respect to the virtual pixel position (X.sub.P,Y.sub.P) according to the expression (D.sub.S).sup.2=(X.sub.S-X.sub.P).sup.2+(Y.sub.S-Y.sub.P).sup.2. The square radius (D.sub.S).sup.2 may be compared to the square radius (R.sub.f).sup.2 of the filter support. If the sample's square radius is less than (or, in a different embodiment, less than or equal to) the filter's square radius, the sample S may be marked as being valid (i.e., inside the filter support). Otherwise, the sample S may be marked as invalid.

The filtering engine 600 may compute a normalized square radius U.sub.S for each valid sample S by multiplying the sample's square radius by the reciprocal of the filter's square radius:

.times. ##EQU00001## The normalized square radius U.sub.S may be used to access the filter coefficient table for the filter coefficient C.sub.S. The filter coefficient table may store filter weights indexed by the normalized square radius.

In various embodiments, the filter coefficient table is implemented in RAM and is programmable by host software. Thus, the filter function (i.e. the filter kernel) used in the filtering process may be changed as needed or desired. Similarly, the square radius (R.sub.f).sup.2 of the filter support and the reciprocal square radius 1/(R.sub.f).sup.2 of the filter support may be programmable.

Because the entries in the filter coefficient table are indexed according to normalized square distance, they need not be updated when the radius R.sub.f of the filter support changes. The filter coefficients and the filter radius may be modified independently.

In one embodiment, the filter coefficient table may be addressed with the sample radius D.sub.S at the expense of computing a square root of the square radius (D.sub.S).sup.2. In another embodiment, the square radius may be converted into a floating-point format, and the floating-point square radius may be used to address the filter coefficient table. It is noted that the filter coefficient table may be indexed by any of various radial distance measures. For example, an L.sup.1 norm or L.sup.infinity norm may be used to measure the distance between a sample position and the virtual pixel center.

Invalid samples may be assigned the value zero for their filter coefficients. Thus, the invalid samples end up making a null contribution to the pixel value summations. In other embodiments, filtering hardware internal to the filtering engine may be configured to ignore invalid samples. Thus, in these embodiments, it is not necessary to assign filter coefficients to the invalid samples.

In some embodiments, the filtering engine 600 may support multiple filtering modes. For example, in one collection of embodiments, the filtering engine 600 supports a box filtering mode as well as a radially symmetric filtering mode. In the box filtering mode, filtering engine 600 may implement a box filter over a rectangular support region, e.g., a square support region with radius R.sub.f (i.e. side length 2R.sub.f). Thus, the filtering engine 600 may compute boundary coordinates for the support square according to the expressions X.sub.P+R.sub.f, X.sub.P-R.sub.f, Y.sub.P+R.sub.f, and Y.sub.P-R.sub.f. Each sample S in the bin neighborhood may be marked as being valid if the sample's position (X.sub.S, Y.sub.S) falls within the support square, i.e., if X.sub.P-R.sub.f<X.sub.S<X.sub.P+R.sub.f and Y.sub.P-R.sub.f<Y.sub.S<Y.sub.P+R.sub.f. Otherwise the sample S may be marked as invalid. Each valid sample may be assigned the same filter weight value (e.g., C.sub.S=1). It is noted that any or all of the strict inequalities (<) in the system above may be replaced with permissive inequalities (.ltoreq.). Various embodiments along these lines are contemplated.

The filtering engine 600 may use any of a variety of filters either alone or in combination to compute pixel values from sample values. For example, the filtering engine 600 may use a box filter, a tent filter, a cone filter, a cylinder filter, a Gaussian filter, a Catmull-Rom filter, a Mitchell-Netravali filter, a windowed sinc filter, or in general, any form of band pass filter or any of various approximations to the sinc filter.

In one set of embodiments, the filtering engine 600 may include a set of filtering units FU(0), FU(1), FU(2), . . . , FU(N.sub.f-1) operating in parallel, where the number N.sub.f of filtering units is a positive integer. For example, in one embodiment, N.sub.f=4. In another embodiment, N.sub.f=8.

The filtering units may be configured to partition the effort of generating each frame (or field of video). A frame of video may comprise an M.sub.P.times.N.sub.P array of pixels, where M.sub.P denotes the number of pixels per line, and N.sub.P denotes the number of lines. Each filtering unit FU(K) may be configured to generate a corresponding subset of the pixels in the M.sub.P.times.N.sub.P pixel array. For example, in the N.sub.f=4 case, the pixel array may be partitioned into four vertical stripes, and each filtering unit FU(K), K=0, 1, 2, 3, may be configured to generate the pixels of the corresponding stripe.

Filtering unit FU(K) may include a system of digital circuits, which implement the processing loop suggested below. The values X.sub.start(K) and Y.sub.start(K) represent the start position for the first (e.g. top-left) virtual pixel center in the K.sup.th stripe of virtual pixel centers. The values .DELTA.X(K) and .DELTA.Y(K) represent respectively the horizontal and vertical step size between virtual pixel centers in the K.sup.th stripe. The value M.sub.H(K) represents the number of pixels horizontally in the K.sup.th stripe. For example, if there are four stripes (N.sub.f=4) with equal width, M.sub.H(K) may be set equal to M.sub.P/4 for K=0, 1, 2, 3. Filtering unit FU(K) may generate a stripe of pixels in a scan line fashion as follows:

TABLE-US-00001 I=0; J=0; X.sub.p=X.sub.start(K); Y.sub.p=Y.sub.start(K); while (J<N.sub.p) { while (I < M.sub.H(K) { PixelValues = Filtration(X.sub.p,Y.sub.p); Send PixelValues to Output Buffer; Xp = Xp+.DELTA.X(K) I = I + 1; } X.sub.p=X.sub.start(K) Y.sub.p=Y.sub.p+.DELTA.Y(K) J=J+1; }

The expression Filtration(X.sub.P, Y.sub.P) represents the filtration of samples in the filter support region of the current virtual pixel position (X.sub.P, Y.sub.P) to determine the components (e.g. RGB values, and optionally, an alpha value) of the current pixel as described above. Once computed, the pixel values may be sent to an output buffer for merging into a video stream. The inner loop generates successive virtual pixel positions within a single row of the stripe. The outer loop generates successive rows. The above fragment may be executed once per video frame (or field). Filtering unit FU(K) may include registers for programming the values X.sub.start(K), Y.sub.start(K), .DELTA.X(K), .DELTA.Y(K), and M.sub.H(K). These values are dynamically adjustable from host software. Thus, the graphics system 100 may be configured to support arbitrary video formats.

Each filtering unit FU(K) accesses a corresponding subset of bins from the sample buffer 500 to generate the pixels of the K.sup.th stripe. For example, each filtering unit FU(K) may access bins corresponding to a column COL(K) of the bin array in virtual screen space as suggested by FIG. 10. Each column may be a rectangular subarray of bins. Note that column COL(K) may overlap with adjacent columns. This is a result of using a filter function with filter support that covers more than one spatial bin. Thus, the amount of overlap between adjacent columns may depend on the radius of the filter support.

The filtering units may be coupled together in a linear succession as suggested by FIG. 11 in the case N.sub.f=4. Except for the first filtering unit FU(0) and the last filtering unit FU(N.sub.f-1), each filtering unit FU(K) may be configured to receive digital video input streams A.sub.K-1 and B.sub.K-1 from a previous filtering unit FU(K-1), and to transmit digital video output streams A.sub.K and B.sub.K to the next filtering unit FU(K+1). The first filtering unit FU(0) generates video streams A.sub.0 and B.sub.0 and transmits these streams to filtering unit FU(1). The last filtering unit FU(N.sub.f-1) receives digital video streams A.sub.Nf-2 and B.sub.Nf-2 from the previous filtering unit FU(N.sub.f-2), and generates digital video output streams A.sub.Nf-1 and B.sub.Nf-1 also referred to as video streams DV.sub.A and DV.sub.B respectively. Video streams A.sub.0, A.sub.1, . . . , A.sub.Nf-1 are said to belong to video stream A. Similarly, video streams B.sub.0, B.sub.1, . . . , B.sub.Nf-1 are said to belong to video stream B.

Each filtering unit FU(K) may be programmed to mix (or substitute) its computed pixel values into either video stream A or video stream B. For example, if the filtering unit FU(K) is assigned to video stream A, the filtering unit FU(K) may mix (or substitute) its computed pixel values into video stream A, and pass video stream B unmodified to the next filtering unit FU(K+1). In other words, the filtering unit FU(K) may mix (or replace) at least a subset of the dummy pixel values present in video stream A.sub.K-1 with its locally computed pixel values. The resultant video stream A.sub.K is transmitted to the next filtering unit. The first filtering unit FU(0) may generate video streams A.sub.-1, and B.sub.-1containing dummy pixels (e.g., pixels having a background color), and mix (or substitute) its computed pixel values into either video stream A.sub.-1, or B.sub.-1, and pass the resulting streams A.sub.0 and B.sub.0 to the filtering unit FU(1). Thus, the video streams A and B mature into complete video signals as they are operated on by the linear succession of filtering units.

The filtering unit FU(K) may also be configured with one or more of the following features: color look-up using pseudo color tables, direct color, inverse gamma correction, and conversion of pixels to non-linear light space. Other features may include programmable video timing generators, programmable pixel clock synthesizers, cursor generators, and crossbar functions.

While much of the present discussion has focused on the case where N.sub.f=4, it is noted that the inventive principles described in this special case naturally generalize to arbitrary values for the parameter N.sub.f (the number of filtering units).

In one set of embodiments, each filtering unit FU(K) may include (or couple to) a plurality of bin scanline memories (BSMs). Each bin scanline memory may contain sufficient capacity to store a horizontal line of bins within the corresponding column COL(K). For example, in some embodiments, filtering unit FU(K) may include six bin scanline memories as suggested by FIG. 12.

Filtering unit FU(K) may move the filter centers through the column COL(K) in a raster fashion, and generate a pixel at each filter center. The bin scanline memories may be used to provide fast access to the memory bins used for a line of pixel centers. As the filtering unit FU(K) may use samples in a 5 by 5 neighborhood of bins around a pixel center to compute a pixel, successive pixels in a line of pixels end up using a horizontal band of bins that spans the column and measures five bins vertically. Five of the bin scan lines memories may store the bins of the current horizontal band. The sixth bin scan line memory may store the next line of bins, after the current band of five, so that the filtering unit FU(K) may immediately begin computation of pixels at the next line of pixel centers when it reaches the end of the current line of pixel centers.

As the vertical displacement .DELTA.Y between successive lines of virtual pixels centers may be less than the vertical size of a bin, not every vertical step to a new line of pixel centers necessarily implies use of a new line of bins. Thus, a vertical step to a new line of pixel centers will be referred to as a nontrivial drop down when it implies the need for a new line of bins. Each time the filtering unit FU(K) makes a nontrivial drop down to a new line of pixel centers, one of the bin scan line memories may be loaded with a line of bins in anticipation of the next nontrivial drop down.

Much of the above discussion has focused on the use of six bin scanline memories in each filtering unit. However, more generally, the number of bin scanline memories may be one larger than the diameter (or side length) of the bin neighborhood used for the computation of a single pixel. (For example, in an alternative embodiment, the bin neighborhood may be a 7.times.7 array of bins.)

Furthermore, each of the filtering units FU(K) may include a bin cache array to store the memory bins that are immediately involved in a pixel computation. For example, in some embodiments, each filtering unit FU(K) may include a 5.times.5 bin cache array, which stores the 5.times.5 neighborhood of bins that are used in the computation of a single pixel. The bin cache array may be loaded from the bin scanline memories.

As noted above, each rendering pipeline of the rendering engine 300 generates sample positions in the process of rendering primitives. Sample positions within a given spatial bin may be generated by adding a vector displacement (.DELTA.X,.DELTA.Y) to the vector position (X.sub.bin, Y.sub.bin) of the bin's origin (e.g. the top-left comer of the bin). To generate a set of sample positions within a spatial bin implies adding a corresponding set of vector displacements to the bin origin. To facilitate the generation of sample positions, each rendering pipeline may include a programmable jitter table which stores a collection of vector displacements (.DELTA.X,.DELTA.Y). The jitter table may have sufficient capacity to store vector displacements for an M.sub.J.times.N.sub.J tile of bins. Assuming a maximum sample position density of D.sub.max samples per bin, the jitter table may then store M.sub.J*N.sub.J*D.sub.max vector displacements to support the tile of bins. Host software may load the jitter table with a pseudo-random pattern of vector displacements to induce a pseudo-random pattern of sample positions. In one embodiment, M.sub.J=N.sub.J=2 and D.sub.max=16.

A straightforward application of the jitter table may result in a sample position pattern, which repeats with a horizontal period equal to M.sub.J bins, and a vertical period equal to N.sub.J bins. However, in order to generate more apparent randomness in the pattern of sample positions, each rendering engine may also include a permutation circuit, which applies transformations to the address bits going into the jitter table and/or transformations to the vector displacements coming out of the jitter table. The transformations depend on the bin horizontal address X.sub.bin and the bin vertical address Y.sub.bin.

Each rendering unit may employ such a jitter table and permutation circuit to generate sample positions. The sample positions are used to compute samples, and the samples are written into sample buffer 500. Each filtering unit of the filtering engine 600 reads samples from sample buffer 500, and may filter the samples to generate pixels. Each filtering unit may include a copy of the jitter table and permutation circuit, and thus, may reconstruct the sample positions for the samples it receives from the sample buffer 500, i.e., the same sample positions that are used to compute the samples in the rendering pipelines. Thus, the sample positions need not be stored in sample buffer 500.

As noted above, sample buffer 500 stores the samples, which are generated by the rendering pipelines and used by the filtering engine 600 to generate pixels. The sample buffer 500 may include an array of memory devices, e.g., memory devices such as SRAMs, SDRAMs, RDRAMs, 3DRAMs or 3DRAM64s. In one collection of embodiments, the memory devices are 3DRAM64 devices manufactured by Mitsubishi Electric Corporation.

RAM is an acronym for random access memory.

SRAM is an acronym for static random access memory.

DRAM is an acronym for dynamic random access memory.

SDRAM is an acronym for synchronous dynamic random access memory.

RDRAM is an acronym for Rambus DRAM.

The memory devices of the sample buffer may be organized into N.sub.MB memory banks denoted MB(0), MB(1), MB(2), . . . , MB(N.sub.MB-1), where N.sub.MB is a positive integer. For example, in one embodiment, N.sub.MB equals eight. In another embodiment, N.sub.MB equals sixteen.

Each memory bank MB may include a number of memory devices. For example, in some embodiments, each memory bank includes four memory devices.

Each memory device stores an array of data items. Each data item may have sufficient capacity to store sample color in a double-buffered fashion, and other sample components such as z depth in a single-buffered fashion. For example, in one set of embodiments, each data item may include 116 bits of sample data defined as follows:

30 bits of sample color (for front buffer),

30 bits of sample color (for back buffer),

16 bits of alpha and/or overlay,

10 bits of window ID,

26 bits of z depth, and

4 bits of stencil.

Each of the memory devices may include one or more pixel processors, referred to herein as memory-integrated pixel processors. The 3DRAM and 3DRAM64 memory devices manufactured by Mitsubishi Electric Corpor