Phase-locked circuit Number:7,522,691 from the United States Patent and Trademark Office (PTO) owispatent

Title: Phase-locked circuit

Abstract: A phase-locked circuit comprises a complex signal processor and a feedback portion wherein the complex signal processor: receives as an input a first complex signal composed of a real part component and an imaginary part component; generates a second complex signal composed of a first signal component and a second signal component and having a second frequency in accordance with a feedback control signal input from the feedback portion; and generates a signal in accordance with a declination of a third complex signal obtained by multiplying the first complex signal with the second complex signal and outputs to the feedback portion. The feedback portion generates the feedback control signal in accordance with a signal input from the complex signal processor, so that the declination converges to a constant value; and the complex signal processor synchronizes a phase of the second complex signal with the first complex signal and outputs.

Patent Number: 7,522,691 Issued on 04/21/2009 to Katakura

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Inventors:	Katakura; Masayuki (Kanagawa, JP)
Assignee:	Sony Corporation (JP)
Appl. No.:	11/137,642
Filed:	May 26, 2005

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Foreign Application Priority Data

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Jun 04, 2004 [JP]			P2004-166998

Current U.S. Class:	375/376 ; 375/344
Current International Class:	H03D 3/24 (20060101)
Field of Search:	375/376,364 327/156

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References Cited [Referenced By]

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U.S. Patent Documents

5574755	November 1996	Persico
6081563	June 2000	Taga et al.
2002/0001361	January 2002	Ueno et al.
2005/0057289	March 2005	Pham
2006/0164137	July 2006	Van De Beek et al.
2007/0241782	October 2007	Teig et al.

Foreign Patent Documents

	05-041662		Feb., 1993		JP
	08-204599		Aug., 1996		JP

Other References

Japanese Office Action No. 2004-166998 .about. Dated: Oct. 16, 2007. cited by other.

Primary Examiner: Payne; David C
Assistant Examiner: Shah; Tanmay K
Attorney, Agent or Firm: Rader Fishman & Grauer PLLC Kananen; Ronald P.

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Claims

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What is claimed is:

1. A phase-locked circuit, comprising a complex signal processor, and a feedback portion, wherein: said complex signal processor receives as an input a first complex signal composed of a real part component and an imaginary part component, phases of which are mutually perpendicular at a first frequency; generates a second complex signal composed of a first signal component and a second signal component and having a second frequency in accordance with a feedback control signal input from said feedback portion, wherein the second frequency is set to have a predetermined polarity; and generates a signal in accordance with a declination of a third complex signal obtained by multiplying said first complex signal with said second complex signal and outputs to said feedback portion; said feedback portion generates said feedback control signal in accordance with a signal input from said complex signal processor, so that said declination converges to a constant value; and said complex signal processor synchronizes a phase of said second complex signal with said first complex signal and outputs; wherein said complex signal processor comprises: a complex signal generation portion for respectively generating said first signal component and said second signal component having a frequency in accordance with said feedback control signal, wherein phases are mutually perpendicular, a first calculation portion for multiplying said first signal component generated by said complex signal generation portion with the real part component of said first complex signal, a second calculation portion for multiplying said second signal component generated by said complex signal generation portion with the imaginary part component of said first complex signal, and a third calculation portion for calculating a sum or difference of multiplication results of said first calculation portion and said second calculation portion; wherein said complex signal generation portion comprises: a signal generation portion for generating a signal having a frequency in accordance with said feedback control signal, cascade-connected m-stage (m indicates positive even numbers) flip-flop, wherein each successively transmits an input signal to a subsequent stage in synchronization with a signal generated by said signal generation portion, and an inverter for performing logical inversion on an output signal of a final stage of said cascade-connected flip-flop and inputting to the initial stage; wherein two signals, phases of which are different by 1/4 cycle, among signals input to or output from said cascade-connected flip-flop are output as said first signal component and said second signal component.

2. A phase-locked circuit as set forth in claim 1, wherein said complex signal processor comprises a signal generation portion for generating a signal having a frequency in accordance with said feedback control signal, a fourth calculation portion for selecting for each cycle of a signal generated by said signal generation portion a coefficient value in accordance with an instantaneous value for said first signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplying the selected coefficient value with a real part component of said first complex signal, a fifth calculation portion for selecting for each cycle of a signal generated by said signal generation portion a coefficient value in accordance with an instantaneous value for said second signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplying the selected coefficient value with an imaginary part component of said first complex signal, and a sixth calculation portion for calculating a sum or difference of multiplication results of said fourth calculation portion and said fifth calculation portion.

3. A phase-locked circuit as set forth in claim 2, wherein: said signal generation portion generates a signal having a 1/k (k indicates positive multiples of 4) cycle for said first signal component and said second signal component; said fourth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said first signal component; and said fifth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said second signal component.

4. A phase-locked circuit as set forth in claim 1, wherein said feedback portion comprises a filter circuit for amplifying a direct-current component of a signal generated by said complex signal processor by a predetermined transmission characteristic and outputting as said feedback control signal.

5. A phase-locked circuit for locking a phase of an output signal to a signal having a frequency shifted exactly by an amount of a second frequency from a signal having a first frequency included in an input signal, comprising: a quadrature signal generation portion for generating two quadrature signals having said second frequency, wherein phases are mutually perpendicular; a first complex signal output portion for multiplying two quadrature signals generated by said quadrature signal generation portion respectively with said input signal, performing on two signals as the multiplication results filter processing for attenuating components at a higher frequency or a lower frequency than said first frequency exactly by an amount of said second frequency, and outputting a first complex signal wherein one of two signals after the filter processing is a real part component and the other is an imaginary part component; a complex signal processor for generating a signal in accordance with a declination of a complex signal obtained by multiplying a second complex signal having a frequency in accordance with a feedback control signal to be input, wherein the frequency is set to have a predetermined polarity, with said first complex signal, and a feedback portion for generating said feedback control signal for controlling feedback in accordance with a signal generated by said complex signal processor, so that said declination converges to a constant value; wherein said complex signal processor outputs as said output signal at least one of a first signal component and a second signal component having mutually perpendicular phases included in said second complex signal or a signal synchronized with the signal component, wherein said complex signal processor comprises: a signal generation portion for generating a signal having a frequency in accordance with said feedback control signal, a fourth calculation portion for selecting for each cycle of a signal generated by said signal-generation portion a coefficient value in accordance with an instantaneous value for said first signal component to have in the cycle from a plurality of predetermined coefficient values and multiplying the selected coefficient value with a real part component of said first complex signal, a fifth calculation portion for selecting for each cycle of a signal generated by said signal generation portion a coefficient value in accordance with an instantaneous value for said second signal component to have in the cycle from a plurality of predetermined coefficient values and multiplying the selected coefficient value with an imaginary part component of said first complex signal, and a sixth calculation portion for calculating a sum or difference of multiplication results of said fourth calculation portion and said fifth calculation portion.

6. A phase-locked circuit as set forth in claim 5, wherein: said complex signal processor generates as a signal in accordance with said declination a signal in accordance with a real part or an imaginary part of a complex signal obtained by multiplying said first complex signal with said second complex signal; and said feedback portion generates said feedback control signal for controlling feedback, so that a signal generated by said complex signal processor converges to a constant value.

7. A phase-locked circuit as set forth in claim 6, wherein said complex signal processor comprises a complex signal generation portion for respectively generating said first signal component and said second signal component having a frequency in accordance with said feedback control signal, wherein phases are mutually perpendicular, a first calculation portion for multiplying said first signal component generated by said complex signal generation portion with a real part component of said first complex signal, a second calculation portion for multiplying said second signal component generated by said complex signal generation portion with an imaginary part component of said first complex signal, and a third calculation portion for calculating a sum or difference of multiplication results of said first calculation portion and said second calculation portion.

8. A phase-locked circuit as set forth in claim 5, wherein: said signal generation portion generates a signal having a 1/k (k indicates positive multiples of 4) cycle for said first signal component and said second signal component; said fourth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said first signal component; and said fifth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said second signal component.

9. A phase-locked circuit as set forth in claim 6, wherein said feedback portion comprises a filter for amplifying a direct-current component of a signal generated by said complex signal processor by a predetermined transmission characteristic and outputting as said feedback control signal.

10. A phase-lock circuit for locking a phase difference of a first output signal and a second output signal to a phase difference in accordance with a first angle based on a first input signal being proportional to a product of a cosine function having a first frequency and a cosine function having the first angle, and a second input signal being proportional to a product of a cosine function having a first frequency and a sine function having the first angle, comprising: a polarity inversion circuit for inverting a polarity of said second input signal and outputting; a first phase-locked circuit, wherein said first input signal is input to a first terminal, said second input signal is input to a second terminal, and said first output signal is output; a second phase-locked circuit, wherein said first input signal is input to a first terminal, an output signal of said polarity inversion circuit is input to second terminal, and said second output signal is output; wherein said first phase-locked circuit and said second phase-locked circuit respectively comprises: a complex signal processor for generating a signal in accordance with a declination of a complex signal obtained by multiplying a first complex signal having a signal input to said first terminal as a real part component and a signal input to said second terminal as an imaginary part component with a second complex signal having a frequency in accordance with a feedback control signal to be input, wherein the frequency is set to have a predetermined polarity; and a feedback portion for generating said feedback control signal for controlling feedback in accordance with a signal generated by said complex signal processor, so that said declination converges to a constant value; wherein said complex signal processor outputs as said first output signal or said second output signal at least one of a first signal component and a second signal component having mutually perpendicular phases included in said second complex signal, or outputs as said first output signal or said second output signal a signal synchronized with one of said first signal component and said second signal component wherein said complex signal processor comprises: a signal generation portion for generating a signal having a frequency in accordance with said feedback control signal, a fourth calculation portion for selecting for each cycle of a signal generated by said signal generation portion a coefficient value in accordance with an instantaneous value for said first signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplying the selected coefficient value with a real part component of said first complex signal, a fifth calculation portion for selecting for each cycle of a signal generated by said signal generation portion a coefficient value in accordance with an instantaneous value for said second signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplying the selected coefficient value with an imaginary part component of said first complex signal, and a sixth calculation portion for calculating a sum or difference of multiplication results of said fourth calculation portion and said fifth calculation portion.

11. A phase-locked circuit as set forth in claim 10, wherein: said complex signal processor generates as a signal in accordance with said declination a signal in accordance with a real part or an imaginary part of a complex signal obtained by multiplying said first complex signal with said second complex signal; and said feedback portion generates said feedback control signal for controlling feedback, so that a signal generated by said complex signal processor converges to a constant value.

12. A phase-locked circuit as set forth in claim 11, wherein said complex signal processor comprises a complex signal generation portion for respectively generating said first signal component and said second signal component having a frequency in accordance with said feedback control signal, wherein phases are mutually perpendicular, a first calculation portion for multiplying said first signal component generated by said complex signal generation portion with a real part component of said first complex signal, a second calculation portion for multiplying said second signal component generated by said complex signal generation portion with an imaginary part component of said first complex signal, and a third calculation portion for calculating a sum or difference of multiplication results of said first calculation portion and said second calculation portion.

13. A phase-locked circuit as set forth in claim 10, wherein: said signal generation portion generates a signal having a 1/k (k indicates positive multiples of 4) cycle for said first signal component and said second signal component; said fourth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said first signal component; and said fifth calculation portion selects a coefficient value in accordance with an instantaneous value in every 1/k cycle of said second signal component.

14. A phase-locked circuit as set forth in claim 11, wherein said feedback portion comprises a filter circuit for amplifying a direct-current component of a signal generated by said complex signal processor by a predetermined transmission characteristic and outputting as said feedback control signal.

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Description

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CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2004-166998 filed in the Japanese Patent Office on Jun. 4, 2004, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a phase-locked circuit for outputting a signal, wherein a phase thereof is locked to an input signal.

2. Description of the Related Art

When using a phase-locked loop (PLL), for example as shown in FIG. 31, from a signal buried in an interfering wave, an output locked (synchronized) to a phase of the signal can be taken out. In this case, even if a frequency of the signal is changed by a Doppler-shift, etc., the PLL can follow the frequency change, and this is a different point from a mere filter.

Also, the phase-locked loop is effectively used also in the case of recovering a continuous signal shown in FIG. 32B from signals sent in a burst state, for example as shown in FIG. 32A. This is used for reproducing a color carrier wave, for example, in analog TV broadcast in the NTSC method, etc.

The phase-locked loop is also widely used for frequency synthesis. FIG. 33 is a basic block diagram of a frequency synthesis circuit (frequency synthesizer).

In this circuit, an oscillation frequency of a VCO (voltage controlled oscillation circuit) 4 is controlled, so that a reference frequency multiplied by 1/N "freq/N" and an output frequency f.sub.OUT multiplied by 1/M "freq/M" become equal by obtaining a phase difference .DELTA..phi. of the both by a phase comparison band 2 via a LPF 3. As a result, the output frequency f.sub.OUT becomes "M.times.f.sub.REF/N". By changing a division ratio M, it becomes possible to adjust the output frequency f.sub.OUT by resolution of f.sub.REF/N. The frequency synthesis circuit composed of a phase-locked loop is widely used for finely adjusting frequency in measuring devices and ratio communication apparatuses, etc.

A real number "a" is obtained by adding two conjugate complex numbers and dividing by 2, wherein the two conjugate complex numbers have positive and negative declinations having an equal size. In totally the same way, a real signal used in signal processing can be considered as a signal obtained by adding two complex signals having positive and negative frequencies.

In the case of performing processing relating to a frequency, such as frequency conversion processing and filter processing, on a real signal as above, two complex signals in positive and negative frequency domains may interfere.

For example, in a communication apparatus, etc., frequency conversion processing for taking out a signal of an intermediate frequency ".omega..sub.IF=.omega..sub.RF-.omega..sub.LO" by multiplying a high frequency signal of an angle frequency ".omega..sub.RF=2.pi.f.sub.RF" and a local oscillation signal of an angle frequency .omega..sub.LO=2.pi.f.sub.LO" by the real signals is often performed. In this processing, as shown in FIG. 34, an image signal existing in an angle frequency .omega..sub.image=.omega..sub.LO-.omega..sub.IF also shifts to the intermediate frequency .omega..sub.IF in the same way as the high frequency signal to be processed, so that it suffers from a disadvantage that it disturbs the communication. It is considered that this is because a complex signal of a negative angle frequency -.omega..sub.image included in the image signal shifts from a negative frequency domain to a positive frequency domain by being multiplied with a complex signal of a positive angle frequency .omega..sub.LO included in the local oscillation signal to bring a frequency shift of "-.omega..sub.image+.omega..sub.LO".

In a phase-locked loop, only a real signal is capable of locking a phase, and positive and negative frequency components cannot be distinguished for use. Therefore, the interference of positive and negative frequency components cannot be fundamentally prevented and it suffers form disadvantages of causing complication of the circuit and a decline of quality of an output signal, etc.

SUMMARY OF THE INVENTION

It is desired to provide a phase-locked circuit capable of using by distinguishing positive and negative frequency components.

According to a first embodiment of the present invention, there is provided a phase-locked circuit for locking a phase of an output signal to an input signal, comprising a complex signal processor, and a feedback portion.

The complex signal processor generates a signal in accordance with a declination of a third complex signal obtained by multiplying a second complex signal having a frequency in accordance with a feedback control signal to be input, wherein the frequency is set to have a predetermined polarity, with a first complex signal as the above input signal. Also, at least one of a first signal component and a second signal component having mutually perpendicular phases included-in the second complex signal or a signal synchronized with the signal component is output as the above output signal.

The feedback portion generates the feedback control signal in accordance with a signal input from the complex signal processor, so that the declination converges to a constant value

The second complex signal has a frequency in accordance with the feedback control signal, wherein the frequency has a predetermined polarity. A signal in accordance with a declination of a complex signal obtained by multiplying the second complex signal with the first complex signal is generated in the complex signal processor.

The declination of a complex signal obtained by multiplying the second complex signal with the first complex signal is equal to a declination obtained by adding a declination of the first complex signal and that of the second complex signal. Therefore, in the complex signal processor, a signal in accordance with the added declination is generated.

In the feedback portion, the feedback control signal for controlling feedback is generated in accordance with a signal generated in the complex signal processor, so that the added declination converges to a constant value (for example, zero).

A declination becoming constant is equivalent to a declination being constant over time and a frequency becoming zero. Accordingly, to converge the added declination to a constant value, it is necessary that the first complex signal and the second complex signal have frequencies of the same size but opposite polarities.

Therefore, when the second complex signal has a negative frequency, the frequency of the second complex signal is controlled, so that the negative frequency cancels out a positive frequency of the first complex signal. When the second complex signal has a positive frequency, the frequency of the second complex signal is controlled, so that the positive frequency cancels out a negative frequency of the first complex signal.

Inversely, when the second complex signal and the first complex signal have frequencies of the same polarity, the added declination always has a frequency and it cannot be converged to a constant value. Therefore, in this case, the feedback control is not operated and a frequency of the second complex signal does not follow a frequency of the first complex signal.

Accordingly, in the output signal, which is at least one of the first signal component and the second signal component in the second complex signal or a signal synchronized with the signal component, a phase is locked to the first complex signal having a frequency of an opposite polarity of a predetermined polarity as above.

A second embodiment of the present invention is a phase-locked circuit for locking a phase of an output signal to a signal having a frequency shifted exactly by an amount of a second frequency from a signal having a first frequency included in an input signal, and includes a quadrature signal generation portion, a first complex signal output portion, a complex signal processor, and the phase-locked circuit of the first embodiment.

The quadrature signal generation portion generates two quadrature signals having the second frequency and mutually perpendicular phases.

The first complex signal output portion multiplies two quadrature signals generated by the quadrature signal generation portion respectively with the input signal, performs on two signals as the multiplication results filter processing for attenuating components at a higher frequency or a lower frequency than the first frequency exactly by an amount of the second frequency, and outputs a first complex signal wherein one of two signals after the filter processing is a real part component and the other is an imaginary part component. The phase-locked circuit of the first embodiment locks a phase of an output signal to the first complex signal.

In the first complex signal output portion, the input signal is multiplied respectively with two quadrature signals having the second frequency generated by the quadrature signal generation portion. Two signals as multiplication results indicate one complex signal, wherein one is a real part and the other is an imaginary part, and this complex signal becomes what obtained by shifting a frequency of the input signal exactly by an amount of the second frequency to the positive or negative direction.

Next, in the first complex signal output portion, filter processing for attenuating signal components at a higher frequency or a lower frequency than the first frequency exactly by an amount of the second frequency is performed on two signals as the multiplication results. As a result, among positive and negative frequency components originally included in the input signal, those moved to one side of a high range and a low range due to the frequency shift are removed, and those moved to the other side remain.

The complex signal after the filter processing is input as the first complex signal to a phase-locked circuit having the same configuration as that in the first embodiment.

Original components of the input signal remain as they are in one of frequency domains, high or low, not attenuated by the filter processing. Therefore, when locking a phase by using only a real part or an imaginary part of the first complex signal, it is interfered by a frequency component of an opposite sign-existing symmetrically about a frequency-zero point. On the other hand, when using the phase-locked circuit of the first embodiment, an output signal having a phase locked to a component having one of positive and negative frequencies is obtained from frequency components included in the first complex signal, thus, it is not affected by an interference as such.

A third embodiment of the present invention is a phase-lock circuit for locking a phase difference of a first output signal and a second output signal to a phase difference in accordance with a first angle based on a first input signal being proportional to a product of a cosine function having a first frequency and a cosine function having the first angle, and a second input signal being proportional to a product of a cosine function having a first frequency and a sine function having the first angle, and comprises a polarity inversion circuit, a first phase lock circuit and a second phase lock circuit.

The polarity inversion circuit inverts a polarity of the second input signal and outputs.

In the first phase-locked circuit, the first input signal is input to a first terminal, the second input signal is input to a second terminal, and the first output signal is output.

In the second phase-locked circuit, the first input signal is input to a first terminal, an output signal of the polarity inversion circuit is input to second terminal, and the second output signal is output

The first phase-locked circuit and the second phase-locked circuit have the same configuration (a complex signal processor and a feedback portion) as that in the first embodiment.

Note that in the complex signal processors of the respective phase-locked circuits, a complex signal having a signal input to the first terminal as a real part component and a signal input to the second terminal as an imaginary part component is used as the first complex signal.

Also, the complex signal processor outputs as the first output signal or the second output signal at least one of a first signal component and a second signal component having mutually perpendicular phases included in the second complex signal, or outputs as the first output signal or the second output signal a signal synchronized with one of the first signal component and the second signal component.

The first phase-locked circuit receives as an input a complex signal, wherein the first input signal is a real part component and the second signal is an imaginary part component. This complex signal has the first frequency and positive and negative frequency components having opposite signs.

Also, the second phase-locked circuit receives as an input a complex signal, wherein the first input signal is a real part component and a polarity inverted signal of the second signal is an imaginary part component. This complex signal also has the first frequency and positive and negative frequency-components having opposite signs.

When comparing signal components having frequencies of the same polarity between the complex signals input to the first and second phase-locked circuits, both of the positive and negative frequencies have a phase difference in accordance with the first angle.

Both of a first output signal to be output from the first phase-locked circuit and a second output signal to be output from the second phase-locked circuit become a signal having a phase locked to a component having a frequency of a specific polarity (an opposite polarity of the predetermined polarity) included in the first complex signal. Therefore, a phase difference of the both is locked to a phase difference in accordance with the first angle.

Note that the first to third embodiments may be configured as below.

The complex signal processor may generate a signal in accordance with a real part or an imaginary part of a complex signal obtained by multiplying the first complex signal with the second complex signal as a signal in accordance with the declination, and the feedback portion may generate the feedback control signal for controlling feedback, so that a signal generated in the complex signal processor converges to a constant value.

In this case, a signal generated in the complex signal processor is a signal in accordance with a real part component or an imaginary part component in a complex signal having a declination obtained by adding a declination of the first complex signal and that of the second complex signal. As a result of controlling feedback, so that the signal converges to a constant value, the added declination converges to a constant value.

The complex signal processor may include a complex signal generation portion, a first calculation portion, a second calculation portion and a third calculation portion.

The first calculation portion multiplies the first signal component generated by the complex signal generation portion with a real part component of the first complex signal.

The second calculation portion multiplies the second signal component generated by the complex signal generation portion with an imaginary part component of the first complex signal.

The third calculation portion calculates a sum or difference of multiplication results of the first calculation portion and the second calculation portion.

According to the above configuration, the complex signal generation portion generates the first signal component and the second signal component having a frequency in accordance with the feedback control signal, phases of which are mutually perpendicular. In the first calculation portion, the first signal component generated by the complex signal generation portion is multiplied with a real part component of the first complex signal. In the second calculation portion, the second signal component generated by the complex signal generation portion is multiplied with an imaginary part component of the first complex signal. In the third calculation portion, a sum or difference of multiplication results of the first calculation portion and the second calculation portion is calculated

A calculation result of the sum or difference becomes a signal corresponding to a real part or an imaginary part of a complex signal obtained by multiplying the first complex signal with the second complex signal.

Alternately, the complex signal processor may include a signal generation portion, a fourth calculation portion, a fifth calculation portion and a sixth calculation portion.

The signal generation portion generates a signal having a frequency in accordance with the feedback control signal.

The fourth calculation portion selects for each cycle of a signal generated by the signal generation portion a coefficient value in accordance with an instantaneous value for the first signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplies the selected coefficient value with a real part component of the first complex signal. Consequently, a pseudo result of multiplying the first signal component with a real part component of the first complex signal is obtained.

The fifth calculation portion selects for each cycle of a signal generated by the signal generation portion a coefficient value in accordance with an instantaneous value for the second signal component to have in the cycle from a plurality of predetermined coefficient values, and multiplies the selected coefficient value with an imaginary part component of the first complex signal. Consequently, a pseudo result of multiplying the second signal component with an imaginary part component of the first complex signal is obtained.

Then, as a result that the sixth calculation portion calculates a sum or difference of multiplication results of the fourth calculation portion and the fifth calculation portion, a signal corresponding to a real part or an imaginary part of a complex signal obtained by multiplying the first complex signal with the second complex signal is obtained.

According to the present invention, it is possible to obtain a signal wherein a phase is locked only to either one of components having positive and negative frequencies included in a complex signal to be input, so that positive and negative frequency components can be distinguished for use, and the mutual interference can be prevented.

BRIEF DESCRIPTION OF DRAWINGS

These and other objects and features of the present invention will become clearer from the following description of the preferred embodiments given with reference to the attached drawings, in which:

FIG. 1 is a view of an example of the configuration of a phase-locked circuit according to a first embodiment;

FIG. 2 is a view of a complex signal expressed on a complex plane;

FIG. 3A and FIG. 3B are views wherein a real signal is expressed by a vector on a complex plane;

FIG. 4 is a view of a coordinate system for expressing a vector of a complex signal by using frequency axes;

FIG. 5A and FIG. 5B are views for illustrating a sine wave signal and a cosine wave signal when time t=0 by a vector on a complex plane;

FIG. 6 is a view of an example of the configuration of a complex signal generation portion in the phase-locked circuit shown in FIG. 1;

FIG. 7A to FIG. 7C show signal waveforms of respective portions in the complex signal generation portion shown in FIG. 6;

FIG. 8 is a view showing an example of frequency characteristics of a feedback portion;

FIG. 9 is a view of an example of the configuration of a phase-locked circuit according to a second embodiment;

FIG. 10 is a view of an example of the configuration of a sine wave multiplier;

FIG. 11A to FIG. 11D are views of a control example of respective switches of the sine wave multiplier shown in FIG. 10 in the case where there are two multiplier coefficients;

FIG. 12 is a view of an example of a relationship of changes of a multiplier coefficient value selected in time series and a sine wave signal to be multiplied;

FIG. 13 is a view of a configuration example of a multiplier in the case where there are two multiplier coefficients;

FIG. 14A to FIG. 14D are views of a control example of respective switches of the multiplier shown in FIG. 13;

FIG. 15 is a view of a configuration example of a phase-locked circuit when using a multiplier in a complex signal processor;

FIG. 16 is a view of an example of a frequency spectrum of an output signal of the sine wave multiplier in the phase-locked circuit shown in FIG. 15;

FIG. 17 is a view of an example of the configuration of a phase-locked circuit according to a third embodiment;

FIG. 18 is a view of an embodiment of the related art using an image removal filter;

FIG. 19 is a view of an embodiment of the related art using an image removal mixer;

FIG. 20 is a view of another configuration example of the phase-locked circuit according to the third embodiment;

FIG. 21 is a view of an example of the configuration of a phase-locked circuit according to a fourth embodiment;

FIG. 22 is a view of an example of the configuration of a phase difference measuring circuit;

FIG. 23 is a view of an example of a one-phase excitation two-phase output type resolver angle sensor;

FIG. 24A and FIG. 24B are views of an example of a two-phase excitation two-phase output type resolver angle sensor;

FIG. 25A to FIG. 25C are views wherein two output signals of a resolver angle sensor are expressed as vectors of a complex frequency;

FIG. 26 is a view for explaining an operation of rotating a vector by -90.degree.;

FIG. 27 is a view wherein complex signal processing performed in the present embodiment is illustrated by vectors;

FIG. 28 is a block diagram of complex signal processing performed in the present embodiment;

FIG. 29 is a simplified view of a flow of a signal in the block diagram shown in FIG. 28;

FIG. 30 is a view of another configuration example of a phase-locked circuit according to a fourth embodiment;

FIG. 31 is a view of an example of taking out a signal from an interference wave by using a PLL;

FIG. 32A and FIG. 32B are views of an example of reproducing a carrier wave signal from a burst signal by using a PLL;

FIG. 33 is a view of an example of a frequency synthesizer using a PLL; and

FIG. 34 is a view for explaining an image signal in frequency conversion processing.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Below, preferred embodiments of the present invention will be explained with reference to the drawings.

First Embodiment

FIG. 1 is a view of an example of the configuration of a phase-locked circuit according to a first embodiment of the present invention.

Before explaining the phase-locked circuit shown in FIG. 1, a relationship of a real signal and a complex signal will be explained.

A complex frequency .omega..sub.S is defined as below. e.sup.j.omega..sup.s.sup.t=Cos .omega..sub.St+jSin .omega..sub.St (1)

Since a complex signal is defined on a complex plane, it can be divided to a real part Cos .omega..sub.st and an imaginary part Sin .omega..sub.st and defined as a set of two signals.

FIG. 2 is a view of a complex signal expressed on a complex plane.

A complex signal can be considered as a vector on a complex plane rotating about an origin "o" at an angle rate .omega.. A real part of the complex signal is a cosine component and an imaginary part is a sine component.

Against such a complex signal, a normal signal is called as a real signal.

When considering real signals of a sine wave and a cosine wave as complex signals, how they can be expressed as complex signals will be discussed below. A sine wave and a cosine wave as real signals can be expressed as below.

.times..times..omega..times.e.omega..times.e.omega..times..times..times..o- mega..times.e.omega..times.e.omega..times..times. ##EQU00001##

As is obvious from the formula (2), a real signal is expressed by a sum of two complex signals having symmetric frequencies to the positive and negative sides.

It is defined that a positive frequency is a vector rotating in the anticlockwise direction and a negative frequency is a vector rotating in the clockwise direction on the complex plane in FIG. 2. When illustrating a relationship of the formulas (2) and (3) based on the definition, it is as shown in FIG. 3.

A real signal 2 Cos .omega..sub.st is a sum of a complex signal e.sup.j.omega.st having a positive frequency and a complex signal e.sup.-j.omega.st having a negative frequency. When illustrating it on the complex plane, as shown in FIG. 3A, it can be expressed as a sum of two vectors rotating inversely to each other. The two vectors superimpose on a real axis at time t=0 and are always axisymmetric about the real axis even when rotating over time. Therefore, when merging the two vectors, the imaginary part is always cancelled to be zero and only the real part remains.

In the same way, a real signal 2 Sin .omega..sub.st is a sum of a complex signal je.sup.j.omega.st having a positive frequency and a complex signal je.sup.-j.omega.st having a negative frequency, which are axisymmetric about the real axis. Therefore, when merging the two vectors, the imaginary part is also always cancelled to be zero and only the real part remains.

To express it as a stationary vector, the coordinate system shown in FIG. 4 will be used.

In the coordinate system in FIG. 4, an x-axis indicating an angle frequency or a frequency of a complex signal is provided in the vertical direction with respect to the complex plane made by a Z-axis indicating an imaginary part and a y-axis indicating a real part.

FIG. 5 is a view of illustrating a sine wave signal and a cosine wave signal at time t=0 by vectors on the complex plane (z-y plane). Note that a phase at time t=0 is assumed to be zero in all cases. FIG. 5A shows vectors of a cosine wave signal Cos .omega..sub.st, and FIG. 5B shows vectors of a sine wave signal Sin .omega..sub.st.

As explained above, any real signal includes two complex signals having symmetric frequencies to the positive and negative sides when seeing it as a complex signal. These vectors rotate inversely to each other over time and the imaginary part is always cancelled out, so that a real signal as a sum of the both does not have an imaginary part.

The phase-locked circuit shown in FIG. 1 handles an input signal as a complex signal and obtains an output signal, wherein the phase is locked to either one of a positive frequency component or a negative frequency component of the complex signal.

The phase-locked circuit shown in FIG. 1 has a complex signal processor 100 and a feedback portion 200.

The complex signal processor 100 has multipliers 101 and 102, an adder 103 and a complex signal generation portion 104.

The complex signal processor 100 is an embodiment of a complex signal processor of the present invention.

The feedback portion 200 is an embodiment of a feedback portion of the present invention.

The complex signal generation portion 104 is an embodiment of a complex signal generation portion of the present invention.

The multiplier 101 is an embodiment of a first calculation portion of the present invention.

The multiplier 102 is an embodiment of a second calculation portion of the present invention.

The adder 103 is an embodiment of a third calculation portion of the present invention.

In the present specification, a complex signal and an actual signal are distinguished by adding an underline "_" to a complex signal.

[Complex Signal Processor 100]

The complex signal processor 100 generates a signal Vpd in accordance with a declination of a complex signal obtained by multiplying a first complex signal _Vin (the real part: Vin.sub.I, the imaginary part: Vin.sub.Q) and a later explained second complex signal _Vlo based on a feedback control signal Vc and the first complex signal _Vin (the real part: Vin.sub.I, the imaginary part: Vin.sub.Q).

The second complex signal _Vlo includes a first signal component Vlo.sub.Q as the imaginary part and a second signal component Vlo.sub.I as the real part component. Phases of the signal components are perpendicular to each other, and the frequencies are in accordance with the feedback control signal Vc. Also, the frequencies are set to have a predetermined polarity, which is constant regardless of the feedback control signal Vc. It is assumed that the frequencies are set to have a negative polarity as an example below.

It is assumed that the first complex signal _Vin has a positive angle frequency .omega. and the second complex signal_Vlo has a negative angle frequency -.omega., and they are expressed as formulas below, respectively. Vin=Vin.sub.I+jVin.sub.Q=Vae.sup.j.omega.t (4) Vlo=Vlo.sub.I+jVlo.sub.Q=e.sup.-j(.omega.t+.theta.) (5)

In the formula (4), "Va" indicates an amplitude of the first complex signal _Vin. Also, ".theta." indicates a phase difference of the first complex signal _Vin and the second complex signal _Vlo.

When multiplying the first complex signal _Vin with the second complex signal _Vlo in the multipliers 101 and 102, the formula below is derived. VinVlo=Vae.sup..omega.te.sup.-j(.omega.t+.theta.)=Vae.sup.-j.theta. (6)

When separating the formula (6) to a real part and an imaginary part, the next formula is derived.

.times.e.omega..times..times.e.omega..times..times..theta..times..times..t- imes..times..omega..times..times..times..times..omega..times..times..times- ..function..omega..times..times..theta..function..omega..times..times..the- ta..times..times..times..times..omega..times..times..function..omega..time- s..times..theta..times..times..omega..times..times..function..omega..times- ..times..theta..times..times..times..times..omega..times..times..function.- .omega..times..times..theta..times..times..omega..times..times..function..- omega..times..times..theta. ##EQU00002##

When assuming that the complex signal processor 100 outputs an imaginary part of the formula (7) as a signal Vpd, the signal Vpd is expressed as the formula below. Vpd=Va{-Cos .omega.tSin(.omega.t+.theta.)+Sin .omega.tCos(.omega.t+.theta.)}=-VaSin .theta. (8)

According to the formula (8), the signal Vpd can be calculated by using two multiplying circuits and one adding circuit.

The multiplier 101 multiplies a first signal component Vlo.sub.Q of the second complex signal _Vlo with a real part component Vin.sub.I of the first complex signal Vin. Namely, the formula (8) below is calculated. Vin.sub.I.times.Vlo.sub.Q=-Va.times.Cos .omega.t.times.Sin(.omega.t+.theta.)

The multiplier 102 multiplies the second signal component Vlo.sub.I of the second complex signal _Vlo with an imaginary part component Vin.sub.Q of the first complex signal _Vin. Namely, the formula (8) below is calculated. Vin.sub.Q.times.Vlo.sub.I=-Va.times.Sin .omega.t.times.Cos(.omega.t+.theta.)

The adder 103 calculates a sum of multiplication results of the multiplier 101 and the multiplier 102. As a result, the signal Vpd in the formula (8) is obtained.

The complex signal generation portion 104 generates a first signal component Vlo.sub.Q and a second signal component Vlo.sub.I having a frequency .omega. in accordance with the feedback control signal Vpd and phases of which are apart by 1/4 cycle (.pi./2) (that is, both phases have a quadrature relationship).

Also, the complex signal generation portion 104 sets a phase relationship of the first signal component Vlo.sub.Q and the second signal component Vlo.sub.I, so that a polarity of a frequency of the second complex signal _Vlo always becomes negative.

Note that, as illustrated in FIG. 6 as a circuit example explained next, when realizing the complex signal generation portion 104 by a circuit, it is normally not necessary to provide a special configuration for maintaining the phase relationship constant, because a circuit has to be added when changing the phase relationship of the two signal components Vlo.sub.I and Vlo.sub.Q.

FIG. 6 is a view of an example of the configuration of the complex signal generation portion 104.

The complex signal generation portion 104 has D-type flip-flops 106 and 107, an inverter 108 and a signal generation portion 105.

The flip-flops 106 and 107 are cascade connected, and an output signal of the final stage of the cascade connection (the flip-clop 107 in the example in FIG. 6) is logically inverted by the inverter 108 and input to the initial stage of the cascade connection (the flip-flop 106 in the example in FIG. 6). An output signal of the flip-flop 106 is output as a second signal component Vlo.sub.I and an output signal of the flip-flop 107 is output as a first signal component Vlo.sub.Q.

The signal generation portion 105 is, for example, a voltage controlled oscillator (VCO) and generates a signal S105 having a frequency in accordance with an amplitude of a feedback control signal Vc. The flip-flops 106 and 107 latch an input signal in synchronization with the signal S105.

FIG. 7A to FIG. 7C show signal waveforms of respective portions in the complex signal generation portion 104 shown as an example in FIG. 6.

An output signal of the inverter 108 is delayed by an amount of two cycles of the signal S105 by the flip-flops 106 and 107 and fed back to an input of the inverter 108. Therefore, positive and negative of the output signal of the inverter 108 is inverted for every two cycles of the signal S105, and the cycle becomes 4 times the cycle of the signal S105.

Accordingly, the first signal component Vlo.sub.Q and the second signal component Vlo.sub.I have 4 times the cycle of the signal S105 (that is, a frequency of 1/4).

Also, the first signal component Vlo.sub.Q has a delay of an amount of one stage of a flip-flop, that is, a delay of 1/4 cycle with respect to the second signal component Vlo.sub.I.

In the example in FIG. 6, a delay circuit is configured by two-stage flip-flops, but the number of stages may be increased to an even number larger than two (four stages, six stages, . . . ). In this case, two signals having a delay difference corresponding to a half of the total number of stages has a delay difference of 1/4 of one cycle, so that they can be used as the first signal component Vlo.sub.Q and second signal component Vlo.sub.I.

[Feedback Portion 200]

The feedback portion 200 generates a feedback control signal Vc for operating feedback control in accordance with the signal Vpd generated in the complex signal processor 100, so that the signal Vpd converges to a constant value.

The feedback portion 200 is configured as a filter circuit for amplifying, for example, a direct-current component of the signal Vpd generated by the complex signal processor 100 by a predetermined transfer function. The transfer function H(s) has a frequency characteristic, for example as shown in FIG. 8, and is expressed by the next formula. H.sub.(s)=Ao(1+.omega.a/s) (9)

A direct-current gain of the transfer function H(s) is infinite, so that the output signal of the complex signal processor 100 has to be zero in a stationary state. Accordingly, from the formula (8), a frequency of the second complex signal _Vlo is controlled, so that the phase difference .theta. becomes zero. As a result, when a frequency of the first complex signal _Vin changes, the frequency of the second complex signal _Vlo follows thereto and changes.

In the formula (4), the first complex signal _Vin is assumed to have a positive frequency, but when it has the same negative frequency as that of the second complex signal _Vlo, the first complex signal _Vin becomes as the formula below. Vin=Vin.sub.I+jVin.sub.Q=Vae.sup.-j.omega.t (10)

When multiplying the first complex signal _Vin with the second complex signal _Vlo, the multiplication result becomes as below. VinVlo=Vae.sup.-jt e.sup.-j(.omega.t+.theta.)=Vae.sup.-j(2.omega.t+.theta.) (11)

In this case, since both of the complex signals have a negative frequency, even when they are multiplied, only a signal having a high frequency, such as an angle frequency of 2.omega., is generated and a signal having a phase difference of .theta. is not generated. Therefore, a phase of the second complex signal _Vlo is not locked to the first complex signal _Vin.

According to the above explained configuration, the second complex signal _Vlo has a frequency in accordance with the feedback control signal Vc, and the frequency has a negative polarity. The signal Vpd in accordance with a declination of a complex signal obtained by multiplying the second complex signal _Vlo with the first complex signal _Vin is generated in the complex signal processor 100.

The declination of the complex signal obtained by multiplying the second complex signal _Vlo with the first complex signal _Vin is equal to a declination obtained by adding a declination of the first complex signal _Vin and a declination of the second complex signal _Vlo. Therefore, a signal Vpd in accordance with the added declination is generated in the complex signal processor 100.

In the feedback portion 200, in accordance with the signal Vpd, a feedback control signal Vc for operating a feedback control is generated, so that the above added declination converges to a constant value (for example, zero).

A declination becoming constant is equivalent to a declination being constant over time and a frequency becoming zero. Accordingly, it is necessary that the first complex signal _Vin and the second complex signal _Vlo have frequencies having the same size and opposite polarities to converge the above added declination to a constant value.

Therefore, the frequency of the second complex signal _Vlo is controlled, so that the negative frequency of the second complex signal _Vlo cancels out the positive frequency of the first complex signal _Vin.

Inversely, when both of the second complex signal _Vlo and the first complex signal _Vin have negative frequencies, the above added declination always has a frequency and it cannot be converged to a constant value. Therefore, in this case, the feedback control does not operate and the frequency of the second complex signal _Vlo does not follow the frequency of the first complex signal _Vin.

Accordingly, a phase of the second complex signal _Vlo is locked only to the first complex signal _Vin having a positive frequency.

As explained above, according to the phase-locked circuit according to the present embodiment, a phase of the second complex signal _Vlo can be locked only to a component of a positive frequency among components having positive and negative frequencies included in an input first complex signal _Vin. Consequently, positive and negative frequency components can be distinguished for handling and the mutual interference can be fundamentally prevented.

Second Embodiment

Next, a second embodiment of the present invention will be explained.

In the phase-locked circuit according to the first embodiment, a circuit using a flip-flop shown in FIG. 6 was described as an example of the complex signal generation portion 104.

Since both of signals Vlo.sub.I and Vlo.sub.Q generated in this circuit are pulses, so that the odd-order harmonics, such as a third-order and fifth-order, are included. Such harmonics may become unfavorable depending on an object for applying the present circuit. In the second embodiment, a phase-locked circuit capable of reducing an effect of harmonics as such will be explained.

FIG. 9 is a view of an example of the configuration of a phase-locked circuit according to the second embodiment of the present invention.

The phase-locked circuit shown in FIG. 9 includes a complex signal processor 100A and a feedback portion 200.

The complex signal processor 100A has first and second sine wave multipliers 111 and 112, an adder 113 and a signal generation portion 114.

The signal generation portion 114 is an embodiment of a signal generation portion of the present invention.

The sine wave multiplier 111 is an embodiment of a fourth calculation portion of the present invention.

The sine wave multiplier 112 is an embodiment of a fifth calculation portion of the present invention.

The adder 113 is an embodiment of a sixth calculation portion of the present invention.

A complex signal processor 110A having a different configuration from that of the phase-locked circuit shown in FIG. 1 will be explained.

[Complex Signal Processor 100A]

Overall processing of the complex signal processor 100A is the same as the complex signal processor 100 explained above.

The complex signal processor 100A generates a signal Vpd in accordance with a declination of a complex signal obtained by multiplying a first complex signal_Vin with a second complex signal _Vlo based on a feedback control signal Vc and the first complex signal _Vin.

The second complex signal _Vlo has a frequency in accordance with the feedback control signal Vc and mutually perpendicular components Vlo.sub.Q and Vlo.sub.I, wherein the frequency is set to be negative.

The signal generation portion 114 is, for example, a VCO and generates a clock signal S114 having a frequency in accordance with the feedback control signal Vc.

The adder 113 adds multiplication results S111 and S112 of later explained sine wave multipliers 111 and 112 and generates a signal Vpd.

The first sine wave multiplayer 111 selects for each cycle of the clock signal S114 a coefficient value in accordance with an instantaneous value for the first signal component Vlo.sub.Q to have in the cycle from a predetermined plurality of coefficient values, and multiplies the selected coefficient value with a real part component Vin.sub.I of the first complex signal _Vin.

The second sine wave multiplier 112 selects for each cycle of the clock signal S114 a coefficient value in accordance with an instantaneous value for the second signal component Vlo.sub.I to have in the cycle from a predetermined plurality of coefficient values, and multiplies the selected coefficient value with an imaginary part component of the first complex signal _Vin.

FIG. 10 is a view of an example of the configuration of the first sine wave multiplier 111.

The sine wave multiplier 111 has a multiplying portion MP1 and a control portion CNT1. The multiplying portion MP1 includes n number of coefficient multiplying circuits M1 to Mn, n number of coefficient selection switches SW1 to SWn, a polarity