Title: Photoelectric conversion device providing advantageous readout of two-dimensional array of transistors
Abstract: The present invention is intended to provide a photoelectric conversion device provided with a plurality of groups comprising a plurality of adjacent photoelectric conversion elements, wherein the plurality of groups are respectively provided with a detection circuit for detecting a peak signal of each group. The device is advantageously incorporated in an image processing device for outputting corresponding image signals.
Patent Number: 6,980,243 Issued on 12/27/2005 to Miyawaki, et al.
| Inventors:
|
Miyawaki; Mamoru (Isehara, JP);
Shinohara; Mahito (Tokyo, JP);
Ueno; Isamu (Hadano, JP)
|
| Assignee:
|
Canon Kabushiki Kaisha (Tokyo, JP)
|
| Appl. No.:
|
687945 |
| Filed:
|
July 29, 1996 |
Foreign Application Priority Data
| May 28, 1993[JP] | 5-127087 |
| Aug 06, 1993[JP] | 5-213547 |
| Current U.S. Class: |
348/302 |
| Intern'l Class: |
H04N 005/33.5; H04N 003/14 |
| Field of Search: |
348/297,302,303,304,308,364,307,301
250/208.1
|
References Cited [Referenced By]
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| 4870266 | Sep., 1989 | Ishizaki et al.
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| 4879470 | Nov., 1989 | Sugawa et al.
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| 5144447 | Sep., 1992 | Akimoto et al.
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| 5162912 | Nov., 1992 | Ueno et al.
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| 5184006 | Feb., 1993 | Ueno.
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| 5210434 | May., 1993 | Ohmi et al.
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| RE34309 | Jul., 1993 | Tanaka et al.
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| 5262870 | Nov., 1993 | Nakamura et al.
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| 5262871 | Nov., 1993 | Wilder et al.
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| 5288988 | Feb., 1994 | Hashimoto et al.
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| 5436662 | Jul., 1995 | Nagasaki et al.
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| 5615399 | Mar., 1997 | Akashi et al.
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| Foreign Patent Documents |
| 0226338 | Jun., 1987 | EP.
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| 0260858 | Mar., 1988 | EP.
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| 0444938 | Sep., 1991 | EP.
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| 0489724 | Jun., 1992 | EP.
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| 0522732 | Jan., 1993 | EP.
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| 0552732 | Jan., 1993 | EP.
| |
Primary Examiner: Moe; Aung
Attorney, Agent or Firm: Fitzpatrick, Cella, Harper & Scinto
Parent Case Text
This application is a continuation of application Ser. No. 08/249,358 filed
May 27, 1994, now abandoned.
Claims
1. An area sensor comprising:
a plurality of photoelectric conversion picture elements adapted to receive an
optical image, each picture element providing a photoelectrically converted output
signal, wherein said plurality of photoelectric conversion picture elements are
divided into a plurality of groups of adjacent picture elements, and wherein said
plurality of groups are arranged two-dimensionally in horizontal and vertical directions;
a peak detection unit adapted to detect in parallel peak signals of the respective
groups arranged in the horizontal direction, and to detect sequentially the peak
signals of the respective groups arranged in the vertical direction, wherein said
peak detection unit includes a plurality of peak detection portions, and wherein
the peak signals of the respective groups arranged in the horizontal direction
are detected by different peak detection portions and the peak signals of the respective
groups arranged in the vertical direction are detected by a single peak detection
portion; and
an outputting unit coupled to said peak detection unit to output the peak signals
of each of said plurality of groups arranged in the two-dimensional form.
2. An area sensor according to claim 1, wherein each of said plurality of photoelectric
conversion picture elements comprises an associated outputting unit adapted to
output a signal.
3. An area sensor according to claim 1, wherein each of said plurality of photoelectric
conversion picture elements is a transistor for accumulating carriers generated
by photoelectric conversion in a respective base.
4. An area sensor according to claim 1, wherein said area sensor is a single
semiconductor integrated circuit.
5. An image processing device, comprising:
an area sensor comprising a plurality of photoelectric conversion picture elements
adapted to receive an optical image, wherein said plurality of photoelectric conversion
picture elements are divided into a plurality of groups of adjacent picture elements,
and wherein said plurality of groups are arranged two-dimensionally in horizontal
and vertical directions;
a peak detection unit adapted to detect in parallel peak signals of the respective
groups arranged in the horizontal direction, and to detect sequentially peak signals
of the respective groups arranged in the vertical direction, wherein said peak
detection unit includes a plurality of peak detection portions, and wherein the
peak signals of the respective groups arranged in the horizontal direction are
detected by different peak detection portions and the peak signals of the respective
groups arranged in the vertical direction are detected by a single peak detection
portion;
an output unit coupled to said peak detection unit to output a peak signal of
each of said plurality of groups arranged two-dimensionally; and
a discriminating unit to discriminate whether or not image information is obtained,
on the basis of the output peak signal.
6. An image processing device according to claim 5, wherein said area sensor
is a single semiconductor integrated circuit.
7. An area sensor comprising:
a plurality of photoelectric conversion picture elements adapted to receive an
optical image, wherein said plurality of photoelectric conversion picture elements
are divided into a plurality of groups of adjacent picture elements, and wherein
said plurality of groups are arranged two-dimensionally in horizontal and vertical
directions;
a peak detection unit adapted to detect in parallel peak signals of the respective
groups arranged in the horizontal direction, and to detect sequentially peak signals
of the respective groups arranged in the vertical direction, wherein said peak
detection unit includes a plurality of peak detection portions, and wherein the
peak signals of the respective groups arranged in the horizontal direction are
detected by different peak detection portions and the peak signals of the respective
groups arranged in the vertical direction are detected by a single peak detection
portion;
an output unit coupled to said peak detection unit to output a peak signal of
each of said plurality of groups arranged two-dimensionally; and
a reading unit to read each signal from a plurality of said photoelectric conversion
picture elements, wherein said peak signal and each said signal are outputted from
different output channels respectively.
8. A sensor according to claim 7, wherein said each signal and said peak signal
are output from a same output portion of the respective picture element and are
then output to the channels through a same output line.
9. An area sensor according to claim 7, wherein said area sensor is a single
semiconductor integrated circuit.
10. An area sensor comprising:
a plurality of photoelectric conversion picture elements for converting a received
optical image into an electrical signal, each picture element reading out said
electrical signal non-destructively, wherein said plurality of photoelectric conversion
picture elements are divided into a plurality of groups of adjacent picture elements,
and wherein said plurality of groups are arranged two-dimensionally in horizontal
and vertical directions;
a peak detection unit adapted to detect in parallel peak signals of the respective
groups arranged in the horizontal direction, and to detect sequentially peak signals
of the respective groups arranged in the vertical direction, wherein said peak
detection unit includes a plurality of peak detection portions, and wherein the
peak signals of the respective groups arranged in the horizontal direction are
detected by different peak detection portions and the peak signals of the respective
groups arranged in the vertical direction are detected by a single peak detection
portion;
an output unit coupled to said peak detection unit to output a peak signal of
each of said plurality of groups arranged two-dimensionally; and
a reading unit to read a signal from a plurality of the photoelectric conversion
picture elements.
11. An area sensor according to claim 10, wherein said area sensor is a single
semiconductor integrated circuit.
12. An image processing device, comprising:
a sensor portion comprising a plurality of photoelectric conversion picture elements
for receiving an optical image, wherein said plurality of photoelectric conversion
picture elements are divided into a plurality of groups of adjacent picture elements
and wherein said plurality of groups are arranged two-dimensionally in horizontal
and vertical directions; and
a peak detection unit to detect in parallel peak signals of the respective groups
arranged in the horizontal direction, and to detect sequentially peak signals of
the respective groups arranged in the vertical direction, wherein said peak detection
unit includes a plurality of peak detection portions, and wherein the peak signals
of the respective groups arranged in the horizontal direction are detected by different
peak detection portions and the peak signals of the respective groups arranged
in the vertical direction are detected by a single peak detection portion.
13. A device according to claim 12, further comprising:
an output unit adapted to output the signals from each of the plurality of picture
elements; and
an image processor adapted to perform image processing on the output signal on
the basis of the peak signal of the respective group.
14. A device according to claim 12, wherein said sensor portion is a single semiconductor
integrated circuit.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a photoelectric conversion device to be used
in image sensors employed in copying machines, facsimile machines, video cameras
and video recorders, optical sensors represented by AE sensors and AF sensors of
cameras and sensors for detecting positions of objects, more specifically, a photoelectric
conversion device suited to detect a light such as a micro spot light.
2. Related Background Art
FIGS. 1A to
1C respectively show an example of a conventional photoelectric
conversion device (sensor) and FIG. 1A shows a 2-dimensional sensor which has 16
sensor cells, as photoelectric conversion elements, in total, including four sensor
cells per line and four sensor cells per row.
In this sensor, each of lines is selected in sequence from the above in the drawing
by a vertical shift register VSR and four discrete signals are outputted by the
horizontal shift register HSR in time series sequence to the output terminal OUT.
Signals of these sensor cells are outputted in sequence in combinations of
line scanning and row scanning.
In an actual sensor, the number of sensor cells amounts to 100 to 100,000 and
therefore any method for reducing the read time and the scan time from one cell
is obviously limited.
On the other hand, those signals from the sensor cells are visible image signals
in most cases. In the case of such visible image, bright signals may be concentrated
only at an extremely small area in one frame as the flame of a match in darkness
and the remaining area may be occupied by dark signals.
Even in such case, the signals of all cells of the conventional sensor have
been outputted in time series sequence and accumulated in an external random access
memory, then required image signal processing has been carried out.
On the other hand, in case of the AE sensor (photo sensor for automatic exposure
control), the size of the cell is expanded to reduce the number of divided parts
and a configuration for ensuring short scanning time is used.
FIG. 1B shows a sensor as described above and each cell (SS
11 . .
. SS
22) has a larger light receiving area than the cell shown in FIG.
1A and the number of divisions is 4.
The sensor shown in FIG. 1B, however, cannot discriminate uniform irradiation
of weak light onto the whole light receiving surface of the cell (ma
1)
from irradiation of strong light only at a part of the light receiving surface
of the cell (ma
2) and therefore it is difficult to apply this sensor to
detection of a spot light onto a small area.
As described above, the sensor has required a long processing time or has malfunctioned
in detection of a light (ma
2) shown in FIG.
1C.
For example, FIG. 2 is a plan view of a pixel of a conventional bipolar sensor.
In FIG. 2,
51 is an emitter (serving as the main electrode area where signals
based on accumulated carriers are outputted),
52 is an output line formed
with AL or the like,
53 is a contact hole for connecting an emitter
51
and an output line
52,
54 is a base (serving as the control electrode
area) where an optical charge is accumulated,
55 is a drive line formed
with poly-Si or the like for sensor operation of the pixels,
56 is a capacitor
C
ox formed between the base
54 and the drive line
55,
and
57 is a gate of a MOS transistor which is formed with the base of an
adjacent pixel as a source and a drain, and comprises part of the drive line
55.
58 is a thick oxidized film for separation between pixels.
FIG. 3 is a sectional view as FIG. 2 is sectioned along line XX′ and
FIG. 4 is a sectional view as FIG. 2 is sectioned along line YY′. In FIGS.
3 and 4,
59 is a thin oxidized film,
60 is a high density n+ layer
provided to separate pixel signals in the YY′ direction,
61 is an
n epitaxial layer,
62 is a collector (serving as the main electrode area),
and
63 is an inter-layer insulation film for separating wires
52
and
55.
In addition, FIG. 5 is an equivalent circuit diagram of an area sensor which
is
formed with the above-described pixels arranged in 2-dimensional format.
In FIG. 5, S is a pixel of the sensor (equivalently comprising a bipolar transistor
31, a capacitor C
OX4 and a PMOS transistor
5),
1 is a vertical output line to be connected to the emitter of the pixel
S,
6 is a MOS transistor for resetting the vertical output line
1,
7 is a terminal for applying pulses to the gate of MOS transistor,
8
is a horizontal drive line,
9 is a buffer MOS transistor for receiving the
output of the vertical shift register and passing a sensor drive pulse,
10
is a terminal for applying the sensor drive pulse,
11 is a wire connected
to the drains of PMOS transistors at the right and left ends,
12 is an emitter-follower
circuit part for setting a source potential of the PMOS transistor
5 to
refresh the pixel S,
13 is a PMOS transistor for setting the base potential
of the emitter-follower
12,
14 is a power supply terminal connected
to the drain terminal of the PMOS transistor
13,
15 is a terminal
for applying pulses to the gate of the PMOS transistor
13,
18 is
an accumulation capacitor for accumulating output signal from the pixel S,
19
is a MOS transistor for transferring output signals to the accumulation capacitor
18,
20 is a terminal for applying pulses to the gate of the MOS transistor
for transfer,
21 is a horizontal output line,
22 is a MOS transistor
for receiving an output of a horizontal shift register and transferring output
signals to the horizontal output line
21,
50 is a MOS transistor
for resetting the horizontal output line
21,
23 is a terminal for
applying pulses to the gate of the MOS transistor
50, and
24 is an amplifier.
A 2-dimensional solid image pickup apparatus shown in FIG. 5 is such that all
pixels
are reset at once, and can be used in a still video camera and the like.
The operation of this image pickup apparatus is briefly described below.
First a low-level pulse is applied to the terminal
15 to set the PMOS
transistor to ON and the output of the emitter-follower circuit part to a positive
potential. The output terminal of this emitter-follower circuit part
12
is connected to the source of the PMOS transistor for the pixel S and, if the source
potential is sufficiently high enough to turn on the PMOS transistor
5 as
compared with the gate potential, holes are injected into the base of the bipolar
transistor
31 for pixels (referred to as the "first reset" up to this point).
Then the transistor
6 is set to ON and the vertical output line
1
is set to the GND level by applying a high-level pulse to the terminal
7.
Next a forward bias is formed between the base and the emitter of the bipolar
transistor
31 by driving the vertical shift register in the above state
and applying a reset pulse for the pixels to the terminal
10 to reset in
sequence the pixels of each line and set the base of the bipolar transistor
31
for all pixels to a fixed potential and to the reverse bias (referred to as the
"second reset" up to this point). After accumulation of photo carriers, a low-level
pulse is applied to the terminal
7 to set the MOS transistor
6 to
OFF, a read pulse is applied from the terminal
10 to each line selected
according to the output of the vertical shift register, a forward bias is formed
between the base and the emitter of the bipolar transistor
31, and the signal
output of pixels for each line is accumulated in the accumulation capacitor
18
through the MOS transistor
19. The signal output accumulated in the accumulation
capacitor
18 is transferred to the horizontal output line
21 through
the MOS transistor
22 for transfer selected by the horizontal shift register
and outputted through the amplifier
24.
In this case, the accumulation time (Ts) of the sensor is a time from the end
of the second reset to application of the read pulse to the terminal
10.
In the case of the 1-dimensional linear sensor, the maximum value of the signal
from each sensor cell (peak signal) is detected and the accumulation time is controlled
according to this maximum value and, in the case of the 2-dimensional area sensor,
it is difficult to detect the peak signal because of the property of the circuit
and therefore it is also difficult to obtain an appropriate signal level for the
whole image. For detecting a position of a pixel which presents the maximum or
maximal output on the light receiving surface, there has been a problem that information
(or all pixel outputs) should be used and therefore the signal processing time
would be longer and a memory would be required.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a photoelectric conversion device
capable of solving the above-described technical problems, detecting various types
of lights and improving the processing speed.
According to the embodiments of the present invention, the above-described
object of the present invention is accomplished by a photoelectric conversion device
which is provided with a plurality of groups each of which comprises a plurality
of adjacent photoelectric conversion elements and means for detecting a peak signal
of each of the above plurality of groups.
In other words, an embodiment of the present invention permits to carry out real-time
signal processing by dividing an sensor array comprising a plurality of cells into
a plurality of groups (blocks) and detecting the peak signal of each group.
A photoelectric conversion device according to another embodiment of the present
invention is provided with a 2-dimensional array of transistors having a control
electrode area which comprises first conductive type semiconductors and is able
to store carriers generated when photo energy is received, first and second main
electrode areas which comprise second conductive type semiconductors different
from the first conductive type semiconductors and from which the signals based
on accumulated carriers are outputted, and a third main electrode area which comprises
the second conductive type semiconductors, and has
a plurality of first common output lines to which the first main electrode area
is electrically connected in one array direction of the transistors,
a plurality of second common output lines to which the second main electrode
area
is electrically connected in the other array direction of the transistors,
a plurality of common drive lines to which the control electrode area is capacitively
connected in one array direction or the other array direction of the transistors, and
means for applying a potential for biasing at least one of first and second
main electrode areas and the control electrode area in the forward direction to
the control electrode areas of all transistors connected to the plurality of common
drive lines and outputting the peak signals based on the accumulated carriers of
a group of transistors to be connected to respective first common output lines
from the respective first common output lines or/and outputting the peak signals
based on the accumulated carriers of the group of transistors to be connected to
respective common output lines from the respective second common output lines.
A photoelectric conversion device according to a further another embodiment of
the present invention is provided with a 2-dimensional array of transistors having
a control electrode area which comprises first conductive type semiconductors and
is able to store carriers generated when photo energy is received, first and second
main electrode areas which comprise second conductive type semiconductors different
from the first conductive type semiconductors and from which the signals based
on accumulated carriers are outputted, and a third main electrode area which comprises
the second conductive type semiconductors, and has
a plurality of first common output lines to which the first main electrode area
is electrically connected in one array direction of the transistors,
a plurality of second common output lines to which the second main electrode
area
of partial or all transistors which are arrayed is electrically connected in common,
a plurality of common drive lines to which the control electrode area is capacitively
coupled in one array direction or the other array direction of the transistors,
means for applying a potential for biasing the second main electrode area and
the control electrode area in the forward direction to the control electrode areas
of partial or all transistors connected to the plurality of common drive lines
and outputting the peak signals based on the carriers accumulated in the partial
or all transistors from the respective second common output lines, and
means for applying a potential for biasing in sequence the first main electrode
area and the control electrode area in the forward direction to respective common
drive lines of the plurality of common drive lines and outputting the signals based
on the accumulated carriers from the first common output lines.
A photoelectric conversion device according to a further another embodiment of
the present invention is provided with a 2-dimensional array of transistors having
a control electrode area which comprises first conductive type semiconductors and
is able to store carriers generated when photo energy is received, a first main
electrode area which comprises second conductive type semiconductors different
from the first conductive type semiconductors and from which the signals based
on accumulated carriers are outputted, and a second main electrode area which comprises
the second conductive type semiconductors, and has
a plurality of first common output lines to which the first main electrode area
is electrically connected in one array direction of the transistors,
a plurality of buffer means the input sides of which are electrically connected
to the plurality of common output lines, respectively, and the output sides of
which are electrically connected in common,
a plurality of common drive lines to which the control electrode area is capacitively
connected in one array direction or the other array direction of the transistors,
means for applying a potential for biasing the first main electrode area and
the control electrode area in the forward direction to the control electrode area
of all transistors connected to the plurality of common drive lines and outputting
the peak signals based on the carriers accumulated in a group of transistors to
be connected to the respective common output lines, and
means for applying a potential for biasing in sequence the first main electrode
area and the control electrode area in the forward direction to respective common
drive lines of the plurality of common drive lines and outputting the peak signals
based on the accumulated carriers of the groups of transistors in the other array
direction from the output sides of the plurality of buffer means.
A photoelectric conversion device according to a further another embodiment of
the present invention is provided with a 2-dimensional array of transistors having
a control electrode area which comprises first conductive type semiconductors and
is able to store carriers generated when photo energy is received, a first main
electrode area which comprises second conductive type semiconductors different
from the first conductive type semiconductors and from which the signals based
on accumulated carriers are outputted, and a second main electrode area which comprises
the second conductive type semiconductors, and has
a plurality of common output lines to which the first main electrode area is
electrically
connected in one array direction of the transistors,
a plurality of first buffer means the input sides of which are electrically connected
to the plurality of common output lines, respectively, and the output sides of
which are electrically connected in common,
a plurality of second buffer means the input sides of which are electrically
connected
to the plurality of common output lines, respectively, and the output sides of
which are electrically connected to the accumulation means, respectively,
a plurality of common drive lines to which the control electrode area is capacitively
connected in one array direction or the other array direction of the transistors,
means for applying a potential for biasing the first main electrode area and
the control electrode area in the forward direction to respective common drive
lines of the plurality of common drive lines in sequence and outputting in sequence
the peak signals based on the carriers accumulated in a group of transistors in
the other array direction from the output side of the plurality of first buffer
means, and
means for outputting peak signals based on the accumulated carriers of the
groups of transistors in one array direction from the accumulation means after
a period while a bias potential is applied in sequence to respective common drive
lines of the plurality of common drive lines.
A photoelectric conversion device according to an embodiment of the present invention
is provided with two main electrode areas (first and second main electrode areas)
of transistors, which are 2-dimensionally arrayed, from which those signals based
on carriers accumulated in a control electrode area are outputted, a plurality
of first common output lines to which the first main electrode area is electrically
connected in one array direction of transistors, and a plurality of second common
output lines to which the second main electrode area is electrically connected
in the other array direction of transistors, and adapted to output peak signals
(for example, a peak signal per row) based on carriers accumulated in a group of
transistors in one array direction from the first common output lines and peak
signals (for example, a peak signal per line) based on carriers accumulated in
the group of transistors in the other array direction from the second common output
lines by applying a potential for biasing at least one of first and second main
electrode areas and the control electrode area in the forward direction (either
of the peak signal per row and the peak signal per line is satisfactory), and detect
a position of a pixel which provides the maximum or maximal output (a row or line
of pixels in the case of either of the peak signal per row and the peak signal
per line) on the 2-dimensional sensor plane in a short period of time by detecting
the peak signal per row and the peak signal per line.
For obtaining sensor signals from the transistors, the main electrode area for
reading the peak signal and the main electrode area for reading the sensor signals
can be jointly used. Specifically, the sensor signals can be read out (the signals
of the row and the line can be read out simultaneously) by applying a potential
for biasing at least one of first and second main electrode areas and the control
electrode area in the forward direction to the control electrode area for each
of rows or lines in sequence and a main electrode area (the fourth main electrode
area) for reading out the sensor signals can be provided in addition to the main
electrode area for reading out the peak signals.
A photoelectric conversion device according to another embodiment of the present
invention is provided with two main electrode areas (first and second main electrode
areas) of transistors, which are 2-dimensionally arrayed, from which those signals
based on carriers accumulated in the control electrode area are outputted, a plurality
of first common output lines to which the first main electrode area is electrically
connected in one array direction of transistors, and a plurality of second common
output lines to which the second main electrode area of partial or all transistors
is electrically connected in the other array direction of transistors, and adapted
to output the peak signals (peak signals of pixels in the partial or overall area
of the light receiving surface of the sensor) based on the carriers accumulated
in partial or all transistors from the second common output lines by applying a
potential for biasing the second main electrode area and the control electrode
area in the forward direction to the control electrode area of partial or all transistors.
The present invention allows to detect the peak signals of all sensors and finish
the accumulating operation under an appropriate dose of exposure during a period
of accumulating operation.
A photoelectric conversion device according to a further another embodiment of
the present invention is provided with one main electrode area (first main electrode
area) of transistors, which are 2-dimensionally arrayed, from which those signals
based on carriers accumulated in the control electrode area are outputted, a plurality
of common output lines to which the first main electrode area is electrically connected
in one array direction of transistors, and buffer means the input sides of which
are electrically connected to the plurality of common output lines, respectively
and the output sides of which are electrically connected in common, and adapted
to output peak signals (for example, a peak signal per row) based on carriers accumulated
in a group of transistors in one array direction from the common output lines to
the control electrode area of all arrayed transistors by applying a potential for
biasing the first main electrode area and the control electrode area in the forward
direction, and peak signals (for example, a peak signal per line) based on carriers
accumulated in a group of transistors in the other array direction from the output
side of the buffer means to the control electrode area of a group of transistors
in the other array direction in sequence by applying a potential for biasing the
first main electrode area and the control electrode area of the transistors in
the forward direction, and further detect a position of a pixel which provides
the maximum or maximal output (a row or line of pixels in the case of one of the
peak signal per row and the peak signal per line) on the 2-dimensional sensor plane
in a short period of time by detecting the peak signal per row and the peak signal
per line.
A photoelectric conversion device according to a further another embodiment of
the present invention is provided with one main electrode area (first main electrode
area) of transistors, which are 2-dimensionally arrayed, from which those signals
based on carriers accumulated in the control electrode area are outputted, a plurality
of common output lines to which the first main electrode area is electrically connected
in one array direction of transistors, first buffer means the input sides of which
are electrically connected to the plurality of common output lines, respectively,
and the output sides of which are electrically connected in common, and second
buffer means the input sides of which are electrically connected to the plurality
of common output lines, respectively, and the output sides of which are electrically
connected to accumulation means, and adapted to output peak signals (for example,
a peak signal per line) based on carriers accumulated in a group of transistors
in the other array direction from the output side of the first buffer means and
peak signals (for example, a peak signal per row) based on carriers of the group
of transistors in the one array direction accumulated in the accumulation means
during the period of applying the bias potential in sequence from the accumulation
means to detect the peak signal per row and the peak signal per line, and detect
a position of a pixel which provides the maximum or maximal output (a row or line
of pixels for detecting one of the peak signal per row and the peak signal per
line) on the 2-dimensional sensor plane within a short period of time. The present
invention disuses means for applying a bias potential to the control electrode
area of all transistors.
Other objects and features of the present invention will be known from the
following description and the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A-1C are respectively a typical diagram for illustrating a photoelectric
conversion device according to the related art;
FIG. 2 is a plan view of pixels of a bipolar transistor according to the related art;
FIG. 3 is a sectional view along line XX′ in FIG. 2.
FIG. 4 is a sectional view along line YY′ in FIG. 2;
FIG. 5 is an equivalent circuit diagram of an area sensor comprising a 2-dimensional
array of pixels shown in FIG. 2;
FIG. 6 is a schematic circuit diagram of a photoelectric conversion device according
to a mode of the present invention;
FIG. 7 is a schematic circuit diagram of a photoelectric conversion device according
to an embodiment of the present invention;
FIG. 8 is a timing chart for illustrating the operation of the photoelectric
conversion device according to the first embodiment;
FIG. 9 is a schematic circuit diagram of the photoelectric conversion device
according to the second embodiment of the present invention;
FIG. 10 is a timing chart for illustrating the operation of the photoelectric
conversion device according to the second embodiment;
FIG. 11 is a schematic circuit diagram of the photoelectric conversion device
according to the third embodiment of the present invention;
FIG. 12 is a schematic circuit diagram of the photoelectric conversion device
according to the fourth embodiment of the present invention;
FIG. 13 is a schematic circuit diagram of the photoelectric conversion device
according to the fifth embodiment of the present invention;
FIG. 14 is a schematic circuit diagram of the photoelectric conversion device
according to the sixth embodiment of the present invention;
FIG. 15 is a schematic circuit diagram of the photoelectric conversion device
according to the seventh embodiment of the present invention;
FIG. 16 is a schematic circuit diagram of the photoelectric conversion device
according to the eighth embodiment of the present invention;
FIG. 17 is a schematic circuit diagram showing the first embodiment of the photoelectric
conversion device according to the present invention;
FIG. 18 is a timing chart of pulses for driving the photoelectric conversion
device shown in FIG. 1;
FIG. 19 is a schematic circuit diagram showing the second embodiment of the
photoelectric conversion device according to the present invention;
FIG. 20 is a schematic circuit diagram showing the third embodiment of the photoelectric
conversion device according to the present invention;
FIG. 21 is a schematic circuit diagram showing the fourth embodiment of the
photoelectric conversion device according to the present invention;
FIG. 22 is a schematic circuit diagram showing a modification of the fourth
embodiment of the photoelectric conversion device according to the present invention;
FIG. 23 is a schematic circuit diagram showing the fifth embodiment of the photoelectric
conversion device according to the present invention;
FIG. 24 is a schematic circuit diagram showing the sixth embodiment of the photoelectric
conversion device according to the present invention;
FIG. 25 is a schematic circuit diagram showing the embodiment of the photoelectric
conversion device according to the present invention;
FIG. 26 is a schematic circuit diagram of a buffer; and
FIG. 27 is a schematic circuit diagram of a buffer.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 6 is a schematic circuit diagram showing an embodiment according to the
present invention and Sij (i=1, 2, 3, 4; j=1, 2, 3, 4).
Sensor cells are divided into four blocks each having four adjacent cells
and the signal output line is commonly connected to the horizontal shift registers
(HSR
1 and HSR
2) for these blocks.
A block is selected by the vertical shift register VSR and the horizontal shift
register and a peak signal is outputted to the terminal out
1 or out
2.
Horizontal shift registers can be, of course, assembled into a single unit with
one output terminal and the peak signals from four blocks can be outputted in parallel
from four output terminals.
Sensor cells to be used for the present invention are required if a signal
of a cell which receives the largest amount of light is generated on the output
line when the output line is commonly connected, and a photo transistor which stores
a photo carrier in the control electrode area such as the base or the gate is preferably used.
Sensor cells are available in a line sensor mode in which the cells are arranged
in a 1-dimensional array or an area sensor mode in which the cells are arranged
in a 2-dimensional array. The size of the light receiving surface of each cell
and the number of cells in each block are appropriately selected and designed in
accordance with an application of the sensor. In addition, sensor cells are housed
in a single chip as a semiconductor integrated circuit. Signals outputted from
this sensor chip are processed as image signals in diversified ways by external circuits.
The first embodiment of the present invention is described, referring to FIG.
7. Bij (i, j=1, 4) is a bipolar transistor as a photo sensor cell, Pij (i,
j=1, 4) is a P type MOS switch provided between the base areas of the above-described
bipolar transistor, Mij (i, j=1, 4) is a MOS switch; M
1j (j=1-4) is
a MOS switch for resetting the sensor output line, M
2j (j=1-4) is a
switch for transferring signals from the output line to the capacitor, M
3j
(j=1-4) is a switch for resetting the potential of the signal readout capacitor
Cj (j=1-4), M
4j (j=1-4) is a switch for selectively supplying output
signals to the output line Y
1 according to clock signals φ
1,
φ
2, φ
3 and φ
4 from the shift
register, and M
5 is a switch for resetting the output line
1.
Y
2 is a shift register and Y
3 is an output amplifier.
A method for operating this sensor is described below, referring to the timing
chart shown in FIG.
8.
The vertical output line VLi (i=1-4) is reset to V
VC voltage and the
readout capacitor Cj (j=1-4) is reset to J
CR voltage by applying a high
level pulse φ
VC to the N type MOS switch M
1j (j=1-4)
and a high level pulse φ
CR to the N type MOS switch M
3j (j=1-4).
Next the pulse φ
BR of the P type MOS gate is set to a low level
to set the P type MOS to ON and the base potential of the bipolar transistor of
Pij (ij=1-4) is set to V
BR. In this case, a voltage of V
BR should
be set to be approximately at least 1V higher than V
VC. When the pulse
φ
BR is set again to a high level after the pulse φ
BR
to the P type MOS gate has been set to a high level and the P type MOS has
been set to OFF, and the vertical line level is set to V
VC, the bipolar
transistor is set to the forward bias and the base potential is converged to the
constant potential determined by the emitter potential V
VC. As shown
in FIG. 7, the emitters of P
11, P
12, P
21 and P
22
are commonly connected to the vertical line VL
1 and therefore
the bases of the above four bipolar transistors are reset by the potential of the
vertical line VL
1. A similar procedure is executed with respect to bipolar
transistors of B
13, B
14, B
23 and B
24 blocks,
bipolar transistors of B
31, B
32, B
41 and B
42
blocks, and bipolar transistors of B
33, B
34, B
43
and B
44.
When the pulse φ
VC is set to a low level, the vertical lines
VL
1-VL
4 come in a floating state and the accumulation period
(Y
4 in FIG. 8) of an optical signal of each cell starts.
The pulse φ
T is set to a high level to transfer signals to the
signal readout capacitor Cj (j=1-4). In this case, the potential V
CR for
resetting the readout capacitor should be set to be lower than the vertical line
reset potential V
VC. If the voltage and related factors are set in advance
as described above, the potential of the vertical line becomes lower than that
in the preceding period when the N type MOS switch M
2j (j=1-4) is set
to ON by the φ
T pulse, and the bipolar transistor Bij (ij=1-4)
is set to the forward bias. In this case, the base-emitter bias of the bipolar
transistor of a cell which has the largest optical signal level among cells is
largest in each block and the emitter potential has a value corresponding to the
peak optical signal in that block.
When the φ
T pulse is set to a low level, a peak signal in B
11,
B
12, B
21 and B
22 is read out to the capacitor
C
2, a peak signal in B
13, B
14, B
23 and
B
24 is read out to the capacitor C
3, a peak signal in B
33,
B
34, B
43 and B
44 is read out to the capacitor C
4.
Signals accumulated in the capacitors according to scanning pulses φ
1,
φ
2, φ
3 and φ
4 through the shift
register
2 are outputted from the amplifier Y
3 through the output
line
1.
Since 2-dimensional information is compressed to a peak signal of a block area
and is serially read out, all sensors are extremely useful as means for determining
an image at a high speed in a wide area to check, for example, whether a light
of an object has been detected on the sensors.
Specifically, when a user observes a camera, a microscope or the like,
a light of the LED which is flickering with external pulses irradiates at and reflects
from an eye of the user. If this reflected light is detected by the sensor according
to the present invention, the reflected light of the LED light is quickly detected
in high accuracy and the presence of the user can be determined. Accordingly, it
is clearly known that the device can be easily started.
As another application, the sensor according to the present invention is greatly
useful in detection of opening and closing of the eyes of an automobile driver.
An external LED light is irradiated to the eyes of a driver according to the above
method and the reflected light is received by the sensor of the invention. Though
a high intensity signal can be detected if the light is reflected from an eye with
a normal cornea, the intensity of the reflected light lowers when a driver is sleepy
and a time of the closed eyelids becomes long. When the sensor output is lower
than the average intensity of the reflected light, a sleepiness preventing apparatus
including a buzzer and a seat shaker to give a warning to the driver can be materialized.
The peak signal information of the blocks is useful to detect product labels
on factory lines. In addition, it can be also attained by the following structure
to distinguish the peak signal of each block from the external light. A capacitor
is connected to each peak output portion in series and signal accumulation is performed
under the external light to clamp the accumulated signal at its level. Subsequently,
accumulation is performed under signal light to detect change of a peak output.
A comparator determines whether the detected change exceeds a predetermined level.
A second embodiment of the invention is described, referring to FIG. 9 showing
an equivalent circuit diagram and FIG. 10 showing the timing chart. The same components
as those in the embodiment 1 are given the same reference symbols and numerals
and the descriptions of these components are omitted.
The second embodiment differs from the first embodiment in that each sensor cell
is provided with a base potential control capacitor Cij (ij=1-4) for carrying out
a reversely biased accumulating operation. Such construction as described above
eliminates a switch for resetting a capacitor for readout operation.
The operation is described below. Pulses φ
VC and φ
T
are set to a high level and the vertical lines VL
1-VL
4 and
the capacitor Ci (i=1-4) to V
VC.
The φ
BR pulse is changed over from an intermediate level to
a low level to set the P type MOS to ON and the base potential is reset to the
V
BR. After resetting, the pulse is reset to the intermediate level.
In this state, the V
BR level can be selected so that the bipolar transistor
is set at OFF.
Then, after the φ
VC pulse is set to the high level to set
the vertical lines VL
1-VL
4 to the V
VC level, the φ
BR
pulse is changed over from the intermediate level to the high level. Thus
the base potential of each bipolar transistor is increased as much as given below
through the capacitor Cij (ij=1-4).
##EQU1##
In this case, the reset voltages V
VC and V
BR of the bipolar
transistor can be set at a bias value at which the current flows in the forward direction.
As in the first embodiment, the emitters of bipolar transistors of B
11,
B
12, B
21 and B
22 blocks are connected to a common
VL
1 line and therefore the current flows from this line and is reset to
the base potential corresponding to the emitter potential. This is the same with
the blocks of other bipolar transistors. After the current has been converged,
the φ
BR pulse is reset to the intermediate level and simultaneously
the φ
BR pulse of the MOS for resetting is set to a low level to
start accumulation of signals. Sensor cells are separated by a P type MOS Pij (ij=1-4).
If the φ
BR pulse and the φ
T pulse are set to
a high level after completion of the accumulation, the peak signals of blocks are
read out to capacitors C
1-C
4. Subsequent readout is the same
as in the first embodiment.
The third embodiment is described below, referring to FIG.
11. The same
components as those in the embodiment
1 are given the same reference symbols
and numerals and the descriptions of these components are omitted. In this embodiment,
the wiring has been improved to ensure a symmetry with the vertical lines VL
1-VL
4
of the first embodiment.
The vertical line VL
1 is extended on B
31, B
32, B
41
and B
42 blocks of bipolar transistors to be symmetrical to the vertical
line VL
2 and the vertical line VL
3 is extended on B
33, B
34,
B
43 and B
44 blocks of bipolar transistors to be symmetrical to the
vertical line VL
4. With this arrangement, the parasitic capacities of the
vertical lines are aligned to enable to align the readout gains of all blocks and
therefore deviations among the blocks are reduced.
The fourth embodiment is described, referring to FIG.
12. The fourth embodiment
differs from the first to third embodiments in that the outputs of all peak output
detection blocks BL
1-BL
4 are not read out in one direction but are
read in parallel in upper and lower directions and therefore the readout speed
is improved.
72 and
73 are respectively a shift register,
74,
80 and
80′ are readout circuits for reading out the signals
of blocks BL
1, BL
2, BL
3 and BL
4,
76,
77,
78 and
79 are vertical output lines of the blocks, and
70
and
71 are horizontal output lines.
The fifth embodiment is described, referring to FIG.
13. In this embodiment,
the number of blocks is increased by using two types of vertical output lines,
for example, a first A
1 wire and a second A
1 wire. 81 output lines
for BL
11, 83 output lines for BL
12, 85 output lines for BL
21
and 87 output lines for BL
22 are used respectively and, for example, the
A
11 wire is used for these output lines, while 82 output lines for BL
31,
84 output lines for BL
32, 86 output lines for BL
41 and 88 output
lines for BL
42 are used respectively and the A
12 wire is used for
these output lines. The signals from these output lines are read out in parallel
into the readout circuits
90-
97, scanned in the shift register
98
and outputted to the shift register
99. It is clearly known that the number
of divided blocks can be increased by combining the embodiments as described above.
The sixth embodiment is described, referring to FIG.
14. The sixth embodiment
is intended to simultaneously implement reading out of ordinary bits in addition
to the peak signal of a desired block area of the sensor.
100 denotes a
vertical shift register for driving the drive line for reading the bits. MOS switches
M
5j (j=1-4) are provided to collect the peak signals of pixels of two
rows from the left and the peak signals of pixels of two rows from the right. The
former peak signals are collected to
101 and the latter peak signals are
collected to
102 according to the φ
P pulse and entered
into comparators
103 and
104 for comparison with the reference level
VREF. In this embodiment, the peak signals of respective blocks are not serially
converted but are simultaneously outputted and a decision signal for checking whether
or not the peak signal has reached a higher peak value than required value and
therefore a state of image can be quickly determined from the above peak data.
On the other hand, the data accumulated in each pixels, are outputted by the
device
operation described with respect to the first embodiment.
Since the peak signals of a desired block of the image and the pixel signals
are simultaneously outputted as described above, the pixel signals can be read
out only when rough image information is obtained with the peak signals of the blocks.
The seventh embodiment of the invention is described, referring to FIG.
15.
Though the reference level VREF and the peak signal are compared in the sixth
embodiment, the seventh embodiment differs from the sixth embodiment in that the
reference level in the seventh embodiment is defined as the darkness level. MOS
switches M
6j (j=1-4) are for changing over the output before and after
accumulation and their switching operations are controlled with pulses φ
S
and φ
N. The φ
N pulse is set to a high level before
accumulation and its output is accumulated in capacitors C
6 and C
8,
respectively, through the MOS switches M
62 and M
64. After
storing the optical signals, the φ
S pulse is set to a high level
and its output is accumulated in capacitors C
5 and C
7, respectively,
through the MOS switches M
61 and M
63. The peak signals of
the block can be detected in reference to the darkness level by entering respective
values of the outputs into comparators
103 and
104.
The configuration of this embodiment is advantageous in that not only whether
there is an incident light to the sensor can be easily determined but also stable
results can be obtained even with environmental changes because the output at the
time of darkness and the output when a light is irradiated change in the same way
even if a change of temperature or the like occurs.
The eighth embodiment is described, referring to FIG.
16. This embodiment
employs a configuration in which the sensor bipolar block B′ ij (ij=1-4)
is provided with two emitters, one of which is provided exclusively for reading
the pixel signals and the other of which is provided for detecting the peak signals,
the peak signal output being connected to the gate of the amplifier.
The MOS amplifier comprises MOS switches M
7i (i=1-4) and a switch
M
75 and the peak outputs of the blocks are entered into the gates of
MOS switches M
7i (i=1-4). Reset switches M
8j (j=1-4) and
a reset pulse φ
RS-EM are provided to reset the vertical lines
for detecting the pea
