Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof Number:7,091,579 from the United States Patent and Trademark Office (PTO) owispatent

Title: Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof

Abstract: Impurity concentration (N.sub.d(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration N.sub.p to an averaged impurity concentration N.sub.dm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.

Patent Number: 7,091,579 Issued on 08/15/2006 to Nemoto

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Inventors:	Nemoto; Michio (Nagano, JP)
Assignee:	Fuji Electric Co., Ltd. (JP)
Appl. No.:	10/371,163
Filed:	February 20, 2003

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Foreign Application Priority Data

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Feb 20, 2002 [JP]			2002-042469
Jul 24, 2002 [JP]			2002-214657

Current U.S. Class:	257/656 ; 257/655; 257/657
Current International Class:	H01L 31/075 (20060101); H01L 31/105 (20060101); H01L 31/117 (20060101)
Field of Search:	257/655,656,657,658

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References Cited [Referenced By]

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U.S. Patent Documents

	6060745		May 2000		Tadokoro et al.
	6798001		September 2004		Fujisawa et al.

Foreign Patent Documents

	401082563		Sep., 1987		JP
	11-26779		Jan., 1999		JP
	2000-223720		Aug., 2000		JP

Other References

"An Advanced FWD Design Concept with Superior Soft Reverse Recovery Characteristics"; Nemoto et al.; ISPSD'2000 Copyright by the IEEE. Catalog No.: 00CH37094C; 4 pgs. cited by other . "Great Improvement in IGBT Turn-on Characteristics with Trench Oxide PiN Schottky (TOPS) Diode"; M. Nemoto et al.; Proceedings of 2001 Inter. Symposium on Power Semiconductor Devices & ICs, Osaka, Japan; pgs. 307-310. cited by other . "The Pinch Rectifier: A Low-Forward-Drop High Speed Power Diode"; B.J. Baliga; IEEE Electron Device Letters, vol. EDL-5, No. 6; Jun. 1984; pp. 194-196. cited by other . A Novel Soft and Fast Recovery Diode (SFD) with Thin P-Layer Formed by Al-Si Electrode; Mutsuhiro Mori et al.; CH2987-6/91/000-0113; IEEE 1991; pp. 113-117. cited by other . "Power Semiconductor Devices"; B.Baliga; PWS Publishing Company, Boston, MA; p. 73. cited by other.

Primary Examiner: Flynn; Nathan J.
Assistant Examiner: Mandala, Jr.; Victor A.
Attorney, Agent or Firm: Rossi, Kimms & McDowell, LLP

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Claims

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What is claimed is:

1. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, wherein the entire first semiconductor layer is thicker than at least one of the second semiconductor layer or the third semiconductor layer.

2. The semiconductor layer as claimed in claim 1, wherein the impurity concentration decreases with the inclination toward each of the second semiconductor layer and the third semiconductor layer to reach each of the second semiconductor layer and the third semiconductor layer.

3. The semiconductor device as claimed in claim 2, wherein in the first semiconductor layer, an impurity concentration at an interface with the third semiconductor layer is higher than an impurity concentration at an interface with the second semiconductor layer.

4. The semiconductor device as claimed in claim 1, wherein the relative maximum impurity concentration is located at a plurality of positions in the direction from the second semiconductor layer to the third semiconductor layer, and the impurity concentration of the first semiconductor layer decreases from each of the positions at each of which the impurity concentration reaches the relative maximum with an inclination toward each of the second semiconductor layer and the third semiconductor layer.

5. The semiconductor device as claimed in claim 1, wherein the impurity concentration becomes constant with a specified concentration in a region on each of a side of the second semiconductor layer and a side of the third semiconductor layer, and wherein a maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.p/J.sub.dm.ltoreq.5, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

6. The semiconductor device as claimed in claim 5, wherein the specified impurity concentration made constant on the side of the third semiconductor layer is higher than that on the side of the second semiconductor layer.

7. The semiconductor device as claimed in claim 5, wherein an impurity concentration N.sub.d(X.sub.j) in the first semiconductor layer at a position of the interface with the second semiconductor layer, which position is at a distance X.sub.j from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, satisfies a relationship expressed as .function..times..times..times..ltoreq. ##EQU00016## where BV is a breakdown voltage of a semiconductor element.

8. The semiconductor device as claimed in claim 5, wherein a lifetime distribution of minority carriers becomes shortest near the interface between the first semiconductor layer and the second semiconductor layer, and becomes longest in the first semiconductor layer near the interface between the first semiconductor layer and the third semiconductor layer.

9. The semiconductor device as claimed in claim 5, wherein an efficiency of minority carrier injection into the first semiconductor layer is equal to or less than 0.7.

10. The semiconductor device as claimed in claim 5, wherein the specified impurity concentration made constant on the side of the second semiconductor layer is equal to that on the side of the third semiconductor layer.

11. The semiconductor device as claimed in claim 5, wherein the maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.2, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

12. The semiconductor device as claimed in claim 5, wherein the third semiconductor layer has a surface impurity concentration equal to or greater than 1.times.10.sup.17 cm.sup.-3, and an integrated impurity concentration in the first semiconductor layer from the interface with the second semiconductor layer to the interface with the third semiconductor layer is between 8.times.10.sup.11 cm.sup.-2 and 2.times.10.sup.12 cm.sup.-2.

13. The semiconductor device as claimed in claim 5, wherein of positions at boundaries at each of which the impurity concentration decreasing from the maximum concentration becomes constant with the specified concentration, with a position on the side of the second semiconductor layer taken at a distance Xa from an end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, and a position on the side of the third semiconductor layer taken at a distance Xb from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, an integrated impurity concentration .times..function..times.d ##EQU00017## in the first semiconductor layer in a region from the distance Xa to the distance Xb satisfies a relationship expressed as .intg..times..times..times..times..times..function..times..times.d.ltoreq- ..times. ##EQU00018## where X is a distance from an end of the second semiconduc tor layer opposite to the first semiconductor layer to a position in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, and N.sub.d(X) is the impurity concentration distribution about a distance X in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer.

14. The semiconductor device as claimed in claim 13, wherein the integrated impurity concentration in the first semiconductor layer from the interface with the second semiconductor layer to the interface with the third semiconductor layer is between 8.times.10.sup.11 cm.sup.-2 and 1.3.times.10.sup.12 cm.sup.-2.

15. The semiconductor device as claimed in claim 13, wherein the integrated impurity concentration .intg..times..times..times..times..times..function..times..times.d ##EQU00019## in the first semiconductor layer in the region from the distance Xa to the distance Xb satisfies a relationship expressed as .intg..times..function..times.d.ltoreq..times..times..times. ##EQU00020## where N.sub.d(X) is the impurity concentration distribution about a distance X in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer.

16. The semiconductor device as claimed in claim 5, wherein a distance Xp from the end of the second semiconductor layer opposite to the first semiconductor layer to a position, at which the impurity concentration in the first semiconductor layer becomes the maximum in the direction from the second semiconductor layer to the third semiconductor layer, satisfies a relationship expressed as .ltoreq..times..times..times..times..times..times..function..times..times- ..times..times..times..times..times..times..ltoreq. ##EQU00021## where BV is a breakdown voltage of a semiconductor element, .epsilon..sub.s is a semiconductor permittivity, q is the elementary electric charge, J.sub.F is a rated current density of the semiconductor element, .nu..sub.sat is a carrier saturation velocity, and N.sub.dm is the averaged impurity concentration in the first semiconductor layer.

17. The semiconductor device as claimed in claim 16, wherein the distance Xp satisfies a relationship expressed as .ltoreq..times..times..function..times..times..ltoreq. ##EQU00022## where BV is a breakdown voltage of a semiconductor element, .epsilon..sub.s is a semiconductor permittivity, q is the elementary electric charge, J.sub.F is a rated current density of the semiconductor element, V.sub.sat is a carrier saturation velocity, and N.sub.dm is the averaged impurity concentration in the first semiconductor layer.

18. A semiconductor device comprising: a first semiconductor layer of a first conduction type: a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, and wherein a maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.5, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

19. The semiconductor layer as claimed in claim 18, wherein the first semiconductor layer has an impurity concentration that reaches a relative maximum at least at one position in a direction from the second semiconductor layer to the third semiconductor layer, and wherein the impurity concentration of the first semiconductor layer decreases from the position at which the impurity concentration becomes the relative maximum with the impurity concentration thereof decreasing toward each of the second semiconductor layer and the third semiconductor layer.

20. The semiconductor device as claimed in claim 18 wherein the impurity concentration decreases with the inclination toward each of the second semiconductor layer and the third semiconductor layer to reach each of the second semiconductor layer and the third semiconductor layer.

21. The semiconductor device as claimed in claim 18, wherein the maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.2, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

22. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, and wherein an integrated impurity concentration .intg..times..function..times..times.d ##EQU00023## in the first semiconductor layer, which is in a region between a position nearest to the second semiconductor layer of positions at each of which the impurity concentration in the first semiconductor layer becomes equal to the averaged impurity concentration N.sub.dm and a position nearest to the third semiconductor layer of the positions at each of which the impurity concentration in the first semiconductor layer becomes equal to the averaged impurity concentration N.sub.dm, satisfies a relationship expressed as .intg..times..function..times..times.d.ltoreq..times..times..times. ##EQU00024## where X is a distance from an end of the second semiconductor layer opposite to the first semiconductor layer to a position in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, N.sub.d(X) is the impurity concentration distribution about the distance X in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, Xc is a distance from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer to the position nearest to the second semiconductor layer of positions at each of which N.sub.d(X) becomes N.sub.d(X)=N.sub.dm, and Xd is a distance from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer to the position nearest to the third semiconductor layer of the positions at each of which N.sub.d(X) becomes N.sub.d(X)=N.sub.dm.

23. The semiconductor device as claimed in claim 22, wherein the integrated impurity concentration in the first semiconductor layer from the interface with the second semiconductor layer to the interface with the third semiconductor layer is between 8.times.10.sup.11 cm.sup.-2 and 1.3.times.10.sup.12 cm.sup.-2.

24. The semiconductor device as claimed in claim 22, wherein the integrated impurity concentration .intg..times..function..times..times.d ##EQU00025## in the first semiconductor layer in the region from the distance Xc to the distance Xb satisfies a relationship expressed as .intg..times..function..times..times.d.ltoreq..times..times..times. ##EQU00026## where N.sub.d(X) is the impurity concentration distribution about a distance X in the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, Xc is a distance from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer to the position nearest to the second semiconductor layer of positions at each of which N.sub.d(X) becomes N.sub.d(X)=N.sub.dm, Xd is a distance from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer to the position nearest to the third semiconductor layer of the positions at each of which N.sub.d(X) becomes N.sub.d(X)=N.sub.dm, and N.sub.dm is the averaged impurity concentration in the first semiconductor.

25. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, wherein the first semiconductor layer has an impurity concentration that reaches a relative maximum at least at one position in a direction from the second semiconductor layer to the third semiconductor layer, and wherein the impurity concentration of the first semiconductor layer decreases from the position at which the impurity concentration becomes the relative maximum with the impurity concentration thereof decreasing toward each of the second semiconductor layer and the third semiconductor layer, and wherein a distance Xp from the end of the second semiconductor layer opposite to the first semiconductor layer to a position, at which the impurity concentration in the first semiconductor layer becomes the maximum in the direction from the second semiconductor layer to the third semiconductor layer, satisfies a relationship expressed as .ltoreq..times..times..function..times..times..ltoreq. ##EQU00027## where BV is a breakdown voltage of a semiconductor element, .epsilon..sub.s is a semiconductor permittivity, q is the elementary electric charge, J.sub.F is a rated current density of the semiconductor element, .nu..sub.sat is a carrier saturation velocity, and N.sub.dm is the averaged impurity concentration in the first semiconductor layer.

26. The semiconductor device as claimed in claim 25, wherein the distance Xp satisfies a relationship expressed as .ltoreq..times..times..times..times..times..times..function..times..times- ..times..times..times..times..times..times..ltoreq. ##EQU00028## where BV is a breakdown voltage of a semiconductor element, .epsilon..sub.s is a semiconductor permittivity, q is the elementary electric charge, J.sub.F is a rated current density of the semiconductor element, V.sub.sat is a carrier saturation velocity, and N.sub.dm is the averaged impurity concentration in the first semiconductor layer.

27. The semiconductor device as claimed in claim 23, wherein the third semiconductor layer has a surface impurity concentration equal to or more than 1.times.10.sup.17 cm.sup.-3, and an integrated impurity concentration in the first semiconductor layer from the interface with the second semiconductor layer to the interface with the third semiconductor layer is between 8.times.10.sup.11 cm.sup.-2 and 2.times.10.sup.12 cm.sup.-2.

28. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, and wherein an impurity concentration N.sub.d(X.sub.j) in the first semiconductor layer at a position of the interface with the second semiconductor layer, which position is at a distance X.sub.j from the end of the second semiconductor layer opposite to the first semiconductor layer in the direction from the second semiconductor layer to the third semiconductor layer, satisfies a relationship expressed as .function..times..times..times..ltoreq. ##EQU00029## where BV is a breakdown voltage of a semiconductor element.

29. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, and wherein a lifetime distribution of minority carriers becomes shortest near the interface between the first semiconductor layer and the second semiconductor layer, and becomes longest in the first semiconductor layer near the interface between the first semiconductor layer and the third semiconductor layer.

30. The semiconductor device as claimed in claim 29, wherein the impurity concentration decreases with the inclination toward each of the second semiconductor layer and the third semiconductor layer to reach each of the second semiconductor layer and the third semiconductor layer, and wherein a maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.pN.sub.dm.ltoreq.5, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

31. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, and wherein an efficiency of minority carrier injection into the first semiconductor layer is equal to or less than 0.7.

32. The semiconductor device as claimed in claim 31, wherein the impurity concentration decreases with the inclination toward each of the second semiconductor layer and the third semiconductor layer to reach each of the second semiconductor layer and the third semiconductor layer, and wherein a maximum impurity concentration N.sub.p in the first semiconductor layer satisfies a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.5, where N.sub.dm is an averaged impurity concentration in the first semiconductor layer.

33. A method of manufacturing a semiconductor device comprising a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, with impurities reaching one of a proximity and an end of each of the second semiconductor layer, and wherein the entire first semiconductor layer is thicker than at least one of the second semiconductor layer or the third semiconductor layer, the method comprising the steps of: providing the first semiconductor layer; and growing the first semiconductor epitaxially and controlling the impurity concentration.

34. The method of manufacturing a semiconductor device as claimed in claim 33, further comprising the steps of: preparing a semiconductor substrate of the first conduction type as the third semiconductor layer; forming the first semiconductor layer on the third semiconductor layer by carrying out epitaxial growth to a specified first position in a direction opposite to the third semiconductor layer while making the content of the impurities of the first conduction type constant, then by carrying out epitaxial growth to a specified second position in the direction opposite to the third semiconductor layer while gradually increasing the content of the impurities of the first conduction type, thereafter by carrying out epitaxial growth to a specified third position in the direction opposite to the third semiconductor layer while gradually decreasing the content of the impurities of the first conduction type, and by carrying out epitaxial growth while making the content of the impurities of the first conduction type constant again; and forming the second semiconductor layer by diffusing impurities of the second conduction type on the surface of a region in which the content of the impurities is made constant in the first semiconductor layer formed by carrying out the epitaxial growth.

35. The method of manufacturing a semiconductor device as claimed in claim 33, further comprising the steps of: preparing a semiconductor substrate of the first conduction type as the third semiconductor layer, carrying out ion implantation with impurity ions of the first conduction type on a surface of the third semiconductor layer; forming the first semiconductor layer on the the surface of the third semiconductor layer by carrying out epitaxial growth while making the content of the impurities of the first conduction type constant; diffusing te ion-implanted impurities into the first semiconductor layer and the third semiconductor layer by carrying out heat treatment; forming the second semiconductor layer by diffusing impurities of the second conduction type on the surface of the first semiconductor layer; thinning the third semiconductor layer; and forming a semiconductor layer of a first conduction type with a high impurity concentration on the surface of the third semiconductor layer.

36. A method of manufacturing a semiconductor device comprising a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, with impurities reaching one of a proximity and an end of each of the second semiconductor layer and the third semiconductor layer, and wherein the entire first semiconductor layer is thicker than at least one of the second semiconductor laver or ther third semiconductor layer, the method comprising the steps of: providing the first semiconductor layer; and growing the first semiconductor epitaxially and controlling the impurity concentration.

37. The method of manufacturing a semiconductor device as claimed in claim 33, further comprising the steps of: preparing a semiconductor substrate of the first conduction type as the third semiconductor layer; forming the first semiconductor layer on the third semiconductor layer by carrying out epitaxial growth to a specified position in a direction opposite to the third semiconductor layer while gradually increasing the content of the impurities of the first conduction type, and then by carrying out epitaxial growth while gradually decreasing the content of the impurities of the first conduction type, and forming the second semiconductor layer on the surface of the first semiconductor layer.

38. The method of manufacturing a semiconductor device as claimed in claim 37, further comprising the steps of: thinning the third semiconductor layer; and forming a semiconductor layer of a first conduction type with a high impurity concentration on a surface of the third semiconductor layer.

39. The method of manufacturing a semiconductor device as claimed in claim 33, further comprising the steps of: preparing a semiconductor substrate of the first conduction type as the third semiconductor layer; forming the first semiconductor layer on the third semiconductor layer by carrying out first epitaxial growth to a specified first position in a direction opposite to the third semiconductor layer while making the content of the impurities of the first conduction type constant to form a first epitaxial layer, by carrying out ion implantation with impurity ions of the first conduction type on a surface of the first epitaxial layer, and then by carrying out second epitaxial growth on the surface of the first epitaxial layer while making the content of the impurities of the first conduction type constant to form a second epitaxial layer; heat treating the first semiconductor layer formed with the first and second epitaxial layers to diffuse the ion-implanted impurities into the first and the second epitaxial layers; and forming the second semiconductor layer by diffusing impurities of the second conduction type on the surface of the first semiconductor layer.

40. The method of manufacturing a semiconductor device as claimed in claim 39, wherein the ion-implanted impurities are diffused toward the second semiconductor layer and the third semiconductor layer to positions respectively reaching the second semiconductor layer and the third semiconductor layer.

41. The method of manufacturing a semiconductor device as claimed in claim 39, wherein the ion-implanted impurities are diffused toward the second semiconductor layer and the third semiconductor layer to positions respectively apart from the second semiconductor layer and the third semiconductor layer.

42. The method of manufacturing a semiconductor device as claimed claim 37, wherein a dose of the ion implantation is equal to or less than 5.times.10.sup.11 cm.sup.-2.

43. The method of manufacturing a semiconductor device as claimed in claim 42, wherein a dose of the ion implantation is equal to or less than 3.times.10.sup.11 cm.sup.-2.

44. The method of manufacturing a semiconductor device as claimed in claim 39, wherein a temperature of the heat treatment is between 1200.degree. C. and 1412.degree. C.

45. The method of manufacturing a semiconductor device as claimed in claim 33, further comprising the steps of: preparing a semiconductor substrate of the first conduction type as the third semiconductor layer; forming the first semiconductor layer on the third semiconductor layer by carrying out epitaxial growth while making the content of the impurities of the first conduction type constant; forming the second semiconductor layer of the second conduction type on the surface of the first semiconductor layer; implanting light ions into the first semiconductor layer by making the ions penetrate one of the second semiconductor layer and the third semiconductor layer; and carrying out heat treatment to electrically activate a region implanted with the light ions.

46. The method of manufacturing a semiconductor device as claimed in claim 45, wherein the heat treatment is carried out so that the light ions exist in a direction from the second semiconductor layer to the third semiconductor layer up to at least one of positions respectively reaching the second semiconductor layer and the third semiconductor layer.

47. The method of manufacturing a semiconductor device as claimed in claim 45, wherein the heat treatment is carried out so that the light ions exist in a direction from the second semiconductor layer to the third semiconductor layer up to positions respectively apart from the second semiconductor layer and the third semiconductor layer.

48. The method of manufacturing a semiconductor device as claimed in claim 33, wherein the epitaxial growth is carried out while stepwisely increasing and decreasing the content of the impurities of the first conduction type.

49. A semiconductor device comprising: a first semiconductor layer of a first conduction type; a second semiconductor layer of a second conduction type formed on one principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer; and a third semiconductor layer of a first conduction type formed on the other principal surface of the first semiconductor layer with an impurity concentration higher than that of the first semiconductor layer, wherein the first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer, wherein the imputity concentration decreases with the inclination toward each of the second semiconductor layer and the third semiconductor layer to reach each of the second semiconductor layer and the third semiconductor layer, and wherein the first semiconductor layer, an impurity concentration at an interface with the second semiconductor layer is equal to an impurity concentration at an interface with the third semiconductor layer.

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Description

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BACKGROUND

In a p-i-n diode shown in FIGS. 1A and 1B (a related device A) that is widely used at present, a large transient current flows therein in the reverse direction when switched from a turned-on state to a turned-off state (at reverse recovery). The current is referred to as a reverse recovery current. During that time, a larger electrical loss occurs in the diode than in a steady state. Thus, it is a requisite for the diode to make the loss small to operate at a high-speed. Furthermore, during that time, electrical duty in the diode becomes higher, as compared with that in the steady state. An increased steady current flowing in the diode or an increased DC bus voltage increases the electrical duty to thereby sometimes damage the diode. For assuring high reliability in a diode used for electric power equipment, it is strongly required that reverse recovery withstanding capability be made far higher than the rating one.

As a current measure for improving reverse recovery characteristics and withstanding capability of the p-i-n diode, there is widely applied lifetime control of minority carriers that is performed by using heavy metal diffusion or electron beam irradiation. Namely, by shortening carrier lifetimes, a total carrier concentration in a steady state can be reduced to reduce the concentration of carriers swept-out by a spread space charge region during the reverse recovery. This can decrease a reverse recovery peak current and reverse recovery charges to reduce reverse recovery loss. Moreover, an electric field strength during the reverse recovery, which is due to holes running through the space charge region, is also relaxed by the reduction in the hole concentration. Thus, the duty is reduced to enhance the reverse recovery withstanding capability.

Also, it is important to make the diode perform soft recovery. In recent years, from the view point of environmental safety, the emphasis has been focused on reducing electromagnetic noise generated from power electronics equipment. One of the ways to achieve that goal is with making reverse recovery of the diode performed in a soft recovery mode to inhibit the cause of noise, such as from oscillation. The measure for the soft recovery is well carried out by lowering the efficiency of minority carrier injection from an anode side. Typical examples of this are presented as a Merged P-I-N/Schottky Diode (MPS) (as disclosed in The Pinch Rectifier by B. J. Baliga, IEEE Electron. Dev. Lett., ED-5, p. 194 (1984)) and a Soft and Fast recovery Diode (SFD) (as disclosed in A Novel Soft and Fast Recovery Diode (SFD) with Thin P-layer Formed by Al--Si Electrode by M. Mori, et al., Proceedings of ISPSD'91, pp. 113 117 (1991)).

The MPS diode is a p-i-n diode with an anode thereof arranged with a p-region and a Schottky region. This arrangement is explained in reference with FIG. 2 is a perspective view showing a principal part of an MPS diode. A surface structure (an anode layer 72a) is formed with p-regions 72b and a Schottky region 72c. In the figure, each of the p-regions 72a has a circular plane shape with the center thereof disposed at each of lattice points of a triangular lattice. Reference numerals 71a, 73a, 74a, 75a, and 76a in the figure denote an n-drift layer, an n-cathode layer, an anode electrode, a cathode electrode, and a voltage withstanding structure, respectively.

The high speed and low-loss characteristics in the reverse recovery operation and the soft recovery characteristics are in a relation that requires a trade-off (as disclosed in An Advanced FWD Design Concept with Superior Soft Reverse Recovery Characteristics by M. Nemoto, et al., Proceedings of ISPSD2000, pp. 119 122 (2000)). Namely, for performing the soft recovery, many minority carriers are made stored particularly on the cathode side. This is for reserving the largest possible number of minority carriers on the cathode side when the space charge region is spread from the anode side toward the cathode side at the reverse recovery. Thus, a decreasing rate of an anode current dir/dt is made lowered. This, however, causes an increase in the reverse recovery loss that requires some time until the reverse recovery is ended. On the contrary, performing high speed and low-loss reverse recovery is to reduce minority carriers stored in the drift layer at turning-on the diode. This, however, results in so-called snappy reverse recovery (hard recovery) to sometimes cause both voltage and current to oscillate.

For example, as is presented in M. Nemoto, et al., Proc. ISPS'98, pp. 305 308 (1998), disappearance of excess carriers in an n.sup.--drift layer before the end of a reverse recovery process causes an abrupt increase in dir/dt. This further causes an accompanied increase in an anode to cathode voltage Vak of a diode to generate a surged voltage. The surged voltage further causes concentration of an electric field to bring about breakdown of the diode. The surged voltage further triggers the voltage itself to oscillate with an oscillation waveform. The oscillation becomes a source of noise radiation from an electric power converting equipment such as an inverter. Therefore, the diode must be provided so that no excess carriers are made to disappear when the diode is in the course of reaching a steady state of current blocking at the reverse recovery.

Moreover, there is also another way of reducing reverse recovery loss by thinning the n.sup.--drift layer within a range, without degrading the breakdown voltage of the element to reduce reverse recovery charges. This, however, reduces carriers stored on the cathode side at the reverse recovery to make the excess carriers liable to disappear during reverse recovery, which easily causes resulting oscillation. Therefore, with current measures, it is becoming difficult to reduce the reverse recovery loss while maintaining the soft recovery characteristics.

One of typical measures for achieving the above trade-off is to combine the previously explained low minority carrier injection structure and the thinned drift layer. By reducing efficiency of minority carrier injection, which increases excess carriers on the cathode side to make the diode perform soft recovery, and by reducing the thickness of the drift layer, the soft recovery can be achieved with high-speed reverse recovery. Moreover, there is also a measure in which irradiation with a beam of light ion particles such as protons or helium ions is carried out for locally controlling lifetime of carriers to make the diode perform improved soft recovery. In these measures, however, the reduced thickness of the drift layer not only lowers breakdown voltage but also imposes limitation in making the diode perform soft recovery. This is because the spread of the space charge region in the drift layer at reverse recovery is mainly dependent on donor distribution in the drift region. Thus, an applied voltage raised within a range below the breakdown voltage of the element eventually increases carriers swept-out into the space charge region by drift even though injection of the minority carriers is lowered. This results in hard recovery.

Another example of the measure for achieving the above trade-off is to provide such a donor distribution that restricts extension of a depletion layer. For example, in a diode shown in FIGS. 3A and 3B (a related device B) that is disclosed in JP-A-8-148699, an n-drift layer 81 is divided into two regions of an n-buffer layer 81a and a constant impurity concentration region 81b. The n-buffer layer 81a on an n-cathode layer 83 side is provided to have low resitivity (high concentration) and the constant impurity concentration region 81b on a p-anode layer 82 side is provided to have high resitivity (low concentration). This restricts extension of a depletion layer at a voltage equal to or above a certain level.

In a diode shown in FIGS. 4A and 4B (a related device C) that is disclosed in JP-A-8-316500, a structure is provided in which the resitivity decreases gradually toward an n-cathode layer so as to make the diode also perform soft recovery. However, in sweeping out carriers at reverse recovery, with the resitivity being higher on a p-anode layer 92 side, the number of the carriers swept out by drift is sometimes rather increased depending on an operation mode of an application such as a high voltage with a low current. This results in hard recovery.

In a diode shown in FIGS. 5A and 5B (a related device D), which is proposed by the present inventor in unpublished and undisclosed application JP-A-2001-48631, which corresponds to U.S. patent application Ser. No. 10/083,673, the disclosure of which is incorporated herein by reference, an n-buffer layer 61a is provided at about mid-point of an n-drift layer 61. The n-buffer layer 61a has a resitivity lower than that of the n-drift layer 61, and has an impurity concentration and a thickness that make the n-buffer layer 61a itself depleted at reverse recovery. This provides a structure by which extension of a depletion layer is controlled to considerably improve the diode both in soft recovery and in a high-speed operation. In such a structure, however, a phenomenon was observed in which the presence of the n-buffer layer 61a increases a rate-of-rise of voltage dV/dt (a phenomenon of increasing dV/dt near a peak of a reverse recovery voltage). This occurs when a space charge region just reaches the n-buffer layer 61a at reverse recovery. From the view point of noise reduction, this has no merit. Thus, the increase in dV/dt must be suppressed.

FIG. 6 is a diagram showing results of simulations of waveforms about anode to cathode voltages Vak and anode currents Ia at revere recovery in the related semiconductor devices A, B, and D shown in FIGS. 1A and 1B, FIGS. 3A and 3B, and FIGS. 5A and 5B, respectively. FIG. 7, FIG. 8, and FIG. 9 are diagrams each showing results of simulations of variations in time about distributions of concentrations of internal carriers (electrons and holes) and electric field strength at a reverse recovery operation in each of the related device A, B, and D together with an impurity concentration distribution therein. Each distribution is taken to a distance from the surface of the p-anode layer in the direction to the n-cathode layer.

In the related device D of FIGS. 5A and 5B, the n-drift layer 61 is formed as follows. On the side of an n-cathode layer 63, a constant impurity concentration region 61c is formed by epitaxial growth with phosphorus taken as an impurity so that the resistivity becomes 65 .OMEGA.cm/52 .mu.m. Next to this, the n-buffer layer 61a having a width of about 5 .mu.m is formed with a dose of phosphorus taken as 2.times.10.sup.11 cm.sup.-2. Thereafter, about the side of a p-anode layer 62, a constant impurity concentration region 61b is formed by epitaxial growth so that the resistivity becomes 90 .OMEGA.cm/60 .mu.m. The integrated impurity concentration of the n-drift layer 61 is about 1.0.times.10.sup.12 cm.sup.-2. The distribution of the impurity concentration in the n-buffer layer 61a is given so as to abruptly rise up to a peak concentration like a pulse. With an averaged concentration over the whole region of the n-drift layer 61 taken as N.sub.dm and the peak concentration of the n-buffer layer taken as N.sub.p, a ratio of N.sub.p/N.sub.dm is given as 20.

As is described in JP-A-2001-48631 (which corresponds to the co-pending application mentioned above) and as is apparent from FIG. 6, the related semiconductor device D of FIGS. 5A and 5B exhibits soft recovery in which oscillation at reverse recovery is inhibited. However, as shown in FIG. 6, the waveform of the reverse recovery voltage Vak for the related device D (shown in dashed line) exhibits an abrupt increase (almost vertical) in the rate-of-change of voltage dV/dt from the time about 0.473 .mu.s. The increase in dV/dt is one of the causes of electromagnetic noise, which needs to be inhibited. As is observed in FIG. 9, a diagram showing results of simulations of variations in time about concentrations of internal carriers (electrons and holes) and electric field strength in the related device D, the space charge region reaches the n-buffer layer 61a at a time between 0.47 .mu.s and 0.475 .mu.s. It is apparent from FIG. 6 that dV/dt is increased during that time. This is a so-called pinning effect of the space charge region (an effect of stopping extension of a depletion region at a buffer layer). By the pinning effect, the spread of the space charge region is stopped at the buffer layer, so that no sweeping out of the carriers by drift occurs any more toward the n-cathode 63 side, causing the current to take hard recovery. However, the presence of the n-buffer layer 61a abruptly increases electric field strength on the side of the p-anode layer 62 to thereby increase dV/dt as shown in FIG. 6.

In the related device A shown in FIGS. 1A and 1B, an n-drift layer 71 (an i layer) is provided by epitaxial growth with the resistivity having 50 .OMEGA.cm/117 .mu.m by taking phosphorus as an impurity. The integrated concentration of the donor in the n-drift layer 71 is about 1.1.times.10.sup.12 cm.sup.-2. Although not so remarkable as in the related device B shown in FIGS. 3A and 3B, the related device A (shown in dash-dot-dot line) also begins to oscillate at a time of 0.504 .mu.s as shown in FIG. 6. As is observed in FIG. 7, a diagram showing results of simulations of variations in time about concentrations of internal carriers (electrons and holes) and electric field strength in the related device A, the carriers disappear from the time 0.50 .mu.s to the time of 0.52 .mu.s, at which oscillation is started.

In the related device B shown in FIGS. 3A and 3B, an n-drift layer 81 is provided by epitaxial growth with the resistivity made as being 63 .OMEGA.cm/70 .mu.m on the side of a p-anode layer 82 and 40 .OMEGA.cm/47 .mu.m on the side of an n-cathode layer 83 by taking phosphorus as an impurity. The integrated concentration of the donor in the whole region of the n-drift layer 81 is about 1.1.times.10.sup.12 cm.sup.-2. It is observed from FIG. 6 that oscillation of the related device B (shown in dotted line) is started after a peak of the reverse recovery current. As is observed in FIG. 8, a diagram showing results of simulations of variations in time about concentrations of internal carriers (electrons and holes) and electric field strength in the related device B, the carriers disappear when the time goes from 0.49 .mu.s to 0.50 .mu.s, during which oscillation is started as is shown in FIG. 6.

The oscillation at reverse recovery is caused by an abrupt increase in current decreasing rate dir/dt at reverse recovery (i.e. hard recovery). The related device A and related device B perform hard recovery. Thus, there is a need for a semiconductor device and a manufacturing method thereof that inhibits voltage and current oscillations during reverse recovery to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics. The present invention addresses this need

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor device, such as a diode, and a manufacturing method thereof that can achieve high-speed and low-loss, and yet benefit from soft recovery characteristics.

According to one aspect of the present invention, the semiconductor device comprises a first semiconductor layer of a first conduction type, a second semiconductor layer of a second conduction type, and a third semiconductor layer of a first conduction type. The second layer is formed on one principal surface of the first layer with an impurity concentration higher than that of the first layer, and the third layer is formed on the other principal surface of the first layer also with the impurity concentration higher than that of the first semiconductor layer. The first semiconductor layer has an impurity concentration decreasing with an inclination toward each of the second semiconductor layer and the third semiconductor layer.

The first layer can have an impurity concentration that reaches a relative maximum at least at one position in a direction from the second semiconductor layer to the third semiconductor layer. Moreover, the impurity concentration of the first layer can decrease from the position at which the impurity concentration becomes the relative maximum with the impurity concentration thereof decreasing toward each of the second layer and the third layer. The impurity concentration also can decrease with the inclination toward each of the second layer and the third layer to reach each of the second layer and the third layer.

In the first layer, an impurity concentration at an interface with the second layer can be equal to an impurity concentration at an interface with the third semiconductor layer. The impurity concentration at an interface with the third layer can be higher than an impurity concentration at an interface with the second layer.

The maximum impurity concentration N.sub.p in the first semiconductor layer can satisfy a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.5, where N.sub.dm is an averaged impurity concentration in the first layer. More specifically, the maximum impurity concentration N.sub.p in the first layer can satisfy a relationship expressed as 1<N.sub.p/N.sub.dm.ltoreq.2.

An integrated impurity concentration

.intg..times..function..times.d ##EQU00001## in the first layer, which is in a region between a position nearest to the second layer of positions at each of which the impurity concentration in the first layer can be equal to the averaged impurity concentration N.sub.dm and a position nearest to the third layer of the positions at each of which the impurity concentration in the first layer can be equal to the averaged impurity concentration N.sub.dm, satisfies a relationship expressed as

.intg..times..function..times.d.ltoreq..times. ##EQU00002## where X is a distance from an end of the second layer opposite to the first layer to a position in the first layer in the direction from the second layer to the third layer, N.sub.d(X) is the impurity concentration distribution about the distance X in the first layer in the direction from the second layer to the third layer, Xc is a distance from the end of the second layer opposite to the first layer in the direction from the second layer to the third layer to the position nearest to the second layer of positions at each of which N.sub.d(X) can become N.sub.d(X)=N.sub.dm, and Xd is a distance from the end of the second layer opposite to the first layer in the direction from the second layer to the third layer to the position nearest to the third layer of the positions at each of which N.sub.d(X) can become N.sub.d(X)=N.sub.dm.

The integrated impurity concentration

.intg..times..function..times.d ##EQU00003## in the first layer in the region from the distance Xc to the distance Xd can satisfy a relationship expressed as

.intg..times..function..times.d.ltoreq..times. ##EQU00004##

The distance Xp from the end of the second layer opposite to the first layer to a position, at which the impurity concentration in the first layer becomes the maximum in the direction from the second layer to the third layer, can satisfy a relationship expressed as

.ltoreq..times..times..function..times..times..nu..times..times..ltoreq. ##EQU00005## where BV is a breakdown voltage of a semiconductor element, .epsilon..sub.s is a semiconductor permittivity, q is the elementary electric charge, J.sub.F is a rated current density of the semiconductor element, .nu..sub.sat is a carrier saturation velocity. More specifically, the distance Xp can satisfy a relationship expressed as

.ltoreq..times..times..function..times..times..nu..times..times..ltoreq. ##EQU00006##

The third layer can have a surface impurity concentration equal to or greater than 1.times.10.sup.17 cm.sup.-3, and an integrated impurity concentration in the first layer from the interface with the second layer to the interface with the third layer can be between 8.times.10.sup.11 cm.sup.-2 and 2.times.10.sup.12 cm.sup.-2. The integrated impurity concentration in the first layer from the interface with the second layer to the interface with the third layer can be between 8.times.10.sup.11 cm.sup.-2 and 1.3.times.10.sup.12 cm.sup.-2.

The impurity concentration N.sub.d(X.sub.j) in the first layer at a position of the interface with the second layer, which position is at a distance X.sub.j from the end of the second layer opposite to the first layer in the direction from the second layer to the third layer, can satisfy a relationship expressed as

.function..times..ltoreq. ##EQU00007##

The impurity concentration can be constant with a specified concentration in a region on each of a side of the second layer and a side of the third layer. The specified impurity concentration made constant on the side of the second semiconductor layer can be equal to that on the side of the third layer. The specified impurity concentration made constant on the side of the third semiconductor layer can be higher than that on the side of the second semiconductor layer.

Positions at boundaries at each of which the impurity concentration decreasing from the maximum concentration can be constant with the specified concentration, with a position on the side of the second layer taken at a distance Xa from an end of the second layer opposite to the first layer in the direction from the second layer to the third layer, and a position on the side of the third layer taken at a distance Xb from the end of the second layer opposite to the first layer in the direction from the second layer to the third layer, an integrated impurity concentration

.intg..times..function..times.d ##EQU00008## in the first layer in a region from the distance Xa to the distance Xb satisfying a relationship expressed as

.intg..times..function..times.d.ltoreq..times. ##EQU00009##

The lifetime distribution of minority carriers can become shortest near the interface between the first layer and the second layer, and can become longest in the first layer near the interface between the first layer and the third layer. The efficiency of minority carrier injection into the first layer can be equal to or less than 0.7.

The relative maximum impurity concentration can be located at a plurality of positions in the direction from the second layer to the third layer, and the impurity concentration of the first layer can decrease from each of the positions at each of which the impurity concentration reaches the relative maximum with an inclination toward each of the second layer and the third layer.

Another aspect of the present invention is a method of manufacturing the above-described semiconductor device, where the first layer is epitaxially grown while controlling the impurity concentration during the growth. The method can involve forming the third layer from a semiconductor of the first conduction type, forming the first layer on the third layer by an epitaxial growth to a specified position in a direction opposite to the third layer, while gradually increasing the content of the impurities of the first conduction type, and then by epitaxially growing while gradually decreasing the content of the impurities of the first conduction type, and forming the second layer on the surface of the first layer.

During the epitaxial growth, the content of the impurities of the first conduction type can be made constant. Thereafter, the first layer can be epitaxially grown to a specified second position in the direction opposite to the third layer while gradually increasing the content of the impurities of the first conduction type, thereafter by carrying out epitaxial growth to a specified third position in the direction opposite to the third layer, while gradually decreasing the content of the impurities of the first conduction type, and by epitaxially growing while holding the content of the impurities of the first conduction type constant again. The second semiconductor layer can be form ed by diffusing the impurities of the second conduction type on the surface of a region in which the content of the impurities is made constant in the first semiconductor layer formed by carrying out the epitaxial growth.

The content of the impurities of the first conduction type can be made constant to form a first epitaxial layer, by implanting with impurity ions of the first conduction type on a surface of the first epitaxial layer, and then forming second epitaxial growth on the surface of the first epitaxial layer while holding the content of the impurities of the first conduction type constant to form a second epitaxial layer. The first layer formed with the first and second epitaxial layers can be heat treated to diffuse the ion-implanted impurities into the first and the second epitaxial layers. The second layer can be formed by diffusing the impurities of the second conduction type on the surface of the first layer.

The ion-implanted impurities can be diffused toward the second layer and the third layer to positions respectively reaching the second layer and the third layer. The ion-implanted impurities can be diffused toward the second layer and the third layer to positions respectively apart from the second layer and the third layer.

The third layer can be thinned and a semiconductor layer of a first conduction type with a high impurity concentration can be formed on a surface of the thinned third layer. Impurity ions of the first conduction type can be implanted on the surface of the third layer. The first layer can be formed on the surface of the third layer with epitaxial growth, while holding the content of the impurities of the first conduction type constant. The ion-implanted impurities can be diffused into the first and the third layer with heat treatment. The second layer can be formed by diffusing impurities of the second conduction type on the surface of the first layer. The third layer can be thinned as previously