Title: Prefabricated semiconductor chip carrier
Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads. A method of manufacturing a semiconductor die carrier includes the steps of individually manufacturing a plurality of electrically conductive leads without use of a lead frame; extending a plurality of the electrically conductive leads from at least one of a plurality of electrically insulative side walls; positioning a semiconductor die such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and electrically connecting the semiconductor die to corresponding ones of the electrically conductive leads.
Patent Number: 6,977,432 Issued on 12/20/2005 to Crane, Jr., et al.
| Inventors:
|
Crane, Jr.; Stanford W. (Boca Raton, FL);
Portuondo; Maria M. (Boca Raton, FL)
|
| Assignee:
|
Quantum Leap Packaging, Inc. (Wilmington, MA)
|
| Appl. No.:
|
755414 |
| Filed:
|
January 13, 2004 |
| Current U.S. Class: |
257/696 |
| Intern'l Class: |
H01L 023/48 |
| Field of Search: |
438/26
257/696
|
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|
Primary Examiner: Coleman; W. David
Attorney, Agent or Firm: Weingarten, Schurgin, Gagnebin & Lebovici LLP
Parent Case Text
This application is a continuation of application Ser. No. 09/964,542, filed
Sept. 28, 2001, which is a continuation of application Ser. No. 08/208,586, filed
Mar. 11, 1994, now U.S. Pat. No. 6,339,191, the disclosures of which are hereby
incorporated by reference herein in their entirety.
Claims
1. A semiconductor die carrier comprising:
a carrier housing including a plurality of electrically insulative side walls;
a plurality of substantially L-shaped electrically conductive leads extending
through at least one of the side walls and arranged in multiple vertically-spaced
rows, the leads secured in said at least one side wall by friction, wherein each
of the leads includes a mounting surface external of the carrier housing for forming
a surface mount electrical connection to a circuit board;
a semiconductor die positioned within said carrier housing such that the electrically
conductive leads are disposed at one or more locations around the periphery of
the die, said semiconductor die comprising a plurality of bonding pads; and
electrically-conductive bond wiring extending between the bonding pads and the
leads for providing electrical connection between the semiconductor die and corresponding
ones of the electrically conductive leads.
2. The semiconductor die carrier according to claim 1, wherein the leads comprise
a first group of leads and a second group of leads, the mounting surfaces of the
first group of leads are positioned for contacting a first level of the circuit
board and the mounting surfaces of the second group of leads are positioned for
contacting a second level of the circuit board.
3. The semiconductor die carrier according to claim 1, further comprising a second
semiconductor die positioned within said carrier housing.
4. The semiconductor die carrier according to claim 1, wherein said carrier housing
further comprises a thermally conductive cap.
5. The semiconductor die carrier according to claim 1, wherein the leads extend
from multiple side walls of the carrier housing.
6. The semiconductor die carrier according to claim 1, wherein the carrier housing
encapsulates the semiconductor die.
7. The semiconductor die carrier according to claim 1, wherein the bond wiring
comprises tape-automated bonding.
8. The semiconductor die carrier according to claim 1, wherein the bond wiring
comprises wire bonding.
9. The semiconductor die carrier according to claim 1, wherein the carrier housing
further comprises a floor.
10. The semiconductor die carrier according to claim 4, wherein the semiconductor
die is mounted to the cap.
11. The semiconductor die carrier according to claim 9, wherein the semiconductor
die is mounted to the floor.
12. The semiconductor die carrier according to claim 11, wherein the floor comprises
an indentation for receiving the semiconductor die.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a prefabricated, peripherally-leaded, semiconductor
chip or die carrier having a reduced size, and methods for making and using the
semiconductor die carrier. In a preferred embodiment, the semiconductor die carrier
has horizontally and vertically spaced rows of multiple leads, with each lead being
assembled into the semiconductor die carrier as an individually manufactured lead
rather than a sub-element of a lead frame.
2. Description of the Related Art
There have been rapid advances in semiconductor technology, memory capacity,
and software development in recent years. Advances in semiconductor packaging,
interconnect technologies, and printed circuit board (PCB) assemblies have been
more modest. The size of the semiconductor package and the number of leads it can
accommodate are now major limiting factors determining computer speed and functionality.
There is a trade-off between fabricating semiconductor packages with an increased
number of leads and the resulting increase in component size. More leads mean a
faster and more efficient transfer of information; however, more leads take up
more space, thus increasing costs, and slowing down the electrical signal as it
travels to interface with other devices.
With respect to semiconductor packages, many different shapes and sizes are
currently available. Conventional semiconductor package technologies include the
laminated ceramic technology, the pressed ceramic technology, and the molded plastic technology.
In accordance with the laminated ceramic technology, a semiconductor die is attached
to a ceramic package having leads from a lead frame extending therefrom. Bonding
pads on the die are connected to the leads using bonding wires. A cap is then glued
to the ceramic package, thereby sealing the die and inner portions of the leads
within the package.
In pressed ceramic technology, a semiconductor die is attached to a lower portion
of a ceramic package having leads from a lead frame extending therefrom. After
the wire bonding procedure, a top portion of the ceramic package is glued to the
lower portion of the ceramic package to seal the die and inner portions of the
leads within the package.
In molded plastic technology, a semiconductor die is configured for housing within
a plastic package from which a set of leads will extend. In the initial stages
of fabrication, the die is attached at a position surrounded by the leads from
a lead frame. Wire bonding then takes place, and thereafter an injection molding
process is carried out to form a plastic package within which the die and inner
portions of the leads are sealed. The leads are then bent to form the finished
package. The steps required to form a conventional molded plastic package may be
understood more fully from the flowchart depicted in FIG. 1.
As can be understood from FIG. 2, conventional package leads are typically configured
for mounting (on a PCB, for example) using plated-through-hole (PTH) technology
or surface-mount technology (SMT).
In PTH technology, a conductive PTH is formed in a PCB. Each lead of a package
is inserted through a corresponding PTH and then soldered to form a solder joint
fastening the lead in conductive contact with the PTH.
In SMT mounting, each lead of a package, rather than being soldered to extend
through a PTH in a PCB, is soldered onto a conductive portion of a top surface
of the PCB. If the package is a leadless die carrier, a conductive section of the
package is soldered onto a conductive portion of a top surface of the PCB known
as a bonding pad. A solder joint then maintains each lead of the leaded die carrier,
or each conductive section of the leadless die carrier, in a fastened relationship
with respect to the PCB. In accordance with SMT mounting, each lead of a leaded
die carrier can have a "Gullwing" configuration; "J-Lead" configuration; or a "Butt
Lead" configuration.
Various conventional PTH and SMT packages are shown in FIG. 2. The PTH packages
include a DIP (Dual In-line Package); an SH-DIP (Shrink DIP); an SK-DIP (Skinny
DIP) or SL-DIP (Slim DIP); an SIP (Single In-line Package); a ZIP (Zig-zag In-line
Package); and a PGA (Pin Grid Array). The SMT packages include an SO or SOP (Small
Out-line Package); a QFP (Quad Flat Package); a LCC (Leadless Chip Carrier); and
a PLCC SOJ (Plastic Leaded Chip Carrier with Butt Leads).
QFPs such as the ones shown in FIG. 2 are typically manufactured using the molded
plastic technology described above. Most QFPs are manufactured using a single-layer
lead frame providing a single row of bent leads extending from each of the four
sides of the QFP.
Multi-row lead configurations are also known. For example, it is known
to provide two rows of leads, formed by using two different lead frames vertically
spaced and insulated from each other, extending from sides of a QFP. It is also
known to provide rows of multiple leads formed using vertically spaced lead frames
with adjacent rows of leads primarily separated from each other by a gaseous dielectric
such as air. With respect to the wire bonding procedure associated with conventional
semiconductor die packages, it is known in PGA packages to position bonding pads
on different stepped levels.
The aforementioned semiconductor die packages suffer from many deficiencies.
QFP technology, for example, is severely limited for a variety of reasons. For
example, the molded plastic technology typically used to manufacture QFPs incorporates
various processes following the wire bonding procedure which can have detrimental
effects on the bonding integrity. These processes include s aling, which involves
high-pressure injection-molding and cooling/heating steps, and the bending of the
leads to achieve desired lead configurations, whereby bonding wire movement, breakage,
and/or shorting can all result. Moreover, the encapsulation process is limited
to the use of molding compounds with low thermal conductivity which can result
in performances at less than an optimum level.
The use of lead frames during the manufacturing of QFP semiconductor packages
and the like also results in numerous disadvantages. First of all, the types of
dies from which conventional lead frames are stamped can be very expensive because
of the number of intricate features involved and the amount of the material that
must be handled. Moreover, the manufacturing tolerances required in stamping the
larger sizes of necessary elements cause the stamping of lead frames to be a low-yield
process. Also, packages which incorporate lead frames are typically tested after
die placement at a point so late in the manufacturing process that if the package
turns out to be defective, any value that may have been added is rendered useless.
Additionally, lead frames typically limit the die placement process to procedures
such as single-row peripheral pad bonding or tape automated bonding (TAB), thereby
resulting in limitations in die placement options and flexibility. Furthermore,
once a conventional QFP is completed, it is very difficult, if not impossible,
to carry out repairs on one or more of the components of the package. In general,
for conventional packaging technology, as the number of required leads increases,
based on increases in the speed and functionality of the relevant die, so does
the size of the lead frame, increasing its manufacturing and tooling costs and
decreasing its efficiency due to the increased distances the signal must travel.
QFP-type packages also tend to take up large amounts of PCB area, due in
part to the use of lead frames during their manufacture. For example, QFPs manufactured
using a single-level lead frame and, therefore, including only a single row of
leads extending from the sides of the QFP, typically require approximately 900
square millimeters of PCB area for a 208-pin QFP, and approximately 1,832 square
millimeters of area for a 304-pin QFP.
Multi-row lead frame packages, to some extent, take up less PCB area in
terms of the number of leads that can be provided. However, various limitations
can render conventional multi-row leaded packages unsuitable for existing and contemplated
packaging needs. Conventional structure, for example, is typically limited to two
rows of leads per side, and all of the leads of both rows must be offset so that
surface mounting can be performed in accordance with conventional mounting technology.
Such characteristics can unnecessarily increase the amount of PCB area that will
be required for mounting. Moreover, lead frames are typically used during the manufacture
of the aforementioned conventional structure and, therefore, such structure is
subject to a compounding of the inherent performance limitations and additional
complexity, noted above.
PGA packages having a stepped configuration are also subject to limitations.
For example, PGAs, unlike QFPS, are not generally suitable for SMT applications.
Instead, PGAs are typically mounted using PTH technology or are plugged into a
socket. Also, PGAs take up significant amounts of PCB space and space and volume
of the PCB and, consequently, can be an impediment to the manufacture of high-density
circuit configurations. Moreover, PGAs are typically expensive due to the cost
of the ceramic package material and the brazed pin assembly that are used.
From the foregoing, it can be understood that conventional semiconductor packages
take up large amounts of board space; are expensive and often experience difficulties
during manufacture; perform insufficiently due to procedures carried out after
chip attachment and wire bonding that tend to inhibit bond integrity; and, after
manufacture, are difficult, if not impossible, to repair. As a result of such limitations,
current semiconductor packaging technology is not sufficient to meet the needs
of existing and/or future semiconductor and computer technology. Semiconductor
packaging technology has already failed to keep pace with silicon die technology,
and as computer and microprocessor speeds continue to climb, with space efficiency
being increasingly important, semiconductor die packages having even smaller area
requirements will be required. The semiconductor die packages discussed above fall
short of current and contemplated semiconductor and computer requirements.
SUMMARY OF THE INVENTION
Accordingly, it is a goal of the present invention to provide a prefabricated
semiconductor die carrier occupying reduced amounts of board area, providing an
increased number of contacts, and capable of meeting the needs of existing and
contemplated semiconductor and computer technology.
Another goal of the present invention is to provide a semiconductor die carrier
manufactured without the use of lead frames and having leads extending from side
portions thereof suitable for mounting using PTH technology, SMT methodology, or
pluggable mounting.
Yet another goal of the present invention is to provide a semiconductor die carrier
wherein a semiconductor die is bonded from multiple rows of pads on the die to
vertically spaced rows of multiple leads while maintaining a very low profile package.
Still another goal of the present invention is to provide a semiconductor die
carrier that is fabricated and tested prior to placement of a semiconductor die
within the carrier, thereby increasing final packaging yields and reducing total
unit cost.
A further goal of the present invention is to provide a semiconductor die carrier
wherein the leads are configured to facilitate the routing of PCB traces for connection
to the leads.
It is also a goal of the present invention to provide methods for making and
using
semiconductor die carriers having characteristics such as those discussed above.
These and other goals may be achieved by using a semiconductor die carrier
comprising a plurality of electrically insulative side walls; a plurality of electrically
conductive leads extending from at least one of the side walls, each of the leads
being individually manufactured without use of a lead frame; a semiconductor die
positioned such that the electrically conductive leads are disposed at one or more
locations around the periphery of the die; and means for providing electrical connection
between the semiconductor die and corresponding ones of the electrically conductive leads.
Also, a method of manufacturing a semiconductor die carrier may be used, the
method comprising the steps of individually manufacturing a plurality of conductive
leads without use of a lead frame; extending a plurality of the electrically conductive
leads from at least one of a plurality of electrically insulative side walls; positioning
a semiconductor die such that the electrically conductive leads are disposed at
one or more locations around the periphery of the die; and electrically connecting
the semiconductor die to corresponding ones of the electrically conductive leads.
It is to be understood that both the foregoing general description and the following
detailed description are exemplary and explanatory, and are not restrictive of
the invention as claimed. The accompanying drawings, which are incorporated in
and constitute a part of the specification, illustrate embodiments of the present
invention and, together with the general description, serve to explain the principles
of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flowchart illustrating steps in a conventional method for manufacturing
a semiconductor package.
FIG. 2 is a view showing conventional PTH and SMT semiconductor packages.
FIG. 3 is a perspective view of a two-tier embodiment of a prefabricated semiconductor
die carrier in accordance with the present invention.
FIG. 4 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 3.
FIG. 5 is a perspective view of a twelve-sided semiconductor die carrier in
accordance with the present invention.
FIG. 6 is a partial perspective view of an eight-sided semiconductor die carrier
in accordance with the present invention.
FIG. 7(
a) is a perspective view of a two-row embodiment of a prefabricated
semiconductor die carrier in accordance with the present invention prior to the
fastening of the side walls to one another and the floor.
FIG. 7(
b) is a perspective view of a two-row embodiment of a prefabricated
semiconductor die carrier in accordance with the present invention prior to the
fastening of the side walls to one another and the floor.
FIG. 8(
a) is a perspective view of an SMT lead with an L-shaped foot
portion configured in accordance with the present invention and positioned on a
bonding pad of a multi-layer conductor such as a PCB.
FIG. 8(
b) is a perspective view of an SMT lead in accordance with the
present invention having an L-shaped foot portion and a horizontal stability portion.
FIG. 9 is a perspective view of another SMT lead with an L-shaped foot portion
configured in accordance with the present invention.
FIG. 10 is a partial perspective view of a conductive lead inserted into a side
wall including insulative structure for preventing over-insertion of the lead.
FIG. 11 is a perspective view of another SMT lead with an L-shaped foot portion
configured in accordance with the present invention.
FIG. 12 is a perspective view of an SMT lead with a straight or Butt Lead foot
portion configured in accordance with the present invention.
FIG. 13 is a perspective view of a PTH lead configured in accordance with the
present invention.
FIG. 14 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 3.
FIG. 15 is a perspective view of a three-tier embodiment of a prefabricated
semiconductor die carrier in accordance with the present invention.
FIG. 16 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 15.
FIG. 17 is a partial side view of the embodiment of the semiconductor die carrier
illustrated in FIG. 15 prior to lead insertion with a dotted line segmenting repeating
sets of passage arrangements.
FIG. 18 is a partial side view of the embodiment of the semiconductor die carrier
illustrated in FIG. 15 after lead insertion with a dotted line segmenting repeating
sets of contact arrangements.
FIG. 19 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 15 showing wire bonding details.
FIG. 20 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 15 showing lead interface details.
FIG. 21 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 15 showing lead interface details.
FIG. 22 is a partial top view of the embodiment of the semiconductor die carrier
illustrated in FIG. 15 showing footprint details with a dotted line segmenting
repeating sets of contact arrangements.
FIG. 23 is a partial top view of the embodiment of the semiconductor die carrier
illustrated in FIG. 15 showing lead interface details with a dotted line segmenting
repeating sets of contact arrangements.
FIG. 24 is a partial side view of the embodiment of the semiconductor die carrier
illustrated in FIG. 15 including a cap.
FIG. 25 is a partial side view of a cavity-down configuration in accordance
with the embodiment of the semiconductor die carrier illustrated in FIG. 15.
FIG. 26 is a partial side view of a die indentation configuration in accordance
with the embodiment of the semiconductor die carrier illustrated in FIG. 15 including
a cap.
FIG. 27 is a partial side view of a same or similar level configuration in accordance
with the embodiment of the semiconductor die carrier illustrated in FIG. 15 including
a cap.
FIG. 28 is a partial side view of a platform configuration in accordance with
the embodiment of the semiconductor die carrier illustrated in FIG. 15 including
a cap.
FIG. 29(
a) is a partial perspective view of a four-tier embodiment of
a prefabricated semiconductor die carrier in accordance with the present invention.
FIG. 29(
b) is a partial perspective view of a three-tier embodiment of
a prefabricated semiconductor die carrier in accordance with the present invention.
FIG. 30 is a partial side view of the embodiment of the semiconductor die carrier
illustrated in FIG. 29(
a) prior to lead insertion with a dotted line segmenting
repeating sets of passage arrangements.
FIG. 31 is a partial side view of the embodiment of the semiconductor die carrier
illustrated in FIG. 29(
a) after lead insertion with a dotted line segmenting
repeating sets of contact arrangements.
FIG. 32 is a partial perspective view of the embodiment of the semiconductor
die carrier illustrated in FIG. 29(
a) showing lead interface details.
FIG. 33(
a) is a partial perspective view of a multiple-wall configuration
in accordance with the embodiment of the semiconductor die carrier illustrated
in FIG. 29(
a).
FIG. 33(
b) is a perspective view of a lead having a stabilizing section
with a notched portion configured for use with a multiple-wall configuration in
accordance with the present invention.
FIG. 33(
c) is a perspective view of a lead having a stabilizing section
with a raised portion configured for use with a multiple-wall configuration in
accordance with the present invention.
FIG. 33(
d) is a partial perspective view of the lead of FIG. 33(
c)
formed within a multiple-wall configuration of a semiconductor die carrier in accordance
with the present invention.
FIG. 34 is a partial top view of the embodiment of the semiconductor die carrier
illustrated in FIG. 29(
a) showing footprint details with a dotted lin s
gmenting repeating sets of contact arrangements.
FIG. 35 is a partial top view of the embodiment of the semiconductor die carrier
illustrated in FIG. 29(
a) showing lead interface details with a dotted line
segmenting repeating sets of contact arrangements.
FIG. 36 is a partial perspective view of an insulating separator configuration
in accordance with the embodiment of the semiconductor die carrier illustrated
in FIG. 29(
a).
FIG. 37 is a partial side view of an insulating separator configuration in accordance
with the embodiment of the semiconductor die carrier illustrated in FIG. 29(
a)
including a cap.
FIG. 38 is a partial side view of a configuration in accordance with the present
invention having a stepped ceramic component to facilitate bonding of smaller dies
having large I/O characteristics.
FIG. 39(
a) is a partial side view of a configuration in accordance with
the present invention having non-coplanar leads to facilitate mounting on a multi-layer
conductor such as a multi-layer PCB.
FIG. 39(
b) is a partial perspective view of a semiconductor die carrier
in accordance with the present invention having coplanar and non-coplanar leads
to facilitate mounting on a multi-layer conductor such as a multi-layer PCB.
FIG. 40 is a partial perspective view of a prefabricated semiconductor die carrier
in accordance with the present invention having lead passages with rounded corners.
FIG. 41 is a perspective view of a multi-die configuration of a prefabricated
semiconductor die carrier in accordance with the present invention.
FIG. 42 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention having upwardly-oriented and downwardly-oriented leads.
FIG. 43 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention having sideways-extending and downwardly-extending leads.
FIG. 44 is a partial bottom view of a prefabricated semiconductor die carrier
in accordance with the present invention having a nested configuration of downwardly-extending leads.
FIG. 45 is a partial bottom view of a prefabricated semiconductor die carrier
in accordance with the present invention having a modified arrangement of downwardly-extending leads.
FIG. 46 is a partial bottom view of a prefabricated semiconductor die carrier
in accordance with the present invention having a nested arrangement of downwardly-extending leads.
FIG. 47(
a) is a partial bottom view of a prefabricated semiconductor
die carrier in accordance with the present invention having a modified arrangement
of downwardly-extending leads.
FIG. 47(
b) is a partial bottom view of a prefabricated semiconductor
die carrier in accordance with the present invention including an arrangement of
downwardly-extending leads arranged in groups having H-shaped spaces incorporated therein.
FIG. 48 depicts a pair of flowcharts comparing a conventional manufacturing
method with a method in accordance with the present invention performed in order
to manufacture, transport, and mount a prefabricated semiconductor die carrier.
FIG. 49(
a) is a perspective view of leads in an upright position on a
bandolier during a manufacturing process in accordance with the present invention.
FIG. 49(
b) is a perspective view of leads positioned sideways on a bandolier
during a manufacturing process in accordance with the present invention.
FIG. 50 is a perspective view of a first type of transportation packaging in
accordance with the present invention.
FIG. 51 is a perspective view of the first type of packaging shown in FIG. 50
with a semiconductor die carrier residing therein.
FIG. 52 is a partial perspective view of the first type of packaging shown in
FIG. 50 with a semiconductor die carrier residing therein.
FIG. 53 is a partial perspective view of the first type of packaging shown in
FIG. 50 with another semiconductor die carrier residing therein.
FIG. 54(
a) is a side view of a second type of transportation packaging
in accordance with the present invention.
FIG. 54(
b) is a perspective view of a semiconductor die carrier particularly
well-suited for use with the type of transportation packaging illustrated in FIG. 54(
a).
FIG. 55 is a perspective view of a third type of transportation packaging in
accordance with the present invention.
FIG. 56 is a perspective view of a pluggable lead configured in accordance with
the present invention.
FIG. 57 is a partial perspective view of the semiconductor die carrier in accordance
with the present invention plugged within a pluggable socket.
FIG. 58 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention plugged within another pluggable socket.
FIG. 59 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention plugged into the pluggable socket illustrated in FIG. 58.
FIG. 60 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention having leads extending straight out of one or more sides
of the carrier.
FIG. 61 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention including leads having an alternate foot configuration.
FIG. 62 is a top view of a single-tier embodiment of a semiconductor die carrier
in accordance with the present invention.
FIG. 63 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention wherein the leads of at least one row alternate with
vias extending into a substrate such as a PCB.
FIG. 64 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention showing an arrangement of bonding extensions inside
the carrier.
FIG. 65 is a perspective view of a rounded lead configured in accordance with
the present invention.
FIG. 66 is a partial perspective view of a semiconductor die carrier in accordance
with the present invention having round lead passages.
FIG. 67 is a chart comparing various embodiments in accordance with the present
invention with conventional QFP technology.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A prefabricated semiconductor die carrier in accordance with the present invention
has multiple rows of electrically conductive leads arranged at vertically spaced
multiple levels around the periphery of the carrier. Such leads may also be arranged
on the top or bottom of the carrier. Each of the leads is manufactured and assembled
into the semiconductor die carrier prior to the die attach step as an individually
manufactured lead, rather than as a sub-element of a lead frame, to facilitate
the multiple-row, multiple-level structure.
The leads of the semiconductor die carrier may be offset from other levels at
the point where the leads extend through side walls of the carrier and/or staggered
at the point where the leads connect to a PCB or other interface surface. At least
the latter configuration allows traces on the PCB to be routed between the staggered leads.
The leads of the semiconductor die carrier extend into the die carrier through
the side walls of the die carrier, forming a series of vertically spaced rows of
multiple leads around the semiconductor die. The portions of the leads extending
through the side walls have wire bond terminals formed thereon. A wire bond insulator
may be used to separate the rows of leads. The semiconductor die can be mounted
within the carrier with the peripheral pads of the die facing up and away from
the PCB, in a cavity-up configuration, or with the peripheral pads of the die facing
down toward the PCB, in a flip-chip or cavity-down configuration.
Encapsulation for the semiconductor die carrier of the present invention
is performed by filling the die cavity with an epoxy, a liquid crystal polymer
such as VECTRA (a trademark of Hoechst Celanese) or other high-temperature material.
The semiconductor die carrier may be capped with a plastic component or thermally
conductive cap that serves as a heat sink.
The semiconductor die carrier of the present invention provides a package having
a reduced size as compared to known semiconductor packages, yet increases the number
of interconnects available for the designer and user. The die carrier may be pluggable
or compatible with either the PTH or SMT methodology. The semiconductor die carrier
is prefabricated and tested prior to introduction of the semiconductor die to the
carrier, thereby increasing finished product yields and reducing total unit cost.
The configuration of the die carrier allows the semiconductor die to be bonded
from multiple rows of pads on the die to multiple levels of vertically spaced rows
of leads while maintaining a very low profile for the die carrier.
The semiconductor die carrier of the present invention provides better coplanarity
of the feet of the leads when mounting using the SMT methodology, for example,
thereby avoiding non-contact between the leads and the surface of the PCB. Such
coplanarity is not always possible using conventional packaging technology due
to the bending of the leads that is required when using a lead frame.
Details relating to the present invention will now be discussed with reference
to the accompanying drawings. For the sake of convenience, the same reference numerals
will be used to designate the same or similar components of the present invention
in the accompanying drawings.
A perspective view of an embodiment of a prefabricated semiconductor die carrier
in accordance with the present invention is shown in FIG. 3. A partial view of
the embodiment of FIG. 3 is shown in FIG. 4. In accordance with the embodiment
of FIG. 3, the semiconductor die carrier includes a semiconductor die
101;
an insulating substrate
102, having a floor
102a and a plurality
of side walls
102b; a plurality of leads
103, including lower
leads
103a and upper leads
103b; a plurality of bonding
pads
104 formed on the semiconductor die; a plurality of bonding terminals
105 formed on the leads
103, respectively; and a plurality of bonding
wires
106 each connecting at least one of the bonding pads
104 of
the die to a corresponding one of the bonding terminals
105 formed on the leads.
While the semiconductor die and semiconductor die carrier of the embodiment
of FIG. 3 are depicted as being square, both the semiconductor die and the die
carrier could assume another shape, such as a rectangle having sides of different
lengths. Also, the number of sides the semiconductor die carrier can be varied,
such that die carriers having twelve sides, for example, as depicted in FIG. 5,
or
