Processor and program execution method capable of efficient program execution Number:7,386,707 from the United States Patent and Trademark Office (PTO) owispatent A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.<H execution, efficient, Processor, and, p, 7386707.html, Patent, pto, 7386707

Title: Processor and program execution method capable of efficient program execution

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

Patent Number: 7,386,707 Issued on 06/10/2008 to Kurata, et al.

Inventors: Kurata; Kazushi (Takatsuki, JP), Tanaka; Tetsuya (Souraku-gun, JP), Higaki; Nobuo (Kobe, JP), Hayashi; Kunihiko (Takatsuki, JP), Kadota; Hiroshi (Toyonaka, JP), Kiyohara; Tokuzo (Osaka, JP), Kimura; Kozo (Toyonaka, JP), Nishida; Hideshi (Nishinomiya, JP), Furukawa; Kazuya (Ibaraki, JP), Fujii; Shigeki (Neyagawa, JP), Sugimura; Toshio (Takarazuka, JP)
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)

Appl. No.: 10/338,408

Filed: January 8, 2003

Foreign Application Priority Data


Jan 09, 2002 [JP]			2002-002816
Jan 07, 2003 [JP]			2003-001616

Current U.S. Class: 712/218 ; 712/227

Field of Search: 712/228,218,227

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Other References

Guangzuo Cui et al.; "Parallel Replacement Mechanism for MultiThread." Advances in Parallel and Distributed Computing, 1997, pp. 338-344. cited by other.

Primary Examiner: Pan; Daniel

Claims

What is claimed is:

1. A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs, the programs stored in a main memory comprising: a plurality of register groups; a select/switch unit selecting one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit restoring, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit saving, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit executing, every time the switching is performed, a program corresponding to a register value group in the execution target register group, wherein the first predetermined period is specified, based on table information in which a plurality of count values are arranged in an order, every time the selection is performed, using the count values in the order, wherein there exists a plurality of candidate register value groups that are candidates for the restoring, a unique priority level is corresponded to each candidate register value group, and the restoring unit determines, based on the priority levels, the restore target from the plurality of candidate register value groups, and performs the restoring, and wherein each candidate register value group is included in one of a plurality of restore groups, a unique estimated execution period is corresponded to each restore group, the restoring unit determines, for each restore group, a candidate register value group included in the restore group as the restore target, and the select/switch unit principally sets, as a time interval from an mth to an m+1 th performing of the switching, an estimated execution period of a restore group that includes a register value group in the execution target register group by the select/switch unit in the mth switching, where m is a natural number.

2. The processor of claim 1, further comprising: a first detecting unit detecting an occurrence of a suspend-cause that results in the program execution being suspended; and a second detecting unit detecting a cancellation of the suspend-cause, wherein when the occurrence of a suspend-cause relating to a program for execution is detected, the program execution unit relinquishes, until the suspend-cause is cancelled, an execution period to be allotted for execution of the program.

3. The processor of claim 2, wherein the select/switch unit performs the switching exceptionally, when the relinquishing is performed by the program execution unit.

4. The processor of claim 3, wherein the program execution unit notifies the select/switch unit at a time of performing the relinquishing, and the select/switch unit performs the switching exceptionally, based on the notification.

5. The processor of claim 4, wherein at a time of determining the restore target from the plurality of candidate register value groups, the restoring unit removes, as a potential restore target, a candidate register value group corresponding to a program that has been targeted for the relinquishing, until the suspend-cause is cancelled.

6. The processor of claim 5, wherein the restoring unit determines, from the candidate register value groups that have not been removed, a candidate register value group having the highest priority level as the restore target.

7. The processor of claim 5, further comprising: a third obtaining unit obtaining information that designates a priority level in each restore group, wherein when the obtaining is performed by the third obtaining unit, the restoring unit determines, as the restore target, a candidate register value group that has not been removed and that corresponds to the designated priority level.

8. The processor of claim 5, further comprising: a third obtaining unit obtaining information that designates a priority level in each restore group, wherein when the obtaining is performed by the third obtaining unit, the restoring unit determines, as the restore target, a candidate register value group that has not been removed and that corresponds to a priority level that is higher than or equal to the designated priority level.

9. The processor of claim 5, wherein when a program is, as a result of a kth performing of the switching, to be executed for the first time after the relinquishing has been stopped, the select/switch unit sets, as a time interval from the kth to a k+1 th performing of the switching, a time period that was not used in the program execution because of the switching being brought forward at a time of the relinquishing, where k is a natural number.

10. The processor of claim 3, further comprising: a pre-cache unit writing, into an external cache for a duration that the relinquishing is performed, data required for executing a program that corresponds to a register value group stored in a register group to be selected as the execution target register group when the relinquishing is stopped.

11. The processor of claim 3, further comprising: a garbage collection unit performing garbage collection for a duration that the relinquishing is performed.

12. The processor of claim 1, further comprising: a fourth obtaining unit obtaining an execution request for a program that is to be executed non-steadily; and a first judging unit judging, when the execution request is obtained by the fourth obtaining unit, whether the program whose execution has been requested is a common-processing program that is executable during the execution of any other program.

13. The processor of claim 12, wherein when judged by the first judging unit that the program whose execution has been requested is a common-processing program, the program execution unit interrupts a program currently being executed and executes the common-processing program, and when the common-processing program has been executed, the select/switch unit does not include the execution period of the common-processing program in the execution period of the program currently being executed.

14. The processor of claim 13, wherein the select/switch unit does not include the execution period of the common-processing program in the execution period of the currently executed program, by stopping a time measurement counter for a duration that the common-processing is executed.

15. The processor of claim 12, wherein the common-processing is processing that results from a handling of a shared resource, and the select/switch unit stops the switching for a duration from a start to an end of the common-processing execution.

16. The processor of claim 1, further comprising: a fourth obtaining unit obtaining an execution request for a program that is to be executed non-steadily; and a second judging unit judging, when the execution request is obtained by the fourth obtaining unit, whether the program for non-steady execution is a specific-processing program that is to be executed following the execution of a specific program.

17. The processor of claim 16, wherein when judged by the second judging unit that the program whose execution is requested is a specific-processing program, the program execution unit executes the specific-processing program following the execution of the specific program, and when the specific-processing program has been executed, the select/switch unit includes a time period consumed to execute the specific-processing program in the consumed time period of an estimated execution period corresponded to the specific program.

18. The processor of claim 16, wherein when judged by the second judging unit that the program whose execution is requested is a specific-processing program, the program execution unit executes the specific-processing program following the execution of the specific program, when the specific-processing program has been executed, the select/switch unit does not include a first consumed time period consumed to execute the specific-processing program in a second consumed time period of an estimated execution period corresponded to the specific program, and when the specific program is next executed, the select/switch unit includes the first consumed time period in a third consumed time period of the estimated execution period corresponded to the specific program.

19. The processor of claim 1, further comprising: a third detecting unit detecting an occurrence of an execution request for an event-use program, wherein the plurality restore groups includes a first restore group to which an order is corresponded, and a second restore group to which an order is not corresponded, an event-use register value group that corresponds to the event-use program is included in the second restore group, and the restoring unit (i) normally performs the determining sequentially starting with the first restore group based on the order corresponded to the first restore group, and (ii) interrupts the order when the occurrence of an execution request for an event-use program is detected by the third detecting unit, and determines the event-use register value group as the restore target.

20. The processor of claim 19, wherein when the occurrence of an execution request for an event-use program is detected by the third detecting unit, the restoring unit restores the event-use register value group into one of the register groups that is not selected as the execution target register group, and the select/switch unit performs the switching, when the restoring of the event-use register value group is completed.

21. The processor of claim 20, further comprising: a first adjustment unit adjusting the execution period of a program, so as to recuperate, when the program is next executed, a time period that was relinquished as a result of the switching being performed exceptionally during a previous execution of the program.

22. The processor of claim 19, further comprising: a second adjustment unit delaying, when an execution frequency of the event-use program exceeds a threshold, the determining of the event-use register value group by the restoring unit, and adjusting the execution frequency so as not to exceed the threshold.

23. The processor of claim 1, further comprising: a third judging unit for judging whether the switching of the selection target is currently possible, wherein when the select/switch unit attempts to perform the switching and the third judging unit judges that switching is not currently possible, the select/switch unit delays the switching until the third judging unit judges that switching is currently possible.

24. The processor of claim 23, further comprising: a third adjustment unit subtracting , from an estimated execution period that corresponds to a specific restore group, a time period by which the estimated execution period is exceeded as a result of the delaying by the select/switch unit.

25. The processor of claim 1, wherein a unique order is corresponded to each restore group, and the restoring unit sequentially performs the determining based on the order corresponded to the restore group.

Description

This application is based on applications no. 2002-002816 and no. 2003-001616 filed in Japan, the content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to processors, and in particular to technology for efficiently executing programs.

2. Related Art

Conventionally, there exist operating systems (OS) that use a single processor to process a plurality of tasks in a pseudo-parallel manner.

An OS such as this makes a processor repeatedly execute the following processing.

The processor is made to store, in a register group within the processor, control information (hereafter "contexts") showing an execution position, a data storage location and the like of a computer program (hereafter, simply "program") corresponding to each task, to execute the task after obtaining a program, data and the like based on the stored context, to update the context following the execution of the task, and to write the updated context into memory.

Here, for the sake of convenience, the writing of a context stored in an external memory into a register group is referred to as "restoring", and the writing of a context stored in a register group into an external memory is referred to as "saving".

FIG. 32 is a functional block diagram of a conventional processor 1001 that executes tasks under the control of an OS such as described above, and additionally shows a context memory 1010 that stores contexts.

Processor 1001 includes a processing execution unit 1002 that executing tasks, a processing control unit 1003 that performs controls relating to the processing conducted by processing execution unit 1002, and a register group 1004 that stores contexts of the tasks to be executed.

Register group 1004 is a collection of registers, each of which is for storing a context (i.e. a register value group) corresponding to a task.

Every time a new context is stored in register group 1004, processing execution unit 1002 obtains a program and data based on the new context, and executes a task.

Processing control unit 1003 saves a context already stored in register group 1004 by overwriting context memory 1010, judges which context should be targeted for storage in register group 1004, and restores a context by reading a targeted context from context memory 1010 based on the judgment and writing the read context into register group 1004.

As a result, it is necessary to interrupt the execution of tasks by processing execution unit 1002 for the duration of the saving, judging and restoring (i.e. updating of contexts) by processing control unit 1003.

FIG. 33 shows the execution of tasks in processor 1001, and the input/output of contexts between register group 1004 and context memory 1010.

Time flows from left to right in this diagram.

Here, the tasks are executed uniformly in the sequence task A, task B, task C and task D, and the processing returns to task A after task D.

Conventionally, when tasks are executed, the saving, judging and restoring described above are performed before a task is executed.

In other words, the saving, judging and restoring are incurred as an overhead in the execution of tasks.

Here, if a single processing cycle is defined as the processing from tasks A to D, the above OS regulates the execution sequence and timing of the tasks (i.e. schedules the tasks) in a single cycle.

Processing control unit 1003 determines, based on this schedule, a context to be targeted for storage in register group 1004 (i.e. the above judging).

By performing the above processing, it is possible for a plurality of tasks to be processed in a pseudo-parallel manner by a single processor.

Furthermore, there also exist processors that use hardware to execute the above saving, judging and restoring, and then process a plurality of tasks in a pseudo-parallel manner.

However, when a plurality of tasks are processed in a pseudo-parallel manner by a single processor as described above, efficient execution of the tasks cannot be conducted, because of the overhead incurred to perform the above saving, judging and restoring before a task is executed, and the subsequent time taken between completing one task and commencing the next task, in comparison to when a single task is executed continuously.

Particularly in the case of broadcasting devices and the like, such as television receivers and communication devices (e.g. mobile telephones), it is necessary for data processing to be executed under near realtime conditions. However, when a plurality of tasks are processed in a pseudo-parallel manner in devices such as these, it is difficult to realize the above near realtime execution of data processing using conventional task execution methods that incur the above overhead.

SUMMARY OF THE INVENTION

In view of the above issue, a first object of the present invention is to provide a processor capable of executing tasks (i.e. programs) efficiently when a plurality of tasks are executed in a pseudo-parallel manner by a single processor.

Furthermore, a second object is to provide a program execution method capable of executing tasks efficiently.

To achieve the first object, a processor is for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs, and the processor includes: a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

According to this structure, a register value group is restored into a register group other than the execution target register group without affecting the current program execution. Then, when a program is to be executed based on this register group, the program can be promptly readied for execution because the overheads associated with restoring, saving, and the like have been eliminated, and thus the program is executed quickly.

Furthermore, as a result of the elimination of these overheads, program execution periods are not affected, even when the switching is conducted frequently, and thus this structure is effective in parallel execution by pseudo-realtime processing.

Here, the program execution unit may start the executing when the switching is performed.

According to this structure, when a program is to be executed, the program is executed promptly, and virtually all overheads are eliminated.

Here, processor may further include a first obtaining unit operable to obtain sequence information that shows a sequence of the register value groups corresponding to the programs, and the restoring unit may determine, based on the sequence information, a register value group to be restored, and perform the restoring.

According to this structure, an execution sequence of the programs is determined by the sequence information.

Here, the first predetermined period may be determined such that, if the restoring is performed on all of the register value groups in the sequence shown in the sequence information, a total time period that the restored register groups are selected as the execution target register group is within a second predetermined period.

According to this structure, pseudo-parallel execution of a plurality of processing operations is conducted within a limited time period.

In other words, this structure is effective in pseudo-parallel realtime processing and the like in which the processing time is limited.

Here, the sequence information may be a table in which identification information unique to each register value group is arrayed in a predetermined order, and the sequence may be shown by the order of the arrayed identification information.

According to this structure, a restore sequence of the register value groups is shown by an order of the arrayed identification information, and this restore sequence can be altered by changing an order of the array.

Here, the table may include identification information that is identical, the identical identification information may be arrayed so as to be dispersed throughout the array, and the number of pieces of identical identification information in the array may be unique for each program corresponding to a register value group specified by a piece of identification information.

According to this structure, an execution timing of each of the programs is equalized.

Here, the plurality of programs may include a management program that is for judging whether the table requires changing, and for changing the table when required, and the number of pieces of identification information in the array that specify a location of a register value group corresponding to the management program may be only one.

According to this structure, there is an opportunity to change the table whenever pseudo-parallel execution is conducted.

Here, the first predetermined period may be unique for each program, each piece of identification information may have appended a piece of time period information that shows the unique time period of a program corresponding to a register value group specified by the piece of identification information, and the management program may perform the changing such that a total of the unique time periods is within the second predetermined period.

According to this structure, the unique time periods are updated by a management program, so that pseudo-parallel execution of a plurality of processing operations is conducted within a limited time period.

Here, when judged during execution of the management program that the table requires changing, the program execution unit may generate a dummy table showing a state of the table after the changing, and perform the changing by replacing the table with the dummy table.

According to this structure, it is possible to change the table without affecting the current program execution.

Here, the plurality of programs may include an image processing program for executing image processing, and the number of pieces of identification information in the array that specify a location of a register value group corresponding to the image processing program may be greater than that of the other programs.

According to this structure, an image-processing program having a large information volume is allotted a longer processing period in total.

Here, the identification information may be address values that show storage locations of the register value groups, and the restoring unit may specify, based on the address values, a location of a register value group for restoring, and perform the restoring.

According to this structure, it is possible to show a restore sequence of the register value groups by the relative size of the address values.

Here, the sequence information may be a table in which the identification information unique to each register value group has attached pointers that point to other identification information, and the sequence may be shown by following the pointers.

According to this structure, a restore sequence of the register value groups is shown by pointers, and this sequence can be altered by changing the targets indicated by the pointers.

Here, the processor may further include a first detecting unit operable to detect an occurrence of a suspend-cause that results in the program execution being suspended; and a second detecting unit operable to detect a cancellation of the suspend-cause, and when the occurrence of a suspend-cause relating to a program for execution is detected, the program execution unit may relinquish, until the suspend-cause is cancelled, an execution period to be allotted for execution of the program.

According to this structure, meaningless program execution is avoided.

Here, there may be a plurality of the suspend-causes, the suspend-cause effective as a trigger of the relinquishing may be unique for each program, and the program execution unit may only perform the relinquishing when an effective suspend-cause of a currently executed program occurs.

According to this structure, it is judged for each program whether to perform the relinquishing when a suspend-cause occurs.

Here, the processor may further include a second obtaining unit operable to obtain suspend information that corresponds (i) information specifying one of the plurality of suspend-causes with (ii) information showing whether the specified suspend-cause has occurred. Furthermore, the register value groups may each include setting information that corresponds (i) information specifying one of the plurality of suspend-causes with (ii) information showing whether the specified suspend-cause is effective, and the program execution unit may refer comparatively to the suspend information and the setting information, and judge whether to perform the relinquishing.

According to this structure, an effective suspend-cause can be specified, even when there is a plurality of suspend-causes.

Here, the suspend information may be bit string data in which a unique bit position is determined for each suspend-cause, and in which each bit position has a value that shows whether a suspend-cause corresponding to the bit position has occurred, the setting information may be bit string data in which a unique bit position is determined for each suspend-cause, and in which each bit position has a value that shows whether a suspend-cause corresponding to the bit position is effective, and the program execution unit may only refers to a bit position of a suspend-cause in the suspend information that corresponds to a bit position in the setting information that has a value showing the suspend-cause to be effective.

According to this structure, the reference range is limited, and thus an effective suspend-cause can be promptly specified, even when there is a plurality of suspend-causes.

Here, the program execution unit may notify the restoring unit at a time of performing the relinquishing, and the restoring unit may perform the restoring while ignoring an order in the sequence of a register value group corresponding to the program that has been targeted for the relinquishing, by not targeting the register value group for restoring until the suspend-cause is cancelled.

According to this structure, unnecessary restoring of register value groups is avoided.

Here, when notified of the relinquishing, the restoring unit may exceptionally set the ignored register value group as a priority restore target candidate in a second performing of the restoring after the notification. Furthermore, if the suspend-cause is cancelled before the start of the second restoring, the restoring unit may determine the register value group as the restore target, and if the suspend-cause is not cancelled before the start of the second restoring, the restoring unit may continue to ignore the register value group until the suspend-cause is cancelled.

According to this structure, it is possible to execute another effective program during a relinquished time period.

Here, when a plurality of register value groups are ignored by the restoring unit, and the suspend-cause is cancelled with respect to two or more of the plurality of register value groups, the restoring unit may set, as the restore target when the restoring is next performed, whichever of the two or more register value groups was ignored later.

According to this structure, the restoring of an ignored register group at a biased time after the cancellation of a suspend-cause is avoided.

Here, the program execution unit may notify the select/switch unit at a time of performing the relinquishing, and the select/switch unit may perform the switching when the notification is received.

According to this structure, it is possible for execution of a subsequent program to be promptly started when the relinquishing is conducted.

Here, the suspend-cause may be a cache-miss occurring at a time of a program execution.

According to this structure, the execution of a subsequent program is promptly started when a cache-miss occurs.

Here, the suspend-cause may be a state of waiting for a processing result from an external apparatus that was requested to perform processing at a time of a program execution.

According to this structure, the execution of a subsequent program is promptly started when the above state occurs.

Here, the suspend-cause may be a state of waiting for a release of a shared resource, when the shared resource is required at a time of a program execution.

According to this structure, the execution of a subsequent program is promptly started when the above state occurs.

Here, the program execution unit may have a CPU for use in program execution, and stop the CPU during an execution period of the relinquishing.

According to this structure, wasted power consumption is avoided.

Here, the program execution unit may have a CPU for use in program execution, and reduce the drive frequency of the CPU during an execution period of the relinquishing.

According to this structure, wasted power consumption is reduced.

Here, the program execution unit may have a CPU for use in program execution, and adjust the drive frequency of the CPU in accordance with a program execution load when the plurality of programs are executed, such that a free processing time period does not occur due to a processing capacity of the CPU being too high with respect to the program execution load.

According to this structure, wasted power consumption is reduced.

Here, there may be two register groups, and the select/switch unit may perform the switching alternately with respect to the two register groups.

According to this structure, pseudo-parallel execution of a plurality of programs is conducted using only two register groups, while at the same time eliminating overheads.

In other words, two register groups is sufficient, irrespective of the number of program to be executed in a pseudo-parallel manner.

Here, the program execution unit may perform pipeline processing having N number of stages, and the saving unit may perform the saving (N-1) clocks after a clock in which the switching was performed.

According to this structure, even when pipeline processing is executed, pseudo-parallel execution of a plurality of programs can be conducted, while at the same time eliminating overheads.

Here, the select/switch unit may determine the selection target from the plurality of register groups by a predetermined sequence, and perform the switching. Furthermore, the restoring unit may determine the restore target from the plurality of register groups by a predetermined sequence, and perform the restoring.

According to this structure, programs are promptly readily for execution because overheads related to restoring, saving and the like have been eliminated, and thus the execution of programs can be quickly completed.

Here, there may exist a plurality of candidate register value groups that are candidates for the restoring, and a unique priority level may be corresponded to each candidate register value group. Furthermore, the restoring unit may determine, based on the priority levels, the restore target from the plurality of candidate register value groups, and perform the restoring.

According to this structure, a candidate register value group to be the restore target is determined from a plurality of candidate register value group, based on the priority levels.

In other words, the flexibility of the restoring is improved as a result of the restore target not being fixed.

Here, each candidate register value group may be included in one of a plurality of restore groups, a unique estimated execution period may be corresponded to each restore group, the restoring unit may determine, for each restore group, a candidate register value group included in the restore group as the restore target, and the select/switch unit may principally set, as a time interval from an m.sup.th to an m+1.sup.th performing of the switching, an estimated execution period of a restore group that includes a register value group in the execution target register group by the select/switch unit in the m.sup.th switching, where m is a natural number.

According to this structure, an estimated execution period corresponded to each restore group is set as the interval between the switching performed by the select/switch unit.

Here, the processor may further include a first detecting unit operable to detect an occurrence of a suspend-cause that results in the program execution being suspended; and a second detecting unit operable to detect a cancellation of the suspend-cause, and when the occurrence of a suspend-cause relating to a program for execution is detected, the program execution unit may relinquish, until the suspend-cause is cancelled, an execution period to be allotted for execution of the program.

According to this structure, it is possible to avoid the program execution unit attempting to execute a program with respect to which a suspend-cause suspending the program execution has occurred.

Here, the select/switch unit may perform the switching exceptionally, when the relinquishing is performed by the program execution unit.

According to this structure, a program corresponding to restored register value group is immediately executed when the relinquishing is conducted.

Here, the program execution unit may notify the select/switch unit at a time of performing the relinquishing, and the select/switch unit may perform the switching exceptionally, based on the notification.

According to this structure, the switching is performed exceptionally in the select/switch unit as a result of the notification being received.

Here, at a time of determining the restore target from the plurality of candidate register value groups, the restoring unit may remove, as a potential restore target, a candidate register value group corresponding to a program that has been targeted for the relinquishing, until the suspend-cause is cancelled.

According to this structure, it is possible to avoid the program execution unit attempting to execute, next time, a program with respect to which a suspend-cause suspending the program execution has occurred.

Here, the restoring unit may determine, from the candidate register value groups that have not been removed, a candidate register value group having the highest priority level as the restore target.

According to this structure, a program corresponding to a register value group to be restored is limited to programs with respect to which a suspend-cause has not occurred, and since the program has a high priority level corresponded, it can be executed with great efficiency.

Here, the processor may further include a third obtaining unit operable to obtain information that designates a priority level in each restore group, and when the obtaining is performed by the third obtaining unit, the restoring unit may determine, as the restore target, a candidate register value group that has not been removed and that corresponds to the designated priority level.

According to this structure, a register value group to be the restore target is altered by changing the designated priority levels.

Here, the processor may further include a third obtaining unit operable to obtain information that designates a priority level in each restore group, and when the obtaining is performed by the third obtaining unit, the restoring unit may determine, as the restore target, a candidate register value group that has not been removed and that corresponds to a priority level that is higher than or equal to the designated priority level.

According to this structure, the opportunity for program execution is improved, because a program with respect to which a suspend-cause has not occurred and that is within a range including a specified priority level, is executed.

Here, when a program is, as a result of a k.sup.th performing of the switching, to be executed for the first time after the relinquishing has been stopped, the select/switch unit may set, as a time interval from the k.sup.th to a k+1.sup.th performing of the switching, a time period that was not used in the program execution because of the switching being brought forward at a time of the relinquishing, where k is a natural number.

According to this structure, when a time period remains unused, this time period is consumed when the program is next executed.

Here, the processor may further include a pre-cache unit operable to write, into an external cache for a duration that the relinquishing is performed, data required for executing a program that corresponds to a register value group stored in a register group to be selected as the execution target register group when the relinquishing is stopped.

According to this structure, the occurrence of a cache-miss at a next program execution time is prevented.

Here, the processor may further include a garbage collection unit operable to perform garbage collection for a duration that the relinquishing is performed.

According to this structure, the occurrence of a memory-release wait at the next program execution time is prevented.

Here, the processor may further include a fourth obtaining unit operable to obtain an execution request for a program that is to be executed non-steadily; and a first judging unit operable to judge, when the execution request is obtained by the fourth obtaining unit, whether the program whose execution has been requested is a common-processing program that is executable during the execution of any other program.

According to this structure, when an execution request for a common-processing program is received, it is recognized that the program is executable during execution of any of the programs.

Here, when judged by the first judging unit that the program whose execution has been requested is a common-processing program, the program execution unit may interrupt a program currently being executed and executes the common-processing program, and when the common-processing program has been executed, the select/switch unit may not include the execution period of the common-processing program in the execution period of the program currently being executed.

According to this structure, the execution period of a currently executed program is not affected by the interrupt execution of a common-processing program,

Here, the select/switch unit may not include the execution period of the common-processing program in the execution period of the currently executed program, by stopping a time measurement counter for a duration that the common-processing is executed.

According to this structure, a time period consumed in the interrupt execution of a common-processing program can easily be removed (i.e. not included) in a consumed amount of the estimated execution period of a currently executed program.

Here, the common-processing may be processing that results from a handling of a shared resource, and the select/switch unit may stop the switching for a duration from a start to an end of the common-processing execution.

According to this structure, a time period consumed in the interrupt operation of a shared resource can be easily removed (i.e. not included) in a consumed amount of the estimated execution period of a currently executed program.

Here, the processor may further include a fourth obtaining unit operable to obtain an execution request for a program that is to be executed non-steadily; and a second judging unit operable to judge, when the execution request is obtained by the fourth obtaining unit, whether the program for non-steady execution is a specific-processing program that is to be executed following the execution of a specific program.

According to this structure, when an execution request for a specific-processing program is received, it is recognized that the program is executable during the execution of a specific program.

Here, when judged by the second judging unit that the program whose execution is requested is a specific-processing program, the program execution unit may execute the specific-processing program following the execution of the specific program, and when the specific-processing program has been executed, the select/switch unit may include a time period consumed to execute the specific-processing program in the consumed time period of an estimated execution period corresponded to the specific program.

According to this structure, an execution period of the specific program is affected by the interrupt execution of a specific-processing program, and shortened as a result.

Furthermore, efficient program execution can be conducted, because when an execution request for a specific-processing program is received the program execution unit (i.e. the CPU) does not have to judge whether or not to accept the request.

Here, when judged by the second judging unit that the program whose execution is requested is a specific-processing program, tile program execution unit may execute the specific-processing program following the execution of the specific program. Furthermore, when the specific-processing program has been executed, the select/switch unit may not include a first consumed time period consumed to execute the specific-processing program in a second consumed time period of an estimated execution period corresponded to the specific program, and when the specific program is next executed, the select/switch unit may include the first consumed time period in a third consumed time period of the estimated execution period corresponded to the specific program.

According to this structure, when an execution request for a specific-processing program is received, the execution period of a specific program is not affected by the interrupt execution of the specific-processing program. Then, when the specific program is next executed, the execution period of the specific program is affected by the interrupt execution of the specific-processing program, and shortened as a result.

In other words, consecutive interrupt processing operations can be processed promptly without being suspended.

Here, the processor may further include a third detecting unit operable to detect an occurrence of an execution request for an event-use program. Furthermore, the plurality restore groups may include a first restore group to which an order is corresponded, and a second restore group to which an order is not corresponded, an event-use register value group that corresponds to the event-use program may be included in the second restore group. Moreover, the restoring unit (i) may normally perform the determining sequentially starting with the first restore group based on the order corresponded to the first restore group, and (ii) may interrupt the order when the occurrence of an execution request for an event-use program is detected by the third detecting unit, and determine the event-use register value group as the restore target.

According to this structure, when an execution request for an event-use program occurs, it is possible to execute the event-use program immediately.

Here, when the occurrence of an execution request for an event-use program is detected by the third detecting unit, the restoring unit may restore the event-use register value group into one of the register groups that is not selected as the execution target register group, and the select/switch unit may perform the switching exceptionally, when the restoring of the event-use register value group is completed.

According to this structure, when an execution request for an event-use program occurs, the event-use program is executed immediately.

Here, the processor may further include a first adjustment unit operable to adjust the execution period of a program, so as to recuperate, when the program is next executed, a time period that was relinquished as a result of the switching being performed exceptionally during a previous execution of the program.

According to this structure, the execution period of a program is adjusted to recuperate a relinquished time period, and thus the execution period of the program is guaranteed, even when relinquishing is conducted.

Here, the processor may further include a second adjustment unit operable, when an execution frequency of the event-use program exceeds a threshold, to delay the determining of the event-use register value group by the restoring unit, and to adjust the execution frequency so as not to exceed the threshold.

According to this structure, it is possible to suppress reductions in the execution frequency of a program corresponding to a register value group that belongs to the first restore group.

Here, the processor may further include a third judging unit for judging whether the switching of the selection target is currently possible, and when the select/switch unit attempts to perform the switching and the third judging unit judges that switching is not currently possible, the select/switch unit may delay the switching until the third judging unit judges that switching is currently possible.

According to this structure, a program can be completed normally.

Here, the processor may further include a third adjustment unit operable to subtract, from an estimated execution period that corresponds to a specific restore group, a time period by which the estimated execution period is exceeded as a result of the delaying by the select/switch unit.

According to this structure, it is possible to prevent a breakdown in the program execution periods caused by the accumulation of exceeded time periods.

In other words, the actual execution period of a program corresponding to register values that belongs to a restore group other than a specific restore group is set to be greater than or equal to an estimated execution period corresponded to the register group, and thus the execution period of the program is guaranteed.

Here, a unique order may be corresponded to each restore group, and the restoring unit may sequentially perform the determining based on the order corresponded to the restore group.

According to this structure, programs are executed in an order corresponded to each restore group.

Here, the processor may further include a changing unit operable to change priority levels corresponded to the candidate register value groups.

According to this structure, the program for execution can easily be changed.

Here, the processor may further include a first detecting unit operable to detect an occurrence of a suspend-cause that results in the program execution being suspended; a second detecting unit operable to detect a cancellation of the suspend-cause; and a power-consumption reducing unit operable to reduce a power consumption of hardware for executing programs. Furthermore, when the occurrence of a suspend-cause relating to a program for execution is detected, the program execution unit may relinquish, until the suspend-cause is cancelled, an execution period to be allotted for execution of the program, and the power-consumption reducing unit may perform the reducing for a duration that the relinquishing is performed.

According to this structure, the reducing by the power-consumption reducing unit is performed during a relinquished time period of an estimate execution period of a currently executed program, in order to achieve power reductions.

Furthermore, by doing nothing in a time period leftover as a result of the execution-suspension of a program, it is possible to maintain, as much as possible, uniform execution cycles (i.e. maintain periodicity) of the programs.

Here, the program execution unit may have a CPU for executing programs, and the power-consumption reducing unit may perform the reducing for the duration that the relinquishing is performed by blocking a clock signal supplied to the CPU.

According to this structure, the power reductions can be easily achieved.

Here, the program execution unit may have a CPU for executing programs, and the power-consumption reducing unit may perform the reducing for the duration that the relinquishing is performed by reducing a voltage applied to the CPU or setting the voltage to zero.

According to this structure, the power reductions can be easily achieved.

Here, the processor may further include a receiving unit for receiving an execution request for a program that is to be executed non-steadily, and the power-consumption reducing unit may stop the reducing if the reducing is being performed when the execution request is received.

According to this structure, an execution request relating to a program other than a program for urgent execution is not accepted, and thus it is possible to omit the program execution-required judgment processing by the program execution unit (i.e. the CPU), and to conduct program execution efficiently.

Here, the execution request may be an interrupt-processing request.

According to this structure, it is possible to stop the reducing by the power-consumption reducing unit when an interrupt-processing request occurs.

Here, the execution request may be an event-processing request for urgently executing a program following the exceptional switching by the select/switch unit.

According to this structure, it is possible to stop the reduction by the power-consumption reducing unit when an event-processing request occurs.

Here, the restoring unit may copy the register value groups stored in the memory, and perform the restoring. Furthermore, following the program execution, the program execution unit may change one or more register value restored into the execution target register group, and the saving unit may only perform the saving when the changing has been performed by the program execution unit.

According to this structure, only changed register values are saved, and thus a time period required for the saving is shortened.

Here, each register of the plurality of register groups may have attached a piece of change information showing whether a register value restored into the register has been changed, and the saving unit may perform the saving by writing, based on the change information, only a changed register value into a location, in the memory, in which the register value prior to being changed is stored.

According to this structure, the existence of a change is easily recognized and only changed register values are saved, and thus a time period required for the saving can be shortened.

Here, each piece of change information may be a 1-bit flag.

According to this structure, changes are shown by the flags.

Here, the first predetermined period may be a fixed time period.

According to this structure, the switching is facilitated.

Here, the first predetermined period may be unique for each of the plurality of programs.

According to this structure, it is possible to allot a program execution period suitable for the execution of each program.

Here, the processor may further include a plurality of caches for storing execution data that is required in the program execution; a specifying unit operable to refer, following the restoring by the restoring unit, to a register value group that was restored, and to specify the execution data of a program that corresponds to the register value group; and a writing unit operable to write the specified execution data into one of the caches that is not being used in the program execution.

According to this structure, the occurrence of a cache-miss is avoided.

To achieve the second object, a program execution method is for executing a program in a processor, the processor including a plurality of register groups and sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs, and the program execution method including: a select/switch step of selecting one of the plurality of register groups as an execution target register group on which a program execution is based, and switching the selection target every time a first predetermined period elapses; a restoring step of restoring, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving step of saving, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution step of executing, every time the switching is performed, a program corresponding to a register value group i