Programming circuit and method having extended duration programming capabilities Number:6,836,145 from the United States Patent and Trademark Office (PTO) owispatent

Title: Programming circuit and method having extended duration programming capabilities

Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

Patent Number: 6,836,145 Issued on 12/28/2004 to Mecier,   et al.

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Inventors:	Mecier; Richard A. (Boise, ID); Ingalls; Charles L. (Meridian, ID)
Assignee:	Micron Technology, Inc. (Boise, ID)
Appl. No.:	165666
Filed:	June 6, 2002

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Current U.S. Class:	326/38 ; 326/88; 327/390; 327/525; 365/96
Field of Search:	326/88,92,38 327/390,589,525,536 365/96,225.7,536

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References Cited [Referenced By]

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U.S. Patent Documents

	5495436		February 1996		Callahan
	5687116		November 1997		Kowshik et al.
	5844298		December 1998		Smith et al.
	5896041		April 1999		Sher et al.

Primary Examiner: Chang; Daniel
Attorney, Agent or Firm: Dorsey & Whitney LLP

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Claims

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What is claimed is:

1. A programming circuit for selectively either isolating a circuit ground node from an external terminal of an integrated circuit or allowing a programming voltage to be coupled from the external terminal to the circuit ground node, the programming circuit comprising: an isolation device coupled between the external terminal and the circuit ground node, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the circuit ground node, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the circuit ground node as long as the absolute value of the voltage coupled to the circuit ground node is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; and a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage, the charge pump circuit comprising: a capacitive device having first and second terminals; a boosting circuit coupled to the first terminal of the capacitive device, the boosting circuit being operable to apply a voltage to the first terminal of the capacitive device that varies between first and second voltages; a first current path coupled between the external terminal and the second terminal of the capacitive device, the first current path allowing current to flow to or from the capacitive device to change the charge of the capacitive device in a first direction when the boosting circuit is applying the first voltage to the first terminal of the capacitive device: and a second current path coupled between the second terminal of the capacitive device and the control terminal of the isolation device, the second current path allowing current to or from the capacitive device to change the charge of the capacitive device in a second direction that is opposite the first direction when the boosting circuit is applying the second voltage to the first terminal of the capacitive device.

2. The programming circuit of claim 1 wherein the isolation device comprises a MOSFET transistor.

3. The programming circuit of claim 2 wherein the isolation device comprises an NMOS isolating transistor.

4. The programming circuit of claim 1, wherein the first current path comprises a MOSFET transistor.

5. The programming circuit of claim 4, wherein the MOSFET transistor comprises an NMOS isolating transistor.

6. The programming circuit of claim 1, wherein the second current path comprises a MOSFET transistor.

7. The programming circuit of claim 6, wherein the MOSFET transistor comprises an NMOS isolating transistor.

8. The programming circuit of claim 1 wherein the capacitive device comprises a MOSFET transistor in which one of the first and second terminals comprises source and drain terminals of the MOSFET transistor and the other of the first and second terminals comprises a gate of the MOSFET transistor.

9. The programming circuit of claim 1, further comprising a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

10. The programming circuit of claim 9 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

11. The programming circuit of claim 10 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the dram of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

12. The programming circuit of claim 10 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

13. A voltage generating circuit for coupling a control voltage to a gate of an NMOS isolating transistor having sufficient magnitude to allow a programming voltage applied to an external terminal to be coupled to the circuit ground node through the NMOS isolating transistor, the voltage generating circuit comprising a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to a gate of the NMOS isolating transistor, the charge pump being operable to receive the programming voltage applied to the external terminal and to increase the programming voltage to generate a voltage applied to the output terminal that is larger than the voltage of the programming voltage, the charge pump circuit comprising: a capacitive device having first and second terminals; a boosting circuit coupled to the first terminal of the capacitive device, the boosting circuit being operable to apply a voltage to the first terminal of the capacitive device that varies between first and second voltages; a charge path coupled between the external terminal and the second terminal of the capacitive device, the charge path allowing charge current to flow through the charge path when the boosting circuit is applying the first voltage to the first terminal of the capacitive device; and a discharge path coupled between the second terminal of the capacitive device and the gate of the NMOS isolating transistor, the discharge path allowing discharge current to flow through the discharge path when the boosting circuit is applying the second voltage to the first terminal of the capacitive device.

14. The voltage generating circuit of claim 13, wherein the charge path comprises an NMOS isolating transistor.

15. The voltage generating circuit of claim 13, wherein the discharge path comprises an NMOS isolating transistor.

16. The voltage generating circuit of claim 13 wherein the capacitive device comprises a MOSFET transistor in which one of the first and second terminals comprises source and drain terminals of the MOSFET transistor and the other of the first and second terminals comprises a gate of the MOSFET transistor.

17. The voltage generating circuit of claim 13, further comprising a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

18. The voltage generating circuit of claim 17 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the gate of the NMOS isolating transistor only as long a the voltage of the gate is below a predetermined voltage.

19. The voltage generating circuit of claim 18 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

20. The voltage generating circuit of claim 18 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the gate of the NMOS isolating transistor and a gate coupled to receive the power supply voltage.

21. A memory device, comprising: a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals; at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array; a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device; and a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising: an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; and a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage, the charge pump circuit comprising: a capacitive device having first and second terminals; a boosting circuit coupled to the first terminal of the capacitive device, the boosting circuit being operable to apply a voltage to the first terminal of the capacitive device that varies between first and second voltages; a charge path coupled between the external terminal and the second terminal of the capacitive device, the charge path allowing charge current to flow through the charge path when the boosting circuit is applying the first voltage to the first terminal of the capacitive device; and a discharge path coupled between the second terminal of the capacitive device and the control terminal of the isolation device, the discharge path allowing discharge current to flow through the discharge path when the boosting circuit is applying the second voltage to the first terminal of the capacitive device.

22. The memory device of claim 21 wherein the isolation device comprises a MOSFET transistor.

23. The memory device of claim 22 wherein the isolation device comprises an NMOS isolating transistor.

24. The memory device of claim 21, wherein the charge path comprises a MOSFET transistor.

25. The memory device of claim 24, wherein the MOSFET transistor comprises an NMOS isolating transistor.

26. The memory device of claim 21, wherein the discharge path comprises a MOSFET transistor.

27. The memory device of claim 26, wherein the MOSFET transistor comprises an NMOS isolating transistor.

28. The memory device of claim 21 wherein the capacitive device comprises a MOSFET transistor in which one of the first and second terminals comprises source and drain terminals of the MOSFET transistor and the other of the first and second terminals comprises a gate of the MOSFET transistor.

29. The memory device of claim 21, further comprising a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

30. The memory device of claim 29 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

31. The memory device of claim 30 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor, and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

32. The memory device of claim 30 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

33. The memory device of claim 21 wherein the programmable elements comprise respective anti-fuses.

34. The memory device of claim 21 wherein the memory array further comprises a plurality of redundant rows of memory cells, and wherein the programmable elements, when programmed, are operable to substitute a redundant row of memory cells for a defective row of memory cells.

35. The memory device of claim 21, further comprising a mode register containing a plurality of the programmable elements, and wherein the programmable elements, when programmed, are operable to control the operating mode of the memory device.

36. A computer system, comprising: an integrated circuit processor having a plurality of external terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and an integrated circuit memory device a plurality of external terminals coupled to the processor bus, the integrated circuit memory device comprising: a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals; at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array; a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device; and a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising: an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; and a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage, the charge pump circuit comprising: a capacitive device having first and second terminals; a boosting circuit coupled to the first terminal of the capacitive device, the boosting circuit being operable to apply a voltage to the first terminal of the capacitive device that varies between first and second voltages; a charge path coupled between the external terminal and the second terminal of the capacitive device, the charge path allowing charge current to flow through the charge path when the boosting circuit is applying the first voltage to the first terminal of the capacitive device; and a discharge path coupled between the second terminal of the capacitive device and the control terminal of the isolation device, the discharge path allowing discharge current to flow through the discharge path when the boosting circuit is applying the second voltage to the first terminal of the capacitive device.

37. The computer system of claim 36 wherein the isolation device comprises a MOSFET transistor.

38. The computer system of claim 37 wherein the isolation device comprises an NMOS isolating transistor.

39. The computer system of claim 36, wherein the charge path comprises a MOSFET transistor.

40. The computer system of claim 39, wherein the MOSFET transistor comprises an NMOS isolating transistor.

41. The computer system of claim 36, wherein the discharge path comprises a MOSFET transistor.

42. The computer system of claim 41, wherein the MOSFET transistor comprises an NMOS isolating transistor.

43. The computer system of claim 36 wherein the capacitive device comprises a MOSFET transistor in which one of the first and second terminals comprises source and train terminals of the MOSFET transistor and the other of the first and second terminals comprises a gate of the MOSFET transistor.

44. The computer system of claim 36, further comprising a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

45. The computer system of claim 44 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

46. The computer system of claim 45 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

47. The computer system of claim 45 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

48. The memory device of claim 36 wherein the programmable elements comprise respective anti-fuses.

49. The memory device of claim 36 wherein the memory array further comprises a plurality of redundant rows of memory cells, and wherein the programmable elements, when programmed, are operable to substitute a redundant row of memory cells for a defective row of memory cells.

50. The memory device of claim 36, further comprising a mode register containing a plurality of the programmable elements, and wherein the programmable elements, when programmed, are operable to control the operating mode of the memory device.

51. A method of supplying a voltage to a gate of a MOSFET transistor to allow the transistor to couple a programming voltage from an external terminal of an integrated circuit to a circuit ground to which a programming element may be coupled, the method comprising: coupling a drain of the MOSFET transistor to the external terminal; and coupling a source of the MOSFET transistor to the circuit ground; boosting the magnitude of the programming voltage to provide a boosted programming voltage, the act of boosting the magnitude of the programming voltage to provide a boosted programming voltage comprising: changing a charge on the capacitive device in a first direction by coupling the programming voltage to a first terminal of the capacitive device while a second terminal of the capacitive device is at a first voltage; changing the voltage at the second terminal of the capacitive device to a second voltage; and changing a charge on the capacitive device in a second direction that is opposite the first direction by coupling the first terminal of the capacitive device to a gate of the MOSFET transistor, thereby applying the boosted programming voltage to the gate of the MOSFET transistor.

52. The method of claim 51 wherein the MOSFET transistor comprises an NMOS transistor.

53. The method of claim 51 wherein the act of changing a charge on the capacitive device in a first direction comprises charging the capacitive device and wherein the act of changing a charge on the capacitive device in a second direction comprises discharging the capacitive device.

54. The method of claim 51 wherein the second voltage is larger than the first voltage.

55. The method of claim 51 wherein the programming voltage comprises a positive voltage, and wherein the act of boosting the magnitude of the programming voltage to provide a boosted programming voltage comprises increasing the programming voltage to a larger positive voltage.

56. The method of claim 51, further comprising precharging the gate of the MOSFET transistor to a predetermined voltage prior to the act of applying the boosted programming voltage to the gate of the MOSFET transistor.

57. A method of programming a programmable element with a programming voltage in an integrated circuit in which the programmable element is coupled to a circuit ground node, the method comprising: when the programmable element is to be programmed: coupling an external terminal of the integrated circuit to the circuit ground node to the circuit ground node through a switching device having a control terminal; coupling a programming voltage to the external terminal; boosting the magnitude of the programming voltage to provide a boosted programming voltage, the act of boosting the magnitude of the programming voltage to provide a boosted programming voltage comprising: changing a charge on a capacitive device in a first direction by coupling the programming voltage to a first terminal of the capacitive device while a second terminal of the capacitive device is at a first voltage; changing the voltage at the second terminal of the capacitive device to a second voltage; and changing a charge on the capacitive device in a second direction that is opposite the first direction by coupling the first terminal of the capacitive device to the control terminal of the switching device thereby applying the boosted programming voltage to the control terminal of the switching device to cause the switching device to couple the programming voltage to the programmable element; and when the programming element is not to be programmed, applying a voltage to the control terminal of the switching device to cause the switching device to isolate the circuit ground node from the external terminal.

58. The method of claim 57, further comprising coupling the circuit ground node to a predetermined voltage when the programming element is not to be programmed.

59. The method of claim 57 wherein the switching device comprises a MOSFET transistor, and wherein the control terminal of the switching device comprises a gate of the MOSFET transistor.

60. The method of claim 59 wherein the MOSFET transistor comprises an NMOS transistor.

61. The method of claim 57 wherein the act of changing a charge on the capacitive device in a first direction comprises charging the capacitive device and wherein the act of changing a charge on the capacitive device in a second direction comprises discharging the capacitive device.

62. The method of claim 57 wherein the second voltage is larger than the first voltage.

63. The method of claim 57 wherein the programming voltage comprises a positive voltage, and wherein the act of boosting the magnitude of the programming voltage to provide a boosted programming voltage comprises increasing the programming voltage to a larger positive voltage.

64. The method of claim 57, further comprising precharging the control terminal of the switching device to a predetermined voltage prior to the act of applying the boosted programming voltage to the control terminal of the switching device.

65. A programming circuit for selectively either isolating a circuit ground node from an external terminal of an integrated circuit or allowing a programming voltage to be coupled from the external terminal to the circuit ground node, the programming circuit comprising: an isolation device coupled between the external terminal and the circuit ground node, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the circuit ground node, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the circuit ground node as long as the absolute value of the voltage coupled to the circuit ground node is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage; and a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

66. The programming circuit of claim 65 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

67. The programming circuit of claim 66 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor, and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

68. The programming circuit of claim 66 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

69. A voltage generating circuit for coupling a control voltage to a gate of an NMOS isolating transistor having sufficient magnitude to allow a programming voltage applied to an external terminal to be coupled to the circuit ground node through the NMOS isolating transistor, the voltage generating circuit comprising: a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to a gate of the NMOS isolating transistor, the charge pump being operable to receive the programming voltage applied to the external terminal and to increase the programming voltage to generate a voltage applied to the output terminal that is larger than the voltage of the programming voltage; and a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

70. The voltage generating circuit of claim 69 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the gate of the NMOS isolating transistor only as long a the voltage of the gate is below a predetermined voltage.

71. The voltage generating circuit of claim 70 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

72. The voltage generating circuit of claim 70 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the gate of the NMOS isolating transistor and a gate coupled to receive the power supply voltage.

73. A memory device, comprising: a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals; at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array; a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device; and a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising: an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming yoltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage; and a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

74. The memory device of claim 73 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

75. The memory device of claim 74 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

76. The memory device of claim 74 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

77. The memory device of claim 73 wherein the programmable elements comprise respective anti-fuses.

78. The memory device of claim 73 wherein the memory array further comprises a plurality of redundant rows of memory cells, and wherein the programmable elements, when programmed, are operable to substitute a redundant row of memory cells for a defective row of memory cells.

79. The memory device of claim 73, further comprising a mode register containing a plurality of the programmable elements, and wherein the programmable elements, when programmed, are operable to control the operating mode of the memory device.

80. A computer system, comprising: an integrated circuit processor having a plurality of external terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and an integrated circuit memory device a plurality of external terminals coupled to the processor bus, the integrated circuit memory device comprising: a command decoder receiving memory command signals through externally accessible input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible input terminals, the address decoder generating row and column addressing signals responsive to the address signals; at least one memory array including a plurality of memory cells arranged in rows and columns, data being written to or read from the memory cells corresponding the address signals responsive to the memory control signals; a data path extending between a plurality of external terminals and the memory array for coupling data signals to and from the memory array; a plurality of programmable elements that are each programmed by coupling a programming current through the respective programmable element, the programmable elements being programmed to alter the operation of the memory device; and a programming circuit for selectively either isolating the programmable elements from one of the external terminals or allowing a programming voltage to be coupled from the external terminal to the programmable elements, the programming circuit comprising: an isolation device coupled between the external terminal and the programmable elements, the isolation device having a first terminal coupled to the external terminal, a second terminal coupled to the programmable elements, and control terminal, the isolation device being operable to couple the programming voltage applied to the external terminal to the programmable elements as long as the absolute value of the voltage coupled to the programmable elements is within a predetermined magnitude of a control voltage applied to the control terminal of the isolation device; a charge pump circuit having a power input coupled to the external terminal and an output terminal coupled to the control terminal of the isolation device, the charge pump being coupled to receive the programming voltage applied to the external terminal and being operable in a program mode to increase the absolute value of the programming voltage in response to a program command signal to generate the control voltage, the charge pump circuit being operable in an isolation mode to generate as the control voltage a voltage having an absolute value that is substantially less than the absolute value of the programming voltage; and a precharge circuit coupled to the circuit ground node, the precharge circuit being operable to apply a precharge voltage to the control terminal of the isolation device responsive to the charge pump circuit transitioning to being enabled.

81. The computer system of claim 80 wherein the precharge circuit comprises: a level translator circuit coupled to receive a power supply signal and to couple the power supply voltage to an output terminal in response to the program command signal; and a voltage limiting device coupled between the output terminal of the level translator circuit and the control terminal of the isolation device, the voltage limiting device being operable to couple the output terminal of the level translator circuit to the control terminal of the isolation device only as long a the voltage of the control terminal is below a predetermined voltage.

82. The computer system of claim 81 wherein the level translator circuit comprises: a first NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to receive the program command signal; an inverter having an output and an input coupled to receive the program command signal; a second NMOS isolating transistor having a drain, a source coupled to ground potential, and a gate coupled to the output of the inverter; a first PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the first NMOS isolating transistor, and a gate coupled to the drain of the second NMOS isolating transistor; and a second PMOS transistor having a source coupled to receive the power supply voltage, a drain coupled to the drain of the second NMOS isolating transistor and the gate of the first PMOS transistor, and a gate coupled to the drain of the first NMOS isolating transistor.

83. The computer system of claim 81 wherein the voltage limiting device comprises an NMOS isolating transistor having its source coupled to the output terminal of the level translator circuit, its drain coupled to the control terminal of the isolation device and a gate coupled to receive the power supply voltage.

84. The memory device of claim 80 wherein the programmable elements comprise respective anti-fuses.

85. The memory device of claim 80 wherein the memory array further comprises a plurality of redundant rows of memory cells, and wherein the programmable elements, when programmed, are operable to substitute a redundant row of memory cells for a defective row of memory cells.

86. The memory device of claim 80, further comprising a mode register containing a plurality of the programmable elements, and wherein the programmable elements, when programmed, are operable to control the operating mode of the memory device.

87. A method of supplying a voltage to a gate of a MOSFET transistor to allow the transistor to couple a programming voltage from an external terminal of an integrated circuit to a circuit ground to which a programming element may be coupled, the method comprising: coupling a drain of the MOSFET transistor to the external terminal; and coupling a source of the MOSFET transistor to the circuit ground; boosting the magnitude of the programming voltage to provide a boosted programming voltage; precharging the gate of the MOSFET transistor to a predetermined voltage thereby applying the boosted programming voltage to a gate of the MOSFET transistor.

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Description

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TECHNICAL FIELD

The present invention relates to programming programmable elements such as anti-fuses used in integrated circuits, and more particularly to a method and apparatus for coupling an externally applied, relatively large programming voltage to programmable elements for a sufficient duration to allow sequentially programming a large number of the programmable elements.

BACKGROUND OF THE INVENTION

Programmable elements such as anti-fuses are a common component in conventional integrated circuits. An anti-fuse is a circuit element that is normally open circuited until it is programmed at which point the anti-fuse assumes a relatively low resistance. Anti-fuses are commonly used to selectively enable certain features of integrated circuits and to perform repairs of integrated circuits. Features of integrated circuits are selected by, for example, "blowing" anti-fuses in a mode register to generate signals that alter the operation of the integrated circuit. Repairs of integrated circuits are typically accomplished by blowing anti-fuses to signal defective portions of the integrated circuit that they should be replaced with redundant circuits. For example, a defective row of memory cells in the array of a dynamic random access memory can be replaced with a redundant row of cells provided for that purpose.

Conventional anti-fuses are similar in construction to capacitors in that they include a pair of conductive plates separated from each other by a dielectric or insulator. Anti-fuses are typically characterized by the nature of the dielectric, which may be, for example, oxide or nitride. Anti-fuses are programmed or "blown" by applying a differential voltage between the plates that is sufficient to break down the dielectric thereby causing the plates to contact each other. Typically at least one voltage used to provide this differential voltage is applied to the chip externally through terminals that are normally used for other purposes. For example, in a dynamic random access memory ("DRAM") device, a high voltage may be applied to one of the data bit terminals after the integrated circuit has been placed in a programming mode by, for example, applying a predetermined combination of bits to other terminals of the integrated circuit.

Although conventional anti-fuses as described above have worked well in many applications, their use nevertheless may create several problems, particularly when used in more recent, high-density integrated circuits. In particular, the programmed resistance of anti-fuses varies over a considerable range, and the programmed resistance may be far higher than is desired. For example, the programmed resistance may be high enough that circuitry connected to the anti-fuse mistakenly determines that the anti-fuse is open circuited. It is generally known that programming anti-fuses with a higher current will both lower the programmed resistance and provide a more uniform resistance. However, the magnitude of the programming voltage that can be applied to anti-fuses is severely limited by the presence of other circuitry in the integrated circuit. In particular, since the terminals on which the programming voltage is applied are typically used for other functions, excessive programming voltages can easily break down the gate oxide layers of MOSFET transistors connected to such terminal thereby making such transistors defective.

Excessive programming voltages can also exceed the breakdown voltage of bipolar transistors that are connected to the input terminals of integrated circuits to provide electrostatic discharge ("ESD") protection for the remaining components of the integrated circuit. While this problem can be alleviated to some extent by increasing the breakdown voltage of the bipolar ESD protection transistors, doing so may reduce the safety margin of the ESD protection. While the problem of breaking down gate oxide layers of MOSFET transistors and exceeding the breakdown voltage of bipolar ESD protection transistors could be alleviated to some extent by using dedicated terminals to program anti-fuses, doing so would further increase the already large number of terminals required for many semiconductor devices, such as DRAM devices. Furthermore, the problem would nevertheless remain because it would be difficult to isolate the programming voltage from the integrated circuit substrate. Failure to isolate the programming voltage from the substrate could cause excessive voltages to be coupled across the gate oxide layers of MOSFET transistors, even though the programming voltage was not applied directly to the gates of the transistors.

The problem of programming voltages breaking down the gate oxide layer of MOSFET's is exacerbated by the wide range of operating voltages of typical integrated circuits. For example, recent integrated circuits are capable of operating with a supply voltage of 1.8 volts in order to minimize power consumption, but they must still be able to operate with a commonly used supply voltage of 3.3 volts.

The limited magnitude of programming voltages that can be applied to external terminals make it important to couple substantially all of the programming voltage to the anti-fuses that are to be programmed. However, since at least one voltage used to provide the differential programming voltage is generally applied through an external terminal that is also used for other purposes, an isolation circuit must be provided between the terminal and the anti-fuse. A MOSFET transistor is often used as an isolation circuit. For example, an NMOS isolating transistor can be used to couple a positive programming voltage to one plate of the anti-fuse. However, for the NMOS isolating transistor to pass the entire magnitude of the programming voltage, a positive voltage having a magnitude that is greater than the magnitude of the programming voltage must be applied to the gate of the NMOS isolating transistor. In fact, the voltage applied to the gate of the NMOS isolating transistor must exceed the positive programming voltage by a threshold voltage V.sub.T for the transistor to couple the full magnitude of the programming voltage to the anti-fuse. If a lesser voltage is applied to the gate of the NMOS isolating transistor, the voltage applied to the anti-fuse will be no greater than the voltage applied to the gate less the threshold voltage V.sub.T.

Several techniques have been used to apply a voltage to the gate of an NMOS isolation transistor that is V.sub.T larger than an externally applied programming voltage. One conventional approach is to use a "bootstrap" circuit, such as a capacitor coupled between the gate of the NMOS isolation transistor and a terminal of the transistor that is coupled to the anti-fuse. The capacitor can be either a discrete capacitor external to the isolation transistor or a parasitic capacitance internal to the isolation transistor. The bootstrap capacitor is charged to at least a relatively small positive bias voltage V.sub.B before the isolation transistor is turned ON. When the bootstrap transistor is turned ON, the voltage on the terminal of the transistor that is coupled to the anti-fuse increases, and this increase is coupled to the gate of the transistor through the capacitor. The voltage on the gate of the transistor thus increases to substantially the sum of the programming voltage and the bias voltage V.sub.B, thereby allowing the NMOS isolating transistor to couple the entire magnitude of the programming voltage to the anti-fuse.

A significant limitation on the use of a bootstrap capacitor is the limited duration in which the voltage applied to the gate of the isolation transistor remains above the programming voltage by at least the threshold voltage V.sub.T. More specifically, when the isolation transistor is initially turned ON, the voltage applied to the gate of the isolation transistor will be V.sub.P +V.sub.B, where V.sub.P is the programming voltage and V.sub.B is the bias voltage, which is assumed to be greater than the threshold voltage V.sub.T. However, as the charge on the capacitor leaks away, both internally and through external circuit components, the voltage applied to the gate of the isolation transistor decreases. In fairly short order, the capacitor discharges to the point where the voltage applied to the gate of the transistor is less than V.sub.P +V.sub.T. Thereafter, the isolation transistor can no longer couple the full magnitude of the programming voltage to the anti-fuse. Programming of additional anti-fuses can then require repetitive cycles of turning OFF the isolation transistor, re-charging the bootstrap capacitor, and again turning ON the isolation transistor. The time required to perform these multiple cycles can unduly increase the time required to program anti-fuses used in semiconductor devices.

Another conventional approach is to provide a semiconductor device using anti-fuses with a charge pump that generates a "supervoltage" having a magnitude that is larger than the sum of the programming voltage and the threshold voltage V.sub.T. The supervoltage is applied to the gate of the NMOS isolation transistor to couple the programming voltage to the anti-fuse. Since the supervoltage exceeds the programming voltage by at least the threshold voltage V.sub.T, the entire magnitude of the programming voltage can be applied to the anti-fuse.

The use of a charge pump avoids the problem of being able to couple the programming voltage to the anti-fuse for only a limited duration. However, it has the disadvantage of requiring a relatively large number of components in the charge pump, thereby increasing the cost of semiconductor devices using this approach. In particular, the amount of circuitry that must be used in the charge pump is a function of the number of voltage boosting stages contained in the charge pump. Since a relatively large number of voltage boosting stages are required to generate a supervoltage having a large magnitude, a large number of components must be used in the charge pump to generate a sufficiently large supervoltage.

Although these conventional isolation circuits have been explained in the context of applying a positive programming voltage to an anti-fuse through an NMOS isolating transistor, it will be understood that the same or similar problem may exist when applying a negative programming voltage to an anti-fuse through a PMOS transistor. Also, although the isolation circuits have been described as being coupled to an anti-fuse, it will be understood that the same or similar problem may exist when applying a programming voltage to other types of programmable elements, such as fuses.

There is therefore a need for an isolation circuit that uses relatively few components yet is capable of coupling substantially the entire magnitude of a programming voltage to an anti-fuse or other programmable element for an extended duration.

SUMMARY OF THE INVENTION

A charge pump according to the invention is used to supply a relatively large voltage to the control terminal of an isolation device, such as the gate of a MOSFET transistor, that couples a circuit ground node to an external terminal of an integrated circuit. A relatively large programming voltage is applied to the external terminal to allow one or more programmable element coupled to the circuit ground node to be programmed. At other times, the isolation device isolates the external terminal from the circuit ground node so that the external terminal can be used for other purposes. The charge pump generates the relatively large voltage by boosting the programming voltage so that relatively few boosting stages are required in the charge pump. The charge pump also preferably includes a precharge circuit to quickly apply a voltage to the control terminal of the isolation device when a pro