Title: Receiver capable of receiving radio signals in a preferred state at all times
Abstract: A receiver has an adder for output intermediate-frequency signals of a plurality of receiving blocks, a demodulator for an added intermediate-frequency signal, adjustable reference-signal generator for supplying phase-shifted reference signals to the PLL circuits of the plurality of receiving blocks, and a plurality of switches. The switches are controlled when power is first supplied to the receiver such that the frequency-divided reference signals to the PLL circuits are in phase with one another. The adjustable reference-signal generator, upon tuning on power, is set in the phase-shift adjusted state stored immediately before previously turning off the power.
Patent Number: 6,959,175 Issued on 10/25/2005 to Ohtaki
| Inventors:
|
Ohtaki; Yukio (Fukushima-ken, JP)
|
| Assignee:
|
Alps Electric Co., Ltd. (Tokyo, JP)
|
| Appl. No.:
|
314610 |
| Filed:
|
December 9, 2002 |
Foreign Application Priority Data
| Dec 10, 2001[JP] | 2001-376088 |
| Dec 10, 2001[JP] | 2001-376091 |
| Current U.S. Class: |
455/139; 455/141; 455/260; 455/265 |
| Intern'l Class: |
H04B 001/16 |
| Field of Search: |
455/335,141,137,139,138,136,132,265,258,260
375/327,347
|
References Cited [Referenced By]
U.S. Patent Documents
| 4079318 | Mar., 1978 | Kinoshita.
| |
| 4406017 | Sep., 1983 | Takahashi.
| |
| 5175729 | Dec., 1992 | Borras et al.
| |
| 5748683 | May., 1998 | Smith et al.
| |
| 6148186 | Nov., 2000 | Fujita.
| |
| 6157260 | Dec., 2000 | Tilley et al.
| |
| 6229399 | May., 2001 | Tobise et al.
| |
| 2002/0173284 | Nov., 2002 | Forrester.
| |
| Foreign Patent Documents |
| 2000/-236206 | Aug., 2000 | JP.
| |
Primary Examiner: Urban; Edward F.
Assistant Examiner: Haroon; Adeel
Attorney, Agent or Firm: Brinks Hofer Gilson & Lione
Claims
1. A receiver comprising:
a plurality of receiving blocks, each receiving block having an antenna, a frequency
mixer that frequency-converts a reception signal received at the antenna, a local
oscillator that supplies a local oscillation signal to the frequency mixer, a PLL
circuit that sets an oscillation frequency of the local oscillator, and an intermediate-frequency
circuit that selects an intermediate-frequency signal out of an output frequency-mixed
signal of the frequency mixer;
an adder that adds together output signals of the plurality of receiving blocks;
a reproduction processor that reproduces an output added signal of the adder;
an adjustable reference-signal generator that:
supplies phase-shifted reference signals respectively to the PLL circuits of
the plurality of receiving blocks, and
adjusts a phase shift of the reference signals such that, upon power being first
supplied to the receiver, the reference signals are set to an initial phase-shift
adjusted state that was stored immediately before turning off power to the receiver
previously and, during steady state operation, output signals of the plurality
of receiving blocks have the same phase; and
a plurality of switches connected between the respective PLL circuits and the
adjustable reference-signal generator, switch-on times of the switches controllable
such that the reference signals frequency-divided by the respective PLL circuits
have the same phase upon power being first supplied to the receiver.
2. A receiver according to claim 1, wherein the adjustable reference-signal generator
comprises a reference-signal oscillator common between the plurality of receiving
blocks to generate reference signals and a plurality of phase shifters to individually
phase-shift the reference signals.
3. A receiver according to claim 1, wherein the adjustable reference-signal generator
comprises a plurality of digital synthesizers supplied with phase data to generate
individually phase-shifted reference signals.
4. A receiver according to claim 1, wherein the reproduction processor, upon
power being first supplied to the receiver, controls the switch-on time of the
plurality of switches depending on phase comparison signals supplied from the PLL circuits.
5. A receiver according to claim 1, wherein the reproduction processor is connected
with a memory that stores the initial phase-shift adjusted state, the phase-shift
adjusted state of the adjustable reference-signal generator stored in the memory
being read out when power is supplied to the receiver thereby setting the adjustable
reference-signal generator to a read-out phase-shift adjusted state.
6. A receiver according to claim 5, wherein the reproduction processor, during
steady operation, updates and stores a new phase-shift adjusted state of the adjustable
reference-signal generator to the memory each time a constant time elapses.
7. An OFDM signal receiver comprising:
a plurality of receiving blocks, each receiving block having an antenna, a frequency
mixer that frequency-converts an OFDM signal received at the antenna, a local oscillator
that supplies a local oscillation signal to the frequency mixer, a PLL circuit
that sets an oscillation frequency of the local oscillator, and an intermediate-frequency
circuit that selects an intermediate-frequency signal out of an output frequency-mixed
signal of the frequency mixer;
an adder that adds together an intermediate frequency signal outputted from the
plurality of receiving blocks;
an analog-digital converter that converts an added intermediate-frequency signal
outputted from the adder into a digital signal;
an OFDM demodulator that OFDM-demodulates the digital signal;
a phase-shift amount controller connected to the OFDM demodulator to set an amount
of phase-shift of the adjustable reference-signal generator such that a demodulated
signal of the OFDM demodulator has a power of at least a predetermined value and
power dispersion of the demodulated signal is minimized, wherein the phase-shift
amount controller includes a power detector that detects the power of the demodulated
signal of the OFDM demodulator and a power dispersion detector that detects the
dispersion of the demodulated signal of the OFDM demodulator.
8. An OFDM signal receiver according to claim 7, wherein the adjustable reference-signal
generator comprises a reference-signal oscillator common between the plurality
of receiving blocks to generate reference signals and a plurality of phase shifters
to individually phase-shift the reference signals.
9. An OFDM signal receiver according to claim 7, wherein the adjustable reference-signal
generator comprises a plurality of digital synthesizers supplied with phase data
to generate individually phase-shifted reference signals.
10. An ODFM signal receiver according to claim 7, further comprising, between
the adder and the analog-digital converter, a second frequency mixer that frequency-converts
the added intermediate-frequency signal into a second intermediate-frequency signal,
a second local oscillator that supplies a second local oscillation signal to the
second frequency mixer, and a second intermediate-frequency circuit that selects
a second intermediate-frequency signal out of an output frequency-mixed signal
of the second frequency mixer.
11. A method of maximizing output signal power while minimizing signal dispersion
of a receiver when power is first supplied to the receiver after power to the receiver
has been terminated, the method comprising:
storing an initial phase-shift adjusted state of an adjustable reference-signal
generator immediately before power to the receiver has been terminated;
supplying phase-shifted reference signals to PLL circuits of a plurality of receiving
blocks of the receiver via the adjustable reference-signal generator when power
is supplied to the receiver;
adjusting a phase shift of the reference signals such that when power is first
supplied to the receiver after power to the receiver has been terminated the reference
signals are set to the initial phase-shift adjusted state;
controlling reference signals frequency-divided by the PLL circuits to have the
same phase upon first supplying power to the receiver; and
adjusting a phase shift of the reference signals such that output signals of
the receiving blocks have the same phase during steady state operation.
12. The method of claim 11, further comprising controlling switch-on times of
switches connected between the PLL circuits and the adjustable reference-signal
generator such that the reference signals frequency-divided by the PLL circuits
have the same phase upon power being first supplied to the receiver.
13. The method of claim 12, further comprising controlling the switches by generating
and comparing phase comparison signals from the PLL circuits, determining phases
of the phase comparison signals, taking the phase comparison signal delayed greatest
in phase as a reference phase comparison signal, determining a phase difference
between the phase comparison signals and the reference phase comparison signal,
and grounding each switch for a time that corresponds to the particular phase difference
associated with that switch.
14. The method of claim 11, further comprising:
detecting power of a demodulated signal from the receiver;
determining a phase difference between reference signals outputted from phase
shifters, searching for a first phase difference at which maximum power of the
demodulated signal is obtained, and adjusting an amount of phase-shift of the phase
shifters such that the phase difference is set to the first phase difference;
after the amount of phase-shift has been adjusted, measuring power and signal
dispersion of the demodulated signal at the first phase difference, changing the
phase difference between the reference signals by a preset amount to one of an
increased phase difference and a decreased phase difference and measuring power
of the demodulated signal at each of the increased and decreased phase differences,
and determining whether the power measured at each of the first, increased, and
decreased phase difference is smaller than a power difference of the maximum power
less a predetermined amount;
when the power measured at the first phase difference is not smaller than the
power difference, detecting a signal dispersion value of the demodulated signal
at the first phase difference and each of the increased and decreased phase difference,
if any of the detected signal dispersion values are less than a preset signal dispersion
value setting the preset signal dispersion value to the smaller signal dispersion
value; and
repeating measurements of the power and signal dispersion value at various phase
differences until power is no longer supplied to the receiver.
15. The method of claim 14, further comprising updating and storing the phase-shift
adjusted state of the adjustable reference-signal generator when the receiver reaches
steady state operation.
Description
This application is based on application No. 2001-376088 and 2001-376091 both
filed on Dec. 10, 2001 in Japan, the contents of which are hereby incorporated
by reference.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to receivers and, more particularly, to a receiver
capable of receiving a radio signal whose electric-field intensity constantly varies.
The receiver remains in a preferred state by receiving the same radio signal by
means of a plurality of receiving blocks and synthesizing, in phase, the output
signals of the receiving blocks.
Additionally, the invention relates to OFDM signal receivers and, more
particularly, to an OFDM signal receiver that receives OFDM signals to be used
in terrestrial-wave digital broadcast and which has a suitable diversity receiving
function for use in a vehicular receiver.
2. Description of the Related Art
In receivers that receive radio signals in which the intensity of the signal
varies
at all times, such as in a vehicular receiver, it is general practice to use a
receiver having a plurality of receiving blocks. One type of such a receiver is
a diversity receiver. The receiver of this kind is arranged with a plurality of
receiving blocks that are connected and arranged in a parallel form. Each of the
receiving blocks has an antenna, a high-frequency amplifier to amplify a received
high-frequency signal, a frequency mixer to frequency-mix together a high-frequency
signal and a local oscillation signal, and an intermediate-frequency circuit to
extract an intermediate-frequency signal out of an output frequency-mixed signal
of the frequency mixer. An adder adds together the intermediate-frequency signals
outputted from the receiving blocks, a demodulator demodulates the added intermediate-frequency
signal, a common local oscillator supplies a local oscillation signal to the frequency
mixers, and a plurality of phase shifters connected and arranged between the frequency
mixers and the common local oscillator individually phase-shift the local oscillation
signals to be supplied to the frequency mixers.
FIG. 5 is a block diagram showing an example of an essential-part configuration
of a known receiver having a plurality of receiving blocks, showing an example
the plurality of receiving blocks are three blocks.
As shown in FIG. 5, the receiver has a first receiving block 50, a second
receiving block 51, a third receiving block 52, an adder (ADD) 53,
a demodulator (DET) 54, a demodulated-signal output terminal 55,
a local oscillator 56 and three phase shifters 57, 58, 59.
In this case, the first receiving block 50 has an antenna 60, a high-frequency
amplifier 61, a frequency mixer 62 and an intermediate-frequency
filter (FIL) 63. The second receiving block 51 has an antenna 64,
a high-frequency amplifier 65, a frequency mixer 66 and an intermediate-frequency
filter (FIL) 67. The third receiving block 52 has an antenna 68,
a high-frequency amplifier 69, a frequency mixer 70 and an intermediate-frequency
filter (FIL) 71. Incidentally, the three antennas 60, 64,
68 are arranged in positions comparatively distant from one another.
In the first receiving block 50, the high-frequency amplifier 61
has an input end connected to the antenna 60 and an output end connected
to a first input end of the frequency mixer 62. The frequency mixer 62
has a second input end connected to an output end of the phase shifter 57
and an output end connected to an input end of the intermediate-frequency filter
63. The intermediate-frequency filter 63 has an output end connected
to a first input end of the adder 53. In the second receiving block 51,
the high-frequency amplifier 65 has an input end connected to the antenna
64 and an output end connected to a first input end of the frequency mixer
66. The frequency mixer 66 has a second input end connected to an
output end of the phase shifter 58 and an output end connected to an input
end of the intermediate-frequency filter 67. The intermediate-frequency
filter 67 has an output end connected to a second input end of the adder
53. In the third receiving block 52, the high-frequency amplifier
69 has an input end connected to the antenna 68 and an output end
connected to a first input end of the frequency mixer 70. The frequency
mixer 70 has a second input end connected to an output end of the phase
shifter 59 and an output end connected to an input end of the intermediate-frequency
filter 71. The intermediate-frequency filter 71 has an output end
connected to a third input end of the adder 53.
Meanwhile, the adder 53 has an output end connected to an input
end of the demodulator 54 while the demodulator 54 has an output
end connected to the demodulated-signal output terminal 55. The phase shifters
57, 58, 59 have respective input ends connected to an output
end of the local oscillator 56. Furthermore, the phase shifters 57,
58, 59 have respective control input ends coupled to a control output
end of the demodulator 54.
The receiver having a plurality of receiving blocks thus configured operates
generally as follows.
When the same radio signal is received at the three antennas 60, 64,
68, the reception signals are respectively amplified by the high-frequency
amplifiers 61, 65, 69 and supplied to the frequency mixers
62, 66, 70. The frequency mixers 62, 66, 70
frequency-mix together the reception signal and the local oscillation signal supplied
from the local oscillator 56 through the phase shifter 57, 58,
59, respectively generates frequency-mixed signals. The intermediate-frequency
filter 63, 67, 71 selects an intermediate-frequency signal
out of the frequency-mixed signal outputted by the frequency mixer 62, 66,
70, and supplies a selected intermediate-frequency signal to the adder 53.
The adder 53 adds/combines, in phase, the three supplied intermediate-frequency
signals to form an added intermediate-frequency signal as mentioned later, and
supplies the added intermediate-frequency signal to the demodulator 54.
The demodulator 54 demodulates the added intermediate-frequency signal and
supplies a demodulated signal to a utilization circuit (not shown) through the
demodulated-signal output terminal 55.
At this time, the demodulator 54 individually adjusts the phase-shift amounts
of the phase shifters 57, 58, 59, to thereby change the phase
of the local oscillation signal outputted from the phase shifter 57, 58,
59, thus carrying out adjustment such that the added intermediate-frequency
signal supplied is maximized in signal power, i.e. such that the intermediate-frequency
signals to be added/combined in the adder 53 are in phase with one another.
By carrying out such adjustment, the added intermediate-frequency signal is maximized
in signal power, to enable radio signal reception in a preferred state.
In general, the OFDM (Orthogonal Frequency Division Multiplex) signal receiver
to be mounted on a moving body, such as an automobile, causes fading so that the
intensity of a reception radio wave fluctuates due to movement of the moving body.
As a result, reception of a reception signal in a preferred state at all times
is impossible. Consequently, in order to avoid not receiving reception signals
in a preferred state (as caused by fading above) at all times, the signal receiver
of this kind adopts a diversity receiving function or the like having a plurality
of receiving blocks to enable reception in a preferred state.
FIG. 11 is a block diagram showing an example of a configuration of a known
OFDM signal receiver having a plurality of receiving blocks, showing an example
having two receiving blocks as the plurality of receiving blocks.
As shown in FIG. 11, this OFDM signal receiver has a first receiving block 141,
a second receiving block 142, a first local oscillator 143, a PLL
circuit 144, a reference-signal oscillator 145, a second local oscillator
146, diversity signal adding means 147, an OFDM demodulator 148
and a demodulated-signal output terminal 149. In this case, the first receiving
block 141 has an antenna 150, a high-frequency filter 151,
a low-noise high-frequency amplifier 152, a first frequency mixer 153,
a first intermediate-frequency filter 154, a second frequency mixer 155,
a second intermediate-frequency filter 156 and an analog-digital converter
(A/D) 157. The second receiving block 142 has an antenna 158,
a high-frequency filter 159, a low-noise high-frequency amplifier 160,
a first frequency mixer 161, a first intermediate-frequency filter 162,
a second frequency mixer 163, a second intermediate-frequency filter 164
and an analog-digital converter (A/D) 165. Meanwhile, the diversity signal
adding means 147 has two digital phase shifters 166, 167,
a mutual correlation detector 168 and an adder 169. Incidentally,
the two antennas 150, 158 are arranged in positions comparatively
distant from each other.
In the first receiving block 141, the high-frequency filter 151
has an input end connected to the antenna 150 and an output end connected
to an input end of the low-noise high-frequency amplifier 152. The low-noise
high-frequency amplifier 152 has an output end connected to a first input
end of the first frequency mixer 153. The first frequency mixer 153
has a second input end connected to an output end of the first local oscillator
143 and an output end connected to an input end of the first intermediate-frequency
filter 154. The first intermediate-frequency filter 154 has an output
end connected to a first input end of the second frequency mixer 155. The
second frequency mixer 155 has a second input end connected to an output
end of the second local oscillator 146 and an output end connected to an
input end of the second intermediate-frequency filter 156. The second intermediate-frequency
filter 156 has an output end connected to an input end of the analog-digital
converter 157. The analog-digital converter 157 has an output end
connected to a first input end connected to the diversity signal adding means 147.
Meanwhile, in the second receiving block 142, the high-frequency
filter 159 has an input end connected to the antenna 158 and an output
end connected to an input end of the low-noise high-frequency amplifier 160.
The low-noise high-frequency amplifier 160 has an output end connected to
a first input end of the first frequency mixer 161. The first frequency
mixer 161 has a second input end connected to an output end of the first
local oscillator 143 and an output end connected to an input end of the
first intermediate-frequency filter 162. The first intermediate-frequency
filter 162 has an output end connected to a first input end of the second
frequency mixer 163. The second frequency mixer 163 has a second
input end connected to an output end of the second local oscillator 146
and an output end connected to an input end of the second intermediate-frequency
filter 164. The second intermediate-frequency filter 164 has an output
end connected to an input end of the analog-digital converter 165. The analog-digital
converter 165 has an output end connected to a second input end connected
to the diversity signal adding means 147.
Furthermore, the first local oscillator 143 has a control end
connected to an output end of the PLL circuit 144 and an output end connected
to a first input end of the PLL circuit 144. The PLL circuit 144
has a second input end connected to an output end of the reference-signal oscillator
145. The OFDM demodulator 148 has an input end connected to an output
end of the diversity signal adding means 147 and an output end connected
to the demodulated-signal output terminal 149.
Meanwhile, in the diversity signal adding means 147, the digital
phase shifter 166 has an input end connected to a first input end of the
diversity signal adding means 147 and an output end connected to a first
input end of the adder 169. The digital phase shifter 167 has an
input end connected to a second input end of the diversity signal adding means
147 and an output end connected to a second input end of the adder 169.
The mutual correlation detector 168 has a first input end connected to a
first input end of the diversity signal adding means 147 and a second input
end connected to a second input end of the diversity signal adding means 147,
respectively. A first control end is coupled to a control end of the digital phase
shifter 166 and a second control end to a control end of the digital phase
shifter 167, respectively. The adder 169 has an output end connected
to an output end of the diversity signal adding means 147.
The OFDM signal receiver having the above configuration operates generally as follows.
In the first receiving block 141, in case an OFDM radio signal is received
at the antenna 150, the reception signal, after removed of unwanted frequency
signal components by the high-frequency filter 151, is amplified by the
low-noise high-frequency amplifier 152 and supplied to the first frequency
mixer 153. The first frequency mixer 153 frequency-mixes together
this reception signal and the first local oscillation signal supplied from the
first local oscillator 143 to generate a first frequency-mixed signal. The
first intermediate-frequency filter 154 selects/outputs a first intermediate-frequency
signal out of the first frequency-mixed signal outputted by the first frequency
mixer 153. The second frequency mixer 155 frequency-mixes together
the first intermediate-frequency signal supplied from the first intermediate-frequency
filter 154 and the second local oscillation signal supplied from the second
local oscillator 143 to generate a second frequency-mixed signal. The second
intermediate-frequency filter 156 selects/outputs a second intermediate-frequency
signal out of the second frequency-mixed signal outputted by the second frequency
mixer 155. The analog-digital converter 157 converts the second intermediate-frequency
signal supplied from the second frequency mixer 155 into a digital intermediate-frequency
signal and supplies it to the following diversity signal adding means 147.
Meanwhile, in the second receiving block 142, the same OFDM radio
signal as the signal received by the first receiving block 141 is received
at the antenna 158, to carry out the same signal-receiving operation as
the signal receiving operation of the first receiving block 141. The digital
intermediate-frequency signal outputted from the second receiving block 142
is supplied to the diversity signal adding means 147.
In this case, the first local oscillation signal generated by the first local
oscillator 143 is set at a stabilized oscillation frequency under the control
of the PLL circuit 144 supplied with the first local oscillation signal
and the reference signal outputted from the reference-signal oscillator 145.
Then, in the diversity signal adding means 147, the digital phase shifter
166 phase-shifts the digital intermediate-frequency signal supplied from
the first receiving block 141 in a manner as described later while the digital
phase shifter 167 phase-shifts the digital intermediate-frequency signal
supplied from the second receiving block 142 in a manner as described later.
Also, the mutual correlation detector 168 detects a mutual correlation between
the digital intermediate-frequency signal supplied from the first receiving block
141 and the digital intermediate-frequency signal supplied from the second
receiving block 142, and corrects the respective phase-shift amounts of
the digital phase shifters 166, 167 depending upon a result of the
detection such that the phase of the digital intermediate-frequency signal outputted
from the digital phase shifter 166 and the phase of the digital intermediate-frequency
signal outputted from the digital phase shifter 167 are in the same phase.
By carrying out such phase correction, the digital intermediate-frequency signal
outputted from the digital phase shifter 166 and the digital intermediate-frequency
signal outputted from the digital phase shifter 167 are added, in phase,
by the adder 169 and outputted as an added digital intermediate-frequency signal.
Thereafter, the OFDM demodulator 148 OFDM-demodulates the added
digital intermediate-frequency signal outputted from the diversity signal adding
means 147, to supply a demodulated signal to a utilization circuit (not
shown) through the demodulated-signal output terminal 149.
According to the OFDM signal receiver, the diversity signal adding means
147 equalizes the phases of the two digital intermediate-frequency signals
and adds together these signals to obtain an added digital intermediate-frequency
signal. Consequently, the added digital intermediate-frequency signal is maximized
in signal power. Thus, it is possible to receive an OFDM radio signal in a preferred
reception state.
The known receiver having receiving blocks in plurality, where applied for the
vehicular application, can realize a comparatively preferred reception state. However,
in the case of the application to a system having a multiplicity of channels as
in a cellular phone system or terrestrial-wave television broadcast, the local
oscillation signal is considerably broadened in its frequency variation range in
order for the local oscillator 56 to cope with the multiplicity of channels.
The phase shifters 57, 58, 59 required for obtaining a required
phase-shift amount over such a broad frequency variation range increases the cost
of manufacture for the local oscillator 56 and phase shifters 57,
58, 59.
Meanwhile, in the receiver of this kind, the wiring of from the local
oscillator 56 via the phase shifter 57, 58, 59 to the
frequency mixer 62, 66, 70 is made as short as possible in
the manufacture of the receiver. However, because the local oscillation signal
is high in frequency and moreover a phase shifter 57, 58, 59
is inserted along this wiring route, it is impossible to neglect the signal loss
due to the insertion/connection of the phase shifter 57, 58, 59.
As a result, a large amount of deterioration exists in the carrier wave vs. noise
ratio of demodulated signals (C/N).
As a consequence, a receiver for resolving this problem has already been proposed
by the same applicant as the present applicant.
FIG. 6 is a block diagram showing an example of an essential-part configuration
of a receiver of the proposal, showing an example that the plurality of receiving
blocks are three blocks.
As shown in FIG. 6, the receiver has a first receiving block 72, a second
receiving block 73, a third receiving block 74, an adder (ADD) 75,
a demodulator (DET) 76, a demodulated-signal output terminal 77,
a reference-signal oscillator 78, and three phase shifters 79, 80,
81. In this case, the first receiving block 72 has an antenna 82,
a high-frequency amplifier 83, a frequency mixer 84, a local oscillator
85, a PLL circuit (PLL) 86 and an intermediate-frequency filter (FIL)
87. The second receiving block 73 has an antenna 88, a high-frequency
amplifier 89, a frequency mixer 90, a local oscillator 91,
a PLL circuit (PLL) 92 and an intermediate-frequency filter (FIL) 93.
The third receiving block 74 has an antenna 94, a high-frequency
amplifier 95, a frequency mixer 96, a local oscillator 97,
a PLL circuit (PLL) 98 and an intermediate-frequency filter (FIL) 99.
In the first receiving block 72, the high-frequency amplifier 83
has an input end connected to the antenna 82 and an output end connected
to a first input end of the frequency mixer 84. The frequency mixer 84
has a second input end connected to an output end of the local oscillator 85
and an output end connected to an input end of the intermediate-frequency filter
87. The local oscillator 85 has an input end connected to an output
end of the PLL circuit 86 and an output end connected to an input end of
the PLL circuit 86. The PLL circuit 86 has a control input end connected
to an output end of the phase shifter 79. The intermediate-frequency filter
87 has an output end connected to a first input end of the adder 75.
In the second receiving block 73, the high-frequency amplifier 89
has an input end connected to the antenna 88 and an output end connected
to a first input end of the frequency mixer 90. The frequency mixer 90
has a second input end connected to an output end of the local oscillator 91
and an output end connected to an input end of the intermediate-frequency filter
93. The local oscillator 93 has an input end connected to an output
end of the PLL circuit 92 and an output end connected to an input end of
the PLL circuit 92. The PLL circuit 92 has a control input end connected
to an output end of the phase shifter 80. The intermediate-frequency filter
93 has an output end connected to a second input end of the adder 75.
In the third receiving block 74, the high-frequency amplifier 95
has an input end connected to the antenna 94 and an output end connected
to a first input end of the frequency mixer 96. The frequency mixer 96
has a second input end connected to an output end of the local oscillator 97
and an output end connected to an input end of the intermediate-frequency filter
99. The local oscillator 97 has an input end connected to an output
end of the PLL circuit 98 and an output end connected to an input end of
the PLL circuit 98. The PLL circuit 98 has a control input end connected
to an output end of the phase shifter 81. The intermediate-frequency filter
99 has an output end connected to a third input end of the adder 75.
Meanwhile, the adder 75 has an output end connected to an input
end of the demodulator 76. The demodulator 76 has an output end connected
to the demodulated-signal output terminal 77. The phase shifters 79,
80, 81 have respective input ends connected to an output end of the
reference-signal oscillator 78. The phase shifters 79, 80,
81 have respective control input ends coupled to a control output end of
the demodulator 76.
The receiver of the proposal operates generally as follows.
When the same radio signal is received at the three antennas 82, 88,
89, the reception signals are respectively amplified by the high-frequency
amplifiers 83, 89, 95 and supplied to the frequency mixers
84, 90, 96. The frequency mixers 84, 90, 96
frequency-mix together the reception signal and the local oscillation signal supplied
from the local oscillator 85, 91, 97, to respectively generate
frequency-mixed signals. At this time, the PLL circuit 86, 92, 98
phase-controls the local oscillation signal generated by the local oscillator 85,
91, 97 by a reference signal supplied from the reference-signal oscillator
78 through the phase shifter 79, 80, 81, and sets a
frequency to the local oscillation signal of the local oscillator 85, 91,
97 depending upon the control result thereof. The intermediate-frequency
filter 87, 93, 99 selects an intermediate-frequency signal
out of the frequency-mixed signal outputted by the frequency mixer 84, 90,
96, and supplies a selected intermediate-frequency signal to the adder 75.
The adder 75 adds/combines together, in phase, the supplied three intermediate-frequency
signals to form an added intermediate-frequency signal, and supplies the added
intermediate-frequency signal to the demodulator 76. The demodulator 76
demodulates the added intermediate-frequency signal and supplies a demodulated
signal to the utilization circuit (not shown) via the demodulated-signal output
terminal 77.
At this time also, the demodulator 76 adjusts individually the shift amounts
of the phase shifters 79, 80, 81. This causes change in the
phase of the reference signal outputted from the phase shifter 79, 80,
81 and in the phase of the local oscillation signal outputted from the local
oscillator 85, 91, 97, thereby effecting adjustment such that
the added intermediate-frequency signal to be supplied to the adder 75 is
maximized in signal power, i.e. such that equalizing the phases of the intermediate-frequency
signals to be added/combined in the adder 75. With such adjustment, the
added intermediate-frequency signal is maximized in signal power. Thus, radio signals
can be received in a preferred state. Meanwhile, because the signal to be phase-shifted
by the phase shifter 79, 80, 81 is a reference signal considerably
lower in frequency than the local oscillation signal, the manufacturing cost for
the phase shifters 79, 80, 81 is not significantly increased.
It is possible to neglect the signal loss due to insertion/connection of the phase
shifters 79, 80, 81.
However, various problems still exist in the conventional receivers of this
kind. In the above circuit, because of the provision of PLL circuits 86,
92, 98 respectively in the first to third receiving blocks 72,
73, 74, setting of the oscillation frequency of the local oscillator
85, 91, 97 in the PLL circuit 86, 92, 98
cannot be established immediately after turning on the power. As a consequence,
the local oscillation signal of the local oscillator 85, 91, 97
is not established in phase state and the added intermediate-frequency signal is
not maximized in signal power. In order to maximize the signal power in the added
intermediate-frequency signal, there is a need to optimally adjust the phase amount
of the reference signal on each of the first to third receiving blocks 72,
73, 74. Normal signal reception is not possible in the duration of
such optimal adjustment conducted after turning on the power.
It is therefore an object of the present invention to provide a receiver that
has a plurality of receiving blocks, each of which has a PLL circuit, and is capable
of setting a maximum signal power in an added intermediate-frequency signal immediately
after turning on the power.
The known ODFM signal receiver having a plurality of receiving blocks, when applied
in vehicular applications, can realize a comparatively preferred reception state.
However, this OFDM signal receiver uses the diversity signal adding means 147
for digital signal processing. In configuring the digital phase shifters 166,
167 and mutual correlation detector 168, included is a complex correlator
formed by a multiplicity of multipliers, dividers and logic circuits. Even if configured
by integrated circuits (ICs), the circuitry in the ICs is complicated, extensive,
and results in increased power consumption.
Meanwhile, in the known ODFM signal receiver having a plurality of receiving
blocks, the analog circuit portions in the receiving blocks 141, 142
are configured independently of each other. Consequently, the analog circuit portion
is enormously complicated as well as extensive, making the entire configuration
large-sized and the manufacturing cost high.
An OFDM signal receiver for solving the problems above has been already proposed
by the same applicant as the present applicant.
FIG. 12 is a block diagram showing an example of an essential-part configuration
of the OFDM signal receiver of the proposal, showing an example the plurality of
receiving blocks configure two blocks.
As shown in FIG. 12, the OFDM signal receiver has a first receiving block 170,
a second receiving block 171, an adder 172, a second frequency mixer
173, a second local oscillator 174, a second intermediate-frequency
filter 175, an analog-digital converter (A/D) 176, an OFDM demodulator
(DET) 177, a demodulated-signal output terminal 178, a reference-signal
oscillator 179, phase shifters 180, 181, a power detector
(PW DET) 182, and a phase control section (CONT) 183. In this case,
the first receiving block 170 has an antenna 184, a high-frequency
filter 185, a low-noise high-frequency amplifier 186, a first frequency
mixer 187, a first local oscillator 188, a PLL circuit (PLL) 189
and a first intermediate-frequency filter 190. The second receiving block
171 has an antenna 191, a high-frequency filter 192, a low-noise
high-frequency amplifier 193, a first frequency mixer 194, a first
local oscillator 195, a PLL circuit (PLL) 196 and a first intermediate-frequency
filter 197.
In the first receiving block 170, the high-frequency filter 185
has an input end connected to the antenna 184 and an output end connected
to the low-noise high-frequency amplifier 186. The low-noise high-frequency
amplifier 186 has an output end connected to a first input end of the first
frequency mixer 187. The first frequency mixer 187 has a second input
end connected to an output end of the first local oscillator 188 and an
output end connected to an input end of the first intermediate-frequency filter
190. The first local oscillator 188 has an input end connected to
an output end of the PLL circuit 189 and an output end connected to an input
end of the PLL circuit 189. The PLL circuit 189 has a control input
end connected to an output end of the phase shifter 180. The first intermediate-frequency
filter 190 has an output end connected to a first input end of the adder 172.
In the second receiving block 171, the high-frequency filter 192
has an input end connected to the antenna 191 and an output end connected
to the low-noise high-frequency amplifier 193. The low-noise high-frequency
amplifier 193 has an output end connected to a first input end of the first
frequency mixer 194. The first frequency mixer 194 has a second input
end connected to an output end of the first local oscillator 195 and an
output end connected to an input end of the first intermediate-frequency filter
193. The first local oscillator 195 has an input end connected to
an output end of the PLL circuit 196 and an output end connected to an input
end of the PLL circuit 196. The PLL circuit 196 has a control input
end connected to an output end of the phase shifter 181. The first intermediate-frequency
filter 197 has an output end connected to a second input end of the adder 172.
Meanwhile, the adder 172 has an output end connected to a first
input end of the second frequency mixer 173. The second frequency mixer
173 has a second input end connected to an output end of the second local
oscillator 174 and an output end connected to an input end of the second
intermediate-frequency filter 175. The second intermediate-frequency filter
175 has an output end connected to an input end of the analog-digital converter
176. The analog-digital converter 176 has an output end connected
to an input end of the OFDM demodulator 177 and to an input end of the power
detector 182. The ODFM demodulator 177 has an output end connected
to the demodulated-signal output terminal 178. The power detector 182
has an output end connected to an input end of the phase control section 183.
The phase shifters 180, 181 have respective input ends connected
to an output end of the reference-signal oscillator 179. The phase shifters
180, 181 have respective control input ends coupled to a control
output end of the phase control section 183.
The OFDM signal receiver of the proposal operates generally as follows.
In case the same one of OFDM radio signal is received at the two antennas 184,
191, the reception signal thereof, after removed of unwanted frequency signal
components by the high-frequency filter 185, 192, is amplified by
the low-noise high-frequency amplifier 186, 193 and supplied to the
first frequency mixer 187, 194. The first frequency mixer 187,
194 mixes together the reception signal and the first local oscillation
signal supplied from the first local oscillator 188, 195 to generate
a first frequency-mixed signal. At this time, the PLL circuit 189, 196
phase-controls the first local oscillation signal generated by the first local
oscillator 188, 195 by means of a reference signal supplied from
the reference-signal oscillator 179 through the phase shifter 180,
181, and set a frequency for the first local oscillation frequency signal
of the first local oscillator 188, 195 depending on a control result
of the same. The first intermediate-frequency filter 190, 197 selects/outputs
a first intermediate-frequency signal out of a first frequency-mixed signal outputted
by the first frequency mixer 187, 194 and supplies two selected/outputted
first intermediate-frequency signals to the adder 172.
The adder 172 adds/combines together, in phase, the two intermediate-frequency
signals supplied to form an added first intermediate-frequency signal, and supplies
it to the second frequency mixer 173. The second frequency mixer 173
frequency-mixes together the added first intermediate-frequency signal and the
second local oscillation signal supplied from the second local oscillator 174
to generate a second frequency-mixed signal. The second intermediate-frequency
filter 175 selects/outputs a second intermediate-frequency signal out of
the second frequency-mixed signal outputted by the second frequency mixer 173.
The analog-digital converter 176 converts the second intermediate-frequency
signal supplied from the second intermediate-frequency filter 175 into a
digital intermediate-frequency signal and supplies an obtained digital intermediate-frequency
signal to the demodulator 177 and power detector 182. The demodulator
177 OFDM-demodulates the digital intermediate-frequency signal and supplies
a demodulated signal to a utilization circuit (not shown) through the demodulated-signal
output terminal 178. The power detector 182 detects a power amount
corresponding to the digital intermediate-frequency signal and supplies a detection
result to the phase control section 183. The phase control section 183
individually controls the phase-shift amounts of the phase shifters 180,
181 depending on a detection result from the power detector 182,
individually changes the phase-shift amounts of the reference signals to be supplied
to the PLL circuits 189, 196, and carries out an adjustment to maximize
the power amount to be detected by the power detector 182.
According to the OFDM signal receiver, by controlling the shift amount
of the shifter 180, 181 in a manner noted before, the digital intermediate-frequency
signal to be OFDM-demodulated by the demodulator 177 is maximized in power
amount. It is, accordingly, possible to receive radio signals in a preferred state.
However, while the above receiver is less complex than the conventional
OFDM signal receiver, other problems still exist. For example, when fading occurs
in an arrival radio wave, it is difficult to improve the bit error rate (BER, i.e.
bit error rate) upon extreme level lowering in a particular frequency component
within a reception signal band.
It is therefore another object of the present invention to provide an OFDM signal
receiver in which the power is at least a predetermined value in a digital intermediate-frequency
signal digital-converted from an added intermediate-frequency signal obtained by
adding, in phase, reception signals on a plurality of receiving blocks. It is also
an object of the present invention to provide an improved bit error rate.
SUMMARY OF THE INVENTION
In order to achieve the foregoing objects, one embodiment of the present invention
includes a plurality of receiving blocks. Each receiving block has an antenna,
a frequency mixer that frequency-converts a reception signal received at the antenna,
a local oscillator that supplies a local oscillation signal to the frequency mixer,
a PLL circuit that sets an oscillation frequency of the local oscillator, and an
intermediate-frequency circuit that selects an intermediate-frequency signal out
of an output frequency-mixed signal of the frequency mixer. The embodiment also
contains an adder that adds together output signals of the plurality of receiving
blocks, a reproduction processor that reproduces an output added signal of the
adder, an adjustable reference-signal generator that supplies phase-shifted reference
signals respectively to the PLL circuits of the plurality of receiving blocks,
and a plurality of switches connected between the respective PLL circuits and the
adjustable reference-signal generator.
The switch-on times of the plurality of switches, upon power being supplied to
the receiver, are controlled such that the reference signals frequency-divided
by the respective PLL circuits are in the same phase. The adjustable reference-signal
generator, during steady state operation, adjusts phase shift of the reference
signals respectively for supply to the PLL circuits such that output signals of
the plurality of receiving blocks are in the same phase and, upon power being supplied
to the receiver, the phases are set in an initial phase-shift adjusted state stored
immediately before previously turning off the power to the receiver.
According to this embodiment, a phase-shift adjusted state of the adjustable
reference-signal generator is stored immediately before turning off the power and
remains stored as long as power is not supplied to the receiver. When the power
is first supplied to the receiver, the switch-on time in the plurality of switches
is controlled and set to adjust the phases of the reference signals frequency-divided
in the PLL circuits to the same phase. Because the added intermediate-frequency
signal is maximized in signal power, there is no need to optimally adjust a phase-shift
amount of the reference signal for each of the plurality of receiving blocks. Thus,
normal signal reception is possible in the receiver immediately after turning on
the power.
In this case, the adjustable reference-signal generator may contain a reference-signal
oscillator common between the plurality of receiving blocks to generate reference
signals and a plurality of phase shifters to individually phase-shift the reference
signals. With this configuration, the adjustable reference-signal generator can
be simplified to reduce the signal loss due to the provision of the plurality of
phase shifters.
Also, the adjustable reference-signal generator may contain a plurality of
digital synthesizers to generate reference signals individually phase-shifted by
being supplied with phase data. With this configuration, because the phase and
frequency of the reference signal can be digitally control-processed, control process
can be simplified in addition to simplification in configuration of the adjustable
reference-signal generator.
Furthermore, there production processor may be configured to, upon turning
on of the power to the receiver, carry out control of the switch-on times of the
plurality of switches depending on phase comparison signals supplied from the PLL
circuits. This permits the reproduction processor to supply phase comparison signals
obtained by the PLL circuit. By comparing phase states of supplied phase comparison
signals, switch-on time is determined for the plurality of switches. Accordingly,
required switch-on time for each switch can be controlled without complicating
the configuration of the control system.
Also, the reproduction processor may be connected with a memory that stores
the initial phase-shift adjusted state of the adjustable reference-signal generator.
The initial phase-shift adjusted state stored in the memory may then be read out
when turning on the power, thereby setting the adjustable reference-signal generator
to a read-out phase-shift adjusted state.
With this configuration, the reproduction processor stores the initial phase-shift
adjusted state of the adjustable reference-signal generator to the memory immediately
before turning off the power. When the power is turned on, the phase-shift adjusted
state of the adjustable reference signal generator stored in the memory is used,
facilitating setting of the adjustable reference-signal generator to the initial
phase-shift state and correctly reproducing a phase-shift adjusted state of the
adjustable reference-signal generator immediately before turning off the power.
In this case, the reproduction processor is preferably configured to, during
steady
state operation, update and store the phase-shift adjusted state of the adjustable
reference-signal generator to the memory at constant time intervals. With this
configuration, because the memory is updated in storage content at a constant time
interval, it is possible to use a memory having a small storage capacity.
Also, in order to achieve the foregoing object, a second embodiment of the
present invention comprises a plurality of receiving blocks. Each receiving block
has an antenna, a frequency mixer that frequency-convertes an OFDM signal received
at the antenna, a local oscillator that supplies a local oscillation signal to
the frequency mixer, a PLL circuit that sets an oscillation frequency to the local
oscillator, and an intermediate-frequency circuit that selects an intermediate-frequency
signal out of an output frequency-mixed signal of the frequency mixer. The embodiment
further includes an adder that adds together the intermediate frequency signal
outputted from the plurality of receiving blocks, an analog-digital converter that
converts an added intermediate-frequency signal outputted from the adder into a
digital signal, an OFDM demodulator that OFDM-demodulates the digital signal, an
adjustable reference-signal generator that supplies phase-shifted reference signals
respectively to the PLL circuits of the plurality of receiving blocks, and a phase-shift
amount controller connected to the OFDM demodulator to set an amount of phase-shift
of the adjustable reference-signal generator such that a demodulated signal of
the OFDM demodulator has a power of at least a predetermined value and power dispersion
in the demodulated signal is minimized.
According to the above embodiment, in order to supply phase-shifted reference
signals respectively to the PLL circuits of the plurality of receiving blocks,
the phase-shift amount controller connected to the OFDM demodulator is used to
adjust the phase-shift amount of the adjustable reference-signal generator. By
carrying out the adjustment, the demodulated signal of the OFDM demodulator is
increased in power to a predetermined value or higher and the signal dispersion
of the demodulated signal is minimized. Accordingly, preferred signal reception
is possible similar to the conventional OFDM signal receiver of this kind. Furthermore,
signal reception with minimal bit error rate is possible.
In this case, the adjustable reference-signal generator may comprise a reference-signal
oscillator common between the plurality of receiving blocks to generate reference
signals and a plurality of phase shifters to individually phase-shift the reference
signals. With this configuration, the adjustable reference-signal generator can
be simplified in configuration and the signal loss due to the provision of a plurality
of phase shifters can be reduced.
Also, the adjustable reference-signal generator may comprise a plurality of
digital synthesizers to generate reference signals individually phase-shifted by
being supplied with phase data. With this configuration, because the phase and
frequency of the reference signal can be digitally control-processed, control process
can be simplified in addition to simplification in configuration of the adjustable
reference-signal generator.
Furthermore, the phase-shift amount controller may include a power detector
for a demodulated signal of the OFDM demodulator and a power dispersion detector
for a demodulated signal of the OFDM demodulator. With this configuration, power
detection and dispersion detection from a demodulated signal can be individually
made without interference between the both detections.
Also, the embodiment may further comprise, between the adder and the analog-digital
converter, a second frequency mixer that frequency-converts the added intermediate-frequency
signal into a second intermediate-frequency signal, a second local oscillator that
supplies a second local oscillation signal to the second frequency mixer, and a
second intermediate-frequency circuit that selects a second intermediate-frequency
signal out of an output frequency-mixed signal of the second frequency mixer.
With this configuration, the receiver is configured in a double super heterodyne
structure. Accordingly, the first and second local oscillation signals can be selected
with respective frequency bands comparatively freely.
In another embodiment, a method of maximizing output signal power while minimizing
signal dispersion of a receiver when power is first supplied to the receiver after
power to the receiver has been terminated comprises storing an initial phase-shift
adjusted state of an adjustable reference-signal generator immediately before power
to the receiver has been terminated, supplying phase-shifted reference signals
to PLL circuits of a plurality of receiving blocks of the receiver via the adjustable
reference-signal generator when power is supplied to the receiver, adjusting a
phase shift of the reference signals such that when power is first supplied to
the receiver after power to the receiver has been terminated the reference signals
are set to the initial phase-shift adjusted state, controlling reference signals
frequency-divided by the PLL circuits to have the same phase upon first supplying
power to the receiver and adjusting a phase shift of the reference signals such
that output signals of the receiving blocks have the same phase during steady state operation.
The method may further comprise controlling switch-on times of switches connected
between the PLL circuits and the adjustable reference-signal generator such that
the reference signals frequency-divided by the PLL circuits have the same phase
upon first supplying power to the receiver.
The switches may be controlled by generating and comparing phase comparison signals
from the PLL circuits, determining phases of the phase comparison signals, taking
the phase comparison signal delayed greatest in phase as a reference phase comparison
signal, determining a phase difference between the phase comparison signals and
the reference phase comparison signal, and grounding each switch for a time that
corresponds to the particular phase difference associated with that switch.
The method may further comprise detecting power of a demodulated signal from
the receiver, determining a phase difference between reference signals outputted
from phase shifters, searching for a first phase difference at which maximum power
of the demodulated signal is obtained, and adjusting an amount of phase-shift of
the phase shifters such that the phase difference is set to the first phase difference,
after the amount of phase-shift has been adjusted, measuring power and signal dispersion
of the demodulated signal at the first phase difference, changing the phase difference
between the reference signals by a preset amount to one of an increased phase difference
and a decreased phase difference and measuring power of the demodulated signal
at each of the increased and decreased phase differences, and determining whether
the power measured at each of the first, increased, and decreased phase difference
is smaller than a power difference of the maximum power less a predetermined amount,
when the power me
