Title: Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
Abstract: An arithmetic device able to optimize the logic level, able to prevent an increase in the component data, able to prevent the area efficiency as an integrated operation efficiency, and circuit, achieving an improvement in the achieving a reduction power consumption, provided with a first selection device for selecting coefficient inputs C0I to CkI in accordance with a control signal ASEL, a second selection device for selecting data inputs D0I to DmI in accordance with a control signal BSEL, a third selection device for selecting cascade inputs P0 to Pn-2 in accordance with a control signal CSEL, an ALU for receiving as input the output signal of the first to third selection devices and performing a logic operation in accordance with instructions of the control signals ALUMD etc., a MAC for receiving as input the output signals of the first to third selection devices and performing operation in accordance with instructions of
Patent Number: 7,020,673 Issued on 03/28/2006 to Ozawa
| Inventors:
|
Ozawa; Kunihiko (Tokyo, JP)
|
| Assignee:
|
Sony Corporation (JP)
|
| Appl. No.:
|
050849 |
| Filed:
|
January 18, 2002 |
Foreign Application Priority Data
| Jan 19, 2001[JP] | P2001-012524 |
| Jan 19, 2001[JP] | P2001-012535 |
| Current U.S. Class: |
708/490; 708/230 |
| Current Intern'l Class: |
G06F 7/38 (20060101) |
| Field of Search: |
708/230,231,490,523,524
|
References Cited [Referenced By]
U.S. Patent Documents
| 5241492 | Aug., 1993 | Girardeau, Jr.
| |
| 5361373 | Nov., 1994 | Gilson.
| |
| 6247036 | Jun., 2001 | Landers et al.
| |
| 6266760 | Jul., 2001 | DeHon et al.
| |
| 6754805 | Jun., 2004 | Juan.
| |
| Foreign Patent Documents |
| 7-503804 | Apr., 1995 | JP.
| |
| 10-307787 | Nov., 1998 | JP.
| |
| WO 94/1412/3 | Jun., 1994 | WO.
| |
Primary Examiner: Ngo; Chuong D
Attorney, Agent or Firm: Rader, Fishman & Grauer PLLC, Kananen; Ronald P.
Claims
What is claimed is:
1. An arithmetic device that reconfigures an operation path by outside control, comprising:
first selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
second selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
arithmetic means receiving as input the output signal of the first selecting
means and the output signal of the second selecting means and performing operations
in accordance with instructions of a control signal; and
delay means for outputting the input data delayed by an amount of delay according
to a value of a control signal.
2. An arithmetic device as set forth in claim 1, wherein the arithmetic means
performs dyadic operation.
3. An arithmetic device as set forth in claim 2, wherein the arithmetic means
performs monadic operation on the result of the dyadic operation.
4. An arithmetic device that reconfigures an operation path by outside control, comprising:
first selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
second selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
third selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
arithmetic means receiving as input the output signal of the first selecting
means, the output signal of the second selecting means, and the output signal of
the third selecting means and performing operation in accordance with instructions
of a control signal; and
delay means for outputting the input data delayed by an amount of delay according
to a value of a control signal.
5. An arithmetic device as set forth in claim 4, wherein the arithmetic means
performs trinomial operation.
6. An arithmetic device as set forth in claim 5, wherein the arithmetic means
performs monadic operation on the result of the trinomial operation.
7. An arithmetic device that reconfigures an operation path by outside control, comprising:
first selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
second selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
third selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
first arithmetic means receiving as input the output signal of the first selecting
means and the output signal of the second selecting means and performing operation
in accordance with instructions of a control signal;
second arithmetic means receiving as input the output signal of the first selecting
means and the output signal of the second selecting means and third selecting means
and performing operation in accordance with instructions of a control signal; and
delay means for outputting the input data delayed by an amount of delay according
to a value of a control signal.
8. An arithmetic device as set forth in claim 7, further comprising a fourth
selecting means for selecting one of the output signal of the first arithmetic
means and the output signal of the second arithmetic means in accordance with a
control signal.
9. An arithmetic device as set forth in claim 7, wherein the first arithmetic
means performs dyadic operation, while the second arithmetic means performs trinomial operation.
10. An arithmetic device as set forth in claim 9, wherein the first arithmetic
means performs monadic operation on the result of the dyadic operation, while the
second arithmetic means performs monadic operation on the result of the trinomial operation.
11. An arithmetic device able to reconfigure operation path by outside control, comprising:
a first selecting means for selecting from a first data group in accordance with
a control signal,
a second selecting means for selecting one from a second data group in accordance
with a control signal,
a first arithmetic means for receiving as input the output signal of the first
selecting means and the output signal of the second selecting means and performing
operation in accordance with instructions of a control signal,
a second arithmetic means for receiving as input the output signal of the first
selecting means and the output signal of the second selecting means and performing
operation in accordance with instructions of a control signal,
a third selecting means for selecting one of the output signal of the first arithmetic
means and the output signal of the second arithmetic means; and
delay means for outputting the input data delayed by an amount of delay according
to a value of a control signal.
12. An arithmetic device able to reconfigure an operation path by outside control, comprising:
a first selecting means for selecting one data from a first data group in accordance
with a control signal,
a second selecting means for selecting one data from a second data group in accordance
with a control signal,
a third selecting means for selecting one data of a third data group in accordance
with a control signal,
a first arithmetic means for receiving as input at least two signals among the
output signal of the first selecting means, the output signal of the second selecting
means, and the output signal of the third selecting means and performing operation
in accordance with instructions of a control signal,
a second arithmetic means for receiving as input at least two signals among the
output signal of the first selecting means, the output signal of the second selecting
means, and the output signal of the third selecting means and performing operation
in accordance with instructions of a control signal,
a fourth selecting means for selecting one of the output signal of the first
arithmetic means and the output signal of the second arithmetic means; and
delay means for outputting the input data delayed by an amount of delay according
to a value of a control signal.
13. A parallel arithmetic device having a plurality of arithmetic devices, each comprising:
first selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
second selecting means for selecting desired data from a plurality of input data
in accordance with a control signal;
arithmetic means for receiving as an input the output signal of the first selecting
means and the output signal of the second selecting means in accordance with a
control signal;
configuration means for reconfiguring an operation path by outside control;
connection means for connecting the inputs and outputs of data of the plurality
of arithmetic devices in cascade;
supply means for supplying the operation result signal of an arithmetic device
as one of a plurality of data inputs of another device; and
delay means for delaying the input data by an amount of delay in accordance with
a value of a control signal and outputting it to the arithmetic device of the next stage.
14. A parallel arithmetic device having a plurality of arithmetic devices, each comprising:
a first selecting means for selecting desired data from a plurality of input
data in accordance with a control signal;
a second selecting means for selecting desired data from a plurality of input
data in accordance with a control signal;
a third selecting means for selecting desired data from a plurality of input
data in accordance with a control signal;
an arithmetic means for receiving as input the output signal of the first selecting
means, the output signal of the second selecting means, and the output signal of
the third selecting means, and performing an operation in accordance with instructions
of a control signal;
configuration means for reconfiguring an operation path under outside control;
connection means for connecting in cascade the inputs and outputs of data of
the plurality of arithmetic devices;
supply means for supplying the operation result signal of an arithmetic device
as one data of the plurality of data inputs of another device; and
a delay means for delaying the input data by an amount of delay in accordance
with a vlaue of a control signal and outputting it to the arithmetic device of
the next stage.
15. A parallel arithmetic device having a plurality of arithmetic devices, each comprising:
a first selecting means for selecting desired data from a plurality of input-data
in accordance with a control signal;
a second selecting means for selecting desired data from a plurality of input
data in accordance with a control signal;
a third selecting means for selecting desired data from a plurality of input
data in accordance with a control signal;
a first arithmetic means for receiving as input the output signal of the first
selecting means and the output signal of the second selecting means and performing
operation in accordance with instructions of a control signal;
a second arithmetic means for receiving as an input the output signal of the
first selecting means, the output signal of the second selecting means, and the
output signal of the third selecting means and performing operation in accordance
with instructions of a control signal;
a fourth selecting means for selecting one of the output of the first arithmetic
means and the output of the second arithmetic means in accordance with a control
signal and outputting the same as an operation result signal;
configuration means for reconfiguring an operation path under outside control;
connection means for connecting in cascade the inputs and outputs of data of
the plurality of arithmetic devices, and
supply means for supplying the operation result signal of one of the plurality
of arithmetic devices as one of the plurality of data inputs of another device; and
a delay means for delaying the input data by an amount of delay in accordance
with a value of a control signal and outputting it to the arithmetic device of
the next stage.
16. A parallel arithmetic device having a plurality of arithmetic devices, each comprising:
a first selecting means for selecting one data from a first data group in accordance
with a control signal;
a second selecting means for selecting one data from a second data group in accordance
with a control signal;
a first arithmetic means receiving as an input the output signal of the first
selecting means and the output signal of the second selecting means and perfonning
operation in accordance with instructions of a control signal;
a second arithmetic means receiving as an input the output signal of the first
selecting means and the output signal of the second selecting means and performing
operation in accordance with instructions of a control signal;
a third selecting means for selecting an output of the first arithmetic means
and an output of the second arithmetic means in accordance with a control signal
and outputting the same as an operation result signal;
configuration means for reconfiguring an operation path under outside control;
connection means for connecting in cascade the inputs and outputs of data of
the first data group of the plurality of arithmetic devices;
supply means for supplying the operation result signal of an arithmetic device
as data of a second data group of another device; and
a delay means for delaying the first data group by an amount of delay in accordance
with a value of a control signal and outputting it to the arithmetic device of
the next stage.
17. A parallel arithmetic device having a plurality of arithmetic devices, each comprising:
a first selecting means for selecting one data from a first data group in accordance
with a control signal;
a second selecting means for selecting one data from a second data group in accordance
with a control signal;
a third selecting means for selecting one from a third data group in accordance
with a control signal;
a first arithmetic means receiving as input at least two signals of the output
signal of the first selecting means, the output signal of the second selecting
means, and the output signal of the third selecting means and performing operation
in accordance with instructions of a control signal;
a second arithmetic means receiving as input at least two signals of the output
signal of the first selecting means, the output signal of the second selecting
means, and the output signal of the third selecting means and performing operation
in accordance with instructions of a control signal;
a fourth selecting means for selecting one of the output of the first arithmetic
means and the output of the second arithmetic means in accordance with a control signal;
configuration means for reconfiguring an operation path under outside control;
connection means for connecting in cascade the inputs and outputs of data of
the first data group and the second data group of the plurality of arithmetic devices;
supply means for supplying the operation result signal of an arithmetic device
as one data of a third data group of another device;
a first delay means for outputting the first data group to the arithmetic device
of the next stage delayed by an amount of delay in accordance with a value of a
control signal; and
a second delay means for outputting the second data group to the arithmetic device
of the next stage delayed by exactly an amount of delay in accordance with a value
of a control signal.
18. An arithmetic device reconfigurable by outside control, comprising:
at least one computing unit having a plurality of inputs and a plurality of outputs,
performing a plurality of operations based on data supplied to the plurality of
inputs in accordance with a control signal and outputting the operation results;
a plurality of input selection devices for selecting one data from the plurality
of input data in accordance with a control signal and supplying the same to different
inputs of the computing unit; and
a delay unit that delays and outputs the plurality of outputs of the at least
one computing unit based on a value of a control signal.
19. An arithmetic device as set forth in claim 18, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to one
input of the input selection device.
20. An arithmetic device reconfigurable by outside control, comprising:
at least one multiple input, multiple output computing unit each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on data supplied to the plurality of inputs in accordance with a control signal,
and outputting the operation results from the plurality of outputs;
a plurality of output selection devices for selecting and outputting one data
from the plurality of input data and the output data of the computing unit in accordance
with a control signal; and
a delay unit that delays and outputs the plurality of outputs of the at least
one multiple input, multiple output computing unit based on a value of a control signal.
21. An arithmetic device as set forth in claim 20, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to the
output selection device.
22. An arithmetic device reconfigurable by outside control, comprising:
at least one computing unit having a plurality of inputs and a plurality of outputs,
performing a plurality of operations based an data supplied to the plurality of
inputs in accordance with a control signal, and outputting the operation results
from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the computing unit,
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and the output data of the computing unit in accordance
with a control signal; and
a delay unit that delays and outputs the plurality of outputs of the at least
one computing unit based on a value of a control signal.
23. An arithmetic device as set forth in claim 22, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data among the plurality of input data and supplying operation results to one input
of the input selection devices and the output selection device.
24. An arithmetic device reconfigurable by outside control, comprising:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying the same to different
inputs of the first computing units,
at least one second computing unit having a plurality of inputs and a plurality
of outputs, supplied at the plurality of inputs with output data of the plurality
of first computing units, performing a plurality of operations based on the plurality
of data supplied in accordance with a control signal, and outputting the operation
results from the plurality of outputs,
a delay unit that sets a delay between the first and second computing units based
on a value of a control signal.
25. An arithmetic device as set forth in claim 24, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to one
input of the input selection device.
26. An arithmetic device reconfigurable by outside control, comprising:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
at least one second computing unit having a plurality of inputs and a plurality
of outputs, supplied at the plurality of inputs with output data of the plurality
of first computing units, performing a plurality of operations based on the plurality
of data supplied in accordance with a control signal, and outputting the operation
results from the plurality of outputs; and
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and the output data of at least one of the first
and second computing units;
a delay unit that sets a delay between the first and second computing units based
on a value of a control signal.
27. An arithmetic device as set forth in claim 26, wherein the plurality of output
selection devices include:
a plurality of first output selection devices for selecting and outputting one
data from a plurality of input data and output data of the first computing unit
in accordance with a control signal and
a plurality of second output selection devices selecting and outputting one data
from a plurality of input data, the output data of the first computing unit, and
the output data of the second computing unit in accordance with a control signal.
28. An arithmetic device as set forth in claim 27, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to the
first output selection device.
29. An arithmetic device as set forth in claim 26, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to the
output selection device.
30. An arithmetic device reconfigurable by outside control, compnsing:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of input selection devices for selecting one data from the plurality
of input data in accordance with a control signal and supplying the same to different
inputs of the first computing units,
at least one second computing unit each having a plurality of inputs and a plurality
of outputs, supplied at the plurality of inputs with the output data of the plurality
of first computing units, performing a plurality of operations based on the plurality
of data supplied in accordance with a control signal, and outputting the operation
results from the plurality of outputs; and
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and at least one output data among the first and
second computing units in accordance with a control signal; and
a delay unit that sets a delay between the first and second computing units based
on a value of a control signal.
31. An arithmetic device as set forth in claim 30, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to one
input of the input selection device.
32. An arithmetic device as set forth in claim 30, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to the
output selection device.
33. An arithmetic device as set forth in claim 30, wherein the plurality of output
selection devices include
a plurality of first output selection devices each selecting and outputting one
data from a plurality of input data and the output data of the first computing
unit in accordance with a control signal and
a plurality of second output selection devices each selecting and outputting
one data from the plurality of input data, the output data of the first computing
unit, and the output data of the second computing unit in accordance with a control signal.
34. An arithmetic device as set forth in claim 33, further comprising at least
one monadic arithmetic means for performing monadic operation on predetermined
data in the plurality of input data and supplying the operation results to the
first output selection device.
35. An arithmetic device reconfigurable by outside control, comprising:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of first input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying the same to different
inputs of the first computing units,
at least one second computing unit each having a plurality of inputs and a plurality
of outputs, performing a plurality of operations based on a plurality of data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs; and
a plurality of second input selection devices each selecting one data from the
plurality of input data and the output data of the second computing units in accordance
with a control signal and supplying it to different inputs of the second computing
unit; and
a delay unit that sets a delay between the first and second computing units based
on a value of a control signal.
36. An arithmetic device reconfigurable by outside control, comprising:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of first input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the first computing units,
at least one second computing unit having a plurality of inputs and a plurality
of outputs,
performing a plurality of operations based on a plurality of data supplied to
the plurality of inputs in accordance with a control signal, and outputting the
operation results from the plurality of outputs,
a plurality of second input selection devices for selecting one data from the
plurality of input data and the output data of the second computing unit in accordance
with a control signal and supplying it to different inputs of the second computing unit;
a plurality of output selection devices each selecting and outputting one data
from a plurality of input data and at least one output data of the second computing
unit in accordance with a control signal; and
a delay unit that sets a delay between the first and second computing units based
on a vlaue of a control signal.
37. An arithmetic device reconfigurable by outside control, comprising:
a plurality of computing units, arranged in multiple stages, each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on data supplied to the plurality of inputs in accordance with a control signal,
and outputting the operation results from the plurality of outputs;
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the plurality of computing units of the first stage; and
a delay unit that delays and outputs the plurality of outputs to a next stage
based on a value of a control signal,
the computing units arranged in stages other than the computing units of the
first stage each being supplied at the plurality of inputs with output data of
the plurality of computing units of the previous stage, performing a plurality
of operations based on the plurality of data supplied in accordance with a control
signal, and outputting the operation results from the plurality of outputs.
38. An arithmetic device reconfigurable by outside control, comprising:
a plurality of computing units, arranged in multiple stages, each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on data supplied to the plurality of inputs in accordance with a control signal,
and outputting the operation results from the plurality of outputs;
a plurality of output selection devices each selecting and outputting one data
from a plurality of input data and at least one output data of the computing units
of the each stage in accordance with a control signal; and
a delay unit that delays and outputs the plurality of outputs to a next stage
based on a value of a control signal,
the computing units arranged in the stages other than the computing units of
the first stage each being supplied at the plurality of inputs with output data
of the plurality of computing units of the previous stage, performing a plurality
of operations based on the plurality of data supplied in accordance with a control
signal, and outputting the operation results from the plurality of outputs.
39. An arithmetic device as set forth in claim 38, wherein the plurality of output
selection devices include
a plurality of first output selection devices each selecting and outputting one
data from a plurality of input data and the output data of the computing unit of
the first stage in accordance with a control signal and
a plurality of second output selection devices each selecting and outputting
one data from the plurality of input data and the output data of the computing
units of the different stages in accordance with a control signal.
40. An arithmetic device reconfigurable by outside control, comprising:
a plurality of computing units, arranged in multiple stages, each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on the data supplied to the plurality of inputs in accordance with a control signal,
and outputting the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the plurality of computing units of the first stage;
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and at least one output data among the computing
units of stages in accordance with a control signal; and
a delay unit that delays and outputs the plurality of outputs to a next stage
based on a value of a control signal,
the computing units arranged in the stages other than the computing units of
the first stage each being supplied at the plurality of inputs with the output
data of the plurality of computing units of the previous stage, performing a plurality
of operations based on the plurality of data supplied in accordance with a control
signal, and outputting the operation results from the plurality of outputs.
41. An arithmetic device as set forth in claim 40, wherein the plurality of output
selection devices include
a plurality of first output selection devices each selecting and outputting one
data from a plurality of input data and the output data of the computing unit of
the first stage in accordance with a control signal and
a plurality of second output selection devices each selecting and outputting
one data from the plurality of input data and the output data of the computing
units of the different stages in accordance with a control signal.
42. A parallel arithmetic device comprising:
a first arithmetic device reconfigurable by outside control having at least two
selecting means each selecting desired data from a plurality of input data in accordance
with a control signal and at least one arithmetic device including at least one
arithmetic means for receiving output signals of the selecting means and performing
operation in accordance with instructions of a control signal;
a second arithmetic device reconfigurable by outside control including at least
one computing unit having a plurality of inputs and a plurality of outputs, performing
a plurality of operations based on data supplied to the plurality of inputs in
accordance with a control signal, and outputting the operation results from the
plurality of outputs; and
delay means for setting any delay between the arithmetic devices according to
a value of a control signal,
the operation results of at least one of the first arithmetic device and second
arithmetic device being supplied as input data of the other arithmetic device.
43. A parallel arithmetic device as set forth in claim 42, wherein the first
arithmetic device includes:
a first selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a second selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a third selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a first arithmetic means receiving as input the output signal of the first selecting
means and the output signal of the second selecting means and performing operation
in accordance with instructions of a control signal, and
a second arithmetic means receiving as input the output signal of the first selecting
means and the output signals of the second selecting means a third selecting means
and performing operation in accordance with instructions of a control signal.
44. A parallel arithmetic device as set forth in claim 43, wherein the first
arithmetic device further comprises a fourth selecting means for selecting one
of the output signal of the first arithmetic means and the output signal of the
second arithmetic means in accordance with a control signal.
45. A parallel arithmetic device as set forth in claim 42, wherein the first
arithmetic device includes a plurality of arithmetic devices and connects the inputs
and outputs of data of the plurality of arithmetic devices in cascade and supplies
the operation result signal of an arithmetic device as one data of a plurality
of data inputs of another device.
46. A parallel arithmetic device as set forth in claim 42, wherein the second
arithmetic device comprises:
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the computing unit and
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and the output data of the computing unit in accordance
with a control signal.
47. A parallel arithmetic device as set forth in claim 42, wherein the second
arithmetic device includes:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of Input data in accordance with a control signal and supplying it to different
inputs of the find computing unit, and
at least one second computing unit having a plurality of inputs and a plurality
of outputs, supplied at the plurality of inputs with output data of the plurality
of first computing units, performing a plurality of operations based on the supplied
plurality of data in accordance with a control signal, and outputting the operation
results from the plurality of outputs,
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and at least one output data of the first and
second computing units in accordance with a control signal.
48. A parallel arithmetic device as set forth in claim 42, wherein the second
arithmetic device includes:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of first input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the first computing unit, and
at least one second computing unit having a plurality of inputs and a plurality
of outputs, performing a plurality of operations based on the plurality of data
supplied to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of second input selection devices each selecting one data from the
plurality of input data and the output data of the second computing units and supplying
it to different inputs of the second computing units, and
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and at least one output data of the second computing
units in accordance with a control signal.
49. A parallel arithmetic device as set forth in claim 42, wherein the second
arithmetic device includes:
a plurality of computing units, arranged in multiple stages, each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on the data supplied to the plurality of inputs in accordance with a control signal,
and outputting the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the plurality of computing units of the first stage, and
a plurality of output selection devices each selecting and outputting one data
from the plurality of input data and at least one output data among the computing
units of stages in accordance with a control signal, the computing units arranged
in the stages other than the computing units of the first stage each being supplied
at the plurality of inputs with the out put data of the plurality of computing
units of the previous stage, performing a plurality of operations based on the
plurality of data supplied in accordance with a control signal, and outputting
the operation results from the plurality of outputs.
50. A parallel arithmetic device comprising:
a plurality of first arithmetic devices reconfigurable by outside control each
having at least two selecting means each selecting desired data from plurality
of input data in accordance with a control signal and at least one arithmetic device
including at least one arithmetic means for receiving output signals of the selecting
means and performing operation in accordance with instructions of a control signal;
a plurality of second arithmetic devices reconfigurable by outside control each
including at least one computing unit each having a plurality of inputs and a plurality
of outputs, performing a plurality of operations based on data supplied to the
plurality of inputs in accordance with a control signal, and outputting the operation
results from the plurality of, outputs, the operation results of the plurality
of first arithmetic devices being supplied to the corresponding second arithmetic
devices and the operation results of the second arithmetic devices being supplied
to the corresponding first arithmetic devices; and
a delay means for setting any delay between arithmetic devices according to a
value of a control signal.
51. A parallel arithmetic device as set forth in claim 50, wherein the first
arithmetic device includes:
a first selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a second selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a third selecting means for selecting desired data from a plurality of input
data in accordance with a control signal,
a first arithmetic means for receiving as input the output signal of the first
selecting means and the output signal of the second selecting means and performing
operation in accordance with instructions of a control signal, and
a second arithmetic means for receiving as input the output signal of the first
selecting means and the output signals of the second selecting means and third
selecting means and performing operation in accordance with instructions of a control signal.
52. A parallel arithmetic device as set forth in claim 51, wherein the first
arithmetic device further comprises a fourth selecting means for selecting one
of the first arithmetic means and the output signal of the second arithmetic means
in accordance with a control signal.
53. A parallel arithmetic device as set forth in claim 50, wherein the first
arithmetic device includes a plurality of arithmetic devices, connects in cascade
the inputs and outputs of data of the plurality of arithmetic devices, and supplies
the operation result signal of each arithmetic device as one data of the plurality
of data inputs of another device.
54. A parallel arithmetic device as set forth in claim 50, wherein the second
arithmetic device comprises:
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the computing unit and
a plurality of output selection devices a selecting and outputting one data from
the plurality of input data and the output data of the computing unit of accordance
with a control signal.
55. A parallel arithmetic device as set forth in claim 50, wherein the second
arithmetic device includes:
a plurality of first computing units each having a plurality of inputs and a
plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the first computing units,
at least one second computing unit each having a plurality of inputs and a plurality
of outputs, supplied at the plurality of inputs with output data of the plurality
of first computing units, performing a plurality of operations based on the plurality
of data supplied in accordance with a control signal, and outputting the operation
results from the plurality of outputs, and
a plurality of output selection devices each selecting and outputting one data
from a plurality of input data and at least one output data of the first and second
computing units in accordance with a control signal.
56. A parallel arithmetic device as set forth in claim 50, wherein the second
arithmetic device includes
a plurality of first computing units each in having a plurality of inputs and
a plurality of outputs, performing a plurality of operations based on data supplied
to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of first input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the first computing units,
at least one second computing unit each having a plurality of inputs and a plurality
of outputs, performing a plurality of operations based on the plurality of data
supplied to the plurality of inputs in accordance with a control signal, and outputting
the operation results from the plurality of outputs,
a plurality of second input selection devices each selecting one data from the
plurality of input data and output data of the second computing unit in accordance
with a control signal, and
a plurality of output selection devices each selecting and outputting one data
from a plurality of input data and at least one output data of the second computing
unit in accordance with a control signal.
57. A parallel arithmetic device as set forth in claim 50, wherein the second
arithmetic device includes:
a plurality of computing units, arranged in, multiple stages, each having a plurality
of inputs and a plurality of outputs, performing a plurality of operations based
on data supplied to the plurality of, inputs in accordance with a control signal
and outputting the operation results from the plurality of outputs,
a plurality of input selection devices each selecting one data from a plurality
of input data in accordance with a control signal and supplying it to different
inputs of the computing units of the first stage, and a plurality of output selection
devices each selecting and outputting one data from a plurality of input data and
at least one output data of the computing units of the stages in accordance with
a control signal,
the computing units arranged in stages other than the computing units of the
first stage each being supplied at the plurality of inputs with output data of
the plurality of computing units of the previous stage performing a plurality of
operations based on the plurality of data supplied in accordance with a control
signal, and outputting the operation results from the plurality of outputs.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an arithmetic device reconfigurable by outside
control, in particular relates to an arithmetic device reconfigurable by outside
control used in a DSP (Digital Signal Processor) etc., including arithmetic logic
units (ALU) for performing arithmetic and logic operations or MAC structure (Multiply-Accumulate
Architecture) computing units for repeating multiplication and addition operations,
etc., or arithmetic devices able to perform so-called butterfly operation or other
multiple input, multiple output operations.
Further, the present invention relates to an arithmetic system including
a reconfigurable arithmetic device, in particular, an arithmetic system including
an arithmetic device able to reconfigure the array of the computing units or the
coefficient parameters at the time of executing operations etc. based on component data.
Further, the present invention relates to an address generation device applicable
to an arithmetic system including a reconfigurable arithmetic device.
Further, the present invention relates to a reconfigurable interleave device
which can be applied to for example an arithmetic system including a reconfigurable
arithmetic device and a data memory whose stored data is read as operation data
by the arithmetic device and in which operation results are written and which absorbs
the difference in the data transfer rates between the arithmetic device and data
memory and accesses them by interleaving.
2. Description of the Related Art
As an arithmetic device reconfigurable by control from the outside, there is
for
example known an integrated circuit arithmetic device configured by a dynamically
configurable gate array as disclosed in Japanese National Patent Publication (Tokuhyo)
No. 7-503804.
This integrated circuit arithmetic device is configured by a dynamically configurable
field programmable gate array (FPGA).
An FPGA is comprised of a large number of input/output (I/O) blocks, programmable
logic blocks, and interconnections and other signal distribution resources for
connecting the logic blocks to the I/O blocks and connecting the I/O blocks to
FPGA pins through input/output pads.
Further, an FPGA program loads component data in the component memory array
of the FPGA.
Further, this arithmetic device has a processor and a reconfigurable instruction
execution unit. By dynamically changing the reconfigurable instruction execution
unit, complicated processing is achieved by the hardware and different combination
logic functions are realized.
However, since the above arithmetic device is comprised using an FPGA and
is reconfigured by switching at the gate level, there are the disadvantages that
optimization of the logic level is difficult, the component data becomes large,
and the area efficiency as an integrated circuit is poor.
Further, a conventional DSP is mostly comprised of a single or two MACs
or ALUs. For example, when performing multiple-item operation such as MEMW=ax+by+cz+dw,
it is necessary to perform the following. Here, reg
1 to reg
4 indicate registers.
reg
1=ax
reg
2=by
reg
3=cz
reg
4=dw
reg1=
reg1+
reg2
reg3=
reg3+
reg4
MEMW=
reg1+
reg3
In this way, with a conventional DSP, it was necessary to rewrite the data in
the registers for a while to obtain the operation results.
That is, in a conventional DSP, it becomes necessary to access the registers
other than in operations actually desired to be performed. Therefore, extra cycles
were involved. This is not desirable from the viewpoint of lowering the power.
Further, in a conventional processor, when performing butterfly operation
and other multiple input and multiple output operations, for example, when performing
the operations of y
0=x-+x
1, y
1=x
0-x
1, even if
part of the input data is in common, it is necessary to perform the operations
separately for each output and necessary to access x
0 for each operation.
Therefore, the efficiency was poor.
Further, with dedicated hardware, the operations were fixed, such as for
simultaneous operations of y
0=x
0+x
1 and y
1=x
0-x
1,
and reconfiguration was not possible.
Further, conventional DSPs and other processors can perform the following operations:
MEMW0=
x[k0]+
x[k1],
MEMW1=
px*(
x[k0]-
x[k1])-
py*(
y[k0]-
y[k1]),
MEMW2=
y/[k0]+
y[k1],
MEMW3=
px*(
x[k0]-
x[k1])+
py*(
y[k0]-
y[k1])
When performing this processing, specifically for example the calculation of
MEMW
1, it is necessary to perform the following. Here, reg
1 to reg
4
indicate registers.
reg1=
x[k0]-
x[k1]
reg2=
px*reg1
reg3=
y[k0]-
y[k1]
reg4=
py*reg3
MEMW1=
reg2-
reg4
That is, in a conventional processor, as explained above, processing was necessary
for temporarily storing values in the registers.
Therefore, the number of unnecessary write operations in the registers
not required for processing operations and the number of read operations from the
registers became greater resulting in the undesirable increase in the number of
processing cycles and the power consumption.
Further, the number of registers has to be increased by the amount of increase
of the intermediate results left temporarily. Further, there was the defect that
when the registers are insufficient, it was necessary to rewrite the data in the
memory requiring further extra cycles and power.
Further, in the above processing, the operation of MEMW
0 and the
operation of MEMW
1 make common use of x[k
0], x[k
1], but with
a conventional processor, it is not possible to simultaneously perform the operations
of x[k
0]+x[k
1], x[k
0]-x[k
1] and therefore there is
also the defect of an increase in the number of cycles required for processing.
A conventional arithmetic system, however, is comprised of for example a CPU,
an
address generation device, a plurality of component data memories, and a reconfigurable
arithmetic device.
In such an arithmetic system, the CPU is used to control the selection of the
plurality of component data memories.
In this case, in order to allow use of the CPU to select the memories while the
address generation device is generating addresses, a synchronization mechanism
is provided between the CPU and the address generation device.
In this way, in a conventional arithmetic system, since it was necessary to provide
a synchronization mechanism between the CPU and the address generation device in
order to allow use of the CPU to select the memories while the address generation
device is generating addresses, the control became complicated, extra hardware
became required, or, depending on the structure of the hardware, synchronization
itself became impossible.
Further, in the above way, a conventional arithmetic system is, for example,
comprised of a CPU, an address generation device, a plurality of component data
memories, and a reconfigurable arithmetic device.
In this arithmetic system, the CPU is used to control the selection of the plurality
of component memories.
In this case, the CPU is used to select the memories while the address generation
device is generating addresses.
In a conventional DSP etc., the address generation pattern is limited to relatively
simple ones such as for loops of the C-language. When trying for complicated access,
the automatically generated addresses are insufficient and it was necessary to
use the ALUs of the DSP to calculate the addresses.
Therefore, the number of cycles required for the processing became greater
than when automatically generating addresses and the efficiency was poor.
Further, for example, an arithmetic system including a reconfigurable arithmetic
device has a data memory, a CPU, an address generation device, and a plurality
of component data memories.
Further, such an arithmetic system uses the CPU to select the component
data of the plurality of component memories, reads out the stored data of the,data
memory in accordance with the addresses generated by for example the CPU or address
generation device as operation data to the arithmetic device, and rewrites the
operation results by the arithmetic device.
When the data memory used in such an arithmetic system etc., however, is for
example provided with two banks (BANK)
0,
1 and when reading out the
data even
2 to the output MEMR
0 and reading out the data even
3
to the output MEMR
1 in a certain cycle and reading out odd
3 to the
output MEMR
0 and odd
3 to the output MEMR
1 in the next cycle
or writing data even
2, even
3 in the BANK
0 in a certain cycle
and writing data odd
2, odd
3 in the BANK
1 in the next cycle,
an ordinary dual port (2R2W) memory becomes necessary as the memory bank.
However, a 2R2Wmemory has the defect of a large cell area. Further, in some
cases, it is necessary to design a dedicated memory, so there is the defect of
a low process portability.
Therefore, a buffer memory device giving a performance equal to that in
the case of use of this dual port memory has been proposed (see Japanese Unexamined
Patent Publication (Kokai) No. 10-307787).
This buffer memory device has a competition control circuit which judges when
access by interleaving is possible or when accessing the same memory bank and the
address signals collide and access by interleaving becomes impossible, sends a
wait signal to the DMA controller when access is impossible, and temporarily suspends
the DMA transfer.
A buffer memory device provided with such a competition control circuit, however,
has the disadvantage that sometimes continuous access of the memory is not possible.
Further, in the above way, a conventional arithmetic system is, for example,
comprised of a CPU, an address generation device, component data memories, and
a reconfigurable arithmetic device.
This arithmetic system is comprised to use the CPU to rewrite the component
data of the component data memories so as to set any array of computing units of
the arithmetic device, coefficient parameters at the time of execution of operations,
etc. and reconfigure the arithmetic device to obtain the desired operation results.
In this conventional arithmetic system, when it is only possible to hold one
set
of the component data simultaneously, it is not possible to rewrite the component
data while executing operation and is not possible to perform operation while rewriting
component data.
That is, when it is only possible to simultaneously store one set of component
data, it is not possible to execute processing and rewrite component data at the
same time.
If the number of reconfigurable elements becomes large, a certain time is required
for rewriting the component data, so when performing operation while repeatedly
switching a plurality of component data etc., it is necessary to rewrite the component
data after the end of each operation and therefore the overhead for reconfiguration
for
