Reference circuits for sampled-data circuits Number:7,522,086 from the United States Patent and Trademark Office (PTO) owispatent

Title: Reference circuits for sampled-data circuits

Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.

Patent Number: 7,522,086 Issued on 04/21/2009 to Lee

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Inventors:	Lee; Hae-Seung (Bedford, MA)
Assignee:	Cambridge Analog Technologies, Inc. (Bedford, MA)
Appl. No.:	11/617,228
Filed:	December 28, 2006

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	60754683	Dec., 2005

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Current U.S. Class:	341/172 ; 341/150; 341/155
Current International Class:	H03M 1/12 (20060101)
Field of Search:	341/155,172,150 324/691

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References Cited [Referenced By]

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U.S. Patent Documents

4595976	June 1986	Parro
5488565	January 1996	Kennon et al.
5565930	October 1996	Bolger et al.
5600322	February 1997	Garavan
5869999	February 1999	Mawet
6232786	May 2001	Barnett
6249240	June 2001	Bellaouar
6404376	June 2002	Kalthoff et al.
6573851	June 2003	Bult
6828753	December 2004	Grasso et al.
6891433	May 2005	Schrader
7009549	March 2006	Corsi

Foreign Patent Documents

	1221686		Jul., 2002		EP
	211841		Aug., 1983		GB
	2247120		Feb., 1992		GB
	0013006		Mar., 2000		WO
	2004043062		May., 2004		WO
	2006047268		May., 2006		WO

Primary Examiner: Jeanglaude; Jean B
Attorney, Agent or Firm: Gauthier & Connors LLP

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Parent Case Text

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PRIORITY INFORMATION

The present application claims priority, under 35 U.S.C. .sctn.119(e), from U.S. Provisional Patent Application, Ser. No. 60/754,683, filed on Dec. 29, 2005. The entire content of U.S. Provisional Patent Application, Ser. No. 60/754,683, filed on Dec. 29, 2005, is hereby incorporated by reference.

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Claims

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What is claimed is:

1. A switched capacitor circuit, comprising: a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a voltage reference level; a waveform generator to generate a predetermined waveform; a switched capacitance circuit operatively connected to said level-crossing detector; a switch operatively coupled to said level-crossing detector; and a voltage reference circuit operatively coupled to said switched capacitance circuit to provide a voltage reference level; said switch turning OFF when said level-crossing detection signal indicates said input signal crossed said voltage reference level.

2. The analog-to-digital converter as claimed in claim 1, wherein said voltage reference means includes an operational amplifier.

3. The analog-to-digital converter as claimed in claim 2, wherein said operational amplifier includes a pre-amplifier.

4. The analog-to-digital converter as claimed in claim 2, wherein said operational amplifier includes a current mirror with gain.

5. The analog-to-digital converter as claimed in claim 1, further comprising: a second level-crossing detector to generate a second level-crossing detection signal when a second input signal crosses a second predetermined level; a second sampling switch, operatively coupled to said second level-crossing detector; and a second switched capacitance circuit, operatively connected to said first sampling switch; said second sampling switch turning OFF when said second level-crossing detection signal indicates said second input signal crossed said second predetermined level.

6. The analog-to-digital converter as claimed in claim 1, wherein said level-crossing detector is a zero-crossing detector.

7. The analog-to-digital converter as claimed in claim 1, wherein said level-crossing detector is a comparator.

8. The analog-to-digital converter as claimed in claim 1, wherein said waveform generator produces a plurality of predetermined waveforms.

9. A switched capacitor circuit, comprising: a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a voltage reference level; a waveform generator, operatively connected to said level-crossing detector, to generate a predetermined waveform; a switched capacitance circuit operatively connected to said level-crossing detector; a switch operatively coupled to said level-crossing detector; and a voltage reference circuit operatively coupled to said switched capacitance circuit to provide a voltage reference level; said switch turning OFF when said level-crossing detection signal indicates said input signal crossed said voltage reference level.

10. The switched-capacitor circuit as claimed in claim 9, wherein said voltage reference means includes an operational amplifier.

11. The switched-capacitor circuit as claimed in claim 10, wherein said operational amplifier includes a pre-amplifier.

12. The switched-capacitor circuit as claimed in claim 10, wherein said operational amplifier includes a current mirror with gain.

13. The switched capacitor circuit as claimed in claim 1, further comprising: a second waveform generator to generate a second predetermined waveform; a second level-crossing detector, operatively connected to said second waveform generator, to generate a second level-crossing detection signal when a second input signal crosses the voltage reference level; and a second switch operatively coupled to said second level-crossing detector; said second switch turning OFF when said second level-crossing detection signal indicates said second input signal crossed the voltage reference level.

14. The switched capacitor circuit as claimed in claim 9, wherein said level-crossing detector is a comparator.

15. The switched capacitor circuit as claimed in claim 9, wherein said level-crossing detectors is a zero-crossing detector.

16. The switched capacitor circuit as claimed in claim 13, wherein said second waveform generator produces a plurality of predetermined waveforms.

17. The switched capacitor circuit as claimed in claim 9, wherein said waveform generator produces a plurality of predetermined waveforms.

18. The switched capacitor circuit as claimed in claim 13, further comprising: a third switch operatively coupled to said second level-crossing detector; and a sampling capacitor operatively connected to said first level-crossing detector; said third switch turning OFF when said second level-crossing detection signal indicates said second input signal crossed said voltage reference.

19. The switched capacitor circuit as claimed in claim 18, further comprising: a fourth switch operatively coupled to said second level-crossing detector; and a second sampling capacitor operatively connected to said first level-crossing detector; said fourth switch turning OFF when said second level-crossing detection signal indicates said second input signal crossed said voltage reference level a second time.

20. A switched capacitor circuit, comprising: a first waveform generator to generate a first predetermined waveform; a first level-crossing detector to generate a first level-crossing detection signal when an input signal crosses a first voltage reference; a first switch operatively coupled to said first level-crossing detector; a first sampling capacitor operatively connected to said first level-crossing detector; a second waveform generator to generate a second predetermined waveform; a second level-crossing detector to generate a second level-crossing detection signal when a second input signal crosses a second voltage reference level; a second switch operatively coupled to said second level-crossing detector; a second sampling capacitor operatively connected to said first level-crossing detector; and a third level-crossing detector differentially coupled to said first and second sampling capacitors; said first switch turning OFF when said first level-crossing detection signal indicates said input signal crossed said first voltage reference; said second switch turning OFF when said second level-crossing detection signal indicates said second predetermined waveform crossed said second voltage reference level.

21. The switched capacitor circuit as claimed in claim 20, wherein said first, second, and third level-crossing detectors are zero-crossing detectors.

22. The switched capacitor circuit as claimed in claim 20, wherein said first, second, and third level-crossing detectors are comparators.

23. The switched capacitor circuit as claimed in claim 20, wherein said first and second waveform generators produce a plurality of predetermined waveforms.

24. A switched capacitor circuit, comprising: a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level; a waveform generator, operatively connected to said level-crossing detector, to generate a first predetermined waveform; a switched capacitance circuit operatively connected to said level-crossing detector; a voltage reference circuit operatively coupled to said switched capacitance circuit to provide a voltage reference level; a switch operatively coupled to said level-crossing detector; and a sampling capacitor operatively connected to said level-crossing detector; said switch turning OFF when said level-crossing detection signal indicates said input signal crossed said first predetermined level.

25. The switched-capacitor circuit as claimed in claim 24, wherein said voltage reference means includes an operational amplifier.

26. The switched-capacitor circuit as claimed in claim 25, wherein said operational amplifier includes a pre-amplifier.

27. The switched-capacitor circuit as claimed in claim 25, wherein said operational amplifier includes a current mirror with gain.

28. The switched capacitor circuit as claimed in claim 24, further comprising: a second waveform generator to generate a second predetermined waveform; a second level-crossing detector, operatively connected to said second waveform generator, to generate a second level-crossing detection signal when a second input signal crosses the voltage reference level; a second switch operatively coupled to said second level-crossing detector; and a second sampling capacitor operatively connected to said level-crossing detector; said second switch turning OFF when said second level-crossing detection signal indicates said second input signal crossed said voltage reference level.

29. The switched capacitor circuit as claimed in claim 28, further comprising: a third switch operatively coupled to said first level-crossing detector; said third switch turning OFF when said first level-crossing detection signal indicates said input signal crossed said first predetermined level.

30. The switched capacitor circuit as claimed in claim 28, wherein said first and second level-crossing detectors are comparators.

31. The switched capacitor circuit as claimed in claim 28, wherein said first and second level-crossing detectors are zero-crossing detectors.

32. The switched capacitor circuit as claimed in claim 28, wherein said second switch is operatively connected between said voltage reference and said second sampling capacitor.

33. The switched capacitor circuit as claimed in claim 28, wherein said second waveform generator produces a plurality of predetermined waveforms.

34. A reference voltage source, comprising: a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a waveform generator to generate a first predetermined waveform; a switch operatively coupled to said level-crossing detector; a sampling capacitor operatively connected to said level-crossing detector; a first bias voltage source operatively connected to an input terminal of the level-crossing detector; and a second bias voltage source operatively connected to said input terminal of the level-crossing detector; said switch turning OFF when said level-crossing detection signal indicates said input signal crossed said predetermined level.

35. The reference voltage source as claimed in claim 34, wherein said level-crossing detector is a comparator.

36. The reference voltage source as claimed in claim 34, wherein said level-crossing detector is a zero-crossing detector.

37. The reference voltage source as claimed in claim 34, wherein said waveform generator is a variable current source.

38. A reference voltage source, comprising: a waveform generator to generate a predetermined waveform; a first transistor operatively connected to said waveform generator; a second transistor operatively connected to said waveform generator; a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a switch operatively coupled to said level-crossing detector; and a sampling capacitor operatively connected to said level-crossing detector; said first switch turning OFF when said level-crossing detection signal indicates said input signal crossed said predetermined level.

39. The reference voltage source as claimed in claim 38, wherein said level-crossing detector is a comparator.

40. The reference voltage source as claimed in claim 38, wherein said level-crossing detector is a zero-crossing detector.

41. The reference voltage source as claimed in claim 38, wherein said waveform generator is a variable current source.

42. A reference voltage source, comprising: a waveform generator to generate a predetermined waveform; an amplifier operatively connected to said waveform generator; a first bias voltage source operatively connected to said amplifier; a second bias voltage source operatively connected to said amplifier; and a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; said waveform generator turning OFF when said level-crossing detection signal indicates said input voltage crossed said predetermined level.

43. The reference voltage source as claimed in claim 42, wherein said level-crossing detector is a comparator.

44. The reference voltage source as claimed in claim 42, wherein said level-crossing detector is a zero-crossing detector.

45. The reference voltage source as claimed in claim 42 wherein said waveform generator is a variable current source.

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Description

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FIELD OF THE PRESENT INVENTION

The present invention relates generally to reference circuits for sampled-data circuits.

BACKGROUND OF THE PRESENT INVENTION

Most sampled-data analog circuits such as switched-capacitor filters, analog-to-digital converters, and delta-sigma modulators require operational amplifiers to process the signal. Consider a switched-capacitor integrator example shown in FIG. 2. First, the switches S.sub.11 and S.sub.13 are closed so that the input voltage v.sub.in is sampled on the sampling capacitor C.sub.S1. Next, the switches S.sub.11 and S.sub.13 are opened and S.sub.12 and S.sub.14 are closed. This operation transfers the charge in the sampling capacitor C.sub.S1 to the integrating capacitor C.sub.I1. The output voltage, v.sub.out, of a first integrator 1100 is typically sampled by another sampled-data circuit, for example, another switched-capacitor integrator. In the circuit shown in FIG. 2, the circuit consisting of switches S.sub.21, S.sub.22, S.sub.23, S.sub.24, and a second sampling capacitor C.sub.S2 comprise a part of the second switched-capacitor integrator. The output voltage, v.sub.out, of the first integrator 10 is sampled on the second sampling capacitor C.sub.S2 by closing switches S.sub.21 and S.sub.23.

An example of a timing diagram is shown in FIG. 3. The clock signal has two non-overlapping phases .phi..sub.1 and .phi..sub.2. The phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.21, and S.sub.23, and phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, S.sub.22, and S.sub.24. With this timing, the circuit performs non-inverting discrete integration with full clock delay. The waveforms at the output of the integrator, v.sub.out, and at the virtual ground node 100, v.sub.1, are also shown in FIG. 3. Different clock phasing arrangements yield different responses from the integrator. For example, if .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and phase .phi..sub.1 is applied to switches S.sub.12, S.sub.14, S.sub.21, and S.sub.23, the circuit performs non-inverting integration with half-clock delay.

For an accurate integration of the input signal, v.sub.1 must be driven as close to ground as possible. In order to accomplish this, the operational amplifier must provide sufficient open-loop gain and low noise. In addition, for fast operation, the operational amplifier 10 of FIG. 2 must settle fast.

In FIG. 3, the voltage v.sub.1 is shown to settle back to ground after a disturbance when the sampling capacitor C.sub.S1 is switched to Node 100 by closing S.sub.12 and S.sub.14. In addition to high open-loop gain and fast settling time, operational amplifiers must provide large output swing for high dynamic range. As the technology scales, it becomes increasingly difficult to achieve these characteristics from operational amplifiers. The primary factors that make the operational amplifier design difficult are low power supply voltages and low device gain.

As noted above, accurate output voltage can be obtained if Node 100 in FIG. 2 is maintained precisely at ground. However, in sampled-data circuits, the only point of time accurate output voltage is required is at the instant the output voltage is sampled by another sampling circuit. Thus, it is not necessary to maintain the voltage at Node 100 at ground all the time.

Zero-crossing detectors can be applied in other switched-capacitor circuits such as algorithmic and pipeline analog-to-digital converters, delta-sigma converters, and amplifiers. These applications often require constant voltage sources, referred to as reference voltages.

Therefore, it is desirable to provide zero-crossing detectors in algorithmic analog-to-digital converters, pipeline analog-to-digital converters, delta-sigma converters, and amplifiers which apply voltage sources, such as reference voltages, in zero-crossing detector based circuits in a manner that reduces the power consumption required in such voltage sources without degrading noise performance or speed of zero-crossing based circuits.

SUMMARY OF THE PRESENT INVENTION

One aspect of the present invention is an analog-to-digital converter. The analog-to-digital converter includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a waveform generator to generate a predetermined waveform; a first switched capacitance circuit; a switched capacitance circuit; a sampling switch, operatively coupled to the level-crossing detector; and a voltage reference circuit operatively coupled to the switched capacitance circuit. The sampling switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.

Another aspect of the present invention is a switched capacitor circuit. The switched capacitor circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a voltage reference level; a waveform generator to generate a predetermined waveform; a switched capacitance circuit operatively connected to the level-crossing detector; a switch operatively coupled to the first level-crossing detector; and a voltage reference circuit operatively coupled to the switched capacitance circuit to provide a voltage reference level. The switch turns OFF when the level-crossing detection signal indicates the input signal crossed the voltage reference level.

Another aspect of the present invention is a switched capacitor circuit. The switched capacitor circuit includes a first waveform generator to generate a first predetermined waveform; a first level-crossing detector to generate a first level-crossing detection signal when an input signal crosses a first voltage reference level; a first switch operatively coupled to the first level-crossing detector; a first sampling capacitor operatively connected to the first level-crossing detector; a second waveform generator to generate a second predetermined waveform; a second level-crossing detector to generate a second level-crossing detection signal when a second input signal crosses a second voltage reference level; a second switch operatively coupled to the second level-crossing detector; a second sampling capacitor operatively connected to the first level-crossing detector; and a third level-crossing detector differentially coupled to the first and second sampling capacitors. The first switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first voltage reference level. The second switch turns OFF when the second level-crossing detection signal indicates the second input signal crossed the second voltage reference level.

Another aspect of the present invention is a switched capacitor circuit. The switched capacitor circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level; a waveform generator to generate a first predetermined waveform; a switched capacitance circuit operatively connected to the level-crossing detector; a voltage reference circuit operatively coupled to the switched capacitance circuit to provide a voltage reference level; a switch operatively coupled to the level-crossing detector; and a sampling capacitor operatively connected to the level-crossing detector. The switch turns OFF when the level-crossing detection signal indicates the input signal crossed the first predetermined level.

Another aspect of the present invention is a reference voltage source. The reference voltage source includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a waveform generator to generate a first predetermined waveform; a switch operatively coupled to the level-crossing detector; a sampling capacitor operatively connected to the level-crossing detector; a first bias voltage source operatively connected to an input terminal of the level-crossing detector; and a second bias voltage source operatively connected to the input terminal of the level-crossing detector. The switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.

Another aspect of the present invention is a reference voltage source. The reference voltage source includes a waveform generator to generate a predetermined waveform; a first transistor operatively connected to the waveform generator; a second transistor operatively connected to the waveform generator; a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a switch operatively coupled to the level-crossing detector; and a sampling capacitor operatively connected to the level-crossing detector. The switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.

Another aspect of the present invention is a reference voltage source. The reference voltage source includes a waveform generator to generate a predetermined waveform; an amplifier operatively connected to the waveform generator; a first bias voltage source operatively connected to the amplifier; a second bias voltage source operatively connected to the amplifier; and a level-crossing detector to generate a level-crossing- detection signal when an input signal crosses a predetermined level. The waveform generator turns OFF when the level-crossing detection signal indicates the input signal crossed a predetermined level.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may take form in various components and arrangements of components, and in various steps and arrangements of steps. The drawings are only for purposes of illustrating a preferred embodiment and are not to be construed as limiting the present invention, wherein:

FIG. 1 illustrates a zero-crossing detector;

FIG. 2 illustrates a switched-capacitor integrator;

FIG. 3 illustrates a timing diagram for the switched-capacitor integrator of FIG. 2;

FIG. 4 illustrates a non-inverting integrator according to the concepts of the present invention;

FIG. 5 illustrates a timing diagram for the non-inverting integrator of FIG. 4;

FIG. 6 illustrates a non-inverting integrator with a waveform generator being a current source according to the concepts of the present invention;

FIG. 7 illustrates another non-inverting integrator according to the concepts of the present invention;

FIG. 8 illustrates a timing diagram for the non-inverting integrator of FIG. 7;

FIG. 9 illustrates another non-inverting integrator according to the concepts of the present invention;

FIG. 10 illustrates another non-inverting integrator according to the concepts of the present invention;

FIG. 11 illustrates a timing diagram for the non-inverting integrator of FIG. 10;

FIG. 12 illustrates another non-inverting integrator according to the concepts of the present invention;

FIG. 13 illustrates another non-inverting integrator according to the concepts of the present invention;

FIG. 14 illustrates a timing diagram for the non-inverting integrator of FIG. 13;

FIG. 15 illustrates a pipeline analog-to-digital converter;

FIG. 16 illustrates a sampling phase of the pipeline analog-to-digital converter of FIG. 15;

FIG. 17 illustrates a second phase of the pipeline analog-to-digital converter of FIG. 15;

FIG. 18 illustrates a pipeline analog-to-digital converter based on a zero-crossing detector;

FIG. 19 illustrates a sampling phase of the pipeline analog-to-digital converter of FIG. 18;

FIG. 20 illustrates a second phase of the pipeline analog-to-digital converter of FIG. 18;

FIG. 21 illustrates a delta-sigma analog-to-digital converter;

FIG. 22 illustrates a bandgap reference circuit;

FIG. 23 illustrates a delta-sigma analog-to-digital converter based on a zero-crossing detector;

FIG. 24 illustrates another delta-sigma analog-to-digital converter based on a zero-crossing detector;

FIG. 25 illustrates a fully-differential analog-to-digital converter based on zero-crossing detectors;

FIG. 26 illustrates an analog-to-digital converter based on zero-crossing detectors;

FIG. 27 illustrates an analog-to-digital converter which provides a bandgap based discrete-time reference voltage;

FIG. 28 illustrates an analog-to-digital converter based on a bandgap reference voltage source;

FIG. 29 illustrates an operational amplifier preceded by a low-to-moderate gain preamplifier for a zero-crossing detector sampled-data circuit;

FIG. 30 illustrates an operational transconductance amplifier for a zero-crossing detector sampled-data circuit;

FIG. 31 illustrates another zero-crossing detector sampled-data circuit; and

FIG. 32 illustrates another zero-crossing detector sampled-data circuit.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention will be described in connection with preferred embodiments; however, it will be understood that there is no intent to limit the present invention to the embodiments described herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the present invention, as defined by the appended claims.

For a general understanding of the present invention, reference is made to the drawings. In the drawings, like reference have been used throughout to designate identical or equivalent elements. It is also noted that the various drawings illustrating the present invention may not have been drawn to scale and that certain regions may have been purposely drawn disproportionately so that the features and concepts of the present invention could be properly illustrated.

It is noted that, in the various Figures, the earth symbol indicates the system's common-mode voltage. For example, in a system with 2.5 V and -2.5 V power supplies, the system's common-mode voltage may be at ground. In a system with a single 2.5 power supply, the system's common-mode voltage may be at 1.25 V.

As noted above, accurate output voltage can be obtained if Node 100 in FIG. 2 is maintained precisely at ground. However, in sampled-data circuits, the only point of time accurate output voltage is required is at the instant the output voltage is sampled by another sampling circuit. Thus, it is not necessary to maintain the voltage at Node 100 at ground all the time.

FIG. 4 illustrates a non-inverting integrator according to the concepts of the present invention. More specifically, as an example, a non-inverting integrator with half-clock delay is illustrated in FIG. 4.

As illustrated in FIG. 4, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. A zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground. The switch S.sub.23 is controlled by the output of the zero crossing detector 30. The output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage v.sub.out. A waveform generator 20 generates a voltage waveform as the output voltage v.sub.out in such way the voltage at Node 100 crosses zero if the charge in capacitors C.sub.S1 and C.sub.I1 is within a normal operating range.

In the timing diagram shown in FIG. 5, the waveform generated by the waveform generator 20 is shown as a ramp. When v.sub.1, the voltage at Node 100, crosses zero at time t.sub.1, the output v.sub.zc of the zero crossing detector 30 goes low, turning the switch S.sub.23 OFF. At that instant, the output voltage v.sub.out is sampled on C.sub.S2.

Since v.sub.1 is very close to zero when the sample of v.sub.2 is taken, an accurate output voltage is sampled on C.sub.S2. A similar operation repeats during the next clock cycle, and the sample of the output voltage is taken at time t.sub.2.

It is noted that the zero crossing detector 30 may optionally have an overflow detection feature that determines when the charge in capacitors C.sub.S1 and C.sub.I1 is outside the normal range of operation. It can be implemented by a logic circuit that makes the output v.sub.zc of the zero-crossing detector 30 to go low when .phi..sub.2 goes low. In the event v.sub.1 fails to cross zero, the sample is taken on the falling edge of .phi..sub.2. At the same time, the logic circuit produces a flag indicating overflow.

In the embodiment described above and in the various embodiments described below, a zero crossing detector is utilized in lieu of a comparator. Typically, a comparator is designed to compare two arbitrary input voltages. A comparator may be implemented as cascaded amplifiers, a regenerative latch, or a combination of both. A comparator may be used to detect a zero voltage level or a predetermined voltage level crossing.

It is noted that the input waveform of the various described embodiments is not arbitrary, but deterministic and repetitive. Thus, the various described embodiments determine the instant the zero voltage level or the predetermined voltage level is crossed than relative amplitudes of the input signals. For such a deterministic input, a zero crossing detector is more efficient.

An example of a zero-crossing detector for the detection of a positive-going input signal is shown in FIG. 1. Initially, node 1 and node 2 are precharged to V.sub.DD and ground, respectively. The ramp input voltage V.sub.IN is applied according to the zero crossing circuit. At the time the input node crosses the threshold, node 1 is discharged rapidly, and node 2 is pulled up to V.sub.DD. Since the zero crossing detector in FIG. 1 is a dynamic circuit, there is no DC power consumption, allowing extremely low power and fast operation. For the detection of zero-crossing of a negative-going signal, a complementary circuit with a PMOS input transistor can be utilized.

As illustrated in FIG. 6, the non-inverting integrator includes a waveform generator which is a current source 200. As illustrated in FIG. 6, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. A zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground. The switch S.sub.23 is controlled by the output of the zero crossing detector 30. The output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage V.sub.out.

The current source 200 charges the capacitors C.sub.S2 and the series connected C.sub.S1 and C.sub.I1, generating a ramp. At the start of .phi..sub.2, the output is briefly shorted to a known voltage V.sub.NEG, the value of which is chosen to ensure the voltage v.sub.1 at Node 100 crosses zero with signals in the normal operating range.

As illustrated in FIG. 7, the non-inverting integrator includes a waveform generator 20 that produces, preferably, a plurality of segments in the waveform with varying rate of change of the output voltage. The first segment may be controlled so as to have the highest rate of change, with subsequent segments having progressively lower rate of change. The detection of zero crossing by the zero crossing detector 30 causes the waveform to advance to the next segment. An output signal v.sub.zc2 of the zero crossing detector 30 remains high until the zero crossing is detected in the last segment of the waveform.

One clock cycle of the timing diagram is shown in FIG. 8. At the start of .phi..sub.2, the waveform generator 20 produces an up ramp. The voltage v.sub.1 is shown to cross zero at time t.sub.1. One output, v.sub.zc1, of the zero crossing detector 30 changes its state after a finite delay t.sub.d1.

The delay t.sub.d1 represents finite delay of a typical zero crossing detector 30. This change of state advances the waveform to the next segment.

Due to the t.sub.d1 of the zero crossing detector 30, the voltage v.sub.1 overshoots by a small amount above ground. The second segment of the waveform generator is a down ramp to permit another zero crossing at time t.sub.2. After a second delay t.sub.d2, the output v.sub.zc2 of the zero crossing detector 30 goes low, causing the switch S.sub.23 to turn OFF, locking the sample of the output voltage v.sub.out.

The delay t.sub.d2 of the second zero crossing is not necessarily the same as the delay associated with the first zero crossing t.sub.d1. The delay t.sub.d2 contributes a small overshoot to the sampled output voltage. The effect of the overshoot can be shown to be constant offset in the sampled charge. In most sampled-data circuits, such constant offset is of little issue.

The zero crossing detector 30 preferably becomes more accurate in detecting the zero crossing as the segments of the waveform advances. The first detection being a coarse detection, it does not have to be very accurate. Therefore, the detection can be made faster with less accuracy. The last zero crossing detection in a given cycle determines the accuracy of the output voltage. For this reason, the last zero crossing detection must be the most accurate.

The accuracy, speed, and the power consumption can be appropriately traded among progressive zero crossing detections for the optimum overall performance. For example, the first detection is made less accurately and noisier but is made faster (shorter delay) and lower power. The last detection is made more accurately and quieter while consuming more power or being slower (longer delay).

An example of a two-segment waveform generator constructed of two current sources (210 and 220) is shown in FIG. 9. As illustrated in FIG. 9, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. A zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground. The switch S.sub.23 is controlled by the output of the zero crossing detector 30. The output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage v.sub.out.

Current sources 210 and 220 charge the capacitors C.sub.S2 and the series connected C.sub.S1 and C.sub.I1 generating two segments of a ramp waveform. At the start of .phi..sub.2, the output is briefly shorted to a known voltage V.sub.NEG, the value of which is chosen to ensure the voltage v.sub.1 crosses zero with signals in the normal operating range. During the first segment, the current source 210 is directed to the output, while during the second segment, the current source 220 is directed to the output, generating two different slopes of ramp.

As illustrated in FIG. 10, the non-inverting integrator includes a level crossing detector 300 having plurality of thresholds. As illustrated in FIG. 10, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. A level crossing detector 300 is used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below. The switch S.sub.23 is controlled by the output of the level crossing detector 300. The output of the level crossing detector 300 is used to determine the time point to take the sample of the output voltage v.sub.out.

The thresholds are predetermined voltage levels. The thresholds of the level crossing detector 300 can be adjusted to minimize overshoot.

For example, the threshold for the first detection may be made negative by a slightly smaller amount than the expected overshoot in the first segment. This minimizes the ramp-down time in the second segment. Also, the threshold for the second segment may be made more positive by the amount of the overshoot in the second segment in order to cancel the effect of the overshoot. Alternatively, the threshold for the first segment may be made more negative than the expected overshoot during the first segment. This permits the second segment to be a positive ramp rather than a negative ramp as shown in FIG. 11.

It is advantageous to make the detection during the last segment to be the most accurate detection. The accuracy of the detection during the last segment is made higher than during other segments. This can be achieved by making the delay longer or making the power consumption higher during the last segment.

As illustrated in FIG. 12, the non-inverting integrator includes a level crossing detector having two zero-crossing detectors, Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320). As illustrated in FIG. 12, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320) are used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below. The switch S.sub.23 is controlled by the output of the Zero Crossing Detector 2 (320). The output of the Zero Crossing Detector 2 (320) is used to determine the time point to take the sample of the output voltage v.sub.out.

The thresholds of the Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320) are selected to minimize overshoot. For example, the threshold for Zero Crossing Detector 1 (310) may be made negative by a slightly smaller amount than the expected overshoot in the first segment. This minimizes the ramp-down time in the second segment. Also, the threshold for Zero Crossing Detector 2 (320) may be made more positive by the amount of the overshoot in the second segment in order to cancel the effect of the overshoot. Alternatively, the threshold for Zero Crossing Detector 1 (310) may be made more negative than the expected overshoot during the first segment. This permits Zero Crossing Detector 2 (320) to be appositive ramp rather than a negative ramp.

In other words, Zero Crossing Detector 1 (310) makes a coarse detection, whereas Zero Crossing Detector 2 (320) makes a fine detection. Thus, it is advantageous to make Zero Crossing Detector 2 (320) to have a higher accuracy.

As illustrated in FIG. 13, the non-inverting integrator includes a level 5 crossing detector having two zero-crossing detectors, Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320). As illustrated in FIG. 13, a clock phase .phi..sub.1 is applied to switches S.sub.11, S.sub.13, S.sub.22, and S.sub.24, and another phase .phi..sub.2 is applied to switches S.sub.12, S.sub.14, and S.sub.21. Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320) are used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below. The switch S.sub.23 is controlled by the output of the Zero Crossing Detector 2 (320). The output of the Zero Crossing Detector 2 (320) is used to determine the time point to take the sample of the output voltage v.sub.out.

Both detectors, Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320), have nominally zero thresholds. The detection thresholds are determined by voltages V.sub.tr1 and V.sub.tr2 applied to the inputs of Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320), respectively. Zero Crossing Detector 1 (310) makes a coarse detection, whereas Zero Crossing Detector 2 (320) makes a fine detection. Thus, it is advantageous to make Zero Crossing Detector 2 (320) to have a higher accuracy.

It is noted that the above-described embodiment may operate as a self-timed system. In this configuration, Rather than supplying constant frequency clock phases .phi..sub.1 and .phi..sub.2, the clock phases are derived from the outputs of Zero Crossing Detector 1 (310) and Zero Crossing Detector 2 (320). FIG. 14 illustrates a self-timed operation.

As illustrated in FIG. 14, the end of the phase .phi..sub.2 is defined by the output of the detection during the last segment. The beginning of the clock phase .phi..sub.1 is defined by a short delay, such as logic delays, after the end of .phi..sub.2. The short delay is generally necessary to ensure non-overlapping clock phases. The end of the clock phase .phi..sub.1 is determined by the zero crossing detection of the previous stage or the following stage in the similar manner.

It is noted that the various embodiments described above can be utilized in a pipeline analog-to-digital converter, an algorithmic analog-to-digital converter, a switched-capacitor amplifier, a delta-sigma modulator, or a self-timed algorithmic analog-to-digital converter. More specifically, zero crossing detectors can be applied in other switched-capacitor circuits such as algorithmic and pipeline analog-to-digital converters, delta-sigma converters, and amplifiers.

These applications often require constant voltage sources, referred to as reference voltages. A pipeline analog-to-digital converter is shown in FIG. 15 in which the first two stages of the pipeline are shown. As in the switched-capacitor integrator in FIG. 2, the pipeline converter operates in two phases as in the switched-capacitor integrator in FIG. 2.

As illustrated in FIG. 15, first stage capacitors C.sub.11-C.sub.14 are connected to either ground, V.sub.in, V.sub.REF, or -V.sub.REF through switches S.sub.11-S.sub.14, respectively. It is noted that only first stage capacitor C.sub.11 can be connected to ground. Each first stage capacitor (C.sub.11-C.sub.14) is connected to the inverted input of amplifier 410. The output V.sub.out(1) of amplifier 410 is feedback to the inverted input of amplifier 410 through switch S.sub.16 and capacitor C.sub.15. It is noted that the inverted input of amplifier 410 may also be connected to ground through switch S.sub.15.

Moreover, as illustrated in FIG. 15, second stage capacitors C.sub.21-C.sub.24 are connected to either ground, V.sub.out(1), V.sub.REF, or -V.sub.REF through switches S.sub.21-S.sub.24, respectively. It is noted that only second stage capacitor C.sub.21 can be connected to ground. Each second stage capacitor (C.sub.21-C.sub.24) is connected to the inverted input of amplifier 420. The output V.sub.out(2) of amplifier 420 is feedback to the inverted input of amplifier 420 through switch S.sub.26 and capacitor C.sub.25. It is noted that the inverted input of amplifier 420 may also be connected to ground through switch S.sub.25.

During the first phase, the sampling phase, the input voltage is sampled on the first stage capacitors C.sub.11-C.sub.14, as shown in FIG. 16. During the sampling phase, the input voltage is compared with -1/2V.sub.REF, 0, and 1/2V.sub.REF. In the second phase, the charge in C.sub.11-C.sub.14 is transferred to the feedback capacitor C.sub.15 as shown in FIG. 17.

Depending on the comparison results from the first phase, the first stage capacitors C.sub.11-C.sub.13 are connected to either V.sub.REF or -V.sub.REF.

The output voltage of the first stage is also sampled by the second stage capacitors C.sub.21-C.sub.24 in the second phase, the transfer phase, of the first stage. Thus, the transfer phase of the first stage coincides with the sampling phase of the second stage.

The operational amplifier 410 must force the voltage at Node 101 to virtual ground in order for the output voltage to be accurate. As in other sampled-data analog circuits, forcing of virtual ground by an operational amplifier is power intensive.

A pipeline converter based on zero-crossing detectors can be substantially more efficient in power consumption and area compared with conventional approaches based on operational amplifiers as illustrated in FIGS. 15-17. An embodiment of a pipeline converter based on zero crossing detection provided by the invention is shown in FIG. 18. Only the first two stages of pipeline are shown for clarity.

As illustrated in FIG. 18, first stage capacitors C.sub.11-C.sub.14 are connected to either ground, V.sub.in, V.sub.REF, or -V.sub.REF through switches S.sub.11-S.sub.14, respectively. It is noted that only first stage capacitor C.sub.11 can be connected to ground. Each first stage capacitor (C.sub.11-C.sub.14) is connected to one input terminal of a zero crossing detector 510. The output V.sub.out(1) of the zero crossing detector 510 controls activation of switch S.sub.25. A ramp generator 610 is connected to the one input terminal of the zero crossing detector 510 through switch S.sub.16 and capacitor C.sub.15. It is noted that the one input terminal of the zero crossing detector 510 may also be connected to ground through switch S.sub.15. It is further noted that capacitor C.sub.15 may also be connected to ground through switch S.sub.16.

Moreover, as illustrated in FIG. 18, second stage capacitors C.sub.21-C.sub.24 are connected to either ground, V.sub.REF, or -V.sub.REF through switches S.sub.21-S.sub.24, respectively. It is noted that only first stage capacitor C.sub.21 can be connected to ground. Each second stage capacitor (C.sub.21-C.sub.24) is connected to one input terminal of a second zero crossing detector 520. The ramp generator 610 is connected to the one input terminal of the second zero crossing detector 520 through switch S.sub.26 and capacitor C.sub.25. It is noted that the one input terminal of the second zero crossing detector 520 may also be connected to ground through switch S.sub.25. It is further noted that capacitor C.sub.25 may also be connected to ground through switch S.sub.26.

As in the pipeline converter of FIGS. 15-17, the pipeline converter in FIG. 18 operates in two phases. The first phase is schematically shown in FIG. 19. For clarity of description, switches are omitted, and only the voltages applied through the omitted switches are indicated. The operation is performed in two phases. During the first phase, the sampling phase, the input voltage is sampled on the first stage capacitors C.sub.11-C.sub.14, as shown in FIG. 19. Also during the sampling phase, the input voltage is compared with -1/2V.sub.REF, 0, and 1/2V.sub.REF.

In the second phase, the transfer phase, the charge in C.sub.11-C.sub.14 is transferred to the feedback capacitor C.sub.15 as shown in FIG. 20. Depending on the comparison results from the first phase, the first stage capacitors C.sub.11-C.sub.13 are connected to either V.sub.REF or -V.sub.REF.

The ramp waveform generator 610 sweeps the output voltage V.sub.out(1) up and then down, causing the input voltage of the zero crossing detector 510 to cross the ground potential or the common-mode voltage. The output status of the zero crossing detector 510 changes, and the sampling switch S.sub.25 of second stage is turned OFF. This locks the accurate voltage on the second stage capacitors C.sub.21-C.sub.24 because the sampling switch is turned OFF at the time the input voltage of the zero crossing detector 510 is at or near the virtual ground.

In pipeline converters, the reference voltages are generally applied during the transfer phase as explained in the preceding description. Depending on the function implemented, however, the reference voltages may be applied during the sampling phase. For example, many delta-sigma converters may apply the reference voltages during the sampling phase. FIG. 21 illustrates an example of a delta-sigma converter.

As illustrated in FIG. 21, a capacitor C.sub.S1 is charged by voltage source V.sub.in through the operations of switches S.sub.11-S.sub.14. Also, a capacitor C.sub.REF is charged by voltage source V.sub.ref through the operations of switches S.sub.31-S.sub.34.

In the delta-sigma converter, as shown in FIG. 21, the input voltage V.sub.in is sampled by capacitor C.sub.S1 during the sampling phase. The reference voltage V.sub.REF is sampled by capacitor C.sub.ref during the same phase. The charge in both capacitors C.sub.S1 and C.sub.ref is transferred to capacitor C.sub.I1 during the transfer phase.

The reference voltages V.sub.REF and -V.sub.REF can be generated from bandgap reference circuits and are driven by operational amplifiers. An example bandgap reference circuit is shown in FIG. 22. A first bias voltage, the base-emitter voltage of Q.sub.1, is applied to the input of an operational amplifier 410. A second bias voltage, the base-emitter voltage of Q.sub.2, is also applied to a non-inverting input of the amplifier 410 through a resistor R.sub.2. It is noted that the output voltage of the amplifier 410 is closely related to the bandgap voltage, which is substantially independent of operating temperature.

Unless large bypass capacitors are used on the reference voltages, it is generally required that the reference voltage settle to an accurate value within the half clock period. In addition, the reference voltages must present low noise, preferably lower than 1/2 LSB at the intended resolution of the A/D converter.

In order to provide fast settling and low noise, the power consumed in the reference voltage circuits can be a substantial portion of overall power consumption A/D converters. In applications other than A/D converters, voltage sources similar to reference voltage sources may be applied for level shifting or other purposes. If similar op-amp based voltage source circuits are employed in zero-crossing detector based circuits, the power consumption of the reference circuit may be overwhelming because the zero-crossing detector based circuits consume little power.

The invention provides configurations for applying voltage sources, such as reference voltages, in zero-crossing detector based circuits in a manner that reduces the power consumption required in such voltage sources without degrading noise performance or speed of zero-crossing based circuits.

An example of a first stage integrator of a zero-crossing detector based delta-sigma converter is illustrated in FIG. 23. In this embodiment, the reference voltage is sampled during the sampling phase of switched-capacitor circuits.

As illustrated in FIG. 23, a first zero-crossing detector ZCD1 controls the sampling instant of the next stage integrator. A first waveform generator is shown as a variable current source I charging capacitor C.sub.I1. A second zero-crossing detector ZCD2 controls the sampling of the reference voltage on sampling capacitor C.sub.REF. During the sampling phase of the first integrator stage, the input voltage V.sub.in is sampled by capacitor C.sub.S1 by turning switches S.sub.11 and S.sub.13 ON, as described with respect to the integrator stage of FIG. 21.

A second waveform generator, shown as a variable current source I.sub.REF charging capacitor C.sub.REF, produces a waveform, for example the two-segment ramp Illustrated in FIG. 7. The output voltage V.sub.2 is compared with the reference voltage V.sub.REF by second zero-crossing detector ZCD2. The first time V.sub.2 crosses V.sub.REF, the second waveform generator advances its output to the next segment by changing the current I.sub.REF. The second segment is preferably a ramp with a slower rate of change than the first segment.

When V.sub.2 crosses V.sub.REF again during the second segment, second zero-crossing detector ZCD2 turns S.sub.R3 OFF. The voltage sampled on capacitor C.sub.REF is equal to V.sub.REF except a small amount of error caused by the undershoot due to the finite delay of second zero-crossing detector ZCD2.

During the transfer phase, both the input voltage V.sub.in sampled on capacitor C.sub.S1 and the reference voltage V.sub.REF is sampled on capacitor C.sub.REF are transferred to the integrating capacitor C.sub.I1. Switches S.sub.12, S.sub.14, S.sub.R2, S.sub.R4, S.sub.21, and S.sub.23 are closed. Switch S.sub.15 is briefly turned ON to precharge V.sub.out. The output voltage V.sub.out begins to rise when switch S.sub.15 is turned OFF. At the time the voltage V.sub.1 at Node 1 crosses zero during the last segment of the ramp generator, first zero-crossing detector ZCD1 turns switch S.sub.23 OFF, then turns switch S.sub.21 OFF. Transferring the charge from capacitor C.sub.S1 and capacitor C.sub.REF1 to capacitor C.sub.I1 and sampling of the output voltage to capacitor C.sub.S2 is complete at this point.

Although only one capacitor, C.sub.REF. is shown to sample the reference voltage, V.sub.REF, in FIG. 23, multiple capacitors can sample the same reference voltage. For example, in the circuit of FIG. 24, capacitors C.sub.REF1 and C.sub.REF2 sample the reference voltage. Second zero-crossing detector ZCD2 turns switches S.sub.R13 and S.sub.R23 OFF to sample the reference voltage in the same manner as in the circuit of FIG. 23.

If the bandwidth of the reference voltage source is greater than the effective bandwidth of second zero-crossing detector ZCD2 in FIG. 23, the noise in V.sub.REF is reduced by the lower bandwidth of second zero-crossing detector ZCD2. This would be the case if no bypass capacitor is connected across V.sub.REF. Such omission of bypass capacitors is highly desirable because it saves die area or extra pins for external bypass capacitors.

Since V.sub.REF only sees the input capacitance of second zero-crossing detector ZCD2, the design of the reference voltage source is greatly simplified. In the reference sampling circuits described above, the reference source must drive the reference sampling capacitor directly. Therefore, the reference source typically uses an operational amplifier.

It is noted that the operational amplifiers can be omitted because the loading on the reference voltage source is very small. In addition, due to the filtering property of second zero-crossing detector ZCD2, the reference voltage source is allowed to have much higher noise spectral density compared with prior art reference sampling circuit.

The small load and higher noise spectral density save substantial power from the reference circuit.

Frequently, switched-capacitor circuits are implemented in a fully-differential configuration. The various embodiments described above can be implemented in fully-differential configuration. As an example, a fully-differential version of the first embodiment is shown in FIG. 25, where only the reference sampling circuit is shown for clarity.

The input voltages are applied differentially (not shown). Two reference voltages V.sub.REFP and V.sub.REFN are sampled on capacitors C.sub.REFP and C.sub.REFN, respectively, during the sampling phase. The zero-crossing detectors ZCD2 and ZCD3 control the sampling of V.sub.REFP and V.sub.REFN by controlling the state of switches S.sub.RP3 and S.sub.RN3. During the transfer phase, switches S.sub.RP2 and S.sub.RN2 are closed.

If reference subtraction is desired, switches S.sub.RP5 and S.sub.RN5 are closed. If reference addition is desired, on the other hand, switches S.sub.RP4 and S.sub.RN4 are closed instead. The first zero-crossing detector ZCD1 controls the operation of the first stage integrator and the sampling of its result by the second stage sampling capacitors, a