Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system Number:7,149,110 from the United States Patent and Trademark Office (PTO) owispatent

Title: Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system

Abstract: A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.

Patent Number: 7,149,110 Issued on 12/12/2006 to Tran,   et al.

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Inventors:	Tran; Hieu Van (San Jose, CA), Nguyen; Hung Q. (Fremont, CA), Levi; Amitay (Cupertino, CA), Nojima; Isao (Los Altos, CA)
Assignee:	Silicon Storage Technology, Inc. (Sunnyvale, CA)
Appl. No.:	10/737,689
Filed:	December 15, 2003

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	10317455	Dec., 2002	6959779
	10211886	Aug., 2002	6865099
	09929542	Aug., 2001	6751118
	09231928	Jan., 1999	6282145

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Current U.S. Class:	365/185.03 ; 365/185.22
Current International Class:	G11C 11/34 (20060101)
Field of Search:	365/185.03,185.22,185.24

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References Cited [Referenced By]

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U.S. Patent Documents

	5841165		November 1998		Chang et al.
	6501682		December 2002		Yoshida
	6522580		February 2003		Chen et al.
	2003/0002345		January 2003		Avni et al.

Primary Examiner: Le; Vu A.
Attorney, Agent or Firm: DLA Piper Rudnick Gray Cary US LLP

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Parent Case Text

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CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation-in-part of application Ser. No. 10/317,455, filed Dec. 11, 2002 now U.S. Pat. No. 6,959,779, which is a continuation-in-part of application Ser. No. 10/211,886, filed Aug. 1, 2002 now U.S. Pat. No. 6,865,099, which is a continuation-in-part of application Ser. No. 09/929,542, filed Aug. 13, 2001 now U.S. Pat. No. 6,751,118, which is a division of application Ser. No. 09/231,928 filed Jan. 14, 1999, issued as U.S. Pat. No. 6,282,145, the subject matter of each of these applications is incorporated herein by reference.

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Claims

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What is claimed is:

1. A method for determining valid voltages for accessing a plurality of digital multilevel memory cells comprising: dynamically detecting a window of valid data voltages for said plurality of digital multilevel memory cells.

2. The method of claim 1 wherein the detecting comprises: incrementing a first programming voltage to program data in said plurality of memory cells; verifying whether said data in at least one of said plurality of memory cell is properly programmed; and repeating said incrementing and verifying until data is verified to be properly programmed in one of said plurality of memory cells.

3. The method of claim 2 wherein said verifying includes voltage mode sensing of the memory cells.

4. The method of claim 2 wherein said verifying includes current mode sensing of the memory cells.

5. The method of claim 2 wherein the memory cells are source side injection flash memory cells.

6. The method of claim 1 further comprising: verifying data in each memory cell of said plurality of memory cell.

7. The method of claim 6 wherein said verifying data at each memory cell includes voltage mode sensing of the memory cells.

8. The method of claim 6 wherein said verifying data in each memory cell includes current mode sensing of the memory cells.

9. The method of claim 6 wherein the verifying data further comprises: incrementing a second programming voltage; verifying whether data in each memory cell is properly programmed within a margin; repeating said incrementing and verifying for each memory cell outside of said margin.

10. The method of claim 9 wherein the margin has a upper margin and a lower margin, the upper margin being different than the lower margin.

11. The method of claim 10 wherein the verifying of said detecting is to another margin, said another margin being different than said upper and lower margins.

12. The method of claim 9 wherein the incrementing the first programming voltage includes incrementing said first programming voltage by a first incremental voltage, and wherein the incrementing the second programming voltage includes incrementing said second programming voltage by a second incremental voltage.

13. The method of claim 12 wherein the first and second incremental voltages are equal.

14. The method of claim 12 wherein the first and second incremental voltages are different.

15. A method for determining valid voltages for accessing a plurality of digital multilevel memory cells, the memory cells being arranged in sectors, the method comprising: dynamically detecting a window of valid data voltages for one of said sectors of said plurality of digital multilevel memory cells.

16. The method of claim 15 wherein the detecting comprises: first incrementing a first programming voltage by a first incremental voltage to program data in said sector of memory cells; first verifying whether said data in at least one memory cells of said sector is properly programmed; and first repeating said first incrementing and first verifying until data is verified to be properly programmed in one memory cell of said sector; second incrementing said first programming voltage by a second incremental voltage to program data in a sector of memory cells; second verifying whether said data in at least one memory cells of said sector is properly programmed; and second repeating said second incrementing and second verifying until data is verified to be properly programmed in one memory cell of said sector.

17. The method of claim 16 wherein said first and second verifying each include voltage mode sensing of the memory cells.

18. The method of claim 16 wherein said first and second verifying each include current mode sensing of the memory cells.

19. The method of claim 16 wherein said memory cells are source side injection flash memory cells.

20. The method of claim 16 further comprising: verifying data in each memory cell of said plurality of memory cells.

21. The method of claim 20 wherein the verifying data further comprises: incrementing a second programming voltage by a third incremental voltage; verifying whether data in each memory cell of a sector is properly programmed; repeating said incrementing and verifying for each memory cell outside of a margin.

22. The method of claim 21 wherein the verifying of said detecting is to another margin, said another margin being different than said first and second margins.

23. The method of claim 21 wherein the first, second, and third incremental voltages are different.

24. The method for determining valid voltages for accessing a plurality of digital multilevel memory cells, the method comprising: detecting a window of valid data voltages for said plurality of digital multilevel memory cells; verifying and programming with incremental small changes in a programming voltage; and verifying and programming with incremental large steps in said programming voltage.

25. The method of claim 24 wherein said small steps are variable.

26. The method of claim 25 wherein said large steps are variable.

27. A method of determining valid voltages for accessing a plurality of digital multilevel cells, the method comprising: detecting a window of valid data voltages for said plurality of digital multilevel memory cells; verifying and programming said plurality of memory cells using incremental changes in a programming voltage, said verifying including verifying a memory cell is properly programmed within a margin, wherein a valid voltage having a highest voltage and a valid voltage having a lowest voltage are verified relative to a first margin, other valid voltages are verified relative to a second margin, the first margin being greater than said second margin.

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Description

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FIELD OF THE INVENTION

This invention relates in general to semiconductor memories, and, in particular, to the design and operation of multilevel nonvolatile semiconductor memories.

BACKGROUND OF THE INVENTION

As the information technology progresses, the demand for high density giga bit and tera bit memory integrated circuits is insatiable in emerging applications such as data storage for photo quality digital film in multi-mega pixel digital camera, CD quality audio storage in audio silicon recorder, portable data storage for instrumentation and portable personal computers, and voice, data, and video storage for wireless and wired phones and other personal communicating assistants.

The nonvolatile memory technology such as ROM (Read Only Memory), EEPROM (Electrical Erasable Programmable Read Only Memory), or FLASH is often a technology of choice for these application due to its nonvolatile nature, meaning it still retains the data even if the power supplied to it is removed. This is in contrast with the volatile memory technology, such as DRAM (Dynamic Random Access Memory), which loses data if the power supplied to it is removed. This nonvolatile feature is very useful in saving the power from portable supplies, such as batteries. Until battery technology advances drastically to ensure typical electronic systems to function for a typical operating lifetime, e.g., 10 years, the nonvolatile technology will fill the needs for most portable applications.

The FLASH technology, due to its smallest cell size, is the highest density nonvolatile memory system currently available. The advance of the memory density is made possible by rapidly advancing the process technology into the realm of nano meter scale and possibly into the atomic scale and electron scale into the next century. At the present sub-micro meter scale, the other method that makes the super high-density memory system possible is through the exploitation of the analog nature of a storage element.

The analog nature of a flash or nonvolatile storage element provides, by theory, an enormous capability to store information. For example, if one electron could represent one bit of information then, for one typical conventional digital memory cell, the amount of information is equal to the number of electrons stored, or approximately a few hundred thousands. Advances in device physics exploring the quantum mechanical nature of the electronic structure will multiply the analog information manifested in the quantum information of a single electron even further.

The storage information in a storage element is hereby defined as a discrete number of storage levels for binary digital signal processing with the number of storage levels equal to 2.sup.N with N equal to the number of digital binary bits. The optimum practical number of discrete levels stored in a nonvolatile storage element depends on the innovative circuit design method and apparatus, the intrinsic and extrinsic behavior of the storage element, all within constraints of a definite performance target, such as product speed and operating lifetime, with a certain cost penalty.

At the current state of the art, all the multilevel systems are only suitable for medium density, i.e. less than a few tens of mega bits, and only suitable for a small number of storage levels per cell, i.e., less than four levels or two digital bits.

As can be seen, memories having high storage capacity and fast operating speed are highly desirable.

The signal path from the data cells to a sense amplifier may have mismatch with the signal path from the reference memory cells to the sense amplifier. The mismatch generates a current ratio error and may be caused by mismatches of the threshold voltage, the width, length, mobility, and oxide thickness of the circuit elements, such as transistors, in the signal paths. The mismatch also may be caused by mismatch in signal paths due to parasitics, such as width and length of interconnects.

Process, temperature, cycling and other variations may alter the usable voltage or current range of memory cells. Programming of data cells should be done in the range, but the range may change over time.

SUMMARY OF THE INVENTION

A method determines valid voltages for accessing the plurality of digital multilevel memory cells. A window of valid data ranges is detected for the plurality of digital multilevel memory cells.

In one aspect, a first programming voltage is incremented to program data in the plurality of memory cells. The method verifies whether the data in at least one of the memory cells is properly programmed and the incrementing and verifying is repeated until data is verified to be properly programmed in one of the plurality of memory cells. In another aspect, a second programming voltage is incremented and data in each memory cell is verified as to whether the memory cell is properly programmed within a margin. The incrementing of the second programming voltage and the verifying of each memory cell outside of a margin is repeated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross section of a source side injection flash memory cell.

FIG. 1B is a transistor symbol corresponding to the source side injection flash memory cell shown in FIG. 1A.

FIG. 1C is a block diagram of a nonvolatile multilevel memory system.

FIG. 1D is a block diagram of an electronic camera system utilizing a nonvolatile multilevel memory system.

FIG. 1E is a block diagram of an electronic audio system utilizing a nonvolatile multilevel memory system.

FIG. 2A is a block diagram of super high-density nonvolatile multilevel memory integrated circuit system.

FIG. 2B is a block diagram of flash power management unit.

FIG. 2C shows voltage mode sensing.

FIG. 3A is a block diagram of super high-density nonvolatile multilevel array architecture.

FIG. 3B is a page select circuit, which together with the segment select decoder selects one bitline at a time for each y-driver.

FIG. 3C is a block diagram of a multilevel sub-array block.

FIG. 4A is one embodiment of a nonvolatile multilevel array unit of inhibit and select segmentation.

FIG. 4B shows an alternate embodiment of the inhibit and select segmentation scheme.

FIG. 4C shows another alternate embodiment of the inhibit and select segmentation scheme.

FIG. 4D shows another alternate embodiment of the inhibit and select segmentation scheme.

FIG. 4E shows another alternate embodiment of the inhibit and select segmentation scheme.

FIG. 4F shows another alternate embodiment of the inhibit and select segmentation scheme.

FIG. 5A is a cross section of inhibit and select segmentation interconnection.

FIG. 5B is a cross section of another embodiment of inhibit and select segmentation interconnection.

FIG. 5C is a 2-step ramp rate control and fast-slow ramp rate control.

FIG. 6 shows a block diagram of multilevel decoding.

FIG. 7 shows one segment decoder that includes segmented power supply decoder, segmented bitline select decoder, inhibit decoder, segmented predecoded common line decoder, and control gate and control line decoder.

FIG. 8 shows a segmented power supply decoder.

FIG. 9A shows a segmented bitline decoder.

FIG. 9B shows a segmented inhibit decoder.

FIG. 9C shows a segmented predecoded common line decoder.

FIG. 10 shows a sub-block decoder for control gate and common line multilevel decoder.

FIG. 11A shows a sub-block of the circuit in FIG. 10 for four control gates and one common line multilevel decoder.

FIG. 11B shows another embodiment of sub-block for four control gates and one common line multilevel decoder with winner-take-all Kelvin connection.

FIG. 11C shows a circuit for one common line driver.

FIG. 12 shows a scheme of the feedthrough-to-driver and feedthrough-to-memory multilevel precision decoding.

FIG. 13 shows a block diagram of a multilevel reference system.

FIG. 14 shows details of a block diagram of a multilevel reference system.

FIG. 15 shows a reference detection scheme.

FIG. 16 shows positional linear reference system.

FIG. 17 shows a positional geometric reference system.

FIG. 18 shows an embodiment of geometric compensation reference scheme.

FIG. 19A shows voltage levels for program verify, margin, read, and restore for one embodiment of the current invention.

FIG. 19B shows voltage levels for program verify, margin, read, and restore for an alternative embodiment of the current invention.

FIG. 20 shows an embodiment of flow diagram of the page programming cycle.

FIG. 21 shows an embodiment of flow diagram after page programming begins.

FIG. 22A shows a continuation of flow diagram after page programming begins.

FIG. 22B shows an alternative embodiment of continuation of flow diagram after page programming begins shown in FIG. 22A.

FIG. 22C shows an alternate embodiment of the flow diagram shown in FIG. 22B.

FIG. 23 shows an embodiment of flow diagram of the page read cycle.

FIG. 24 shows a continuation of flow diagram of the page read cycle in FIG. 23.

FIG. 25 shows a continuation of flow diagram of the page read cycle in FIG. 24.

FIG. 26 shows details of an embodiment of a single y-driver YDRVS 110S.

FIG. 27 shows details of a latch block, a program/read control block, and program/program inhibit block included in the single y-driver YDRVS 110S.

FIG. 28 is a block diagram illustrating a memory system for a multilevel memory.

FIG. 29A is a block diagram illustrating an inverter mode sensing circuit.

FIG. 29B is a block diagram illustrating a voltage mode sensing circuit.

FIG. 30 is a block diagram illustrating a wide range, high speed voltage mode sensing circuit.

FIG. 31 is a block diagram illustrating a wide range, high speed mode sensing circuit having a local source follower stage and a global common source stage.

FIG. 32 is a block diagram illustrating a wide range, high speed mode sensing circuit with a local PMOS source follower stage and a global source follower stage.

FIG. 33 is a block diagram illustrating a wide range, high speed mode sensing circuit with a local NMOS source follower stage and a global source following stage.

FIG. 34 is a block diagram illustrating a global sense amplifier having an auto zeroing function.

FIG. 35 is a block diagram illustrating an auto zero sense amplifier.

FIG. 36 is a block diagram illustrating a memory system for a multilevel memory including local autozero sense amplifiers and global autozero sense amplifiers.

FIG. 36A is a block diagram illustrating a memory system for a multilevel memory including local autozero sense amplifiers.

FIG. 37 is a block diagram illustrating a memory system including single ended autozero sense amplifiers.

FIG. 38 is a block diagram illustrating a memory system including differential autozero sense amplifiers.

FIG. 39 is a block diagram illustrating a memory system including crossed bitlines.

FIG. 40 is a block diagram illustrating a current sense amplifier including an autozero.

FIG. 41 is a block diagram including a current sense amplifier including autozero and replica loading.

FIG. 42 is a block diagram illustrating a two-stage current sense amplifier including autozero.

FIG. 43 is a block diagram illustrating a two-stage current sense amplifier including autozero.

FIG. 44 is a block diagram illustrating a two-stage indirect current sense amplifier having autozero.

FIG. 45 is a block diagram illustrating a two-stage indirect current sense amplifier having autozero.

FIG. 46 is a block diagram illustrating a memory system including a low voltage sense amplifier.

FIG. 46A is a block diagram illustrating a memory system including a low voltage sense amplifier.

FIG. 47 is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 47A is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 47B is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 48 is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 48A is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 48B is a block diagram illustrating a memory system including a low voltage sense amplifier according to another embodiment.

FIG. 49 is a schematic diagram illustrating a shared sense amplifier segmented reference array.

FIG. 50 is a schematic diagram illustrating a memory cell replica sense amplifier.

FIG. 51 is a schematic diagram illustrating a differential current sense amplifier.

FIG. 52 is a schematic diagram illustrating a two-stage differential current sense amplifier.

FIG. 53 is a schematic diagram illustrating a current difference sense amplifier.

FIG. 54 is a schematic diagram illustrating a current difference sense amplifier.

FIG. 55 is a schematic diagram illustrating a dynamic sense amplifier.

FIG. 56 is a graph illustrating control signals and voltage levels of the dynamic sense amplifier of FIG. 55.

FIG. 57 is a schematic diagram illustrating the dynamic charge sense amplifier.

FIG. 58 is a flow diagram illustrating a single bit current sensing binary search.

FIG. 59 is a flow diagram illustrating a multiple bit current sensing bit search.

FIG. 60 is a block diagram illustrating a memory system with a built-in concurrent byte redundancy.

FIG. 61 is a block diagram illustrating a portion of the non-volatile multilevel memory integrated circuit system 2000 that executes a seek window programming procedure.

FIG. 62 is a flow chart illustrating an asymmetrical margining programming procedure.

FIG. 63 is a flow diagram illustrating a seek window and programming procedure.

FIG. 64 is a flow diagram illustrating a seek window and programming procedure in a second embodiment.

FIG. 65 is a flow diagram illustrating a seek window and programming procedure in a third embodiment.

FIG. 66 is a flow diagram illustrating a seek window and programming procedure in accordance with a fourth embodiment.

FIG. 67 is a timing diagram illustrating the programming voltage in an unequal margin verify-program procedure.

FIG. 68 is a diagram illustrating one embodiment of the reference voltage margin of the programming procedures of FIGS. 62 67.

FIG. 69 is a timing diagram illustrating the voltage of an unequal incremental double ramp rate verify-erase procedure.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Described are the design method and apparatus for a super high density nonvolatile memory system capable of giga to tera bits as applied to the array architecture, reference system, and decoding schemes to realize the optimum possible number of storage levels within specified performance constraints. Method and apparatus for multilevel program and sensing algorithm and system applied to flash memory is also described.

Array architectures and operating methods are described that are suitable for a super high density, in the giga to tera bits, for multilevel nonvolatile "green" memory integrated circuit system. "Green" refers to a system working in an efficient and low power consumption manner. The system and method solves the issues associated with super high density multilevel memory system, such as, precision voltage control in the array, severe capacitive loading from MOS transistor gates and parasitics, high leakage current due to memory cells and from cells to cells, excessive power consumption due to large number of gates and parasitics, and excessive memory cell disturbances due to large memory density.

An Inhibit and Select Segmentation Scheme uses a truly-floating-bitline scheme to greatly reduce the capacitance from junctions and parasitic interconnects to a small value.

A Multilevel Memory Decoding scheme is capable of greater than 10-bit multilevel operation. The Multilevel Memory Decoding Scheme includes the Power Supply Decoded Decoding Scheme, the Feedthrough-to-Memory Decoding Scheme, and the Feedthrough-to-Driver Decoding Scheme. The Multilevel Memory Decoding scheme also includes a "winner-take-all" Kelvin Decoding Scheme, which provides precise bias levels for the memory at a minimum cost. A constant-total-current-program scheme is described. Fast-slow and 2-step ramp rate control programming are described. A reference system method and apparatus includes the Positional Linear Reference System, Positional Geometric Reference System, and the Geometric Compensation Reference System. An apparatus and method may provide multilevel programming, reading, and margining.

A sense amplifier system includes local sense amplifiers coupled to memory subarrays and global sense amplifiers coupled to groups of local sense amplifiers.

Method and apparatus described herein are applicable to digital multilevel as well as analog multilevel system.

Memory Cell Technology

To facilitate the understanding of the invention, a brief description of a memory cell technology is described below. In an embodiment the invention applies to Source Side Injection (SSI) flash memory cell technology, which will be referred to as SSI flash memory cell technology. The invention is equally applicable to other technologies such as drain-side channel hot electron (CHE) programming (ETOX), P-channel hot electron programming, NROM (nitride programmable read only memory), SONOS (silicon-oxide-nitride-oxide-silicon), MONOS (metal-oxide-nitride-oxide-silicon), 2-D or 3-D flash, bi-directional memory cell (e.g., two storage nodes, one near drain and one near source of a memory cell; two floating gates of same one memory cell), phase change memory, molecular memory, polymer memory, spin memory, single electron memory, nano particle memory, other hot electron programming schemes, Fowler-Nordheim (FN) tunneling, ferro-electric memory, and other types of memory technology.

A cell structure of one typical SSI flash cell is symbolically shown in FIG. 1A. Its corresponding transistor symbol is shown in FIG. 1B. The cell is made of two polysilicon gates (abbreviated as poly), a floating gate poly FG 100F and a control gate poly CG 100C. The control gate CG 100C also acts as a select gate that individually select each memory cell. This has the advantage of avoiding the over erase problem which is typical of stacked gate CHE flash cell. The floating gate has a poly tip structure that points to the CG 100C, this is to enhance the electric field from the FG 100F to the CG 100C which allows a much lower voltage in FN erase without using a thin interpoly oxide.

The thicker interpoly oxide leads to a higher reliability memory cell. The cell is also fabricated such that a major portion of the FG 100F overlaps the source junction 100S. This is to make a very high coupling ratio from the source 100S to FG 100F, which allows a lower erase voltage and is advantageous to the SSI programming, which will be described shortly. A structural gap between the FG 100F and at CG 100C is also advantageous for the efficient SSI programming.

The SSI flash memory cell enables low voltage and low power performance due to its intrinsic device physics resulting from its device structure. The SSI flash cell uses efficient FN tunneling for erase and efficient SSI for programming. The SSI flash cell programming requires a small current in hundreds of nano amps and a moderate voltage range of .about.8 to 11 volts. This is in contrast to that of a typical drain-side channel hot electron memory cell programming which requires current in hundreds of microamp to milliamp range and a voltage in the range of 11 to 13 volts.

The SSI flash memory cell erases by utilizing Fowler-Nordheim tunneling from the floating gate poly to the control gate poly by applying a high erase voltage on the control gate CG 100C, e.g., 8 13 volts, and a low voltage on the source 100S, e.g., 0 0.5 volts. The high erase voltage together with high coupling from the source to the floating gate creates a localized high electric field from the FG 100F tip to the CG 100C and causes electrons to tunnel from the FG 100F to the CG 100C near the tip region. The resulting effect causes a net positive charge on the FG 100F.

The SSI flash memory cell programs by applying a high voltage on the source 100S (herein also known as common line CL), e.g., 4 13 V, a low voltage on the CG 100C, e.g., 0.7 2.5 V, and a low voltage on the drain 100D (herein also known as the bitline BL), e.g., 0 1 V. The high voltage on the source 100S strongly couples to the FG to strongly turn on the channel under the FG (it will be equivalently referred to as the FG channel). This in turn couples the high voltage on the source 100S toward the gap region. The voltage on the CG 100C turns on the channel directly under the CG 100C (it will be equivalently referred to as the CG channel). This in turn couples the voltage on the drain 100D toward the gap region. Hence, the electrons flow from the drain junction 100D through the CG channel, through the gap channel, through the FG channel, and finally arrive at the source junction.

Due to the gap structure between the CG 100C and the FG 100F, in the channel under the gap, there exists a strong lateral electric field (EGAPLAT) 100G. As the EGAPLAT 100G reaches a critical field, electrons flowing across the gap channel become hot electrons. A portion of these hot electrons gains enough energy to cross the interface between the silicon and silicon dioxide into the silicon dioxide. And as the vertical field Ev is very favorable for electrons to move from the channel to the FG 100F, many of these hot electrons are swept toward the FG 100F, thus, reducing the voltage on the FG 100F. The reduced voltage on the FG 100F reduces electrons flowing into the FG 100F as programming proceeds.

Due to the coincidence of favorable Ev and high EGAPLAT 100G in the gap region, the SSI memory cell programming is more efficient over that of the drain-side CHE programming, which only favors one field over the other. Programming efficiency is measured by how many electrons flow into the floating gate as a portion of the current flowing in the channel. High programming efficiency allows reduced power consumption and parallel programming of multiple cells in a page mode operation.

Multilevel Memory Integrated Circuit System:

The challenges associated with putting together a billion transistors on a single chip without sacrificing performance or cost are tremendous. The challenges associated with designing consistent and reliable multilevel performance for a billion transistors on a single chip without sacrificing performance or cost are significantly more difficult. The approach taken here is based on the modularization concept. Basically everything begins with a manageable optimized basic unitary block. Putting appropriate optimized unitary blocks together makes the next bigger optimized block.

A super high density nonvolatile multilevel memory integrated circuit system herein described is used to achieve the performance targets of read speed, write speed, and an operating lifetime with low cost. Read speed refers to how fast data could be extracted from a multilevel memory integrated circuit system and made available for external use such as for the system microcontroller 2001 shown in FIG. 1C which is described later. Write speed refers to how fast external data could be written into a multilevel memory integrated circuit system. Operating lifetime refers to how long a multilevel memory integrated circuit system could be used in the field reliably without losing data.

Speed is modularized based on the following concept, T=CV/I, where switching time T is proportional to capacitance C multiplied by the voltage swing V divided by the operating current I. Methods and apparatuses are provided by the invention to optimize C, V, and I to achieve the required specifications of speed, power, and optimal cost to produce a high performance high-density multilevel memory integrated circuit system. The invention described herein makes the capacitance independent of memory integrated circuit density, to the first order, and uses the necessary operating voltages and currents in an optimal manner.

A nonvolatile multilevel memory system is shown in FIG. 1C. A super high density nonvolatile multilevel memory integrated circuit (IC) system 2000 is a digital multilevel nonvolatile flash memory integrated circuit capable of storing 2.sup.N storage levels per one memory cell, with N=number of digital bits. A system microcontroller 2001 is a typical system controller used to control various system operations. Control signals (CONTROL SIGNALS) 196L, input/output bus (IO BUS) 194L, and ready busy signal (R/BB) 196RB are for communication between the system microcontroller 2001 and the super high density nonvolatile multilevel memory integrated circuit system 2000.

An electronic camera system (SILICONCAM) 2008 utilizing super high density nonvolatile multilevel memory IC system 2000 is shown in FIG. 1D. The system (SILICONCAM) 2008 includes an integrated circuit system (ECAM) 2005 and an optical lens block (LENS) 2004. The integrated circuit system (ECAM) 2005 includes an image sensor (IMAGE SENSOR) 2003, an analog to digital converter block (A/D CONVERTER) 2002, a system microcontroller 2001, and the multilevel memory IC system 2000. The optical lens block (LENS) 2004 is used to focus light into the IMAGE SENSOR 2003, which converts light into an analog electrical signal. The IMAGE SENSOR 2003 is a charge coupled device (CCD) or a CMOS sensor. The block (A/D CONVERTER) 2002 is used to digitize the analog electrical signal into digital data. The microcontroller 2001 is used to control various general functions such as system power up and down, exposure time and auto focus. The microcontroller 2001 is also used to process image algorithms such as noise reduction, white balance, image sharpening, and image compression. The digital data is stored in the multilevel memory IC system 2000. The digital data can be down loaded to another storage media through wired or wireless means. Future advances in process and device technology can allow the optical block (LENS) 2004 to be integrated in a single chip with the ECAM 2005.

An electronic audio system (SILICONCORDER) 2007 utilizing super high density nonvolatile multilevel memory IC system 2000 is shown in FIG. 1E. The SILICONCORDER 2007 includes an integrated circuit system (SILICONAUDIO) 2006, a MICROPHONE 2012, and a SPEAKER 2013. The system (SILICONAUDIO) 2006 includes an anti-alias FILTER 2010, an A/D CONVERTER 2002, a smoothing FILTER 2011, a D/A CONVERTER 2009, a system microcontroller 2001, and the multilevel memory IC system 2000. The FILTER 2010 and the FILTER 2011 can be combined into one filter block if the signals are multiplexed appropriately. The microcontroller 2001 is used to control various functions such as system power up and down, play, record, message management, audio data compression, and voice recognition. In recording a sound wave, the MICROPHONE 2012 converts the sound wave into an analog electrical signal, which is filtered by the FILTER 2010 to reduce non-audio signals. The filtered analog signal is then digitized by the A/D CONVERTER 2002 into digital data. The digital data is then stored in compressed or uncompressed form in the multilevel memory IC system 2000. In playing back the stored audio signal, the microcontroller 2001 first uncompresses the digital data if the data is in compressed form. The D/A CONVERTER 2009 then converts the digital data into an analog signal which is filtered by a smoothing filter (FILTER) 2011. The filtered output analog signal then goes to the SPEAKER 2013 to be converted into a sound wave. The signal filtering can be done by digital filtering by the microcontroller 2001. External digital data can be loaded into the multilevel memory IC system 2000 through wired or wireless means. Future advances in process and device technology can allow the MICROPHONE 2012 and the SPEAKER 2013 to be integrated in a single chip with the SILICONAUDIO 2006.

A circuit block diagram of the super high density nonvolatile multilevel memory integrated circuit system 2000 based on the concepts described above and also on ideas described below, is shown in FIG. 2A. For the purpose of discussion, a giga bit nonvolatile multilevel memory chip is described.

A circuit block 100 includes a regular memory array.

It includes a total of for example, 256 million nonvolatile memory cells for a 4-bit digital multilevel memory cell technology or 128 million cells for a 8-bit digital multilevel memory cell technology. An N-bit digital multilevel cell is defined as a memory cell capable of storing 2.sup.N levels. A reference array (MFLASHREF) 106 is used for the reference system. A redundancy array (MFLASHRED) 102 is used to increase production yield by replacing bad portions of the regular memory array of the circuit block 100. An optional spare array (MFLASHSPARE) 104 can be used for extra data overhead storage such as for error correction.

A y-driver block (YDRV) 110 including a plurality of single y-drivers (YDRVS) 110S is used for controlling the bitlines during write, read, and erase operation. Block YDRVS 110S will be described in detail below in the description of the multilevel algorithm. Multiples of y-driver block (YDRV) 110 are used for parallel multilevel page writing and reading to speed up the data rate during write to and read from the multilevel memory IC system 2000. A reference y-driver block (REFYDRV) 116 including a plurality of single reference y-drivers (REFYDRVS) 116S is used for the reference array block (MFLASHREF) 106. A redundant y-driver block (RYDRV) 112 including a plurality of single redundant y-drivers (RYDRVS) 112S is used for the redundant array (MFLASHRED) 102. The function of block (RYDRVS) 112S is similar to that of block (YDRVS) 110S. A spare y-driver block (SYDRV) 114 including a plurality of single spare y-drivers (SYDRVS) 114S is used for the spare array (MFLASHSPARE) 104. The function of block (SYDRVS) 114S is similar to that of block (YDRVS) 110S. A page select block (PSEL) 120 is used to select one bitline out of multiple bitlines for each single y-driver (YDRVS) 110S inside the block (YDRV) 110. Corresponding select circuit blocks for reference array, redundant array, and spare array are a reference page select block (PRSEL) 126, a redundant page select block 122, and a spare page select block 124. A byte select block (BYTESEL) 140 is used to enable one byte data in or one byte data out of the blocks (YDRV) 110 at a time. Corresponding blocks for reference array, redundant array, and spare array are a reference byte select block 146, a redundant byte select block 142, and a spare byte select block 144. The control signals for circuit blocks 116, 126, 146, 112, 122, 142, 114, 124, and 144 are in general different from the control signals for circuit blocks 110, 120, and 140 of the regular memory array of the circuit block 100. The control signals are not shown in the figures.

A multilevel memory precision decoder block (MLMDEC) 130 is used for address selection and to provide precise multilevel bias levels over temperature, process corners, and power supply as required for consistent multilevel memory operation for the regular memory array of the circuit block 100 and for the redundant array 102. A multilevel memory precision decoder block (MLMSDEC) 134 is used for address selection and to provide precise multilevel bias levels over temperature, process corners, and power supply as required for consistent multilevel memory operation for the spare array 104.

An address pre-decoding circuit block (XPREDEC) 154 is used to provide decoding of addresses A<16:AN>. The term AN denotes the most significant bit of addresses depending on the size of the memory array. The outputs of block (XPREDEC) 154 couple to blocks (MLMDEC) 130 and block (MLMSDEC) 134. An address pre-decoding block (XCGCLPRED) 156 is used to provide decoding of addresses A<11:15>. The outputs of block 156 also couple to blocks (MLMDEC) 130 and block (MLMSDEC) 134.

A page address decoding block (PGDEC) 150 is used to provide decoding of addresses A<9:10>. The outputs of block (PGDEC) 150 couple to blocks (PSEL) 120. A byte address decoding block (BYTEDEC) 152 is used to provide decoding of addresses A<0:8>. The outputs of block (BYTEDEC) 152 couple to blocks (BYTESEL) 140. An address counter block (ADDRCTR) 162 provides addresses A<11:AN>, A<9:10>, and A<0:8> for row, page, and byte addresses, respectively. The outputs of the block (ADDRCTR) 162 couple to blocks (XPREDEC) 154, (XCGCLPRED) 156, (PGDEC) 150, and (BYTEDEC) 152. The inputs of the block (ADDRCTR) 162 are coupled from the outputs of an input interface logic block (INPUTLOGIC) 160.

The input interface logic block (INPUTLOGIC) 160 is used to provide external interface to systems off-chip such as the microcontroller 2001. Typical external interface for memory operation are read, write, erase, status read, identification (ID) read, ready busy status, reset, and other general purpose tasks. Serial interface can be used for the input interface to reduce pin counts for high-density chip due to a large number of addresses. Control signals 196L are used to couple the INPUTLOGIC 160 to the system microcontroller 2001. The INPUTLOGIC 160 includes a status register that is indicative of the status of the memory chip operation such as pass or fail in program or erase, ready or busy, write protected or unprotected, cell margin good or bad, restore or no restore, etc. The margin and restore concepts are described more in detail in the multilevel algorithm description.

An algorithm controller block (ALGOCNTRL) 164 is used to handshake the input commands from the block (INPUTLOGIC) 160 and to execute the multilevel erase, programming and sensing algorithms as needed for multilevel nonvolatile operation. The ALGOCNTRL 164 is also used to algorithmically control the precise bias and timing conditions as required for multilevel precision programming.

A test logic block (TESTLOGIC) 180 is used to test various electrical features of the digital circuits, analog circuits, memory circuits, high voltage circuits, and memory array. The inputs of the block (TESTLOGIC) 180 are coupled from the outputs of the INPUTLOGIC 160. The block (TESTLOGIC) 180 also provides timing speed-up in production testing such as faster write/read and mass modes. The TESTLOGIC 180 is also used to provide screening tests associated with memory technology such as various disturb and reliability tests. The TESTLOGIC 180 also allows an off-chip memory tester to directly take over the control of various on-chip logic and circuit bias blocks to provide various external voltages and currents and external timing. This feature permits, for example, screening with external voltage and external timing or permits accelerated production testing with fast external timing.

A fuse circuit block (FUSECKT) 182 is a set of nonvolatile memory cells configured at the external system level, at the tester, at the user, or on chip on-the-fly to achieve various settings. These settings can include precision bias levels, precision on-chip oscillator, programmable logic features such as write-lockout feature for portions of an array, redundancy fuses, multilevel erase, program and read algorithm parameters, or chip performance parameters such as write or read speed and accuracy.

A reference control circuit block (REFCNTRL) 184 is used to provide precision reference levels for precision voltage levels as required for multilevel programming and sensing.

A redundancy controller block (REDCNTRL) 186 is for redundancy control logic.

A voltage algorithm controller block (VALGGEN) 176 provides various specifically shaped voltage signals of amplitude and duration as required for multilevel nonvolatile operation and to provide precise voltage levels with tight tolerance, as required for precision multilevel programming, erasing, and sensing.

A circuit block (BGAP) 170 is a bandgap voltage generator based on the bandgap circuit principle to provide a precise voltage level over process, temperature, and supply as required for multilevel programming and sensing.

A voltage and current bias generator block (V&IREF) 172 is an on-chip programmable bias generator. The bias levels are programmable by the settings of the control signals from the FUSECKT 182 and also by various metal options. A precision oscillator block (PRECISIONOSC) 174 provides accurate timing as required for multilevel programming and sensing.

Input buffer blocks 196 are typical input buffer circuits, for example, TTL input buffers or CMOS input buffers. Input/output (io) buffer blocks 194 includes typical input buffers and typical output buffers. A typical output buffer is, for example, an output buffer with slew rate control, or an output buffer with level feedback control. A circuit block 196R is an open drained output buffer and is used for ready busy handshake signal (R/BB) 196RB.

A voltage multiplier (also known as charge pump) block (VMULCKT) 190 provides voltage levels above the external power supply required for erase, program, read, and production tests. A voltage multiplying regulator block (VMULREG) 192 provides regulation for the block (VMULCKT) 190 for power efficiency and for transistor reliability such as to avoid various breakdown mechanisms.

A flash power management block (FPMU) 198 is used to efficiently manage power on-chip such as powering up only the circuit blocks in use. The FPMU 198 also provides isolation between sensitive circuit blocks from the less sensitive circuit blocks by using different regulators for digital power (VDDD) 1032/(VSSD) 1033, analog power (VDDA) 1030/(VSSA) 1031, and IO buffer power (VDDIO) 1034/(VSSIO) 1035. The FPMU 198 also provides better process reliability by stepping down power supply VDD to lower levels required by transistor oxide thickness. The FPMU 198 allows the regulation to be optimized for each circuit type. For example, an open loop regulation could be used for digital power since highly accurate regulation is not required; and a closed loop regulation could be used for analog power since analog precision is normally required. The flash power management also enables creation of a "green" memory system since power is efficiently managed.

Block diagram of the FPMU 198 is shown in FIG. 2B. A VDD 1111 and a VSS 1000 are externally applied power supply and ground lines, respectively. A block (ANALOG POWER REGULATOR) 198A is an analog power supply regulator, which uses closed loop regulation. The closed loop regulation is provided by negative feedback action of an operational amplifier (op amp) 1003 configured in a voltage buffer mode with a reference voltage (VREF1) 1002 on the positive input of the op amp 1003. A filter capacitor (CFILL) 1004 is used for smoothing transient response of the analog power (VDDA) 1030. A ground line (VSSA) 1031 is for analog power supply. A block (DIGITAL POWER REGULATOR) 198B is a digital power supply regulator, which uses open loop regulation. The open loop regulation is provided by source follower action of a transistor 1006 with a reference voltage (VREF2) 1005 on its gate. A pair of filter capacitor (CFIL4) 1009 and (CFIL2) 1007 are used for smoothing transient response of digital power (VDDD) 1032. A loading element (LOAD1) 1008 is for the transistor 1006. A ground line (VSSD) 1033 is for digital power supply. A block (IO POWER REGULATOR) 198C is an IO power supply regulator, which uses open loop regulation similar to that of the digital power supply 198B. The open loop regulation is provided by a transistor 1011 with a reference voltage (VREF3) 1010 on its gate. A loading element (LOAD2) 1013 is for transistor 1011. A pair of capacitors (CFIL5) 1014 and (CFIL3) 1012 are used for smoothing transient response of IO power (VDDIO) 1034. A ground line (VSSIO) 1035 is for IO power supply. A block 198D includes various circuits that require unregulated power supply such as transmission switches, high voltage circuits, ESD structures, and the like.

A block (PORK) 1040 is a power on reset circuit which provides a logic signal (PON) 1041 indicating that the power supply being applied to the chip is higher than a certain voltage. The signal (PON) 1041 is typically used to initialize logic circuits before chip operation begins.

A block (VDDDET) 1050 is a power supply detection circuit, which provides a logic signal (VDDON) 1051 indicating that the operating power supply is higher than a certain voltage. The block (VDDDET) 1050 is normally used to detect whether the power supply is stable to allow the chip to take certain actions such as stopping the programming if the power supply is too low.

A block (FPMUCNTRL) 1060 is a power supply logic controller, that receives control signals from blocks (PORK) 104, (VDDDET) 1050, (INPUTLOGIC) 160, (ALGOCNTRL) 164, and other logic control blocks to power up and power down appropriately power supplies and circuit blocks. The FPMUCNTRL 1060 is also used to reduce the power drive ability of appropriate circuit blocks to save power. A line (PDDEEP) 1021 is used to power down all regulators. Lines (PDAPOW) 1020, (PDDPOW) 1022, and (PDIOPOW) 1023 are used to power down blocks 198A, 198B, and 198C, respectively. Lines (PDDEEP) 1021, (PDAPOW) 1020, (PDDPOW) 1022, and (PDIOPOW) 1023 come from block (FPMUCNTRL) 1060.

It is possible that either closed or open loop regulation could be used for any type of power supply regulation. It is also possible that any power supply could couple directly to the applied power supply (VDD) 1111 without any regulation with appropriate consideration. For example, VDDA 1030 or VDDIO 1034 could couple directly to VDD 1111 if high voltage transistors with thick enough oxide are used for analog circuits or IO buffer circuits, respectively.

A typical memory system operation is as follows: a host such as the microcontroller 2001 sends an instruction, also referred to as a command, such as a program instruction via the CONTROL SIGNALS 196L and the IO BUS 194L to the multilevel memory chip 2000 (see FIG. 1C). The INPUTLOGIC 160 interprets the incoming command as a valid command and initiates the program operation internally. The ALGOCNTRL 164 receives the instruction from the INPUTLOGIC 160 to initiate the multilevel programming algorithmic action by outputting various control signals for the chip. A handshake signal such as the ready busy signal R/BB 196RB then signals to the microcontroller 2001 that the multilevel memory chip 2000 is internally operating. The microcontroller 2001 is now free to do other tasks until the handshake signal R/BB 196RB signals again that the multilevel memory chip 2000 is ready to receive the next command. A timeout could also be specified to allow the microcontroller 2001 to send the commands in appropriate times.

Read Operation:

A read command including a read operational code and addresses is sent by the microcontroller 2001 via the CONTROL SIGNALS 196L and 10 BUS 194L. The INPUTLOGIC 160 decodes and validates the read command. If it is valid, then incoming addresses are latched in the ADDRCTR 162. The ready busy signal (R/BB) 196RB now goes low to indicate that the multilevel memory device 2000 has begun read operation internally. The outputs of ADDRCTR 162 couple to blocks (XPREDEC) 154, (XCGCLPRED) 156, (PGDEC) 150, (BYTEDEC) 152, and (REDCNTRL) 186. The outputs of blocks 154, 156, 150, 152, and 186 couple to blocks (MLMDEC) 130, (MLSMDEC) 134, and block 100 to enable appropriate memory cells. Then the ALGOCNTRL 164 executes a read algorithm. The read algorithm will be described in detail later in the multilevel algorithm description. The read algorithm enables blocks (BGAP) 170, (V&IREF) 172, (PRECISIONOSC) 174, (VALGGEN) 176, and (REFCNTRL) 184 to output various precision shaped voltage and current bias levels and algorithmic read timing for read operation, which will be described in detail later in the description of the multilevel array architecture. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) 130, (MLMSDEC) 134, and block 100.

In an embodiment, the read algorithm operates upon one selected page of memory cells at a time to speed up the read data rate. A page includes a plurality of memory cells, e.g., 1024 cells. The number of memory cells within a page can be made programmable by fuses, e.g., 512 or 1024 to optimize power consumption and data rate. Blocks (PGDEC) 150, (MLMDEC) 130, (MLMSDEC) 134, 100, and (PSEL) 120 select a page. All memory cells in the selected page are put in read operating bias condition through blocks (MLMDEC) 130, (MLMSDEC) 134, 100, (PSEL) 120, and (XCGCLPRED) 156. After the readout voltage levels are stable, a read transfer cycle is initiated by the block (ALGOCNTRL) 164. All the readout voltages from the memory cells in the selected page are then available at the y-drivers (YDRVS) 110S, (RYDRVS) 112S, and (SYDRVS) 114S inside block (YDRV) 110, (RYDRV) 112, and (SYDRV) 114, respectively.

Next, in the read transfer cycle the ALGOCNTR 164 executes a multilevel read algorithm to extract the binary data out of the multilevel cells and latches them inside the YDRVS 110S, RYDRVS 112S, and SYDRVS 114S. This finishes the read transfer cycle. A restore flag is now set or reset in the status register inside the INPUTLOGIC 160. The restore flag indicates whether the voltage levels of the multilevel memory cells being read have been changed and whether they need to be restored to the original voltage levels. The restore concept will be described more in detail in the multilevel algorithm description. Now the ready busy signal (R/BB) 196RB goes high to indicate that the internal read operation is completed and the multilevel memory device 2000 is ready to transfer out the data or chip status. The microcontroller 2001 now can execute a status read command to monitor the restore flag or execute a data out sequence. The data out sequence begins with an external read data clock provided by the microcontroller 2001 via the CONTROL SIGNAL 196L coupled to an input buffer 196 to transfer the data out. The external read data clock couples to the blocks (BYTEDEC) 152 and (BYTESEL) 140, 142, and 144 to enable the outputs of the latches inside blocks (YDRV) 110 or (RYDRV) 112 or (SYDRV) 114 to output one byte of data at a time into the bus IO<0:7> 1001. The external read data clock keeps clocking until all the desired bytes of the selected page are outputted. The data on bus IO<0:7> 1001 is coupled to the microcontroller 2001 via IO BUS 194L through IO buffers 194.

Program Operation:

A program command including a program operational code, addresses, and data is sent by the microcontroller 2001 via CONTROL SIGNALS 196L and IO BUS 194L. The INPUTLOGIC 160 decodes and validates the command. If it is valid, then incoming addresses are latched in the ADDRCTR 162. The data is latched in the latches inside YDRV 110, RYDRV 112, and SYDRV 114 via blocks (BYTEDEC) 152, (BYTESEL) 140, 142, and 144, respectively. The ready busy signal (R/BB) 196RB now goes low to indicate that the memory device has begun program operation internally. The outputs of ADDRCTR 162 couple to blocks (XPREDEC) 154, (XCGCLPRED) 156, (PGDEC) 150, (BYTEDEC) 152, and (REDCNTRL) 186. The outputs of blocks 154, 156, 150, 152, and 186 couple to blocks (MLMDEC) 130, (MLSMDEC) 134, and 100 to enable appropriate memory cells. Then the (ALGOCNTRL) 164 executes a program algorithm, which will be described in detail later in the multilevel algorithm description. The (ALGOCNTRL) 164 enables blocks (BGAP) 170, (V&IREF) 172, (PRECISIONOSC) 174, (VALGGEN) 176, and (REFCNTRL) 184 to output various precision shaped voltage and current bias levels and algorithmic program timing for the program operation, which will be described in detail later in the description of the multilevel array architecture. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) 130, (MLMSDEC) 134, and block 100.

In an embodiment, the program algorithm operates upon one selected page of memory cells at a time to speed up the program data rate. Blocks (PGDEC) 150, (MLMDEC) 130, (MLMSDEC) 134, 100, and (PSEL) 120 select a page. All memory cells in the selected page are put in appropriate program operating bias condition through blocks (MLMDEC) 130, (MLMSDEC) 134, 100, (PSEL) 120, and (XCGCLPRED) 156. Once the program algorithm finishes, program flags are set in the status register inside the block (INPUTLOGIC) 160 to indicate whether the program has been successful. That is, all the cells in the selected page have been programmed correctly without failure and with enough voltage margins. The program flags are described more in detail in the multilevel algorithm description. Now the ready busy signal (R/BB) 196RB goes high to indicate that the internal program operation is completed and the memory device is ready to receive the next command.

Erase Operation:

An erase command including an erase operational code and addresses is sent by the microcontroller 2001 via CONTROL SIGNALS 196L and IO BUS 194L. The INPUTLOGIC 160 decodes and validates the command. If it is valid, then incoming addresses are latched in the ADDRCTR 162. The ready busy signal (R/BB) 196RB now goes low to indicate that the memory device has begun erase operation internally. The outputs of ADDRCTR 162 couple to blocks (XPREDEC) 154, (XCGCLPRED) 156, (PGDEC) 150, (BYTEDEC) 152, and (REDCNTRL) 186. The outputs of blocks 154, 156, 150, 152, and 186 couple to blocks (MLMDEC) 130, (MLSMDEC) 134, and 100 to enable appropriate memory cells. Then the ALGOCNTRL 164 executes an erase algorithm. The ALGOCNTRL 164 enables blocks (BGAP) 170, (V&IREF) 172, (PRECISIONOSC) 174, (VALGGEN) 176, and (REFCNTRL) 184 to output various precision shaped voltage and current bias levels and algorithmic erase timing for erase operation. The shaped voltage for erase is to minimize electric field coupled to memory cells, which minimizes the damage to memory cells during erasing. The precision bias levels are coupled to the memory cells through blocks (MLMDEC) 130, (MLMSDEC) 134, and block 100.

In an embodiment, the erase algorithm operates upon one selected erase block of memory cells at a time to speed up the erase time. An erase block includes a plurality of pages of memory cells, e.g., 32 pages. The number of pages within an erase block can be made programmable by fuses to suit different user requirements and applications. Blocks (PGDEC) 150, (MLMDEC) 130, (MLMSDEC) 134, 100, and (PSEL) 120 select a block. All memory cells in the selected block are put in erase operating bias condition through blocks (MLMDEC) 130, (MLMSDEC) 134, 100, (PSEL) 120, and (XCGCLPRED) 156. Once the erase algorithm finishes, the erase flags are set in the status register inside the block (INPUTLOGIC) 160 to indicate whether the erase has been successful. That is, all the cells in the selected page have been erased correctly to desired voltage levels without failure and with enough voltage margins. Now the ready busy signal (R/BB) 196RB goes high to indicate that the internal erase operation is completed and the multilevel memory device 2000 is r