Self-aligned V0-contact for cell size reduction Number:7,061,035 from the United States Patent and Trademark Office (PTO) owispatent An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.<H reduction, contact, Self, aligned, V0, 7061035.html, Patent, pto, 7061035

Title: Self-aligned V0-contact for cell size reduction

Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Patent Number: 7,061,035 Issued on 06/13/2006 to Lian, et al.

Inventors: Lian; Jingyu (Wallkill, NY); Nagel; Nicolas (Kanagawa-ken, JP); Gernhardt; Stefan (Kanagawa-ken, JP); Bruchhaus; Rainer (Kanagawa-ken, JP); Hilliger; Andreas (Kanagawa-ken, JP); Wellhausen; Uwe (Dresden, DE)
Assignee: Infineon Technologies AG (Munich, DE)

Appl. No.: 677852

Filed: October 1, 2003

Current U.S. Class: 257/295 ; 257/296; 257/310

Current International Class: H01L 29/94 (20060101)

Field of Search: 257/295,296,306,310

References Cited [Referenced By]

U.S. Patent Documents


5543644	August 1996	Abt et al.
6051858	April 2000	Uchida et al.
6249014	June 2001	Bailey
6423592	July 2002	Sun
6717197	April 2004	An
6720600	April 2004	Okita
6746878	June 2004	Komuro et al.
6809360	October 2004	Kato
2001/0044205	November 2001	Gilbert et al.
2003/0006439	January 2003	Bailey
2003/0124791	July 2003	Summerfelt et al.
2003/0146460	August 2003	Zambrano et al.
2003/0155595	August 2003	Okita

Primary Examiner: Richards; N. Drew
Attorney, Agent or Firm: Fish & Richardson P.C.

Claims

We claim:

1. An FeRAM comprising: a ferroelectric material sandwiched between a top electrode and a bottom electrode; a V0-contact for providing an electrical connection with an underlying CS-contact, the V0-contact being formed in a hole and being aligned by the bottom electrode; a liner layer covering a sidewall of the bottom electrode for providing a atop to an etch of the V0-contact hole; and an alumina spacer deposited on the walls of the V0-contact hole following etching of the hole so that the alumina spacer extends over substantially the entire walls of the V0-contact hole.

Description

FIELD OF THE INVENTION

The present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.

BACKGROUND OF THE INVENTION

V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. In prior art FeRAM memories, in order to simplify process development, a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.

FIG. 1 shows a top view of a conventional layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 110. There is a huge space between the V0-mask 101 and the masks 103, 105, 107.

FIG. 2 shows a cross-sectional view of the conventional layout of an FeRAM memory chip 200. A cover layer 201 (solid line) is over a BE-mask 107 (the cover layer can be A1.sub.2O.sub.3, for example). The TE 207 and a bottom electrode BE 209 sandwich a PZT ferroelectric layer 211 forming a ferroelectric capacitor 213 of a capacitor stack 223 of the FeRAM memory chip 200. An encapsulation layer 216 (solid line) is deposited onto the TE 207 prior to depositing the TE-mask 105. An encapsulation layer 215 (solid line) covers the ferroelectric capacitor 213. The cover layer 201 and encapsulation layers 215, 216 help protect the ferroelectric capacitor 213 from damage.

A TW-contact 205 extends through the cover layer 201, TF-mask 105, and the encapsulation layers 215, 216, to provide an electrical connection to a top electrode TE 207.

A CS-contact 223 provides a contact to the source/drain of a CMOS device. A V0-contact 221 passes though a dielectric covering 222 and connects electrically to the CS-contact 223. As can be seen, there is a huge space between the V0-contact 221 and a capacitor stack contact 223, making the memory chip 200 large. In the prior art, despite the cover and encapsulation layers, this huge space has been necessary to prevent short circuits and capacitor damage.

It would be desirable to reduce the size of the memory cell and overall FeRAM chip without the resulting short circuits or capacitor damage.

SUMMARY OF THE INVENTION

The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

BRIEF DESCRIPTION OF THE FIGURES

Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which:

FIG. 1 shows a top view of a conventional layout of a V0-mask, TW-mask, TE-mask and BE-mask of a FeRAM memory chip mask.

FIG. 2 shows a cross-sectional view of a conventional layout of an FeRAM memory chip.

FIG. 3 shows a top view of a layout of a V0-mask, TW-mask, TE-mask and BE-mask of an FeRAM memory chip mask of the present invention.

FIG. 4 shows a crossesectional view of the layout of an FeRAM memory chip of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.

FIG. 3 shows a top view of a layout of a V0-mask 101, TW-mask 103, TE-mask 105 and BE-mask 107 of a FeRAM memory chip mask 301 of the present invention. As can been seen, in the present invention the huge space between the V0-mask 101 and the masks 103, 105, 107 has been eliminated.

FIG. 4 shows a cross-sectional view of the layout of an FeRAM memory chip 400 of the present invention. To improve the protection for the ferroelectric capacitor 213, a high quality single layer or multi-layer cover is used for an encapsulation layer 415 and a cover layer 403 illustrated in FIG. 4.

The process flow is as follows:

a) Encapsulation of the capacitor 213 is performed as early and as is well as possible. One encapsulation layer 216 (solid line) is deposited over the TE 207 before depositing the TE-mask so that it is under the TE-mask, and the encapsulation layer 415 is deposited before depositing the BE-mask 107 so that it is under the BE-mask 107 as is currently done. The TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).

b) The BE-electrode 209 is then etched as steeply as possible and the cover layer 403 is deposited. Next the dielectric layer 222 is applied. To protect the capacitor and bottom electrode during the etching of the hole for a VO-contact 405 through the layer 222, the cover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on the cover layer 403. Then, an alumina spacer 4000 is deposited on the side walls of the hole. Due to the effect of the spacer, the cover layer 403 remains intact on BE-sidewalls 407. The result is almost vertical BE sidewalls 407, good step coverage for the ALD-deposition of Alumina inside the VO-contact hole 405, highly selective etch of the hole for the VO-contact 4085, and no `noses" ("noses" means that the sidewalls of the VO-contact hole 405 are smooth), thus providing a good Alumina spacer 4000 deposited on the walls of the VO-contact hole 405.

c) A break-through etch is next used to clean the bottom of the V0-contact 405 and creates an electrical contact with the CS-contact 223 underneath.

This process can be used even when the TE 207 and BE 209 are etched together.

This process also works well with dry etching techniques.

Still other materials and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.

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