Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions Number:6,773,989 from the United States Patent and Trademark Office (PTO) owispatent A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.<H semiconductor, protruding, Self, aligned, me, 6773989.html, Patent, pto, 6773989

Title: Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.

Patent Number: 6,773,989 Issued on 08/10/2004 to Wang

Inventors: Wang; Chih Hsin (San Jose, CA)
Assignee: Silicon Storage Technology, Inc. (Sunnyvale, CA)

Appl. No.: 10/356,783

Filed: January 30, 2003

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
917023	Jul., 2001	6627946

Current U.S. Class: 438/257 ; 257/E21.682; 257/E27.103; 257/E29.129; 438/264; 438/267; 438/593; 438/594

Current International Class: H01L 27/115 (20060101); H01L 29/423 (20060101); H01L 21/70 (20060101); H01L 29/40 (20060101); H01L 21/8247 (20060101)

Field of Search: 438/257,264,267,593,594,597

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Other References

US. patent application Ser. No. 09/401,622, Johnson, filed Sep. 22, 1999..

Primary Examiner: Quach; T. N.
Attorney, Agent or Firm: Gray Cary Ware & Freidenrich LLP

Parent Case Text

PRIORITY

This application is a Divisional of 09/917,023 filed Jan. 26, 2001 now U.S. Pat. No. 6,627,946 which claims the benefit of U.S. Provisional Application No. 60/234,314, filed Sep. 20, 2000, and entitled Super Self-Aligned Flash EEPROM Cell, and U.S. Provisional Application No. 60/233,988, filed Sep. 20, 2000, and entitled Super Self-Aligned Flash EEPROM Cell, and U.S. Provisional Application No. 60/242,096, filed Oct. 19, 2000, and entitled Ultra Self-Aligned Flash EEPROM Cell With SAC, U.S. Provisional Application No. 60/275,517, filed Mar. 12, 2001, and entitled Super Self-Aligned Flash E2PROM Cell, and U.S. Provisional Application No. 60/287,047, filed Apr. 26, 2001, and entitled An Ultra Self-Aligned Flash E2PROM Cell With Low Source Resistance and High Source Coupling.

Claims

What is claimed is:

1. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having an upper portion and a lower portion wherein the upper portion has a greater width than that of the lower portion; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the wider upper portion of the first trench that is disposed over the second layer of insulation material and the first layer of conductive material; e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

2. The method of claim 1, wherein a lower portion of each block is disposed adjacent to the first conductive layer and is insulated therefrom by the second insulation layer.

3. The method of claim 1, wherein the formation of the second layer of insulation material includes forming insulation material on side walls of the first trenches and forming insulation material on an upper surface of the first layer of conductive material.

4. The method of claim 1, further comprising the steps of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, each of the second trenches being formed between selected pairs of the blocks and extending through the first layer of conductive material and the first layer of insulation material to expose the second terminal; forming a third layer of insulation material along side walls of the second trenches; filing each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

5. The method of claim 1, wherein each of the blocks forms a control gate having a notch underneath the protruding portion.

6. The method of claim 1, wherein the formation of the first trenches comprises the steps of: forming at least one layer of material over the first layer of conductive material, selectively etching through the at least one layer of material to form the top portions of the first trenches; forming side wall spacers on side walls of each of the first trenches; etching between the side wall spacers in each of the first trenches and through the first layer of conductive material to form the bottom portions of the first trenches; and removing the side wall spacers from each of the first trenches; wherein the bottom portions of the first trenches have a smaller width than that of the top portions of the first trenches.

7. The method of claim 1, further comprising the step of: forming a layer of metalized silicon on each of the blocks of second conductive material.

8. The method of claim 1, wherein: the formation of the first trenches includes the formation of intermediate trenches between selected pairs of the first trenches across the active regions and isolation regions, the intermediate trenches are substantially parallel to one another and extend in the second direction; and the filling of the first trenches includes the filling of the intermediate trenches with the second conductive material to form blocks of the second conductive material in the intermediate trenches.

9. The method of claim 8, further comprising the step of forming a layer of metalized silicon on each of the blocks of second conductive material.

10. The method of claim 8, further comprising the steps of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, the second trenches being formed by removing the second conductive material in the intermediate trenches, and extending the intermediate trenches through the first layer of conductive material and the first layer of insulation material to expose the second terminal; forming a third layer of insulation material along side walls of the second trenches; filling each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

11. The method of claim 1, further comprising the steps of: forming a side wall spacer of insulating material along a side wall of each of the blocks of conductive material; and forming a layer of metalized silicon on each of the first terminals immediately adjacent to one of the side wall spacers, wherein each of the layers of metalized silicon is self-aligned to the one of the side wall spacers.

12. The method of claim 11, further comprising the steps of: forming a layer of metalized silicon on each of the blocks of second conductive material, wherein for each of the first trenches, a side wall of the first trench aligns an edge of the metalized silicon to an edge of the block of second conductive material; and forming a third layer of insulation material over the layer of metalized silicon, wherein for each of the first trenches, the side wall of the first trench aligns an edge of the third layer of insulation material to the edge of the metalized silicon and to the edge of the block of second conductive material.

13. The method of claim 11, further comprising the step of: forming a conductive material over each of the layers of metalized silicon and against the side wall spacer self aligned thereto.

14. The method of claim 11, wherein the formation of each of the side wall spacers includes forming a layer of insulation material between the side wall spacer and the side wall of the block of conductive material.

15. The method of claim 1, further comprising the steps of: forming a second side wall spacer of insulating material along a side wall of each of the blocks of conductive material such that pairs of the second side wall spacers are adjacent to but spaced apart from each other with one of the first terminals substantially therebetween; forming a layer of metalized silicon on each one of the first terminals between a pair of the second side wall spacers corresponding to the one first terminal such that the layer of metalized silicon is self-aligned to the one first terminal by the corresponding pair of second side wall spacers; forming a layer of passivation material over the active regions; forming contact openings through the passivation material, wherein for each of the contact openings: the contact opening extends down to and exposes one of the metalized silicon layers, the contact opening has a lower portion bounded by the corresponding pair of second side wall spacers, and the contact opening has an upper portion that is wider than a spacing between the corresponding pair of second side wall spacers; and filling each of the contact openings with a conductive material.

16. The method of claim 1, further comprising the step of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, each of the second trenches being formed adjacent to one of the blocks of second conductive material and exposing a portion of the first layer of conductive material.

17. The method of claim 16, further comprising the steps of: forming a third layer of insulation material along side walls of the second trenches; forming a lens shaped oxide layer on the exposed portion of the first layer of conductive material in each of the second trenches.

18. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having a side wall with an indentation formed therein; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the indentation in the first trench side wall that is disposed over the second layer of insulation material and the first layer of conductive material; e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

19. The method of claim 18, wherein a lower portion of each block is adjacent the first conductive layer and is insulated therefrom by the second insulation layer.

20. The method of claim 18, wherein the formation of the second layer of insulation material includes forming insulation material on side walls of the first trenches and forming insulation material on an upper surface of the first layer of conductive material.

21. The method of claim 18, further comprising the steps of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, each of the second trenches being formed between selected pairs of the blocks and extending through the first layer of conductive material and the first layer of insulation material to expose the second terminal; forming a third layer of insulation material along side walls of the second trenches; filling each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

22. The method of claim 18, wherein each of the blocks forms a control gate having a notch underneath the protruding portion.

23. The method of claim 18, wherein the formation of the first trenches comprises the steps of: forming at least one layer of material over the first layer of conductive material, selectively etching through the at least one layer of material to form top portions of the first trenches; forming side wall spacers on side walls of each of the first trenches; etching between the side wall spacers in each of the first trenches and through the first layer of conductive material to form bottom portions of the first trenches; and removing the side wall spacers from each of the first trenches; wherein the bottom portions of the first trenches have a smaller width than that of the top portions of the first trenches.

24. The method of claim 18, further comprising the step of: forming a layer of metalized silicon on each of the blocks of second conductive material.

25. The method of claim 18, wherein: the formation of the first trenches includes the formation of intermediate trenches between selected pairs of the first trenches across the active regions and isolation regions, the intermediate trenches are substantially parallel to one another and extend in the second direction; and the filling of the first trenches includes the filling of the intermediate trenches with the second conductive material to form blocks of the second conductive material in the intermediate trenches.

26. The method of claim 25, further comprising the step of forming a layer of metalized silicon on each of the blocks of second conductive material.

27. The method of claim 25, further comprising the steps of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, the second trenches being formed by removing the second conductive material in the intermediate trenches, and extending the intermediate trenches through the first layer of conductive material and the first layer of insulation material to expose the second terminal; forming a third layer of insulation material along side walls of the second trenches; filling each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

28. The method of claim 18, further comprising the steps of: forming a side wall spacer of insulating material along a side wall of each of the blocks of conductive material; and forming a layer of metalized silicon on each of the first terminals immediately adjacent to one of the side wall spacers, wherein each of the layers of metalized silicon is self-aligned to the one of the side wall spacers.

29. The method of claim 28, further comprising the steps of: forming a layer of metalized silicon on each of the blocks of second conductive material, wherein for each of the first trenches, a side wall of the first trench aligns an edge of the metalized silicon to an edge of the block of second conductive material; and forming a third layer of insulation material over the layer of metalized silicon, wherein for each of the first trenches, the side wall of the first trench aligns an edge of the third layer of insulation material to the edge of the metalized silicon and to the edge of the block of second conductive material.

30. The method of claim 28, further comprising the step of: forming a conductive material over each of the layers of metalized silicon and against the side wall spacer self aligned thereto.

31. The method of claim 28, wherein the formation of each of the side wall spacers includes forming a layer of insulation material between the side wall spacer and the side wall of the block of conductive material.

32. The method of claim 18, further comprising the steps of: forming a second side wall spacer of insulating material along a side wall of each of the blocks of conductive material such that pairs of the second side wall spacers are adjacent to but spaced apart from each other with one of the first terminals substantially therebetween; forming a layer of metalized silicon on each one of the first terminals between a pair of the second side wall spacers corresponding to the one first terminal such that the layer of metalized silicon is self-aligned to the one first terminal by the corresponding pair of second side wall spacers; forming a layer of passivation material over the active regions; forming contact openings through the passivation material, wherein for each of the contact openings: the contact opening extends down to and exposes one of the metalized silicon layers, the contact opening has a lower portion bounded by the corresponding pair of second side wall spacers, and the contact opening has an upper portion that is wider than a spacing between the corresponding pair of second side wall spacers; and filling each of the contact openings with a conductive material.

33. The method of claim 18, further comprising the step of: forming a plurality of spaced apart second trenches across the active regions and isolation regions which are substantially parallel to one another and extend in the second direction, each of the second trenches being formed adjacent to one of the blocks of second conductive material and exposing a portion of the first layer of conductive material.

34. The method of claim 33, further comprising the steps of: forming a third layer of insulation material along side walls of the second trenches; forming a lens shaped oxide layer on the exposed portion of the first layer of conductive material in each of the second trenches.

35. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) forming first side wall spacers of a material on side walls of the first trenches; e) forming a second side wall spacer of a material on each of the first side wall spacers; f) forming second trenches in each of the active regions, wherein each of the second trenches have a side wall that is immediately adjacent to one of the first side wall spacers; g) removing the first side wall spacers to form an indentation in each of the second trench side walls; h) filling each of the second trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the second trench side wall indentation that is disposed over the second layer of insulation material and the first layer of conductive material; i) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and j) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

36. The method of claim 35, wherein each of the first spacers is formed directly over the second layer of insulation material.

37. The method of claim 35, wherein each of the second spacers is formed directly over the second layer of insulation material.

38. The method of claim 35, wherein a lower portion of each block is disposed adjacent to the first conductive layer and is insulated therefrom by the second insulation layer.

39. The method of claim 35, wherein each of the blocks forms a control gate having a notch underneath the protruding portion.

40. The method of claim 35, wherein the formation of the second trenches includes exposing the first layer of the conductive material in each of the active regions.

41. The method of claim 40, wherein the formation of the second layer of insulation material includes forming insulation material on side walls of the second trenches and forming insulation material on an upper surface of the first layer of conductive material.

42. The method of claim 35, further comprising the steps of: forming a third layer of insulation material in each of the second trenches; filing each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

43. The method of claim 35, wherein the formation of the first trenches comprises the steps of: forming at least one layer of material over the first layer of conductive material, selectively etching through the at least one layer of material to form top portions of the first trenches, wherein the first and second spacers are then formed in the first trenches; etching between the second side wall spacers in each of the first trenches and through the first layer of conductive material to form bottom portions of the first trenches; and wherein the bottom portions of the first trenches have a smaller width than that of the top portions of the first trenches.

44. The method of claim 35, further comprising the steps of: forming a third side wall spacer of insulating material along a side wall of each of the blocks of conductive material; and forming a layer of metalized silicon on each of the second terminals immediately adjacent to one of the third side wall spacers, wherein each of the layers of metalized silicon is self-aligned to the one of the third side wall spacers.

45. The method of claim 44, further comprising the steps of: forming a layer of metalized silicon on each of the blocks of second conductive material, wherein for each of the second trenches, a side wall of the second trench aligns an edge of the metalized silicon to an edge of the block of second conductive material; forming a block of material adjacent to each of the blocks of second conductive material; and forming a third layer of insulation material over the layer of metalized silicon, wherein for each of the blocks of material, a side wall of the block of material aligns an edge of the third layer of insulation material to an edge of the metalized silicon and to an edge of the block of second conductive material.

46. The method of claim 44, further comprising the step of: forming a conductive material over each of the layers of metalized silicon and against the third side wall spacer self aligned thereto.

47. The method of claim 44, wherein the formation of each of the third side wall spacers includes forming a layer of insulation material between the third side wall spacer and the side wall of the block of conductive material.

48. The method of claim 35, further comprising the steps of: forming a third side wall spacer of insulating material along a side wall of each of the blocks of conductive material such that pairs of the third side wall spacers are adjacent to but spaced apart from each other with one of the first terminals substantially therebetween; forming a layer of metalized silicon on each one of the first terminals between a pair of the third side wall spacers corresponding to the one first terminal such that the layer of metalized silicon is self-aligned to the one first terminal by the corresponding pair of third side wall spacers; forming a layer of passivation material over the active regions; forming contact openings through the passivation material, wherein for each of the contact openings: the contact opening extends down to and exposes one of the metalized silicon layers, the contact opening has a lower portion bounded by the corresponding pair of third side wall spacers, and p2 the contact opening has an upper portion that is wider than a spacing between the corresponding pair of third side wall spacers; and filling each of the contact openings with a conductive material.

49. A self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate, the method comprising the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction, and forming a first layer of conductive material in each of the active regions adjacent to the first trenches and disposed over a first layer of insulation material; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) forming first side wall spacers of a material on side walls of the first trenches; e) forming a second side wall spacer of a material on each of the first side wall spacers; f) forming second trenches in each of the active regions, wherein each of the second trenches have a side wall that is immediately adjacent to one of the first side wall spacers; g) removing the first side wall spacers to form an indentation in each of the second trench side walls; h) filling each of the second trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the second trench side wall indentation that is disposed over the second layer of insulation material and the first layer of conductive material; i) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and j) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

50. The method of claim 49, wherein each of the first spacers is formed directly over the second layer of insulation material.

51. The method of claim 49, wherein each of the second spacers is formed directly over the second layer of insulation material.

52. The method of claim 49, wherein a lower portion of each block is disposed adjacent to the first conductive layer and is insulated therefrom by the second insulation layer.

53. The method of claim 49, wherein each of the blocks forms a control gate having a notch underneath the protruding portion.

54. The method of claim 49, wherein the formation of the second trenches includes exposing the first layer of the conductive material in each of the active regions.

55. The method of claim 54, wherein the formation of the second layer of insulation material includes forming insulation material on side walls of the second trenches and forming insulation material on an upper surface of the first layer of conductive material.

56. The method of claim 49, further comprising the steps of: forming a third layer of insulation material in each of the second trenches; filing each of the second trenches with a conductive material that is insulated from the first conductive layer by the third layer of insulation material.

57. The method of claim 49, wherein the formation of the first trenches comprises the steps of: forming at least one layer of material over the first layer of conductive material, selectively etching through the at least one layer of material to form top portions of the first trenches, wherein the first and second spacers are then formed in the first trenches; etching between the second side wall spacers in each of the first trenches and through the first layer of conductive material to form bottom portions of the first trenches; and wherein the bottom portions of the first trenches have a smaller width than that of the top portions of the first trenches.

58. The method of claim 49, further comprising the steps of: forming a third side wall spacer of insulating material along a side wall of each of the blocks of conductive material; and forming a layer of metalized silicon on each of the second terminals immediately adjacent to one of the third side wall spacers, wherein each of the layers of metalized silicon is self-aligned to the one of the third side wall spacers.

59. The method of claim 58, further comprising the steps of: forming a layer of metalized silicon on each of the blocks of second conductive material, wherein for each of the second trenches, a side wall of the second trench aligns an edge of the metalized silicon to an edge of the block of second conductive material; forming a block of material adjacent to each of the blocks of second conductive material; and forming a third layer of insulation material over the layer of metalized silicon, wherein for each of the blocks of material, a side wall of the block of material aligns an edge of the third layer of insulation material to an edge of the metalized silicon and to an edge of the block of second conductive material.

60. The method of claim 58, further comprising the step of: forming a conductive material over each of the layers of metalized silicon and against the third side wall spacer self aligned thereto.

61. The method of claim 58, wherein the formation of each of the third side wall spacers includes forming a layer of insulation material between the third side wall spacer and the side wall of the block of conductive material.

62. The method of claim 49, further comprising the steps of: forming a third side wall spacer of insulating material along a side wall of each of the blocks of conductive material such that pairs of the third side wall spacers are adjacent to but spaced apart from each other with one of the first terminals substantially therebetween; forming a layer of metalized silicon on each one of the first terminals between a pair of the third side wall spacers corresponding to the one first terminal such that the layer of metalized silicon is self-aligned to the one first terminal by the corresponding pair of third side wall spacers; forming a layer of passivation material over the active regions; forming contact openings through the passivation material, wherein for each of the contact openings: the contact opening extends down to and exposes one of the metalized silicon layers, the contact opening has a lower portion bounded by the corresponding pair of third side wall spacers, and the contact opening has an upper portion that is wider than a spacing between the corresponding pair of third side wall spacers; and filling each of the contact openings with a conductive material.

Description

TECHNICAL FIELD

The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type. The present invention also relates to a semiconductor memory array of floating gate memory cells of the foregoing type.

BACKGROUND OF THE INVENTION

Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.

One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.

Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.

In the split-gate architecture, the control-gate FET is known to play a major role in disturbing mirror cells, as well as affecting the programming injection efficiency for source-side-injection FLASH cells. A good process control on the Lcg (also called the WL (word-line) poly length, which is the length of the control or select gate that is disposed over the channel) can ensure a full turn-off of the control-gate device, and hence can effectively prevent any disturbance in a mirror cell during programming (program disturb). The present invention is a method to realize a self aligned FLASH cell with improved full turn-off of the control-gate device with better program disturb characteristics. The present invention is also such a device.

SUMMARY OF THE INVENTION

In the present invention, the WL (control/select gate) poly length is controlled by a photo lithography process, which provides excellent scalability and control over the WL poly length as compared to a WL poly formed by a spacer process. Since the tight control on the photo process is a by-product of logic technology, the present invention thus offers a better control on WL poly length, and hence a better suppression of program disturb in mirror cells. An additional advantage of the present invention is that it allows the formation of cells with different WL poly lengths on the same wafer.

The present invention also results in the formation of the WL poly having a substantially rectilinear shape or planar side wall portion, which makes it easier and more controllable to form the side wall spacer, and to address issues of WL-to-BL (Bit Line) & WL-to-source block shorts. Further, in the first embodiment of the present invention, the WL poly is defined by a WL trench rather than by a spacer etch. Thus, the memory cell is immune from WL-WL shorts due to isolation or trench oxide-to-active topography, and the WL poly has a flat surface which makes contact formation on the WL strap easier (no WL strap needed). The first embodiment further presents an advantage over prior art in that it enables to the option to perform "after development inspection" for critical dimension inspection, e.g. after the photo lithography definition of the WL dimension. If the control on the critical dimension WL is off target, the error can be detected and the wafer can be re-worked to correctly define this critical dimension.

The present invention is a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, where each memory cell has a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate. The method includes the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having an upper portion and a lower portion wherein the upper portion has a greater width than that of the lower portion; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the wider upper portion of the first trench that is disposed over the second layer of insulation material and the first layer of conductive material; e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

In another aspect of the present invention for the self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, the method includes the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having a side wall with an indentation formed therein; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the indentation in the first trench side wall that is disposed over the second layer of insulation material and the first layer of conductive material; e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.

In yet another aspect of the present invention, an electrically programmable and erasable memory device includes a substrate of semiconductor material of a first conductivity type, first and second spaced-apart terminals in the substrate of a second conductivity type with a channel region therebetween, a first insulation layer disposed over said substrate, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal, a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough, and an electrically conductive control gate having a first portion and a second portion, the first portion being substantially rectangularly shaped and positioned adjacent to the second insulation layer and the floating gate, the second portion being substantially rectangularly shaped and having a width that is greater than that of the first portion so that a portion of the second portion extends over a portion of the second insulation layer and a portion of the floating gate.

In yet one more aspect of the present invention, an array of electrically programmable and erasable memory devices includes a substrate of semiconductor material of a first conductivity type, and spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions. Each of the active regions includes a column of memory cells extending in the first direction, where each of the memory cells includes first and second spaced-apart regions formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween, a first insulation layer disposed over said substrate including over said channel region, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second region, and a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough. A plurality of electrically conductive control gates each extend across the active regions and isolation regions in a second direction substantially perpendicular to the first direction and having a first portion that is substantially rectangular in shape and a second portion that is substantially rectangular in shape, the second portion having a width that is greater than that of the first portion, wherein each of the control gates intercepts one of the memory cells in each of the active regions such that the first portion is positioned adjacent to the second insulation layer and the floating gate therein and the second portion partially extends over the second insulation layer and the floating gate.

In yet one additional aspect of the present invention, an electrically programmable and erasable memory device includes a substrate of semiconductor material of a first conductivity type, first and second spaced-apart terminals in the substrate of a second conductivity type, with a channel region therebetween, a first insulation layer disposed over said substrate, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal, a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and an electrically conductive control gate. The control gate includes a substantially planar side wall portion positioned adjacent to the second insulation layer and the floating gate, and a protruding portion that protrudes from the planar side wall portion to partially extend over the floating gate and is insulated therefrom.

In a further aspect of the present invention, an array of electrically programmable and erasable memory devices includes a substrate of semiconductor material of a first conductivity type, and spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions. Each of the active regions includes a column of memory cells extending in the first direction, where each of the memory cells includes first and second spaced-apart terminals formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween, a first insulation layer disposed over said substrate including over said channel region, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of said channel region and over a portion of the second terminal, and a second insulation layer disposed over and adjacent the floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough. A plurality of electrically conductive control gates each extend across the active regions and isolation regions in a second direction substantially perpendicular to the first direction. Each of the control gates includes a substantially planar side wall portion and a protruding portion that protrudes from the planar side wall portion, wherein each of the control gates intercepts one of the memory cells in each of the active regions such that the substantially planar side wall portion is positioned adjacent to the second insulation layer and the floating gate, and said protruding portion partially extends over the floating gate and is insulated therefrom.

Another aspect of the invention is a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, where each memory cell has a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate. The method includes the steps of: a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material; b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions; c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material; d) forming first side wall spacers of a material on side walls of the first trenches; e) forming a second side wall spacer of a material on each of the first side wall spacers; f) forming second trenches in each of the active regions, wherein each of the second trenches have a side wall that is immediately adjacent to one of the first side wall spacers; g) removing the first side wall spacers to form an indentation in each of the second trench side walls; h) filling each of the second trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region: the block is adjacent to the second layer of insulation material and is insulated from the substrate, and the block includes a protruding portion formed by the second trench side wall indentation that is disposed over the second layer of insulation material and the first layer of conductive material; i) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and j) forming a plurality of second terminals in the substrate, wherein in