Self-luminous device and electric machine using the same Number:7,142,781 from the United States Patent and Trademark Office (PTO) owispatent To provide a self-luminous device capable of clear, multi-gray scale, color display and an electric machine provided with the same. Gray scale display is attained by a time division driving method in which an EL element (109) provided in a pixel (104) is controlled to emit light or not to emit light by means of time, thereby avoiding being affected by fluctuation in characteristic in current controlling TFTs (108).<H electric, luminous, Self, luminous, d, 7142781.html, Patent, pto, 7142781

Title: Self-luminous device and electric machine using the same

Abstract: To provide a self-luminous device capable of clear, multi-gray scale, color display and an electric machine provided with the same. Gray scale display is attained by a time division driving method in which an EL element (109) provided in a pixel (104) is controlled to emit light or not to emit light by means of time, thereby avoiding being affected by fluctuation in characteristic in current controlling TFTs (108).

Patent Number: 7,142,781 Issued on 11/28/2006 to Koyama, et al.

Inventors: Koyama; Jun (Kanagawa, JP), Inukai; Kazutaka (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Atsugi, JP)

Appl. No.: 10/942,808

Filed: September 17, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
09835551	Apr., 2001	6936846

Foreign Application Priority Data


Apr 17, 2000 [JP]			2000-114592

Current U.S. Class: 396/109 ; 257/89; 313/489; 315/169.3; 396/110; 396/48

Current International Class: G03B 17/00 (20060101); G03B 13/00 (20060101); H01J 1/62 (20060101); H01J 13/56 (20060101); H01L 29/20 (20060101)

Field of Search: 396/109,110,48 257/99 313/489 315/169.3

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Other References

Tsutsui et al., "Electroluminescence in Organic Thin Films", Photochemical Processes in Organized Molecular Systems, 1991, pp. 437-450. cited by oth- er .
M. A. Baldo et al., "Highly Efficient Phosphorescent Emission from Organic Electroluminescent Devices", Nature vol. 395, Sep. 10, 1998, pp. 151-154. cited by other .
M. A. Baldo et al., "Very High-Efficiency Green Organic Light-Emitting Devices Based on Electrophosphorescence", Applied Physics Letters vol. 75, No. 1, Jul. 5, 1999, pp. 4-6. cited by other .
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Primary Examiner: Pham; Long
Assistant Examiner: Rao; Shrinivas H.
Attorney, Agent or Firm: Fish & Richardson P.C.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser. No. 09/835,551, filed Apr. 17, 2001 now U.S. Pat. No. 6,936,846, now allowed, which claims the benefit of a foreign priority application filed in Japan as Ser. No. 2000-114592 on Apr. 17, 2000. This application claims priority to each of the prior applications, and the disclosures of the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.

Claims

What is claimed is:

1. A camera having at least one self-light emitting device comprising: a first semiconductor island formed on an insulating surface, said first semiconductor island having at least first and second impurity regions and a channel region therebetween; second semiconductor island formed on said insulating surface, said second semiconductor island separated from said first semiconductor island; an insulating film formed on said first semiconductor island and said second semiconductor island; a gate electrode formed over said first semiconductor island with said insulating film interposed therebetween; a capacitor forming electrode formed over said second semiconductor island with said insulating film interposed therebetween, wherein said gate electrode and said capacitor forming electrode are formed in a same conductive layer and electrically connected to each other; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein one of said first and second impurity regions is electrically connected to one of said cathode and said anode.

2. The camera according to claim 1 wherein said camera is a video camera.

3. The camera according to claim 1 further comprising a switching thin film transistor having a drain region electrically connected to said gate electrode.

4. A camera having at least one self-light emitting device comprising: a first semiconductor island formed on an insulating surface, said first semiconductor island having at least first and second impurity regions and a channel region therebetween; a second semiconductor island formed on said insulating surface, said second semiconductor island separated from said first semiconductor island; an insulating film formed on said first semiconductor island and said second semiconductor island; a gate electrode formed over said first semiconductor island with said insulating film interposed therebetween; a capacitor forming electrode formed over said second semiconductor island with said insulating film interposed therebetween wherein said gate electrode and said capacitor forming electrode are formed in a same conductive layer and electrically connected to each other; a capacitor having said capacitor forming electrode and said second semiconductor island with said insulating film interposed therebetween; an interlayer insulating film formed over said capacitor forming electrode; a current supply line formed over said interlayer insulating film wherein said current supply line is electrically connected to one of said first and second impurity regions of the first semiconductor island; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode, wherein said second semiconductor island is covered by said current supply line.

5. The camera according to claim 4 wherein said camera is a video camera.

6. The camera according to claim 4 further comprising a switching thin film transistor having a drain region electrically connected to said gate electrode.

7. The camera according to claim 4 wherein said first and second semiconductor islands comprise crystalline silicon.

8. The camera according to claim 4 further comprising a driver circuit formed on said insulating surface, said driver circuit comprising thin film transistors having a crystalline channel region.

9. A camera having at least one self-light emitting device comprising: a gate wiring formed over a substrate; a first switching element formed over said substrate and including at least one first thin film transistor wherein a gate electrode of said first thin film transistor is electrically connected to said gate wiring; a source wiring extending across said gate wiring; a second switching element formed over said substrate and including at least one second thin film transistor, said second thin film transistor comprising a semiconductor island having at least first and second impurity regions and a channel region, a gate insulating film formed on said semiconductor island and a gate electrode formed on said gate insulating film, wherein said gate electrode is electrically connected to said source wiring through at least said first switching element; a current supply line extending across said gate wiring and electrically connected to one of said first and second impurity regions of the second thin film transistor; a capacitor electrically connected between said gate electrode of the second thin film transistor and said current supply line wherein said capacitor is covered by said current supply line; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode.

10. The camera according to claim 9 wherein said camera is a video camera.

11. The camera according to claim 9 wherein said semiconductor island comprises crystalline silicon.

12. The camera according to claim 9 further comprising a driver circuit formed over said substrate, said driver circuit comprising thin film transistors having a crystalline channel region.

13. A camera having at least one self-light emitting device comprising: a gate wiring formed over a substrate; a first switching element formed over said substrate and including at least one first thin film transistor wherein a gate electrode of said first thin film transistor is electrically connected to said gate wiring; a source wiring extending across said gate wiring; a second switching element formed over said substrate and including at least one second thin film transistor, said second thin film transistor comprising a semiconductor island having at least first and second impurity regions and a channel region, a gate insulating film formed on said semiconductor island and a gate electrode formed on said gate insulating film, wherein said gate electrode is electrically connected to said source wiring through at least said first switching element; a current supply line extending across said gate wiring and electrically connected to one of said first and second impurity regions of the second thin film transistor; a capacitor having a first electrode comprising a same material as said semiconductor island, a second electrode comprising a same material as the gate electrode of the second thin film transistor and electrically connected to said gate electrode of the second thin film transistor and an insulating film comprising a same material as said gate insulating film between said first and second gate electrodes wherein said capacitor is located below said current supply line; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode, wherein said first electrode is separated from said semiconductor island and is electrically connected to said current supply line.

14. The camera according to claim 13 wherein said camera is a video camera.

15. The camera according to claim 13 wherein said semiconductor island comprises crystalline silicon.

16. The camera according to claim 13 further comprising a driver circuit formed over said substrate, said driver circuit comprising thin film transistors having a crystalline channel region.

17. A computer having at least one self-light emitting device comprising: a first semiconductor island formed on an insulating surface, said first semiconductor island having at least first and second impurity regions and a channel region therebetween; a second semiconductor island formed on said insulating surface, said second semiconductor island separated from said first semiconductor island; an insulating film formed on said first semiconductor island and said second semiconductor island; a gate electrode formed over said first semiconductor island with said insulating film interposed therebetween; a capacitor forming electrode formed over said second semiconductor island with said insulating film interposed therebetween, wherein said gate electrode and said capacitor forming electrode are formed in a same conductive layer and electrically connected to each other; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein one of said first and second impurity regions is electrically connected to one of said cathode and said anode.

18. The computer according to claim 17 wherein said computer is selected from the group consisting of a personal computer and a mobile computer.

19. The computer according to claim 17 further comprising a switching thin film transistor having a drain region electrically connected to said gate electrode.

20. A computer having at least one self-light emitting device comprising: a first semiconductor island formed on an insulating surface, said first semiconductor island having at least first and second impurity regions and a channel region therebetween; a second semiconductor island formed on said insulating surface, said second semiconductor island separated from said first semiconductor island; an insulating film formed on said first semiconductor island and said second semiconductor island; a gate electrode formed over said first semiconductor island with said insulating film interposed therebetween; a capacitor forming electrode formed over said second semiconductor island with said insulating film interposed therebetween wherein said gate electrode and said capacitor forming electrode are formed in a same conductive layer and electrically connected to each other; a capacitor having said capacitor forming electrode and said second semiconductor island with said insulating film interposed therebetween; an interlayer insulating film formed over said capacitor forming electrode; a current supply line formed over said interlayer insulating film wherein said current supply line is electrically connected to one of said first and second impurity regions of the first semiconductor island; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode, wherein said second semiconductor island is covered by said current supply line.

21. The computer according to claim 20 wherein said computer is selected from the group consisting of a personal computer and a mobile computer.

22. The computer according to claim 20 further comprising a switching thin film transistor having a drain region electrically connected to said gate electrode.

23. The computer according to claim 20 wherein said first and second semiconductor islands comprise crystalline silicon.

24. The computer according to claim 20 further comprising a driver circuit formed on said insulating surface, said driver circuit comprising thin film transistors having a crystalline channel region.

25. A computer having at least one self-light emitting device comprising: a gate wiring formed over a substrate; a first switching element formed over said substrate and including at least one first thin film transistor wherein a gate electrode of said first thin film transistor is electrically connected to said gate wiring; a source wiring extending across said gate wiring; a second switching element formed over said substrate and including at least one second thin film transistor, said second thin film transistor comprising a semiconductor island having at least first and second impurity regions and a channel region, a gate insulating film formed on said semiconductor island and a gate electrode formed on said gate insulating film, wherein said gate electrode is electrically connected to said source wiring through at least said first switching element; a current supply line extending across said gate wiring and electrically connected to one of said first and second impurity regions of the second thin film transistor; a capacitor electrically connected between said gate electrode of the second thin film transistor and said current supply line wherein said capacitor is covered by said current supply line; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode.

26. The computer according to claim 25 wherein said computer is selected from the group consisting of a personal computer and a mobile computer.

27. The computer according to claim 25 wherein said semiconductor island comprises crystalline silicon.

28. The computer according to claim 25 further comprising a driver circuit formed over said substrate, said driver circuit comprising thin film transistors having a crystalline channel region.

29. A computer having at least one self-light emitting device comprising: a gate wiring formed over a substrate; a first switching element formed over said substrate and including at least one first thin film transistor wherein a gate electrode of said first thin film transistor is electrically connected to said gate wiring; a source wiring extending across said gate wiring; a second switching element formed over said substrate and including at least one second thin film transistor, said second thin film transistor comprising a semiconductor island having at least first and second impurity regions and a channel region, a gate insulating film formed on said semiconductor island and a gate electrode formed on said gate insulating film, wherein said gate electrode is electrically connected to said source wiring through at least said first switching element; a current supply line extending across said gate wiring and electrically connected to one of said first and second impurity regions of the second thin film transistor; a capacitor having a first electrode comprising a same material as said semiconductor island, a second electrode comprising a same material as the gate electrode of the second thin film transistor and electrically connected to said gate electrode of the second thin film transistor and an insulating film comprising a same material as said gate insulating film between said first and second gate electrodes wherein said capacitor is located below said current supply line; and a light emitting element comprising a cathode, an anode and a light emitting material interposed between said cathode and said anode wherein the other one of said first and second impurity regions is electrically connected to one of said cathode and said anode, wherein said first electrode is separated from said semiconductor island and is electrically connected to said current supply line.

30. The computer according to claim 29 wherein said computer is selected from the group consisting of a personal computer and a mobile computer.

31. The computer according to claim 29 wherein said semiconductor island comprises crystalline silicon.

32. The computer according to claim 3 further comprising a driver circuit formed over said substrate, said driver circuit comprising thin film transistors having a crystalline channel region.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a self-luminous device (or an EL display device) manufactured by forming a light emitting element (such as an EL (Electro Luminescence) element) on a substrate, and an electric machine having the self-luminous device as a display (display unit). The light emitting element here is also called an OLED (Organic Light Emitting Device).

The light emitting element has a layer containing an EL material that can provide EL (Electro Luminescence: the luminescence generated by applying an electric field) (hereinafter referred to as EL layer), in addition to an anode and a cathode. The luminescence generated from an EL material includes light emission (fluorescence) upon returning from the singlet excitation to the ground state and light emission (phosphorescence) upon returning from the triplet excitation to the ground state. The self-luminous device of the present invention can use both types of light emitting elements with one type containing fluorescent EL materials and the other type containing phosphorescent EL materials.

2. Description of the Related Art

The technology for forming a TFT on a substrate has made a great progress in recent years, and application of the thus formed TFT to an active matrix display device is being developed. In particular, a TFT formed of a polysilicon film has a field mobility (often abbreviated as mobility) higher than that of a conventional TFT that is formed of an amorphous silicon film, and hence is capable of operating at high speed.

An active matrix self-luminous device has a pixel structure generally as the one shown in FIG. 3. In FIG. 3, reference symbol 301 denotes a TFT functioning as a switching element (hereinafter referred to as switching TFT), 302, a TFT functioning as an element for controlling current supplied to an EL element 303 (current controlling element) (hereinafter referred to as current controlling TFT), and 304, a capacitor (storage capacitor). The switching TFT 301 is connected to a gate wiring 305 and a source wiring (data line) 306. The current controlling TFT 302 has a drain region connected to the EL element 303 and has a source region connected to a power supply line 307.

When the gate wiring 305 is selected, a gate of the switching TFT 301 is opened, a data signal from the source wiring 306 is stored in the capacitor 304, and a gate of the current controlling TFT 302 is opened. After the gate of the switching TFT 301 is closed, the gate of the current controlling TFT 302 is kept open due to the electric charges stored in the capacitor 304 and the EL element 303 emits light during the gate is opened. How much light is emitted from the EL element varies depending on the amount of current flowing therethrough.

In other words, in analog-driven gray scale display, the amount of light emitted from the EL element varies as a result of control over the amount of current flowing into the gate of the current controlling TFT 302 by means of a data signal inputted from the source wiring 306.

FIG. 4A is a graph showing a transistor characteristic of the current controlling TFT. Denoted by reference symbol 401 is a curve showing a so-called Id-Vg characteristic (also called Id-Vg curve), where Id represents drain current and Vg represents gate voltage. With this graph, one can tell how much current will flow at a given gate voltage.

When driving the EL element, the voltage within an area indicated by a dotted line 402 around the curve of the Id-Vg characteristic is usually used. The area enclosed by the line 402 is enlarged in FIG. 4B.

In FIG. 4B, the shaded area is called a sub-threshold region. The term actually denotes a region in which the gate voltage is about the same as a threshold voltage (V.sub.TH). When the gate voltage changes in this region, the drain current is changed exponentially. The current control is made by using the gate voltage of this region.

A data signal inputted in a pixel when the switching TFT 301 of FIG. 3 is opened is first stored in the capacitor 304, and the signal serves as the gate voltage for the current controlling TFT 302 without undergoing any change. At this point, the gate voltage determines the drain current in a 1:1 ratio in accordance with the Id-Vg characteristic shown in FIG. 4A. Thus a given amount of current flows in the EL element 303 in accordance with the data signal, and the EL element emits light in an amount corresponding to this given amount of current.

As described above, the amount of light emitted from the EL element is controlled by means of the inputted signal, and the control over the amount of light to be emitted provides gray scale display. This is a method so-called analog gray scale in which gray scale display is provided by variations in signal amplitude.

However, the analog gray scale method has a drawback and it is helpless against fluctuation in characteristic of TFTs. As an example, let's assume the case where the Id-Vg characteristic of one switching TFT differs from the Id-Vg characteristic of its adjacent pixel's switching TFT allocated for the same scale as the one switching TFT in gray scale display (which means shift toward plus or minus on the whole).

The switching TFTs in this case differ from each other in drain current, depending on how much the characteristics differ between the TFTs. This makes the gate voltage applied to one current controlling TFT in one pixel differ from the gate voltage applied to the other current controlling TFT in the adjacent pixel. Therefore different amounts of current flow in the two EL elements thereof to cause them to emit different amounts of light, with the result that the EL elements intended for the same scale in gray scale display now cannot play their intended roles.

Even when the same gate voltage is applied to the current controlling TFTs in the adjoining pixels, the current controlling TFTs cannot output the same amount of drain current if they are different from each other in Id-Vg characteristic. Moreover, as is apparent from FIG. 4A, the gate voltage used here is in the region where a change in gate voltage exponentially changes the drain current. Therefore if there is even a slightest difference in Id-Vg characteristic, equality in gate voltage does not always assure equality in amount of current outputted. Then it can be expected that EL elements in adjoining pixels may emit light in amounts greatly different from each other.

Since the fluctuation between switching TFTs and the fluctuation between current controlling TFTs affect synergistically, acceptable fluctuation in Id-Vg characteristic is in an even narrower range in actuality. The analog gray scale method is thus extremely sensitive to the fluctuation in characteristic of the TFTs, which forms an obstacle toward achieving multi-color display in conventional active matrix self-luminous devices.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above problems, and an object of the present invention is therefore to provide an active matrix self-luminous device capable of clear, multi-gray scale, color display. Another object of the present invention is to provide an electric machine having such an active matrix self-luminous device as a display unit.

According to the present inventors' opinion, in order to obtain a pixel structure unsusceptible of fluctuation in TFT characteristic, a digital-driven gray scale method in which a current controlling TFT is used merely as a switching element for controlling current is more advantageous than the conventional analog-driven gray scale method in which how much light is emitted from an EL element is controlled by controlling the amount of current.

Then the present inventors have thought of an active matrix self-luminous device for displaying an image in digital-driven gray scale of time division method (hereinafter referred to as time division gray scale).

Further, speeding up of panel display is realized in this device by dividing a video line when a video signal is inputted to a source driver circuit so that plural data are inputted at once. The video signal here designates a data signal to be inputted to the source driver circuit defined in this specification.

FIGS. 5A to 5F show the entire drive timing over writing periods and display periods when an image is displayed in time division gray scale. Explained here is a case in which display is made in 64 gray scales by a 6 bit digital driving method. The writing period is a time period required for signals to be written into all pixels that constitute one frame. The display period is a time period during which pixels are lit up to display based on the written signals.

During the writing period, an EL driving power source is turned off (none of pixels are lighted) so as not to apply voltage to the EL elements in the pixels. On the other hand, the EL driving power source is turned on during the display period so that the voltage is applied to the EL elements in the pixels. If a data signal for lighting a pixel is inputted in this state, the pixel is lit up.

A time period an image in a display region takes to be displayed completely is one frame. In a general EL display, oscillation frequency is 60 Hz and, as shown in FIG. 5A, there are 60 frames in one second. For instance, when 6 bit digital gray scale (64 gray scales) display is made in the fourth frame, this one frame is divided into sixteen and the ratio of the writing periods to the display periods is set to 6:10, so that signals can be written 6 times in total during the writing periods (.apprxeq.6.24 msec.) as shown in FIG. 5B. The writing made in 6 times will be denoted by Writing 1 to Writing 6 with Writing 1 completed first and Writing 6 completed last. The display periods will be denoted by Display 1 to Display 6 corresponding to Writing 1 to Writing 6, respectively.

The display periods are set so as to satisfy Display 1: Display 2: Display 3: Display 4: Display 5: Display 6=1: 1/2: 1/4: 1/8: 1/16: 1/32.

FIG. 5C shows the display periods establishing the above ratio in accordance with the 6 times writing (Writing 1 to Writing 6) during one frame.

Here numerical values written in the bottom of FIG. 5C indicate the relation between the length of the writing periods and the length of the display periods.

Specifically, the numerical values show that the display period (Display 1) for Writing 1 is 320 when the writing period is 63. When each writing period is 63, the display period in Display 2 is 160, the display period in Display 3 is 80, the display period in Display 4 is 40, the display period in Display 5 is 20, and the display period in Display 6 is 10.

One writing period (one Writing) and one display period (one Display) are put together to form one field. That means there are 6 fields in total in FIG. 5C which are the same in writing period but are different in display period. Here, the first field that appears first in forming one frame is called Field 1 (F1), and the rest of the fields, i.e., from the second field to the sixth field are called Field 2 (F2) to Field 6 (F6) in accordance with the order they appear.

However, the order in which Field 1 to Field 6 appear is not fixed. Combining appropriate display periods provides display in desired gray scale out of 64 gray scales.

The actual timing is set such that display periods are combined by dispersing the six fields different in display period as shown in FIG. 5D.

In FIG. 5D, given pixels are lit up during a period of Display 1, then Writing 5 is started, and Display 5 is started after finishing inputting data signals to all the pixels. Subsequently, data signals are inputted to all the pixels in Writing 4, followed by start of Display 4. In this way, given pixels are similarly lit up sequentially in Writing 2, Writing 3, and Writing 6 in their respective fields.

FIG. 5E shows Field 5 out of the six fields illustrated in FIG. 5D. Field 5 of FIG. 5E includes a period in which data is written when a certain gate wiring is selected by a data signal inputted from a gate circuit (Writing 5), and a display period in which pixels are lit up when a signal from a source wiring is inputted to the selected gate wiring (Display 5).

The illustration of FIGS. 5A to 5F is premised on VGA panel display (640.times.480 resolutions). Therefore there are 480 gate wirings, and a period for selecting all of the gate wirings including some dummies is the writing period of FIG. 5E.

A signal inputted from a source wiring in a writing period is called dot data. Dot data inputted from a source driver circuit during one gate selection period is sampled in a period shown in FIG. 5F. This indicates that the signal inputted from the source wiring is written while data is written in the gate selected in the writing period of FIG. 5E. The time period in which data are sampled at once is 40 nsec.

The dot data from the source driver circuit are inputted such that sixteen of them are simultaneously inputted for every 40 nsec. as shown in FIG. 5F.

The dot data selected in one gate selection period are held in respective latches 1 (6001) in the source driver circuit shown in FIG. 6 until all of the data are sampled. After sampling of all the data is completed, latch data are inputted from a latch line 6003 and all the data are simultaneously moved into latches 2 (6002). Note that a shift register 6004 selects video signals inputted from video lines 6006 in response to a clock pulse from a clock line 6005.

A line data latch period in FIG. 5F, separated from the sampling period, is a data moving period in which latch signals are inputted when the data are to be moved from the latches 1 (6001) to the latches 2 (6002).

Shown in FIG. 7 is a pixel structure in the active matrix self-luminous device according to the present invention. In FIG. 7, reference symbol 701 denotes a TFT functioning as a switching element (hereinafter referred to as switching TFT, or pixel TFT), 702, a TFT functioning as an element for controlling current supplied to an EL element 703 (current controlling element) (hereinafter referred to as current controlling TFT, or EL driving TFT), and 704, a capacitor (storage capacitor or auxiliary capacitor). The switching TFT 701 is connected to a gate wiring 705 and a source wiring (data line) 706. The current controlling TFT 702 has a drain region connected to the EL element 703 and has a source region connected to a power supply line (or current supply line) 707.

When the gate wiring 705 is selected, a gate of the switching TFT 701 is opened, a data signal from the source wiring 706 is stored in the capacitor 704, and a gate of the current controlling TFT 702 is opened. After the gate of the switching TFT 701 is closed, the gate of the current controlling TFT 702 is kept open due to the electric charges stored in the capacitor 704 and the EL element 703 emits light during the gate is opened. How much light is emitted from the EL element 703 varies depending on the amount of current flowing therethrough.

In other words, in digital-driven gray scale display, a data signal inputted from the source wiring 706 opens or closes the gate of the current controlling TFT 702 and the current flows when an EL driving power source is turned on to cause the EL element to emit light.

A function of the current controlling TFT of a pixel is to exert control over whether the pixel is lighted (display) or turned off (not-displayed) during the display period. Switching between a display period and a writing period is made by a power source to the right of the panel through an FPC terminal.

The power source (denoted by 709 in 72 of FIG. 7) installed outside the panel functions as a switch for switching between a writing period and a display period. In a writing period, data signals are inputted to the pixels while this power source is turned off (so as not to apply voltage to the pixels).

When inputting data to all the pixels is completed bringing the writing period to an end, the power source (709 in 72 of FIG. 7) is turned on to light pixels (display) at once. This period corresponds to the display period. The period in which the EL elements emit light to light the pixels is any of Display 1 to Display 6 out of the six fields.

One frame comes to an end after all of the six fields appear separately. At this point, gray scale of the pixel is controlled by adding up the display periods. If Display 1 and Display 2 are added together, for instance, 76% of luminance can be obtained in relation to full lighting of 100% luminance. If Display 3 and Display 5 are added together, the luminance obtained is 16%.

The descriptions above are for the case of 64 gray scales. However, the present invention is also capable or other gray scale display.

Assuming a case where N (N is an integer equal to or larger than 2) bit gray scale (2.sup.n gray scales) display is aimed, at first, one frame is divided into N fields (consisting of F1, F2, F3, . . . F(n-1), and F(n)) in accordance with N bit gray scales as shown in FIG. 8. One frame will be divided into larger number of fields as the number of gray scales is increased, and a driver circuit accordingly has to be driven at a higher frequency.

Each of the N fields is further divided into a writing period (Ta) and a display period (Ts).

The display periods of the N fields F1, F2, F3, . . . , F(n-1), and F(n) are denoted by Ts1, Ts2, Ts3 . . . Ts(n-1) and Ts(n), respectively. The display periods of the N fields are set so as to satisfy the relation of Ts1: Ts2: Ts3: . . . : Ts(n-1): Ts(n)=2.sup.0: 2.sup.-1: 2.sup.-2: . . . : 2.sup.-(n-2): . . . : 2.sup.-(n-1).

Under this condition, in one arbitrary field, pixels are sequentially selected (strictly speaking, switching TFTs of the pixels are selected) and a given gate voltage (namely, a data signal) is applied to gate electrodes of the current controlling TFTs. An EL element of a pixel to which a data signal for making current flow in the current controlling TFT emits light when the power source is turned on after the writing period is ended. The EL element thus lights the pixel during the display period allocated to this field.

This operation is repeated for all of the N fields. The gray scale for the respective pixels in one frame depends on the result of adding up the display periods. Accordingly, the gray scale of one arbitrary pixel is controlled by controlling the length of time during which the pixel is lit up for each field (how long each display period lasts).

As described above, a feature of the present invention is that, by using the digital-driven time division gray scale method in an active matrix self-luminous device, an image can be displayed in gray scale without being affected by TFT characteristics, which has been the problem in analog-driven gray scale display. Moreover, the present invention is successful in improving the aperture ratio of the pixels by arranging in a specific manner the storage capacitor formed in each pixel in the pixel portion in order to diminish fluctuation in characteristic of TFTs.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are diagrams showing the structure of a self-luminous device;

FIG. 2 is a diagram showing in section the structure of the self-luminous device;

FIG. 3 is a diagram showing the structure of a pixel portion in a conventional self-luminous device;

FIGS. 4A and 4B are diagrams illustrating a TFT characteristic utilized in an analog gray scale method;

FIGS. 5A to 5F are diagrams illustrating an operation mode of a time division gray scale method;

FIG. 6 is a diagram showing a source driver circuit of the self-luminous device;

FIG. 7 is a diagram showing a pixel structure in a pixel portion of the self-luminous device;

FIG. 8 is a diagram showing an operation mode of the time division gray scale method;

FIG. 9 is a top view of the entire panel of the self-luminous device;

FIG. 10 is a diagram showing protective circuits of FPC input portions;

FIG. 11 is a diagram showing a gate driver circuit of the self-luminous device;

FIG. 12 is a diagram showing a source driver circuit of the self-luminous device;

FIGS. 13A to 13E are diagrams showing a process of manufacturing the self-luminous device;

FIGS. 14A to 14E are diagrams showing the process of manufacturing the self-luminous device;

FIGS. 15A to 15C are diagrams showing the process of manufacturing the self-luminous device;

FIG. 16 is a diagram showing the appearance of the self-luminous device;

FIGS. 17A and 17B are diagrams showing the appearance of the self-luminous device;

FIGS. 18A to 18C are diagrams showing a process of forming a contact structure;

FIGS. 19A and 19B are diagrams showing the top structure of a pixel portion of the self-luminous device;

FIG. 20 is a diagram showing in section the structure of the self-luminous device;

FIG. 21 is a diagram showing a part of a source driver circuit of the self-luminous device;

FIGS. 22A and 22B are, respectively, a picture showing a driver circuit in a pixel portion of a self-luminous device to which the present invention is applied and a picture of an image displayed by the self-luminous device;

FIG. 23 is a picture of a self-luminous device to which the present invention is applied;

FIGS. 24A and 24B are diagrams each showing the structure of an EL element;

FIG. 25 is a graph showing a characteristic of an EL element;

FIGS. 26A to 26F are diagrams showing specific examples of an electric machine;

FIGS. 27A and 27B are a diagram showing the structure of connection between an EL element and a current controlling TFT and a graph showing voltage-current characteristics of the EL element and the current controlling TFT, respectively;

FIG. 28 is a graph showing voltage-current characteristics of an EL element and a current controlling TFT; and

FIG. 29 is a graph showing the relation between the gate voltage and the drain current in a current controlling TFT.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A and 1B are schematic block diagrams showing an active matrix self-luminous device according to this embodiment mode. The active matrix self-luminous device shown in FIGS. 1A and 1B has TFTs formed on a substrate. The TFTs constitute a pixel portion 101 and a data signal side driver circuit 102 and gate signal side driver circuits 103 with the three of them arranged on the periphery of the pixel portion. Denoted by 113 in the drawings is a time division gray scale data signal generating circuit (SPC: Serial-to-Parallel Conversion Circuit).

The data signal side driver circuit 102 has a shift register circuit 102a, a latch 1 (102b), and a latch 2 (102c). Other than these, a buffer (not shown) is also included in the driver circuit 102.

Only one data signal side driver circuit is provided in the active matrix self-luminous device of this embodiment. However, two source signal side driver circuits may be provided such that the pixel portion is sandwiched between the two at its top and bottom.

Each of the gate signal side driver circuits 103 has a shift register, a buffer, and the like (none of them are shown).

The pixel portion 101 has 640.times.480 (width.times.length) pixels. Each pixel has a switching TFT and a current controlling TFT arranged therein. A switching TFT 105 is connected to a gate wiring 106 and a source wiring (data line) 107. A current controlling TFT 108 has a drain region connected to an EL element 109 and has a source region connected to a power supply line 110.

When the gate wiring 106 is selected, a gate of the switching TFT 105 is opened, a data signal from the source wiring 107 is stored in a capacitor 112, and a gate of the current controlling TFT 108 is opened. That is, the data signal inputted from the source wiring 107 causes current to flow in the current controlling TFT 108 so that the EL element emits light.

Now, the operation of the active matrix self-luminous device according to the present invention and the signal flow thereof are described.

The description given first is of the operation of the data signal side driver circuit 102. The data signal side driver circuit 102 includes, basically, the shift register 102a, the latch 1 (102b), and the latch 2 (102c). A clock signal (CK) and a start pulse (SP) are inputted to the shift register 102a. The shift register 102a sequentially generates timing signals in response to the clock signal (CK) and the start pulse (SP). The generated timing signals are sequentially supplied through the buffer (not shown) to downstream circuits.

The timing signals from the shift register 102a are buffered and amplified by the buffer and the like. The source wiring to which the timing signals are supplied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected to the source wiring. Rise and fall of the timing signals could be "dulled" by the load capacitance being large. Therefore the buffer is provided to prevent the dulling.

The timing signals (digital data signals) buffered and amplified by the buffer are supplied to the latch 1 (102b). The latch 1 (102b) has a latch for processing a 6 bit digital signal. Upon receiving the inputted timing signals, the latch 1 (102b) sequentially takes in 6 bit digital data signals supplied from the time division gray scale data signal generating circuit 104 and holds them inside.

A period of time required for writing digital data signals into all stages of the latch 1 (102b) is the writing period. Specifically, the writing period extends from a time point at which writing of a digital data signal into a latch of the leftmost stage of the latch 1 (102b) is started to a time point at which writing of a digital data signal into a latch of the rightmost stage is completed. The writing period may also be referred to as line period.

After the writing period is ended, latch signals start to be supplied to the latch 2 (102c) in timing with the operation of the shift register 102a. At this instant, the digital data signals that have been written and held in the latch 1 (102b) are sent to the latch 2 (102c) all at once and held there in the latch 2 (102c).

The latch 1 (102b) from which the digital signals have been sent to the latch 2 (102c) again sequentially takes in digital signals newly supplied from the time division gray scale data signal generating circuit 104 in response to timing signals from the shift register 102a.

Meanwhile, the latch 2 (102c) receives latch signal inputted thereto.

In each of the gate signal side driver circuits 103, timing signals from its shift register (not shown) are supplied to its not-shown buffer, and then supplied to corresponding gate wirings (scanning lines).

The time division gray scale data signal generating circuit (SPC: Serial-to-Parallel Conversion Circuit) 113 is a circuit for lowering the frequency of digital signals inputted from the external to 1/m of the original frequency. The frequency of a signal necessary for the operation of the driver circuits also can be lowered to 1/m of the original one by dividing the digital signals inputted from the external.

In the present invention, data signals inputted to the pixel portion is digital signals and, unlike liquid crystal display devices, voltage gray scale display is not employed by the present invention. Therefore digital data signals having information in the form of "0" or "1" can be inputted directly to the pixel portion.

The pixel portion 101 has a plurality of pixels 104 arranged in a matrix-like manner. FIG. 1B shows an enlarged view of the pixels 104. In FIG. 1B, the switching TFT 105 is connected to the gate wiring 106 into which a gate signal is inputted and to the source wiring 107 into which a video signal is inputted.

The current controlling TFT 108 has a gate connected to the drain region of the switching TFT 105. The current controlling TFT 108 has the drain region connected to the EL element 109 and has the source region connected to the power supply line 110. The EL element 109 is composed of an EL layer, an anode (pixel electrode) connected to the current-controlling TFT 108, and a cathode (opposite electrode) provided so as to oppose the anode across the EL layer sandwiched therebetween. The cathode is connected to a given power source 111.

The switching TFT may either be an n-channel TFT or a p-channel TFT.

When the current controlling TFT 108 is an n-channel TFT, the drain region of the current controlling TFT 108 is connected to the cathode of the EL element 109 whereas the drain region of the current controlling TFT 108 is connected to the anode of the EL element 109 if the current controlling TFT 108 is a p-channel TFT.

A capacitor 112 is provided to hold the gate voltage of the current controlling TFT 108 when the switching TFT 105 is not selected (when it is in OFF state). The capacitor 112 is connected to the drain region of the switching TFT 105 and the power supply line 110.

Digital data signals to be inputted to the pixel portion structured as above are generated in the time division gray scale data signal generating circuit 113. This circuit converts a video signal (signal including image information) that is a digital signal into a digital data signal for time division gray scale display. The circuit 113 also generates a timing impulse necessary for time division gray scale display and other signals.

Typically, the time division gray scale data signal generating circuit 113 includes: means for dividing one frame into a plurality of fields corresponding to N(N is an integer of 2 or larger) bit gray scales; means for selecting the writing period or the display period in each of the plural fields; and means for setting the display periods so as to satisfy the relation of Ts1: Ts2: Ts3: . . . : Ts(n-1):Ts(n)=2.sup.0: 2.sup.-1: 2.sup.-2: . . . : 2.sup.-(n-2): 2.sup.-(n -1).

The time division gray scale data signal generating circuit 113 may either be disposed outside the self-luminous device of the present invention or be formed unitarily. When the circuit 113 is disposed outside the self-luminous device, digital data signals generated in the circuit are inputted to the self-luminous device of the present invention.

Next, FIG. 2 schematically shows in section the structure of the active matrix self-luminous device according to the present invention.

In FIG. 2, reference symbols 11 and 12 denote a substrate and an insulating film serving as a base (hereinafter referred to as base film), respectively. The substrate 11 is a transparent substrate, and typical examples of a transparent substrate usable as the substrate 11 include a glass substrate, a quartz substrate, a glass ceramic substrate and a crystalline glass substrate. However, the material for the substrate has to be resistant to heat of the highest process temperature in the manufacturing process.

The base film 12 is effective especially when using a substrate containing moving ions or a substrate having conductivity. The base film 12 is not necessary for a quartz substrate. An insulating film containing silicon can be used as the base film 12. The term "insulating film containing silicon" herein refers to an insulating film containing oxygen or nitrogen, or both, in a given proportion to silicon. Specific examples thereof include a silicon oxide film, silicon nitride film, and a silicon oxynitride film (expressed as SiOxNy, where x and y are arbitrary integers).

Reference symbol 201 denotes a switching TFT that is an n-channel TFT. However, the switching TFT may be a p-channel TFT. Denoted by reference symbol 202 is a current controlling TFT, and FIG. 2 shows the case where the current controlling TFT 202 is a p-channel TFT. To elaborate, a gate electrode of the current controlling TFT is connected to an anode of an EL element in this case. If an n-channel TFT is used as the current controlling TFT on the other hand, the gate electrode thereof is connected to a cathode of the EL element.

An n-channel TFT has a field effect mobility higher than that of a p-channel TFT, and hence operates at high-speed and is easy for a large amount of current to flow. Moreover, an n-channel TFT is smaller in size than a p-channel TFT when amounts of current flowing in the two are the same.

However, note that it is not necessary to limit the switching TFT and the current controlling TFT of the present invention to n-channel TFTs, but both or one of them may be a p-channel TFT.

The switching TFT 201 is formed to have: an active layer including a source region 13, a drain region 14, LDD regions 15a to 15d, a separate region 16, and channel forming regions 17a and 17b; gate insulating films 18; gate electrodes 19a and 19b; a first interlayer insulating film 20; a source wiring 21; and a drain wiring 22. The gate insulating films 18 or the first interlayer insulating film 20 may be common to all TFTs on the substrate, or different insulating films or first interlayer insulating films may be provided for different circuits or elements.

The switching TFT shown in FIG. 2 has the gate electrodes 19a and 19b that are electrically connected, and thus forms a so-called double gate structure. Needless to say, the switching TFT 201 of FIG. 2 may not always take the double gate structure, namely, it may have the triple gate structure or other multi-gate structure (meaning a structure that has an active layer with two or more channel forming regions serially connected to each other).

The multi-gate structure is very effective in reducing OFF current. If the OFF current of the switching TFT is lowered enough, the capacitance necessary for the capacitor 112 shown in FIG. 1B can be reduced that much. In other words, the area occupied by the capacitor 112 can be diminished. Therefore giving the multi-gate structure to the switching TFT is also effective in increasing the effective light emission area of the EL element 109.

In the switching TFT 201, the LDD regions 15a to 15d are arranged so as not to overlap with the gate electrodes 19a and 19b through the gate insulating films 18. Such structure is very effectual in reducing OFF current. An appropriate length (width) for each of the LDD regions 15a to 15d is 2.0 to 12.0 .mu.m, typically 6.0 to 10.0 .mu.m.

It is even more desirable in reducing OFF current to provide an offset region (which is formed of a semiconductor layer having the same composition as the channel forming region and to which the gate voltage is not applied) at each boundary between t