Semi-fixed circuit Number:7,394,755 from the United States Patent and Trademark Office (PTO) owispatent A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.<H circuit, fixed, Semi, fixed, circ, 7394755.html, Patent, pto, 7394755

Title: Semi-fixed circuit

Abstract: A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.

Patent Number: 7,394,755 Issued on 07/01/2008 to Nishijima, et al.

Inventors: Nishijima; Seiichi (Kawasaki, JP), Yoda; Katsuhiro (Kawasaki, JP), Fujita; Daisuke (Kawasaki, JP)
Assignee: Fujitsu Limited (Kawasaki, JP)

Appl. No.: 10/859,534

Filed: June 3, 2004

Foreign Application Priority Data


Sep 22, 2003 [JP]			2003-330313

Current U.S. Class: 370/210 ; 370/254; 375/341; 375/354; 455/418

Current International Class: H04J 13/00 (20060101)

Field of Search: 370/210,254 455/418 375/341,354

References Cited [Referenced By]

U.S. Patent Documents


4117541	September 1978	Ali
6687315	February 2004	Keevill et al.

Foreign Patent Documents


63067628	Mar., 1988	JP
63204919	Aug., 1988	JP
04292018	Oct., 1992	JP

Primary Examiner: Jackson; Blane
Attorney, Agent or Firm: Arent Fox LLP.

Claims

What is claimed is:

1. A semi-fixed circuit capable of operations of a matched filter and a butterfly computation circuit, comprising: a shift register; a plurality of multipliers performing multiplication; a plurality of adders performing addition; and a connection circuit controlling connection of said shift register, said plurality of multipliers and said plurality of adders; wherein the operations of the matched filter and the butterfly computation circuit are possible in accordance with the connection of said connection circuit.

2. The semi-fixed circuit according to claim 1, wherein operations of the matched filter and a fast Fourier transform circuit are possible in accordance with the connection of said connection circuit.

3. The semi-fixed circuit according to claim 1, further comprising: a memory storing data to be given as input for said multipliers or said adders; and a schedule circuit controlling sequence of inputting the data in said memory into said multipliers or said adders.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-330313, filed on Sep. 22, 2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semi-fixed circuit, and particularly relates to a semi-fixed circuit capable of a plurality of kinds of circuit operations.

2. Description of the Related Art

As data processing required in many communication standards, for example, the mobile communication standard W-CDMA, and wireless LAN standards IEEE802.11a and IEEE802.11b, a quasi-random code generator by a scrambler, a convolution coder (convolution encoder), an error detecting type CRC (Cyclic Redundancy check) circuit, and a linear feedback shift register is conventionally used. Fast Fourier transform (FFT) constituted of a Viterbi decoder, a matched filter, and butterfly computation executing complex multiplication and complex addition is used.

In the following Patent Documents 1 and 2, a pseudo-random number generating circuit using a linear feedback shift register is described. In the following Patent Document 3, a variable CRC generating circuit is described.

[Patent Document 1] Japanese Patent Application Laid-open No. 63-67628.

[Patent Document 2] Japanese Patent Application Laid-open No. 63-204919.

[Patent Document 3] Japanese Patent Application Laid-open No. 4-292018.

A scrambler, a convolution encoder and the like are constituted of separate fixed circuits, since their processing contents differ. Even the same scramblers are constituted of separate fixed circuits when they are the scramblers with different standards. It reduces the efficiency of using hardware resources to construct all of them by separate fixed circuits.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semi-fixed circuit capable of realizing circuits having different functions such as a scrambler and a convolution encoder with one circuit.

Another object of the present invention is to provide a semi-fixed circuit capable of realizing a plurality of kinds of circuits, which are the circuits having the same functions such as scramblers, with one circuit.

According to one aspect of the present invention, there is provided a semi-fixed circuit capable of operations of a plurality of kinds of scramblers or descramblers, and comprising a plurality of flip flops connectable in series, a first selector capable of selecting any one signal out of at least an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal and outputting the signal to a first flip flop out of the plurality of flip flops, and a second selector capable of selecting any one signal out of at least an exclusive OR signal of an output signal of a second flip flop out of the plurality of flip flops and a second feedback signal, the output signal of the second flip flop, and the second feedback signal and outputting the signal to the first selector as the first feedback signal.

According to another aspect of the present invention, there is provided a semi-fixed circuit capable of simultaneous processing of a plurality of bits of a plurality of kinds of CRC (Cycle Redundancy Check) circuits, and comprising a plurality of flip flops, a first exclusive OR circuit selectively computing an exclusive OR based on a first input bit signal and output signals of said plurality of flip flops to output an output signal corresponding to a shift of first time, and a second exclusive OR circuit selectively computing an exclusive OR based on a second input bit signal and the output signal corresponding to the shift of the first time to output an output signal corresponding to a shift of second time.

According to still another aspect of the present invention, there is provided a semi-fixed circuit capable of simultaneous processing of a plurality of bits of a plurality of kinds of scramblers or descramblers and comprising a plurality of flip flops, a first exclusive OR circuit selectively computing an exclusive OR based on a fist input bit signal and output signals of the plurality of flip flops to output an output signal corresponding to a shift of first time, and a second exclusive OR circuit selectively computing an exclusive OR based on a second input bit signal and the output signals of said plurality of flip flops to output an output signal corresponding to a shift of second time.

According to still another aspect of the present invention, there is provided a semi-fixed circuit capable of viterbi-decoding of coded data convolutedly coded at a plurality of kinds of coding rates, and comprising a branch metric computation circuit for computing a plurality of branch metrics for viterbi-decoding the coded data convolutedly coded and selecting and outputting a branch metric corresponding to a coding rate, and a path metric computation circuit for selecting a necessary branch metric from the plurality of branch metrics and computing a path metric.

According to still another aspect of the present invention, there is provided a semi-fixed circuit capable of operations of a matched filter and a butterfly computation circuit, and comprising a shift register, a plurality of multipliers for performing multiplication, a plurality of adders for performing addition, and a connection circuit for controlling connection of the shift register, the plurality of multipliers and the plurality of adders, wherein the operations of the matched filter and the butterfly computation circuit are possible in accordance with the connection of the connection circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram showing a constitution example of a transmitter of the wireless LAN standard IEEE802.11a, and FIG. 1B is a diagram showing a constitution example of a receiver of the wireless LAN standard IEEE802.11a;

FIG. 2A is a diagram showing a constitution example of a transmitter of the wireless LAN standard IEEE802.11b, and FIG. 2B is a diagram showing a constitution example of a receiver of the wireless LAN standard IEEE802.11b;

FIG. 3 is a diagram showing a constitution example of a scrambler of the wireless LAN standard IEEE802.11a;

FIG. 4 is a diagram showing a constitution example of a scrambler of the wireless LAN standard IEEE802.11b;

FIG. 5 is a diagram showing a constitution example of a descrambler of the wireless LAN standard IEEE802.11b;

FIG. 6 is a diagram showing a constitution example of a semi-fixed circuit according to a first embodiment of the present invention;

FIG. 7 is a diagram showing a constitution example of a semi-fixed circuit according to a second embodiment;

FIG. 8 is a diagram showing a constitution example of an input EOR circuit;

FIG. 9 is a diagram showing a constitution example of a middle stage EOR circuit;

FIG. 10 is a diagram showing a constitution example of a CRC circuit;

FIG. 11 is a diagram showing a constitution example of a semi-fixed circuit according to a third embodiment of the present invention;

FIG. 12 is a diagram showing a constitution example of a flip flop circuit;

FIG. 13 is a diagram showing a constitution example of a convolution encoder of a coding rate of 1/2 of the IEEE802.11a;

FIG. 14 is a diagram showing a constitution example of a semi-fixed circuit according to a fourth embodiment of the present invention;

FIG. 15 is a diagram showing a constitution example of an input EOR circuit;

FIG. 16 is a diagram showing a constitution example of a linear feedback shift register (LFSR) of the W-CDMA standard;

FIG. 17 is a diagram showing a constitution example of a semi-fixed circuit according to a fifth embodiment of the present invention;

FIG. 18 is a diagram showing a constitution example of an input EOR circuit;

FIGS. 19A and 19B are diagrams showing constitution examples of a first type of scrambler or descrambler;

FIGS. 20A and 20B are diagrams showing constitution examples of a second type of scrambler or descrambler;

FIGS. 21A and 21B are diagrams showing constitution examples of a third type of scrambler or descrambler;

FIGS. 22A and 22B are diagrams showing constitution examples of a semi-fixed circuit according to a sixth embodiment of the present invention;

FIG. 23 is a diagram showing a constitution example of a convolution encoder of a coding rate of 1/2;

FIG. 24 is a diagram showing a constitution example of a semi-fixed circuit of a convolution encoder capable of simultaneous processing of N bits per one shift;

FIG. 25 is a diagram showing a constitution example of a computing element in FIG. 24;

FIG. 26 is a diagram showing the linear feedback shift register (LFSR) of the W-CDMA standard in FIG. 16 divided into four computing elements;

FIG. 27 is a diagram showing a constitution example of a LFSR capable of simultaneous batch processing of N bits;

FIGS. 28A and 28B are diagrams showing constitution examples of a first computing element in FIG. 27;

FIG. 29 is a diagram showing a constitution example of a circuit including 32 stages of flip flops and an input selector;

FIGS. 30A to 30C are diagrams showing constitution examples of the input selectors;

FIG. 31 is a diagram showing an internal constitution example of a first EOR computing element;

FIG. 32 is a diagram showing an internal constitution example of a second EOR computing element;

FIG. 33 is a diagram showing a constitution example of a semi-fixed circuit according to an eighth embodiment of the present invention;

FIG. 34 is a diagram showing a constitution example of a first computing element in FIG. 33;

FIG. 35 is a diagram showing a constitution example of a circuit including 32 stages of flip flops and an input selector;

FIGS. 36A to 36F are diagrams showing constitution examples of the input selectors;

FIG. 37 is a diagram showing an internal constitution example of a first EOR computing element;

FIG. 38 is a diagram showing an internal constitution example of a second EOR computing element;

FIG. 39 is a diagram showing a constitution example of a semi-fixed circuit according to a ninth embodiment of the present invention;

FIG. 40 is a diagram showing a constitution example of a branch metric computing element part;

FIG. 41 is a diagram showing a constitution example of an ACS part;

FIG. 42 is a diagram showing a constitution example of a selector and an ACS;

FIGS. 43A and 43B are diagrams showing constitution examples of a matched filter;

FIG. 44 is a diagram showing a constitution example of a butterfly computing element;

FIG. 45 is a diagram showing a constitution example of a fast Fourier transform (FFT) circuit;

FIG. 46 is a diagram showing a constitution example of a semi-fixed circuit capable of selectively realizing the matched filter and butterfly computation;

FIG. 47 is a diagram showing a constitution example of a butterfly computing element;

FIG. 48 is a diagram showing an internal constitution example of a multiplier in FIG. 47; and

FIG. 49 is a diagram showing an entire constitution example of an LSI including a semi-fixed circuit according to an eleventh embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1A shows a constitution example of a transmitter of the wireless LAN standard IEEE802.11a. Input data is transmitted by radio as a transmission signal via a scrambler 101, a convolution encoder 102, an interleave processing circuit 103, a modulation circuit 104, an inverse FFT circuit 105, a D/A conversion circuit 106 and an RF circuit 107 in sequence. The scrambler 101 performs scramble processing to prevent electric power from concentrating on a specific frequency as a result that the same bits are inputted. The convolution encoder 102 performs redundancy coding for error correction (Viterbi decode). The interleave processing circuit 103 previously sorts transmit bits in accordance with the rule since the Viterbi decode has characteristics of being weak in a burst (continuous) error at the time of transmission and strong in a random error. The modulation circuit 104 performs modulation based on inputted data. The inverse FFT circuit 105 performs inverse fast Fourier transformation of the modulated data. The D/A conversion circuit 106 converts a signal into an analogue form from a digital form. The RF circuit 107 converts the signal into a signal in a radio frequency.

FIG. 1B shows a constitution example of a receiver of the wireless LAN standard IEEE802.11a. A signal received by radio is outputted as data via an RF circuit 111, an A/D conversion circuit 112, a synchronous processing circuit 113, an FFT circuit 114, a demodulator circuit 115, a deinterleave processing circuit 116, a Viterbi decoder 117 and a descrambler 118 in sequence. The RF circuit 111 converts a signal in a radio frequency into a signal in a predetermined frequency. The A/D conversion circuit 112 converts a signal into the digital form from the analogue form. The synchronous processing circuit 113 includes a matched filter, and detects a starting (synchronizing) point as a leading position of a frame. The FFT circuit 114 performs fast Fourier transform. The demodulation circuit 115 performs demodulation in timing synchronism with the modulation signal. The deinterleave processing circuit 116 returns the bit sequence to the arrangement before interleaving. The viterbi decoder 117 decodes the transmit bits from the convolutedly encoded redundant bits. The descrambler 118 returns the scrambled data to the original state.

FIG. 2A shows a constitution example of a transmitter of the wireless LAN standard IEEE802.11b. Inputted data is transmitted as a transmission signal by radio via a CRC bit adding processing circuit 201, a scrambler 202, a modulation circuit 203, a diffusion circuit 204 and a transmission circuit 205 in sequence. A diffusion code generating circuit 206 generates a diffusion code and outputs it to the diffusion circuit 204. The CRC bit adding processing circuit 201 adds a CRC bit for determining an error of data. The CRC bit is determined based on the data. Then, the transmitter regards the transmission data as a polynominal expression, and adds a residual obtained when dividing the polynominal expression by a generated polynominal expression previously determined, to the transmission data as a code for checking. The receiver divides the received data by the generated polynominal expression and determines the presence or absence of an error in accordance with whether it is divisible or not. The diffusion circuit 204 performs spectrum diffusion of the modulation signal. The transmission circuit 205 includes a D/A conversion circuit and the RF circuit.

FIG. 2B shows a constitution example of a receiver of the wireless LAN standard IEEE802.11b. A signal received by radio is outputted as data via a receiving circuit 211, an inverse diffusion circuit 212, a demodulation circuit 213, a CRC processing circuit 214 and a descrambler 215 in sequence. A diffusion code generating circuit 216 generates a diffusion code and outputs it to the inverse diffusion circuit 212. The receiving circuit 211 includes the RF circuit and the A/C conversion circuit. The inverse diffusing circuit 212 multiplies the received signal by the same code as the diffusion code, whereby the received signal is inversely diffused, and the signal before diffusion is restored. The CRC processing circuit 214 calculates the CRC bit and checks the presence or the absence of an error.

FIG. 3 shows a constitution example of the scrambler 101 (FIG. 1A) of the wireless LAN standard IEEE802.11a. For example, seven flip flops FF1 to FF7 are connected in series. An exclusive OR (hereinafter, called EOR) circuit 302 performs EOR computation of the output signals of the flip flops FF4 and FF7 and outputs the result. The flip flop FF1 receives the output signal of the EOR circuit 302. An EOR circuit 301 performs EOR computation of an input signal INPUT and the output signal of the EOR circuit 302, and outputs the result as an output signal OUTPUT. The descrambler 118 in FIG. 1B has the same constitution as the scrambler in FIG. 3. This is because the same codes can be outputted as the output signal OUTPUT if the initial values are the same and synchronized with each other. There is no correlation between internal states of the flip flops and the input signal INPUT.

FIG. 4 shows a constitution example of the scrambler 202 (FIG. 2A) of the wireless LAN standard IEEE802/11b. For example, seven flip flops FF1 to FF7 are connected in series. An EOR circuit 402 performs EOR computation of the output signals of the flip flops FF4 and FF7 and outputs the result. An EOR circuit 401 performs EOR computation of the input signal INPUT and the output signal of the EOR circuit 402, outputs the result as the output signal OUTPUT, and outputs the result to the flip flop FF1.

FIG. 5 shows a constitution example of the descrambler 215 (FIG. 2B) of the wireless LAN standard IEEE802.11b. For example, seven flip flops FF1 to FF7 are connected in series. A flip flop FF1 receives the input signal INPUT. An EOR circuit 502 performs EOR computation of the output signals of the flip flops FF4 and FF7 and outputs the result. An EOR circuit 501 performs EOR computation of the input signal INPUT and the output signal of the EOR circuit 502, and outputs the result as the output signal OUTPUT.

In the IEEE802.11b, the constitutions of the scrambler in FIG. 4 and the descrambler in FIG. 5 differ. The numbers of flip flops of both of them are seven and the same. The scrambler in FIG. 4 outputs a different output signal (code) OUTPUT when the bit string of the input signal INPUT differs even if the initial value of the flip flop is the same. There is the correlation between the input signal INPUT and the internal states of the flip flops. In order to reconstitute the input signal INPUT of the scrambler of the transmitter in the descrambler of the receiver, the internal states of the flip flops of the scrambler of the transmitter are also reproduced in the receiver (descrambler), and then, the EOR of the flip flop output of the receiver (descrambler) and the output signal OUTPUT (the input signal INPUT of the descrambler in FIG. 5) of the transmitter (scrambler) is obtained. It is the descrambler in FIG. 5 that realizes this. In FIG. 5, the internal states of the flip flops of the scrambler in FIG. 4 are reproduced by inputting the input signal INPUT into the flip flop FF1 as it is.

FIG. 6 shows a constitution example of a semi-fixed circuit according to the first embodiment of the present invention. This semi-fixed circuit is capable of operations of the scrambler (descrambler) of the wireless LAN standard IEEE802.11a in FIG. 3, the scrambler of the wireless LAN standard LEEE802.11b in FIG. 4, and the descrambler of the wireless LAN standard IEEE802.11b in FIG. 5.

J pieces of Flip flops FF1 to FFJ are connected in series. Middle stage EOR circuits 602 are connected to connection lines between the respective flip flops. As shown in FIG. 9, the middle stage EOR circuit 602 receives an output signal A1 of the flip flop and an output signal (feedback signal) A3 of the previous adjacent middle stage EOR circuit 602. An EOR circuit 901 performs EOR computation of the signals A1 and A3 and outputs the result as a signal A2. A selector 902 alternatively selects the signal A1, A2 or A3 in accordance with a selection signal SELECT, and outputs the result to the subsequent adjacent middle stage EOR circuit 602. For example, in each of the middle stage EOR circuits 602 corresponding to the EOR circuit 302 in FIG. 3, the EOR circuit 402 in FIG. 4 and the EOR circuit 502 in FIG. 5, the selector 902 selects the signal A2 and outputs it. In the middle stage EOR circuit 602 connected to the final stage flip flop FF7, the selector 902 selects the signal A1 and outputs it. In each of the other middle stage EOR circuits 602, the selector 902 selects the feedback signal A3 and outputs it.

An output signal (feedback signal) FB of the middle stage EOR circuit 602 connected to between the flip flops FF1 and FF2 is inputted into an input EOR circuit 601. As shown in FIG. 8, the input EOR circuit 601 receives the feedback signal FB and the input signal INPUT. An EOR circuit 801 performs EOR computation of the feedback signal FB and the input signal INPUT, and outputs the signal A2. When the feedback signal FB is set as the signal A1, and the input signal INPUT is set as the signal A3, a selector 802 alternatively selects the signal A1, A2 or A3 in accordance with the selection signal SELECT, and outputs the result to the flip flop FF1. The signal A2 becomes the output signal OUTPUT. In the case of FIG. 3, the selector 802 selects the signal A1. In the case of FIG. 4, the selector 802 selects the signal A2. In the case of FIG. 5, the selector 802 selects the signal A3.

In FIG. 6, an enable signal ENABLE is a signal to control whether the flip flops FF1 to FFJ are brought into an enable state or not. For example, only the flip flops FF1 to FF7 are in the enable state. An initial value signal LOAD is a signal for setting initial values at the flip flops FF1 to FFJ. As described above, by controlling the selection state of the input EOR circuit 601 and the middle stage EOR circuit 602 in accordance with the selection signal SELECT, the scramblers and the descrambler in FIG. 3 to FIG. 5 can be alternatively selected and operated.

The scrambler in the fixed circuit has the structure of the hardware dependent on such parameters as shift register length, a tap position inputted into the EOR circuit, and the number of taps inputted into the EOR circuit, and has the problem that if these parameters change, hardware has to be prepared apart from this. According to the semi-fixed circuit of this embodiment, by providing the input EOR circuit 601 and the middle stage EOR circuit 602, the operations of various kinds of scramblers and descramblers including three scramblers or descramblers of FIG. 3 to FIG. 5 are made possible with one semi-fixed circuit.

Second Embodiment

FIG. 7 shows a constitution example of a semi-fixed circuit according to a second embodiment of the present invention. This semi-fixed circuit is made by adding a decoder 701 to the semi-fixed circuit in FIG. 6. The decoder 701 outputs a signal of 2L+2 bits based on the selection signal SELECT of L+1 bits, and controls selection states of L pieces of middle stage EOR circuits 602 and one input EOR circuit 601.

In order to control L pieces of middle stage EOR circuits 602 and one input EOR circuit 601, the selection signal SELECT of 2L+2 bits is originally necessary, but the selection signal SELECT can be made L+1 bits by utilizing the fact that as a result of grouping the flip flops and the middle stage EOR circuits 602 to be used and the flip flops and the middle EOR circuits 602 not to be used out of all the number of patterns and subtracting the combination patterns of setting in the group not to be used from all the numbers of patterns, there are (2 raised to (L-1).sup.th power).times.3 possible patterns.

As described above, the decoder 701 decodes the input signal SELECT of a small number of bits and outputs an output signal of a large number of bits, and selects the middle stage EOR circuit 602 and the input EOR circuit 601. By using the decoder 701, the amount of selection signal can be reduced.

Third Embodiment

FIG. 10 shows a constitution example of CRC circuits in the CRC bit adding processing circuit 201 (FIG. 2A) and the CRC processing circuit 214 (FIG. 2B). An EOR circuit 1001 computes EOR of the input signal IN and a feedback signal from a flip flop FF of a final stage, and outputs the result to a flip flop of an initial stage. For example, four flip flops FF are connected in series via EOR circuits 1002. Each of the EOR circuits 1002 computes EOR of the output signal of the EOR circuit 1001 and an output signal of the flip flop FF of the previous stage, and outputs the result to the flip flop FF of the subsequent stage. The output signals of the respective flip flops FF become output signals OUT0, OUT1, OUT2 and OUT3.

As for the CRC circuit in FIG. 10, the example with four taps, in which the EOR circuits are interposed between all the flip flops is explained for simplification, but in the constitution of the actual CRC circuit, the number of taps are, for example, 16 in the IEEE802.11b, and the EOR circuits 1002 are interposed between the flip flops FF at irregular intervals.

FIG. 11 shows a constitution example of a semi-fixed circuit according to the third embodiment of the present invention. This semi-fixed circuit is a circuit made by adding the function of the CRC circuit in FIG. 10 to the semi-fixed circuit of the first embodiment (FIG. 6). Since the semi-fixed circuit of this embodiment is basically the same as the semi-fixed circuit of the first embodiment, only the point differing from the first embodiment will be explained. 16 is the basis of the number of taps I corresponding to the number of flip flop circuits 1101.

A plurality of flip flop circuits 1101 each have a constitution in FIG. 12 unlike FIG. 6. An EOR circuit 1201 computes EOR of input data from the input EOR circuit 601 and the output signal A2 of the flip flop of the previous stage, and outputs the signal A1. A selector 1203 selects the signal A1 or A2 in accordance with a selection signal FF_SELECT, and outputs the result to a flip flop 1204. The flip flop 1204 receives an output signal of the selector 1203 and outputs the signal.

In order to realize the CRC circuit in FIG. 10, the selector 1203 selects the signal A1 and outputs the signal A1. In order to realize the circuit in FIG. 6, the selector 1203 selects the signal A2 and outputs the signal.

In the CRC circuit in FIG. 10, there is the case where output signals OUT0 to OUT3 are outputted as they are, and the case where the outputs of them are inverted and outputted. Therefore, in FIG. 11, EOR circuits 1102 and 1103 are added. When the inverted signal INV_OUT is 1, the inverted output is performed, and when it is 0, non-inverted output is performed. The EOR circuit 1103 computes EOR of the output signal of the input EOR circuit 601 and the inverted signal INV_OUT, and outputs the result. Each of a plurality of EOR circuits 1102 operates EOR of the output signal of each of the flip flops 1101 and inverted signal INV_OUOT, and outputs the result.

The CRC circuit and the like of the fixed circuit have the structure of the hardware dependent on parameters, and have the problem that when the parameters change, hardware has to be prepared apart from this. According to this embodiment, a scrambler of an optional constitution and a CRC circuit of an optional constitution can be realized with one semi-fixed circuit.

Fourth Embodiment

FIG. 13 shows a constitution example of the convolution encoder 102 of a coding rate of 1/2 (FIG. 1A) of the IEEE802.11a. For example, six flip flops FF1 to FF6 are connected in series. The input signal INPUT is inputted into the flip flop FF1 of the initial stage. An EOR circuit 1301 computes EOR of the input signal INPUT and the output signals of the flip flops FF2, FF3, FF5 and FF6, and outputs an output signal OUTPUT1. An EOR circuit 1302 computes EOR of the input signal INPUT and output signals of the flip flops FF1, FF2, FF3 and FF6, and outputs an output signal OUTPUT2.

FIG. 14 shows a constitution example of a semi-fixed circuit according to a fourth embodiment of the present invention. The semi-fixed circuit is the circuit made by adding the function of the convolution encoder in FIG. 13 to the semi-fixed circuit of the third embodiment (FIG. 11). The semi-fixed circuit of this embodiment is basically the same as the semi-fixed circuit of the third embodiment, and only the point differing from the third embodiment will be explained.

In the third embodiment, the middle stage EOR circuits 602 are provided only at the lower stage of the flip flops 1101, but in the fourth embodiment, the middle stage EOR circuits 602 are also provided at the upper stage as well as at the lower stage from the flip flops 1101. The middle stage EOR circuits 602 at the upper stage correspond to the EOR circuit 1301 in FIG. 13. The middle EOR circuits 602 at the lower stage correspond to the EOR circuit 1302 in FIG. 13.

An input EOR circuit 1401 is provided instead of the input EOR circuit 601 in FIG. 11, and has a constitution in FIG. 15. The input signal INPUT, a feedback signal FB1 from the middle EOR circuit 602 at the upper stage, and a feedback signal FB2 from the middle stage EOR circuit 602 at the lower stage are inputted into the input EOR circuit 1401. The feedback signal FB1 is inputted into a selector 1503 as the signal A1, the input signal INPUT is inputted into the selector 1503 as the signal A3, and the feedback signal FB2 is inputted into the selector 1503 as a signal A5.

An EOR circuit 1501 computes EOR of the feedback signal FB1 and the input signal INPUT, and outputs the signal A2. The signal A2 is outputted as the output signal OUTPUT 1. An EOR circuit 1502 computes EOR of the feedback signal FB2 and the input signal INPUT, and outputs a signal A4. The signal A4 is outputted as the output signal OUTPUT2. A decoder 1402 in FIG. 14 decodes the selection signal SELECT as the decoder 701 in FIG. 7 and outputs a selection signal. The selector 1503 alternatively selects a signal from the signals A1 to A5 in accordance with the output signal of the decoder 1402, and outputs the result to the flip flop FF1 of the initial stage. In order to realize the convolution decoder in FIG. 13, the selector 1503 selects the signal A3 and outputs it.

The convolution encoder and the like of the fixed circuit have the structure of hardware dependent on parameters, and has the problem that when these parameters change, hardware has to be prepared apart from this. According to this embodiment, a scrambler of an optional constitution, a CRC circuit of an optional constitution and a convolution encoder of an optional constitution can be realized with one semi-fixed circuit.

Fifth Embodiment

FIG. 16 shows a constitution example of a linear feedback shift register (LFSR) of the W-CDMA standard. The linear feedback shift register is used for a diffusion code generating circuit of the W-CDMA standard. The position of the diffusion code generating circuit of the W-CDMA standard is the same as in the diffusion code generating circuits 206 and 216 of the IEEE802.11b in FIGS. 2A and 2B. The linear feedback shift register does not take in the input data, but performs shift operation of bit arithmetic processing with repeatability based on a value initially set at the flip flop.

The linear feedback shift register (hereinafter, called LFSR) has a first circuit 1611 and a second circuit 1612. First, the first circuit 1611 will be explained. A plurality of flip flops FF are connected in series. An EOR circuit 1604 computes EOR of signals of the flip flop FF of a final stage (left end) and the other flip flops FF, and feeds back and inputs the result to the flip flop FF of an initial stage (right end). An EOR circuit 1603 computes EOR of the signals of the three flip flops FF and outputs the result.

Next, the second circuit 1612 will be explained. A plurality of flip flops FF are connected in series. An EOR circuit 1606 computes EOR of the signals of four flip flops FF, and feeds back and inputs the result to the flip flop FF of an initial stage (right end). An EOR circuit 1605 computes EOR of signals of three flip flops FF and outputs the result.

An EOR circuit 1601 computes EOR of the output signals of the flip flops at the final stages of the first circuit 1611 and the second circuit 1612, and outputs the output signal OUTPUT1. The EOR circuit 1602 computes EOR of the output signals of the EOR circuits 1603 and 1605, and outputs the output signal OUTPUT2.

FIG. 17 shows a constitution example of a semi-fixed circuit according to a fifth embodiment of the present invention. The semi-fixed circuit is a circuit made by adding the function of LFSR in FIG. 16 to the semi-fixed circuit of the fourth embodiment (FIG. 14). Only the point in which the semi-fixed circuit of this embodiment differs from he fourth embodiment will be explained.

The semi-fixed circuit of this embodiment has a first circuit 1711 and a second circuit 1712. The first circuit 1711 and the second circuit 1712 correspond to the first circuit 1611 and the second circuit 1612 in FIG. 16, respectively, and each of the circuits corresponds to the circuit in FIG. 14.

An input EOR circuit 1701 is provided instead of the input EOR circuit 1401 in FIG. 14, and has a constitution in FIG. 18. Input signals 1725 and 1726 are the signals obtained by selecting outputs of the flip flops 1101 at the final stages in accordance with the number of stages of the LFSR constituted this time from the outputs of the optional flip flops 1101. Input signals 1721 and 1722 are output signals of the middle stage EOR circuits 602 at the upper stages. The input signals INPUT1 and INPUT2 are not used in the LFSR in FIG. 16, and they correspond to the input signal INPUT in the above-described fourth embodiment. Input signals 1723 and 1724 are output signals of the middle stage EOR circuits 602 at the lower stages.

An EOR circuit 1801 computes EOR of the signals 1721 and 1722 and the input signals INPUT1 and INPUT2, and outputs the result. An EOR circuit 1802 computes EOR of the signals 1723 and 1724 and the input signals INPUPT1 and INPUT2, and outputs the result.

In FIG. 17, a decoder 1702 decodes a selection signal SELECT and outputs a selection signal, and controls the selection states of the input EOR circuit 1701 and the middle stage EOR circuits 602 of the first circuit 1711. A decoder 1703 decodes the selection signal SELECT and outputs a selection signal, and controls the selection states of the input EOR circuit 1701 and the middle stage EOR circuits 602 of the second circuit 1712.

In FIG. 18, a selector 1804 alternatively selects a signal from the signals 1725 and 1726, the signals 1721 and 1722, and an output signal of the EOR circuit 1801 in accordance with the selection signal, and outputs output signals 1732 and 1733. A selector 1805 alternatively selects a signal from the signals 1725 and 1726, the signals 1723 and 1724, and an output signal of the EOR circuit 1802 in accordance with the selection signal, and outputs output signals 1734 and 1735. A selector 1803 alternatively selects a signal from the signals 1721 and 1722, the output signal of the EOR circuit 1801, the input signals INPUT1 and INPUT2, the output signal of the EOR circuit 1802, and the signals 1723 and 1724, and outputs an output signal 1731 to the flip flop FF1 at the initial stage.

In FIG. 17, an EOR circuit 1704 computes EOR of the signals 1732 and 1733, and outputs the output signal OUTPUT1. An EOR circuit 1705 computes EOR of the signals 1734 and 1735, and outputs the output signal OUTPUT2. The signal 1733 is outputted as the output signal OUTPUT3, and the signal 1735 is outputted as the output signal OUTPUT4.

In order to realize the LFSR in FIG. 16, the selector 1804 selects and outputs the input signal 1725, the selector 1803 selects and outputs the input signal 1721, and the selector 1805 selects and outputs the input signal 1723, in the input EOR circuit 1701 of the first circuit 1711. In the input EOR circuit 1701 of the second circuit 1712, the selector 1804 selects and outputs the input signal 1726, the selector 1803 selects and outputs the input signal 1722, and the selector 1805 selects and outputs the input signal 1724.

The LFSR and the like of the semi-fixed circuit have the structure of hardware dependent on parameters, and has the problem that when these parameters change, hardware has to be prepared apart from this. According to this embodiment, a scrambler of an optional constitution, a CRC circuit of an optional constitution, a convolution encoder of an optional constitution, and an LFSR of an optional constitution can be realized with one semi-fixed circuit.

Sixth Embodiment

FIG. 22A shows a constitution example of a semi-fixed circuit according to a sixth embodiment of the present invention. This semi-fixed circuit can selectively realize a plurality of kinds of CRC circuits such as the CRC circuit in FIG. 10, and performs foresight processing of an amount of several shifts at one time by simultaneously inputting a plurality of bits instead of inputting one bit at a time by shifting it as shown in FIG. 10.

For example, input signals IN[0] to IN[5] are inputted by 6 bits in parallel. Output signals of selectors 2201 to 2204 are inputted into the flip flops FF1 to FF4. Output signals OUT0 to OUT3 of the flip flops FF1 to FF4 are initial set values corresponding to a shift of zero time. A plurality of E circuits 2211 each have a constitution in FIG. 22B, and each receive the signal A1 and a signal B1. An EOR circuit 2231 computes EOR of the signals A1 and B1, and outputs the signal A2. A selector 2232 selects and outputs the signal A1 or signal A2.

Data D00, D01, D02 and D03 are output signals corresponding to a shift of first time. Data D10, D11, D12 and D13 are output signals corresponding to a shift of second time. Data D20, D21, D22 and D23 are output signals corresponding to a shift of third time. Data D30, D31, D32 and D33 are output signals corresponding to a shift of fourth time. Data D40, D41, D42 and D43 are output signals corresponding to a shift of fifth time. Data D50, D51, D52 and D53 are output signals corresponding to a shift of sixth time.

The selector 2201 alternatively selects data from the data D00, D10, D20, D30, D40 and D50 and outputs the data to the flip flop FF1. The selector 2202 alternatively selects data from the data D01, D11, D21, D31, D41 and D51 and outputs the data to the flip flop FF2. The selector 2203 alternatively selects data from the data D02, D12, D22, D32, D42 and D52 and outputs the data to the flip flop FF3. The selector 2204 alternatively selects data from the data D03, D13, D23, D33, D43 and D53 and outputs the data to the flip flop FF4.

The semi-fixed circuit can select parallel inputs of one bit to six bits. For example, when parallel input signals IN[0] to IN[5] of six bits are inputted, the selectors 2201 to 2204 select the data D50, D51, D52 and D53. When parallel input signals IN[0] to IN[4] of five bits are inputted, the selectors 2201 to 2204 select the data D40, D41, D42 and D43.

By providing the E circuit 2211, it becomes possible to realize the CRC circuit in which the EOR circuits 1002 in FIG. 10 are interposed at irregular intervals. In the E circuit 2211, the signal A2 is selected when the EOR circuit is interposed, and when the EOR circuit is not interposed, the signal A1 is selected.

Here, the maximum number of foresight shifts which can be outputted at one time is constituted to be 6. In this case, six bits from IN[0] to IN[5] are simultaneously inputted at one time. Then, the output signals OUT0 to OUT3 at the time of initial setting of the flip flops FF1 to FF4 are obtained. At the same time, an output Dtb of the number of shifts 1 to 6 is obtained. t expresses (shift times -1) and b expresses a digit position of a bit. In this case, the four selectors 2201 to 2204 select the sixth input from the top. Namely, D50, D51, D52 and D53 in order from left. In doing so, the output from the number of shifts 7 to 12 is obtained by inputting the subsequent six bits. If five bits are inputted at one time as input, a circuit 2222 is not used. Namely, considering that the circuit 2222 does not exist, an operation of taking the input data of five bits at a time is performed. In order to do this, the selectors 2201 to 2204 select the fifth input data from the top and input the next five-bit input signals.

In this embodiment, in order to respond to the constitution in which the EOR circuit 1002 at the rightmost end in FIG. 10 is not interposed, the signal A1 is selected in the setting of all the E circuits 2211 of the circuit 2221 in FIG. 22A.

The constitution in FIG. 22A is obtained from the relationship between the number of shifts t-1 obtained from FIG. 10 and t, as shown in the following expression. In this case, "x" means EOR. {OUT0[t], OUT1[t], OUT2[t], OUT3[t]}={OUT3[t-1]xIN[t-1], OUT3[t-1]xIN[t-1]xOUT0[t-1], OUT3[t-1]xIN[t-1]xOUT1[t-1], UT3[t-1]xIN[t-1]xOUT2[t-1]}

The CRC circuit in FIG. 10 is serial processing in which when one bit is inputted, one bit is outputted. In this embodiment, a plurality of CRC computations can be performed at one time by providing the circuits for performing a plurality of times of shift processing in advance instead of repeating a one-bit shift.

Seventh Embodiment

FIG. 19A is a constitution example of a first type of scrambler (including a descrambler. The same shall apply hereinafter.). An EOR circuit 1901 computes EOR of the input signal IN and the output signal of an EOR circuit 1902, and outputs the output signal OUT. For example, four flip flops FF1 to FF4 are connected in series. The output signal of the EOR circuit 1901 is inputted into the flip flop FF1. An EOR circuit 1904 computes EOR of the output signals of the flip flops FF3 and FF4, and outputs the result. An EOR circuit 1903 computes EOR of the output signal of the EOR circuit 1904 and the output signal of the flip flop FF2, and outputs the result. The EOR circuit 1902 computes EOR of the output signal of the EOR circuit 1903 and the output signal of the flip flop FF1, and outputs the result to the EOR circuit 1901.

FIG. 19B shows a constitution example of a scrambler capable of simultaneously receiving a plurality of input bits of the scrambler in FIG. 19A and performing foresight processing of several shifts at one time. For example, input signals IN[0] to IN[5] of six bits are inputted in parallel. The EOR circuit 1911 performs EOR computation and outputs the result. The respective output signals OUT[2] to OUT[5] are fed back to and inputted into the flip flops FF1 to FF4. The output signals OUT[0] to OUT[5] are signals corresponding to the first to the sixth shifts, respectively.

FIG. 20A is a constitution example of a second type of scrambler. An EOR circuit 2001 computes EOR of the input signal IN and an output signal of an EOR circuit 2002, and outputs the output signal OUT. For example, four flip flops FF1 to FF4 are connected in series. The output signal of the EOR circuit 2002 is inputted into the flip flop FF1. An EOR circuit 2004 computes EOR of the output signals of the flip flops FF3 and FF4 and outputs the result. An EOR circuit 2003 computes EOR of the output signal of the EOR circuit 2004 and the output signal of the flip flop FF2 and outputs the result. The EOR circuit 2002 computes EOR of the output signal of the EOR circuit 2003 and the output signal of the flip flop FF1, and outputs the result to the EOR circuit 2001 and the flip flop FF1.

FIG. 20B shows a constitution example of a scrambler capable of simultaneously receiving a plurality of input bits of the scrambler in FIG. 20A and performing foresight processing of several shifts at one time. For example, input signals IN[0] to IN[5] of six bits are inputted in parallel. An EOR circuit 2011 performs EOR computation and outputs the result. An EOR circuit 2021 computes EOR of the input signal IN[5] and the output signal OUT[5], and outputs the result to the flip flop FF1. An EOR circuit 2022 computes EOR of the input signal IN[4] and the output signal OUT[4], and outputs the result to the flip flop FF2. An EOR circuit 2023 computes EOR of the input signal IN[3] and the output signal OUT[3], and outputs the result to the flip flop FF3. An EOR circuit 2024 computes EOR of the input signal IN[2] and the output signal OUT[2], and outputs the result to the flip flop FF4. The output signals OUT[0] to OUT[5] are output signals corresponding to the first to the sixth shifts, respectively.

FIG. 21A is a constitution example of a third type of scrambler. An EOR circuit 2101 computes EOR of the input signal IN and an output signal of the EOR circuit 2102, and outputs the output signal OUT. For example, four flip flops FF1 to FF4 are connected in series. The input signal IN is inputted into the flip flop FF1. An EOR circuit 2104 computes EOR of the output signals of the flip flops FF3 and FF4, and outputs the result. An EOR circuit 2103 computes EOR of the output signal of the EOR circuit 2104 and the output signal of the flip flop FF2, and outputs the result. The EOR circuit 2102 computes the output signal of the EOR circuit 2103 and the output signal of the flip flop FF1, and outputs the result to the EOR circuit 2101.

FIG. 21B shows a constitution example of a scrambler capable of simultaneously receiving a plurality of input bits of the scrambler in FIG. 21A and performing foresight processing of several shifts at one time. For example, input signals IN[0] to IN[5] of 6 bits are inputted in parallel. An EOR circuit 2111 performs EOR computation and outputs the result. The input signals IN[5] to IN[2] are inputted into the flip flops FF1 to FF4, respectively. The output signals OUT[0] to OUT[5] are output signals corresponding to the first to the sixth shifts.

FIG. 23 shows a constitution example of the convolution encoder of a coding rate of 1/2. For example, four flip flops FF1 to FF4 are connected in series. The input signal IN is inputted into the flip flop FF1 of the initial stage. An EOR circuit 2301 computes EOR of the input signal INPUT and the output signals of the flip flops FF1 to FF4, and outputs an output signal OUT1. An EOR circuit 2302 computes EOR of the input signal INPUT, and the output signals of the flip flops FF1 to FF4, and outputs an output signal OUT2. The operation of the convolution encoder is to perform shift-in by one bit of input data and output 2 bits.

FIG. 24 shows a constitution example of a semi-fixed circuit of a convolution encoder capable of simultaneous processing of N bits per one shift of the convolution encoder in FIG. 23. A first convolution computing element 2401 corresponds to a computing element 2311 in FIG. 23, and receives an input signal of N bits and outputs the output signal OUT1 of N bits. The computing element 2311 includes the flip flops FF1 to FF4 and the EOR circuit 2301. A second convolution computing element 2402 corresponds to a computing element 2312, and receives the input signal of N bits and outputs the output signal OUT2 of N bits. The computing element 2312 includes the flip flops FF1 to FF4 and the EOR circuit 2302. The semi-fixed circuit in FIG. 24 can selectively realize the scramblers in FIG. 19B, FIG. 20B and FIG. 21B.

FIG. 25 shows the same constitutional example of the computing elements 2401 and 2402 in FIG. 24, which simultaneously receives a plurality of bits and performs foresight processing of several shifts at one time. For example, the input signals IN[0] to IN[5] of six bits are inputted in parallel. The output signals of respective selectors 2501 to 2504 are inputted into the flip flops FF1 to FF4, respectively, and the flip flops FF1 to FF4 output signals D0 to D3. An E circuit 2521 has the constitution of FIG. 22B. The output signals OUT[0] to OUT[5] are output signals corresponding to the first to the sixth shifts, respectively. Signals W0 to W5 are outputted in a feedback circuit 2522.

The selector 2501 alternatively selects the signal W0, W1, W2, W3, W4 or W5 and outputs the result to the flip flop FF1. The selector 2502 alternatively selects the signal D0, W0, W1, W2, W3 or W4, and outputs the result to the flip flop FF2. The selector 2503 alternatively selects the signal D1, D0, W0, W1, W2 or W3, and outputs the result to the flip flop FF3. The selector 2504 alternatively selects the signal D2, D1, D0, W0, W1 or W2, and outputs the result to the flip flop FF4. The feedback circuit 2522 is not used when the convolution encoder in FIG. 23 is realized, and is used when the scramblers in FIG. 19B, FIG. 20B and FIG. 21B are realized.

In FIG. 23, the value the data stored in the flip flop at a certain position at a certain time has after being shifted once is simply the value which the flip flop at the previous stage holds and outputs at present. When the number of shifts, which are performed, is larger than the number of flip flops, the data shifted in at the oldest time, which the flip flop at the final stage has at this time, disappears, and is replaced with newly inputted data. Then, since the data result which the flip flop is supposed to have at each time is obtained, an EOR computation, namely, a convolution encode is performed thereafter in accordance with the placement of the EOR circuit in the tap position where the data exists.

Five selectors 2511 to 2515 are set to select the input signals IN[0] to IN[4], respectively in the case of the convolution encoder in FIG. 23. Seeing the relationship between each shift timing and the bit shifted in and shifted out in this timing, in the case of convolution coding rate of 1/M at the initial shift, by arranging M pieces of convolution computing elements 2401 and 2402 in FIG. 24, the convolution encode corresponding to the input signal IN can be simultaneously outputted by N bits at one shift-in. The input signal IN of N=6 bits is constituted of IN[0] to IN[5], and is simultaneously coded and outputted with the convolution encoder.

The presence or absence of the E circuit 2521 is determined by the constitution of the convolution operation that is desired to be realized. When the constitution in which the EOR circuits exist between all the flip flops included in the convolution encoder desired to be realized is taken, all the E circuits 2521 perform EOR computation.

In this case, the constitution with N=6 is adopted. When six bits are simultaneously outputted, the four selectors 2501 to 2504 select the sixth input from the top. Namely, they select W5, W4, W3 and W2 from the left. Input is performed for IN[0] to IN[5] with six bits as one set. By setting the selectors 2501 to 2504, the simultaneous output of 6 bits or less is possible. The outputs corresponding to the inputs of IN[0] to IN[5] are OUT[0] to OUT[5] respectively.

In order to realize the scrambler in FIG. 19B, the selectors 2511 to 2515 select and output the middle signal. In order to realize the scrambler in FIG. 20B, the selectors 2511 to 2515 select and output the right signal. In order to realize the scrambler in FIG. 21B, the selectors 2511 to 2515 select and output the left signal.

The conventional scrambler and convolution encoder perform serial processing of outputting one bit when receiving one bit. According to the semi-fixed circuit of this embodiment, a plurality of scramble processings and convolution encoder processings can be performed by providing the circuits for previously performing a plurality of shift processings instead of repeating one bit shift. The semi-fixed circuit of this embodiment can constitute a scrambler of an optional constitution for performing simultaneous processing of inputting a plurality of bits, and a convolution encoder of an optional constitution.

Eighth Embodiment

FIG. 26 is a diagram showing that the linear feedback shift registor (LFSR) of the W-CDMA standard in FIG. 16 is divided into four computing elements 2701 to 2704. The first circuit 1611 is divided into the computing elements 2701 and 2702. The computing element 2701 includes a plurality of flip flops FF and the EOR circuit 1603. The computing element 2702 includes a plurality of flip flops FF and the EOR circuit 1604. The second circuit 1612 is divided into the computing elements 2703 and 2704. The computing element 2703 includes a plurality of flip flops FF and the EOR circuit 1606. The computing element 2704 includes a plurality of flip flops FF and the EOR circuit 1605. The number of flip flops is, for example, 25. After the internal states of the flip flops are initially set, bit lines uniquely corresponding to the setting of the initial values are outputted in series.

FIG. 27 is a constitution example of an LFSR capable of simultaneous batch processing of N bits of the LFSR in FIG. 26. The first circuit 1611 has the first computing element 2701 and the second computing element 2702. The second circuit 1612 has he third computing element 2703 and the fourth computing element 2704. The first computing element 2701 and the third computing element 2703 perform the EOR computation of the internal states of the flip flops. The second computing element 2702 and the fourth computing element 2704 constitute a feedback loop to update the internal states of the flip flops. The first to the fourth computing elements 2701 to 2704 can input and output signals to each other. The first computing element 2701 outputs the output signal OUTPUT1 of N bits. The second computing element 2702 outputs the output signal OUTPUT2 of N bits. The first to the fourth computing elements 2701 to 2704 have the same constitutions.

FIG. 28A shows a constitution example of the first computing element 2701 in FIG. 27. A circuit 2800 includes 32 stages of flip flops and their input selectors (see FIG. 29), and receives a signal 2850. The signal 2850 includes a signal 2849, and is an 8.times.4-bit signal of the update values of the flip flops of the first to fourth computing elements. The signal 2849 is a signal of the update value of the flip flops of the first computing element 2701 outputted from an internal state selector 2828.

FIG. 29 shows a constitution example of the circuit 2800. A signal 2920 is an input signal to a selector relating to the flip flop FF0, and includes the signal 2849 from the first computing element, a signal 2912 from the second computing element, a signal 2913 from the third computing element and a signal 2914 from the fourth computing element. For example, the signal 2849 from the first computing element is a signal of eight bits indicating the update values of the flip flops. A circuit 2901 includes a selector 2907, and selects input data for the flip flop FF0 of the first computing element. The selector 2907 is an update value selector for the flip flop FF0, and performs selection by the number of bits of simultaneous parallel processing.

Similarly to the circuit 2901 for the first computing element, a circuit 2902 is a circuit for selecting input data for the flip flop FF0 of the second computing element, a circuit 2903 is a circuit for selecting input data for the flip flop FF0 of the third computing element, and a circuit 2904 is a circuit for selecting input data for the flip flop FF0 of the fourth computing element. The signals 2912 to 2914 are inputted into the circuits 2902 to 2904, respectively. A selector 2931 alternatively selects the output signals of the circuit 2901 to 2904, and outputs the signal to the flip flop FF0. The flip flop FF0 holds the signal and outputs it.

Similarly to the signal 2920, a signal 2921 is an input signal to a selector relating to the flip flop FF1, and a signal 2922 is an input signal to a selector relating to the flip flop FF31. Similarly to the circuit 2901, a circuit 2905 is a circuit for selecting input data for the flip flop FF1 of the first computing element, and a circuit 2906 is a circuit for selecting input data for the flip flop FF31 of the first computing element. The input data are also alternatively selected and inputted into the flip flops FF1 to FF31.

For eight-bit batch processing, in the circuit 2901, it is necessary to set the data of the eighth bit for the flip flop FF0 in the update value selector 2907 for the flip flop FF0, and therefore FF update value [7] is selected. For seven-bit batch processing, the upper FF update value [6] is selected, and in this way, the FF update value upper than the number of bits to be processed by batch is sequentially selected. It is necessary to set the initial values of the flip flops for the flip flops FF0 to FF31 separately before operation.

FIG. 30A shows the input selector 2907 for the flip flop FF1 in the circuit 2905. This selector makes selection from the output value of the flip flop FF0, and the FF update value [0] to FF update value [6] of seven bits.

FIG. 30B shows the input selector 2907 for the flip flop FF2. This selector makes selection from the output values of the flip flops FF1 and FF0, and the FF update value [0] to FF update value [5] of six bits.

FIG. 30C shows the input selector 2907 for the flip flop FFn. This selector makes selection from the output values of the flip flops FF (n-8).about.FF (n-1).

In FIG. 28A, a first EOR computing element 2811 has the selection EOR circuits 2831a to 2831d of 32 stages and the like as shown in FIG. 31. The selection EOR circuits 2831a to 2831d each have an EOR circuit 2891 and a selector 2892 as shown in FIG. 28B. The EOR circuit 2891 computes EOR of the input signals A1 and B1, and outputs the signal A2. The selector 2892 selects and outputs the signal A1 or the signal A2.

In FIG. 31, the selection EOR circuit 2831a receives an output signal 3100 of the flip flop FF0, and outputs it to a selection EOR circuit 2831b of the next stage. The signal 3100 is outputted to the internal state selector 2821 (FIG. 28A) as an in-progress operation result.

The selection EOR circuit 2831b receives an output signal 3101 of the flip flop FF1 and the output signal of the selection EOR circuit 2831a, and outputs the result to a selection EOR circuit 2831c of the next stage. The signal 3101 is outputted to the internal state selector 2821 (see FIG. 28A) as an in-progress operation result [1].

The selection EOR circuit 2831c receives an output signal 3102 of the flip flop FF2 and the output signal of the selection EOR circuit 2831b, and outputs the result to the selection EOR circuit of th