Semiconductor device having ferroelectric capacitor and method for manufacturing the same Number:6,762,065 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor device having ferroelectric capacitor and method for manufacturing the same

Abstract: A lower electrode is formed on an insulating film on a semiconductor substrate. A pair of ferroelectric films are formed on the lower electrode separately from each other. An upper electrode is formed on each of the pair of ferroelectric films. A portion of the lower electrode on which the ferroelectric film is formed is thicker than a portion thereof on which the ferroelectric film is not formed. Such a structure is obtained by sequentially depositing the lower electrode, the ferroelectric film, and the upper electrode on the insulating film, forming a mask on the upper-electrode, using this mask to etch the upper-electrode and the ferroelectric film to thereby pattern a pair of upper electrodes and a pair of ferroelectric electrodes, forming such a mask that continuously covers the pair of upper electrodes and the pair of ferroelectric films, and then etching the lower-electrode material film.

Patent Number: 6,762,065 Issued on 07/13/2004 to Kanaya,   et al.

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Inventors:	Kanaya; Hiroyuki (Yokohama, JP), Taniguchi; Yasuyuki (Tokyo, JP), Ozaki; Tohru (Tokyo, JP), Kumura; Yoshinori (Yokohama, JP)
Assignee:	Kabushiki Kaisha Toshiba (Kawasaki, JP)
Appl. No.:	10/448,359
Filed:	May 30, 2003

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	801920	Mar., 2001	6603161

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Foreign Application Priority Data

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Mar 10, 2000 [JP]			2000-066734
Mar 27, 2000 [JP]			2000-087403
Mar 27, 2000 [JP]			2000-087417

Current U.S. Class:	438/3 ; 257/E21.01; 257/E21.021; 257/E21.252; 257/E21.311; 257/E21.664; 257/E27.104
Current International Class:	H01L 27/115 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/8246 (20060101); H01L 21/311 (20060101); H01L 21/3213 (20060101)
Field of Search:	438/3,396

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References Cited [Referenced By]

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U.S. Patent Documents

	5330931		July 1994		Emesh et al.
	5374578		December 1994		Patel et al.
	5489548		February 1996		Nishioka et al.
	5576240		November 1996		Radosevich et al.
	5777839		July 1998		Sameshima et al.
	5838605		November 1998		Bailey
	5903492		May 1999		Takashima
	5907762		May 1999		Evans et al.
	6081417		June 2000		Matsuki
	6235577		May 2001		Jeon
	6278153		August 2001		Kikuchi et al.
	6284586		September 2001		Seliskar et al.
	6339008		January 2002		Takenaka

Foreign Patent Documents

	4-11-3976		Jun., 1999		JP

Other References

Takashima et al., A Sub-40-ns Chain FRAM Architecture with 7-ns Cell-Plate-Line Drive, Nov. 1999, IEEE Journal of Solid State Circuits, vol. 34, No. 11, pp. 1557-1563. . Takashima et al., Gain Cell Block Architecture for Gigabit-Scale Chain Ferroelectric RAM, 1999, Symposium on VLSI Circuits Digest of Technical Papers, pp. 103-104..

Primary Examiner: Hoang; Huan
Assistant Examiner: Le; Thao P.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

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Parent Case Text

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This application is a divisional application of application Ser. No. 09/801,920, file on Mar. 9, 2001 now U.S. Pat. No. 6,603,161 now U.S. Pat. No. 6,603,161.

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Claims

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What is claimed is:

1. A method for manufacturing a semiconductor device comprising: sequentially forming a lower electrode, a ferroelectric film, and an upper electrode on a first interlayer insulating film formed on a semiconductor substrate; forming a first mask on said upper electrode; using said first mask to sequentially etch said upper electrode and said ferroelectric film to leave on said lower electrode a pair of laminated structure comprising said ferroelectric film and said upper electrode; forming a second mask having such a pattern shape that continuously covers at least said pair of laminated structure; using said second mask to etch said lower electrode to thereby leave portions of said lower electrode in which said pair of laminated structures composing said ferroelectric film and said upper electrode are formed.

2. The method according to claim 1, wherein when said first mask is used to etch said upper electrode and said ferroelectric film, a surface of said lower electrode is etched.

3. The method according to claim 1, further comprising: forming a second interlayer insulating film on the entire top surface after using said second mask to etch said lower electrode; forming a third mask on said interlayer insulating film; using said third mask to etch said second interlayer insulating film to form a pair of first openings leading to surfaces of the upper electrodes of said pair of laminated structure and a second opening leading to a surface of said lower electrode; and forming a pair of first metal layer so as to fill said pair of first openings and forming a second metal layer so as to fill said second opening.

4. A method for manufacturing a semiconductor device comprising: forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate; leaving said lower electrode only at selected portions of said first interlayer insulating film, while removing the other portions; forming a second interlayer insulating film on the entire top surface including a surface of said lower electrode and then executing a flattening process to expose said lower electrode; forming a third interlayer insulating film on the entire top surface and then forming two openings in said third interlayer insulating film so as to lead to the surface of said lower electrode; sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of said two openings; and executing a flattening process to leave laminated structures in said two openings, said laminated structures composing said ferroelectric film and said upper electrode.

5. A method for manufacturing a semiconductor device comprising: forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate; leaving said lower electrode only at selected portions of said first interlayer insulating film, while removing said other portions; forming a second interlayer insulating film on an entire top surface including a surface of said lower electrode and then executing a flattening process; forming two openings in said second interlayer insulating film so as to lead to said surface of said lower electrode; sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of said two openings; and leaving laminated structures only in said two openings, said laminated structures comprising said ferroelectric film and said upper electrode.

6. The method according to claim 5, wherein the step of leaving said laminated structures only in said two openings composes etching back said laminated structures.

7. The method according to claim 5, wherein the step of leaving said laminated structures only in said two openings composes executing a flattening etching process on said laminated structures.

8. A method for manufacturing a semiconductor device comprising: forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate; forming a first opening in said first interlayer insulating film; forming a lower electrode on an entire top surface; executing a flattening process to expose said first interlayer insulating film, while leaving said lower electrode in said first opening; forming a third interlayer insulating film on the entire top surface; forming a pair of second openings in said third interlayer insulating film so as to lead to a surface of said lower electrode; sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of said pair of second openings; and flattening said ferroelectric film and said upper electrode to leave said ferroelectric film and said upper electrode in said pair of second openings.

9. A method for manufacturing a semiconductor device comprising: forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate; forming a first opening in said first interlayer insulating film; forming a first lower electrode on an entire top surface; executing a flattening process to expose said first interlayer insulating film, while leaving said first lower electrode in said first opening; forming a third interlayer insulating film on the entire top surface; forming a pair of second openings in said third interlayer insulating film so as to lead to a surface of said lower electrode; sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of said pair of second openings; and flattening said second lower electrode, said ferroelectric film, and said upper electrode to leave said second lower electrode, said ferroelectric film, and said upper electrode in said pair of second openings.

10. A method for manufacturing a semiconductor device comprising: forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate; leaving said first lower electrode only at selected portions of said first interlayer insulating film, while removing the other portions; forming a second interlayer insulating film on an entire top surface including a surface of said first lower electrode and then executing a flattening process to expose said first lower electrode; forming a third interlayer insulating film on the entire top surface and then forming two openings in said third interlayer insulating film so as to lead to said surface of said lower electrode; sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of said two openings; and executing a flattening process to leave laminated structures in said two openings, said laminated structures composing said second lower electrode, said ferroelectric film, and said upper electrode.

11. A method for manufacturing a semiconductor device comprising: forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate; leaving said first lower electrode only at selected portions of said first interlayer insulating film, while removing the other portions; forming a second interlayer insulating film on the entire top surface including a surface of said first lower electrode and then executing a flattening process; forming two openings in said second interlayer insulating film so as to lead to said surface of said first lower electrode; sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of said two openings; and executing one of an etchback process and flattening etching process to leaving laminated structures only in said two openings, said laminated structures composing said second lower substrate, said ferroelectric film, and said upper electrode.

12. The method according to claim 11, wherein the step of leaving said laminated structures only in said two openings composes etching back said laminated structures.

13. The method according to claim 11, wherein the step of leaving said laminated structures only in said two openings composes executing a flattening etching process on said laminated structures.

14. A method for manufacturing semiconductor storage device comprising: forming a plurality of transistors in and on a semiconductor substrate; forming an interlayer insulating film on the entire top surface; forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on said interlayer insulating film to constitute a plurality of ferroelectric capacitors; forming an etching mask on each upper-electrode forming area of said upper-electrode material film; and using said etching mask to separate said upper electrodes of said plurality of ferroelectric capacitors, while separating, in order to allow said lower electrode to be shared by one set of plurality of ferroelectric capacitors, said lower electrode between the adjacent said ferroelectric capacitors of the set.

15. The method according to claim 14, wherein said etching mask is patterned such that the space between the upper electrodes of said one set of ferroelectric capacitors is smaller than a space between the upper electrodes of said one set of ferroelectric capacitors and the upper electrodes of a different adjacent set of ferroelectric capacitors, and said etching is executed using a space dependency of etching so that when said upper electrode material film, ferroelectric film, and lower electrode material film have been completely etched between said one set of ferroelectric capacitors and the different adjacent set of ferroelectric capacitors, the lower electrode material film remains unetched in said one set of ferroelectric capacitors.

16. A method for manufacturing a semiconductor storage device comprising: forming an isolation film in a semiconductor substrate and partitioning said semiconductor substrate into a plurality of element forming areas; forming a plurality of transistors in each of said plurality of element forming areas, said transistors each having a first and a second diffusion regions in such a manner that said transistor is adjacent, at one side, to said first diffusion region, which is shared by the adjacent transistor on this side, while said transistor is adjacent, at said other side, to said second diffusion region, which is shared by the adjacent transistor on this side; forming a first interlayer insulating film on an entire top surface; burying a contact plug in said first interlayer insulating film, said contact plug being connected to each of said first diffusion regions of said plurality of transistors; sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on said first interlayer insulating film to constitute a plurality of ferroelectric capacitors; forming an etching mask on each upper-electrode forming area of said upper-electrode material film; an etching step of using said etching mask to separate upper electrodes of each of said ferroelectric capacitor while separating said adjacent pairs of ferroelectric capacitors in such a manner that said pair of ferroelectric capacitors share said lower electrode connected to said contact plug; forming a second interlayer insulating film so as to cover the entire top surface; and forming a wiring layer on said second interlayer insulating film, for connecting the upper electrode of said ferroelectric capacitor to said second diffusion region of the corresponding transistor.

17. The method according to claim 16, wherein said etching mask is patterned such that the space between the upper electrodes of said one set of ferroelectric capacitors is smaller than a space between the upper electrodes of said one set of ferroelectric capacitors and the upper electrodes of a different adjacent set of ferroelectric capacitors, and said etching is executed using a space dependency of etching so that when said upper electrode material film, ferroelectric film, and lower electrode material film have been completely etched between said one set of ferroelectric capacitors and the different adjacent set of ferroelectric capacitors, the lower electrode material film remains unetched in said one set of ferroelectric capacitors.

18. A method for manufacturing a semiconductor storage device comprising: forming a plurality of transistors in a semiconductor substrate, said transistors each having a first and a second diffusion regions in such a manner that said transistor is adjacent, at one side, to said first diffusion region, which is shared by the adjacent transistor on this side, while said transistor is adjacent, at said other side, to said second diffusion region, which is shared by the adjacent transistor on this side; forming a first interlayer insulating film on an entire top surface; forming an opening in said first interlayer insulating film so as to lead a surface of said first diffusion region of each of said plurality of transistors and forming a plug electrode in said opening; sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on said first interlayer insulating film so as to contact with said plug electrode; forming a mask pattern for etching said upper-electrode material film so that a pair of upper electrodes are located on said plug electrode; using said mask pattern to etch said upper-electrode material film, said ferroelectric film, and said lower-electrode material film to thereby form a pair of upper electrodes, a ferroelectric film, and a lower electrode on said plug electrode; forming a second interlayer insulating film on the entire top surface; and forming a wiring layer for connecting said second diffusion areas of said plurality of transistors and said upper electrodes together.

19. A method for manufacturing a semiconductor storage device comprising: forming a plurality of transistors in a semiconductor substrate, said transistors each having a first and a second diffusion regions in such a manner that said transistor is adjacent, at one side, to said first diffusion region, which is shared by the adjacent transistor on this side, while said transistor is adjacent, at said other side, to said second diffusion region, which is shared by the adjacent transistor on this side; forming a first interlayer insulating film on an entire top surface; forming a first opening in said first interlayer insulating so as to lead a surface of said first diffusion area of each of said plurality of transistors and forming a plug electrode in said opening; sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on said first interlayer insulating film so as to contact with said plug electrode; forming a mask pattern for etching said upper-electrode material film; using said mask pattern to etch said upper-electrode material film to thereby form a pair of upper electrodes; forming a side wall insulating film on side walls of said pair of upper electrodes and arranging, on said plug electrode, a portion of said side wall insulating film located between said pair of upper electrodes; using said mask pattern and said side wall insulating film to sequentially etch said ferroelectric film and said lower-electrode material film to thereby form a pair of ferroelectric films and a lower electrode on said plug electrode; forming a second interlayer insulating film on the entire top surface; and forming a wiring layer for connecting said second diffusion regions of said plurality of transistors and said upper electrodes together.

20. The method according to claim 19, wherein the step of forming said plug electrode composes burying a plug electrode material in said opening, then etching said plug electrode material back to a position lower than a surface of said first interlayer insulating film, and subsequently depositing and burying in an upper part of said opening, an oxidation-resistant conductive material that does not lose conductivity thereof in an oxidative environment.

21. The method according to claim 19, further comprising: burying, before forming said lower electrode material film, an oxidation-resistant conductive material in said opening so as to contact with a top surface of said plug electrode, the oxidation-resistant conductive material not losing conductivity thereof in an oxidative environment.

22. The method according to claim 19, wherein the step of forming said plug electrode includes a step of burying an oxidation-resistant conductive material in said opening as a plug electrode material, the oxidation-resistant conductive material not losing conductivity thereof in an oxidative environment.

23. The method according to claim 19, wherein the step of forming said wiring layer further comprises steps of forming a second opening in said second interlayer insulating film above the second diffusion region and burying the plug electrode in said second opening.

24. The method according to claim 19, wherein when the side wall insulating film is formed on the side walls of said pair of upper electrodes, said side wall insulating film located between said pair of upper electrodes substantially fills a space between said pair of upper electrodes.

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Description

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-066734, filed Mar. 10, 2000; No. 2000-087403, filed Mar. 27, 2000; and No. 2000-087417, filed Mar. 27, 2000, the entire contents of all of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the ferroelectric capacitor.

Ferroelectric substances have a hysteresis characteristic between applied electric fields and the amount of electric polarization; thus, polarization remains even if a voltage applied between opposite ends of the ferroelectric substance is returned to zero. That is, the ferroelectric substance is characterized in that electric polarization generated when electric fields are applied remains even after the application of electric fields has been stopped and in that the direction of the polarization is reversed when electric fields of a certain intensity or more are applied in a direction opposite to that of the above electric fields.

Memory which consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, hereafter named "Series connected TC unit type ferroelectric RAM" is gathering the industry's attention. In these Series connected TC unit type ferroelectric RAMs, the cell area per memory cell is reduced based on the non-volatile characteristic of ferroelectric substances, by connecting opposite ends of a ferroelectric capacitor (C) between a source and a drain of a cell transistor (T) to constitute a unit cell and connecting a plurality of such unit cells in series.

These Series connected TC unit type ferroelectric RAMs are known, for example, from "High-Density Chain Ferroelectric Random Access Memory (CFRAM)", VLSI Circuit Symposium, 1997, p.83-84, "A Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drive", ISSCC Tech. Digest Papers, pp.102-103, Feb 1999, and "Ferro Electric RAM", D. Takashima et al., JSSCC, pp.787-792, May 1998".

FIG. 1 shows an equivalent circuit of the Series connected TC unit type ferroelectric RAMs described in these documents. In this figure, eight transistors T0 to T7 are connected in series, and ferroelectric capacitors are each connected between a source and a drain of a corresponding one of the transistors to constitute a cell array block. The cell array block has one end connected to a bit line BL via a selection gate transistor ST1 and the other end connected to a plate line PL via a selection gate transistor ST2 (or directly).

The transistors T0 to T7 have their gates connected to word lines WL0 to WL7, respectively, and the selection gate transistors ST1 and ST2 have their gates connected to selection gate lines BS1 and BS2, respectively. Specifically, the word lines WL0 to WL7 and the selection gate lines BS1 and BS2 are configured by continuously forming corresponding gate electrodes between a plurality of other cell array blocks (not shown).

The Series connected TC unit type ferroelectric RAMs are advantageous in that the unit cell area can be reduced by sharing a diffusion layer of the adjacent transistor within the cell array block; theoretically, these memories can achieve 4F.sup.2 (F denotes a minimum size). Further, the area occupied by peripheral circuits can be reduced compared to ordinary ferroelectric memories, thereby reducing the chip size and costs.

The Series connected TC unit type ferroelectric RAMs also have an excellent characteristic that the plate line PL connected to the other end can be formed of the diffusion layer formed outside the cell array and thus has low resistance, whereby drivers are not required to have high performance. The Series connected TC unit type ferroelectric RAMs can thus operate faster than ordinary ferroelectric memories.

As described above, the Series connected TC unit type ferroelectric RAMs have various characteristics, but also have problems.

That is, for memory cells of a capacitor on plug (COP) structure in which, for example, a tungsten plug (W plug) is formed on a source and a drain diffusion layer of a transistor as a contact plug with a ferroelectric capacitor formed on the W plug, a barrier metal must be interposed between the W plug and the ferroelectric capacitor to prevent oxidation of the W plug, but no metal has been found suitable to be such a barrier metal.

Thus, an upper and a lower electrode of the ferroelectric capacitor are connected to the source and drain diffusion layers of the transistor by separately forming metal wiring.

FIGS. 2A to 2E show a conventional method for manufacturing a ferroelectric capacitor for a series connected TC unit type ferroelecric RAM, in the order of steps.

First, as shown in FIG. 2A, a lower electrode 12, a ferroelectric film 13, and an upper electrode 14 are sequentially deposited on an interlayer insulating film 11 provided on a semiconductor substrate.

Then, as shown in FIG. 2B, an etching mask 15 having a predetermined pattern shape is formed and used to etch the upper electrode 14.

Then, the mask 15 is removed and a new etching mask 16 having a predetermined pattern shape is subsequently formed as shown in FIG. 2C. In this case, the mask 16 is shaped so as to continuously cover the two upper electrodes 14. The mask 16 us used to etch the remaining part of the ferroelectric film 13 and lower electrode 12.

Then, as shown in FIG. 2D, an interlayer insulating film 17 is deposited on the entire top surface, wiring grooves 18 and contact holes 19 for the two upper electrodes 14 are formed in the interlayer insulating film 17, and a wiring groove 20 and a contact hole 21 for the lower electrode 12 are further formed.

Subsequently, contact plugs/wires 22 are formed so as to fill the wiring grooves 18 and 20 and the contact holes 19 and 21. The contact plugs/wires 22 are connected to a source and a drain diffusion layers of a transistor (not shown).

In this conventional method, when the contact hole 21 for the lower electrode 12 is formed, the interlayer insulated layer 17 and the ferroelectric film 13 must be etched. An etching rate for the ferroelectric film is low, about one tenths (for example, 50 nm/sec.) of that for the interlayer insulating film, thus requiring a large amount of time to form the deep contact hole 21 for the lower electrode 12. Consequently, when the contact holes 19 for the upper electrodes 14 are formed, relatively large parts of the upper electrodes 14 are removed as shown in FIG. 2D, thereby disadvantageously degrading capacitor characteristics or inducing capacitor leakage.

Furthermore, it has been found that since the contact hole 21 for the lower electrode 12 penetrates the ferroelectric film 13, an etching gas may damage the ferroelectric film to degrade polarization.

BRIEF SUMMARY OF THE INVENTION

The present invention has been made in view of the foregoing. An object of the invention is to provide a semiconductor device, a semiconductor storage device and a method of manufacturing the same, in which the degradation of capacitor characteristics or the capacitor leakage is prevented when a part of the upper electrode is etched in the process of making contact holes and in which the damage to the ferroelectric film is reduced to prevent the deterioration of the ferroelectric capacitor, which would otherwise occur due to polarization.

According to the present invention, there is provided a semiconductor device comprising a first interlayer insulating film formed on a semiconductor substrate, a lower electrode formed on the first interlayer insulating film, a pair of ferroelectric films formed on the lower electrode separately from each other, and a pair of upper electrode formed on the pair of ferroelectric films, wherein the lower electrode, the pair of ferroelectric films, and the pair of upper electrodes constitute a pair of ferroelectric capacitors and portions of the lower electrode which are located under the pair of ferroelectric films are thicker than the other portions of the lower electrode.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising sequentially forming a lower electrode, a ferroelectric film, and an upper electrode on a first interlayer insulating film formed on a semiconductor substrate, forming a first mask on the upper electrode, using the first mask to sequentially etch the upper electrode and the ferroelectric film to leave on the lower electrode a pair of laminated structure comprising the ferroelectric film and the upper electrode, forming a second mask having such a pattern shape that continuously covers at least the pair of laminated structure, using the second mask to etch the lower electrode to thereby leave portions of the lower electrode in which the pair of laminated structures comprising the ferroelectric film and the upper electrode are formed.

According to the present invention, there is provide a semiconductor device comprising an interlayer insulating film formed on a semiconductor substrate, a lower electrode formed on the interlayer insulating film, a pair of ferroelectric films formed on the lower electrode separately from each other and each having a recess portion, and a pair of upper electrodes formed so as to fill recess portions of the pair of ferroelectric films, wherein the lower electrode, the pair of ferroelectric films, and the pair of upper electrode constitute a pair of ferroelectric capacitors.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the lower electrode and then executing a flattening process to expose the lower electrode, forming a third interlayer insulating film on the entire top surface and then forming two openings in the third interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the two openings, and executing a flattening process to leave laminated structures in the two openings, the laminated structures comprising the ferroelectric film and the upper electrode.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the lower electrode and then executing a flattening process, forming two openings in the second interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the two openings, and leaving laminated structures only in the two openings, the laminated structures comprising the ferroelectric film and the upper electrode.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate, forming a first opening in the first interlayer insulating film, depositing a lower electrode on the entire top surface, executing a flattening process to expose the first interlayer insulating film, while leaving the lower electrode in the first opening, forming a third interlayer insulating film on the entire top surface, forming a pair of second openings in the third interlayer insulating film so as to lead to a surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the pair of second openings, and flattening the ferroelectric film and the upper electrode to leave the ferroelectric film and the upper electrode in the pair of second openings.

According to the present invention, there is provide a semiconductor device comprising a first interlayer insulating film formed on a semiconductor substrate, a first lower electrode formed on the first interlayer insulating film, a pair of second lower electrodes formed on the first lower electrode separately from each other and each having a recess portion, a pair of ferroelectric films formed so as to fill recess portions of the pair of second lower electrodes and each having a recess portion, and a pair of upper electrodes formed so as to fill recess portions of the pair of ferroelectric films, wherein the first lower electrode, the pair of second lower electrodes, the pair of ferroelectric films, and the pair of upper electrode constitute a pair of ferroelectric capacitors.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate, forming a first opening in the first interlayer insulating film, forming a first lower electrode on the entire top surface, executing a flattening process to expose the first interlayer insulating film, while leaving the first lower electrode in the first opening, forming a third interlayer insulating film on the entire top surface, forming a pair of second openings in the third interlayer insulating film so as to lead to a surface of the lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the pair of second openings, and flattening the second lower electrode, the ferroelectric film, and the upper electrode to leave the second lower electrode, the ferroelectric film, and the upper electrode in the pair of second openings.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the first lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the first lower electrode and then executing a flattening process to expose the first lower electrode, forming a third interlayer insulating film on the entire top surface and then forming two openings in the third interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the two openings, executing a flattening process to leave laminated structures in the two openings, the laminated structures comprising the second lower electrode, the ferroelectric film, and the upper electrode.

According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the first lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the first lower electrode and then executing a flattening process, forming two openings in the second interlayer insulating film so as to lead to the surface of the first lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the two openings, and executing one of an etchback process and flattening etching process to leaving laminated structures only in the two openings, the laminated structures composing the second lower substrate, the ferroelectric film, and the upper electrode.

According to the present invention, there is provide a semiconductor storage device comprising a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate, a first interlayer insulating film formed so as to cover the plurality of transistors, and a plurality of ferroelectric capacitors each comprising a laminated structure of a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the first interlayer insulating film, wherein the plurality of ferroelectric capacitors constitute sets each comprising two of these ferroelectric capacitors, the lower electrode is shared by the one set of ferroelectric capacitors, the upper electrode is individually separated between the one set of ferroelectric capacitors, and a space between the upper electrodes of the one set of ferroelectric capacitors is smaller than a space between the upper electrodes of the one set of ferroelectric capacitors and the upper electrodes of an adjacent set of ferroelectric capacitors.

More specifically, the one set of ferroelectric capacitors have their peripheries formed into inclined surfaces extending continuously from a top surface of the upper electrode to a bottom surface of the lower electrode and having no step, and the individual upper electrodes of the one set of ferroelectric capacitors are separated by a generally V-shaped groove.

Thus, the upper electrodes of the ferroelectric capacitors are not spaced at equal intervals, and the space between the upper electrodes of one set of ferroelectric capacitors on the shared lower electrode is smaller than the space between the upper electrodes of one set of ferroelectric capacitors and the upper electrodes of the adjacent set of ferroelectric capacitors, thereby reducing the unit cell area.

According to the present invention, the semiconductor substrate preferably partitioned into a plurality of element forming areas each having the plurality of transistor formed therein, adjacent ones of the plurality of transistors share a diffusion area and are arranged in a row, and the ferroelectric capacitors are connected in parallel with the transistors to constitute a cell array block.

In this case, gate electrodes of the transistors extended in a direction crossing a transistor arranging direction of the cell array block constitute a word line, and the space between the upper electrodes of the one set of ferroelectric capacitors is smaller than the width of the word line.

When the upper electrodes are separated by the space smaller than the width of the word line, the upper electrodes have larger areas to provide excellent characteristics even if the ferroelectric capacitors are arranged at a very small pitch. Specifically, the word line width is equal to a minimum dimension according to design rules.

Furthermore, according to the present invention, there is provide a semiconductor storage device comprising a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate, a first interlayer insulating film formed so as to cover the plurality of transistors, and a plurality of ferroelectric capacitors each comprising a laminated structure of a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the first interlayer insulating film, wherein the plurality of ferroelectric capacitors constitute sets each comprising two of these ferroelectric capacitors, the lower electrode is shared by the one set of ferroelectric capacitors, the upper electrode is individually separated between the one set of ferroelectric capacitors and has a space, the one set of ferroelectric capacitors have peripheries thereof formed into inclined surfaces extending continuously from a top surface of the upper electrode to a bottom surface of the lower electrode and having no step, and the individual upper electrodes of the one set of ferroelectric capacitors are separated by a generally V-shaped groove.

According to the present invention, there is provided a method for manufacturing semiconductor storage device comprising forming a plurality of transistors in and on a semiconductor substrate, forming an interlayer insulating film on the entire top surface, forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the interlayer insulating film to constitute a plurality of ferroelectric capacitors, forming an etching mask on each upper-electrode forming area of the upper-electrode material film, using the etching mask to separate the upper electrodes of the plurality of ferroelectric capacitors, while separating, in order to allow the lower electrode to be shared by one set of plurality of ferroelectric capacitors, the lower electrode between the adjacent ferroelectric capacitors of the set.

According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming an isolation film in a semiconductor substrate and partitioning the semiconductor substrate into a plurality of element forming areas, forming a plurality of transistors in each of the plurality of element forming areas, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, burying a contact plug in the first interlayer insulating film, the contact plug being connected to each of the first diffusion areas of the plurality of transistors, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film to constitute a plurality of ferroelectric capacitors, forming an etching mask on each upper-electrode forming area of the upper-electrode material film, using the etching mask and etching to separate upper electrodes of each of the ferroelectric capacitor while separating the adjacent pairs of ferroelectric capacitors in such a manner that the pair of ferroelectric capacitors share the lower electrode connected to the contact plug, forming a second interlayer insulating film so as to cover all of the top surface, and a step of forming a wiring layer on the second interlayer insulating film, for connecting the upper electrode of the ferroelectric capacitor to the second diffusion region of the corresponding transistor.

According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming a plurality of transistors in a semiconductor substrate, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, forming an opening leading to a surface of the first diffusion region of each of the plurality of transistors and forming a plug electrode in the opening, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film so as to contact with the plug electrode, forming a mask pattern for etching the upper-electrode material film so that a pair of upper electrodes are located on the plug electrode, using the mask pattern to etch the upper-electrode material film, the ferroelectric film, and the lower-electrode material film to thereby form a pair of upper electrodes, a ferroelectric film, and a lower electrode on the plug electrode, forming a second interlayer insulating film on the entire top surface, and forming a wiring layer for connecting the second diffusion regions of the plurality of transistors and the upper electrodes together.

According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming a plurality of transistors in a semiconductor substrate, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, forming a first opening leading to a surface of the first diffusion region of each of the plurality of transistors and forming a plug electrode in the opening, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film so as to contact with the plug electrode, forming a mask pattern for etching the upper-electrode material film, using the mask pattern to etch the upper-electrode material film to form a pair of upper electrodes, forming a side wall insulating film on side walls of the pair of upper electrodes and arranging, on the plug electrode, a portion of the side wall insulating film located between the pair of upper electrodes, using the mask pattern and the side wall insulating film to sequentially etch the ferroelectric film and the lower-electrode material film to form a pair of ferroelectric films and a lower electrode on the plug electrode, forming a second interlayer insulating film on the entire top surface, and forming a wiring layer for connecting the second diffusion regions of the plurality of transistors and the upper electrodes together.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is an equivalent circuit diagram of a series connected TC unit type ferroelectric RAM;

FIGS. 2A to 2E are sectional views showing a conventional method for manufacturing a ferroelectric capacitor of the series connected TC unit type ferroelectric RAM, in the order of steps;

FIGS. 3A to 3F show a method for manufacturing a series connected TC unit type ferroelectric RAM according to a first embodiment of the present invention, in the order of steps;

FIG. 4 is a pattern top view of the series connected TC unit type ferroelectric RAM shown in FIG. 3F;

FIG. 5 is a sectional view of a sectional structure obtained after the step in FIG. 2B according to a conventional method and a sectional structure of a capacitor obtained after the step in FIG. 3C according to the first embodiment;

FIG. 6 is a sectional view showing a step of a method for manufacturing a series connected TC unit type ferroelectric RAM according to a first variation of the first embodiment of the present invention;

FIG. 7 is a sectional view showing a step of the method for manufacturing a series connected TC unit type ferroelectric RAM according to the first variation of the first embodiment of the present invention, the step being different from that in FIG. 6;

FIG. 8 is a view showing the sectional structure of a series connected TC unit type ferroelectric RAM of a COP structure according to a second embodiment of the present invention, which has been manufactured in the same manner as in the first embodiment;

FIGS. 9A to 9F are sectional views showing a method for manufacturing a series connected TC unit type ferroelectric RAM according to a third embodiment of the present invention, in the order of steps;

FIGS. 10A to 10D are sectional views showing several steps of manufacturing a series connected TC unit type ferroelectric RAM according to a first variation of the third embodiment of the present invention;

FIG. 11 is a sectional view showing a step of manufacturing a series connected TC unit type ferroelectric RAM according to a second variation of the third embodiment of the present invention;

FIGS. 12A to 12C are sectional views showing several steps of manufacturing a series connected TC unit type ferroelectric RAM according to a third variation of the third embodiment of the present invention;

FIGS. 13A and 13B are sectional views showing several steps of manufacturing a series connected TC unit type ferroelectric RAM according to a fourth variation of the third embodiment of the present invention;

FIGS. 14A to 14C are sectional views showing several steps of manufacturing a series connected TC unit type ferroelectric RAM according to a fifth variation of the third embodiment of the present invention;

FIG. 15 is a sectional view showing the sectional structure of a series connected TC unit type ferroelectric RAM of the COP structure according to a fourth embodiment of the present invention, which has been manufactured in the same manner as in the third embodiment;

FIGS. 16A to 16G are sectional views showing a method for manufacturing a series connected TC unit type ferroelectric RAM according to a fifth embodiment of the present invention, in the order of steps;

FIGS. 17A to 17C are sectional views showing several steps of manufacturing a series connected TC unit type ferroelectric RAM according to a first variation of the fifth embodiment of the present invention;

FIG. 18 is a sectional view showing a step of manufacturing a series connected TC unit type ferroelectric RAM according to a second variation of the fifth embodiment of the present invention;

FIG. 19 is a sectional view showing the sectional structure of a series connected TC unit type ferroelectric RAM of the COP structure according to a sixth embodiment of the present invention, which has been manufactured in the same manner as in the fifth embodiment;

FIGS. 20A to 20E are sectional views showing a method for manufacturing a series connected TC unit type ferroelectric RAM according to a seventh embodiment of the present invention, in the order of steps;

FIG. 21 is a sectional view showing a step of manufacturing a series connected TC unit type ferroelectric RAM according to a first variation of the seventh embodiment of the present invention;

FIG. 22 is a sectional view showing a step of the method for manufacturing a series connected TC unit type ferroelectric RAM according to the first variation of the seventh embodiment of the present invention, the step being different from that in FIG. 21;

FIG. 23A is a view showing a layout of a cell array area of a series connected TC unit type ferroelectric RAM according to an eighth embodiment of the present invention;

FIGS. 23B and 23C are different sectional views of FIG. 23A;

FIGS. 24A to 24F are sectional views showing specific steps of manufacturing the series connected TC unit type ferroelectric RAM according to the eight embodiment of the present invention;

FIG. 25 is a sectional view of a step of etching an upper electrode according to a comparative example;

FIG. 26 is a sectional view of a step of etching a lower electrode according to a comparative example;

FIGS. 27A and 27B are a top view and a sectional view showing how ferroelectric capacitors are arranged in the series connected TC unit type ferroelectric RAM according to the eighth embodiment of the present invention;

FIGS. 28A and 28B are a top view and a sectional view showing how ferroelectric capacitors are arranged in a series connected TC unit type ferroelectric RAM according to a comparative example;

FIGS. 29A and 29B are sectional views of a series connected TC unit type ferroelectric RAM according to a ninth embodiment of the present invention;

FIG. 30 is an equivalent circuit diagram of a series connected TC unit type ferroelectric RAM having a cell array of one transistor and one capacitor according to the present invention;

FIG. 31 is a sectional view showing the element structure of the series connected TC unit type ferroelectric RAM shown in FIG. 30 as seen in the direction of word lines;

FIG. 32A is a view showing a layout of a cell array area of a series connected TC unit type ferroelectric RAM according to a tenth embodiment of the present invention;

FIGS. 32B and 32C are different sectional views of FIG. 32A;

FIGS. 33A, 33B, 34A, 34B, 35A, 35B, 36A, 36B, 37A, 37B, 38A, 38B, 39A, and 39B are sectional views showing steps of manufacturing the series connected TC unit type ferroelectric RAM according to the tenth embodiment of the present invention;

FIGS. 40A and 40B are different sectional views of a cell array area of a series connected TC unit type ferroelectric RAM according to an eleventh embodiment of the present invention;

FIGS. 41A and 41B are different sectional views of a cell array area of a series connected TC unit type ferroelectric RAM according to a twelfth embodiment of the present invention;

FIG. 42A is a view showing a layout of a cell array area of a series connected TC unit type ferroelectric RAM according to a thirteenth embodiment of the present invention;

FIGS. 42B and 42C are different sectional views of FIG. 42A;

FIGS. 43A, 43B, 44A, 44B, 45A, 45B, 46A, 46B, 47A, 47B, 48A, 48B, 49A, and 49B are sectional views showing steps of manufacturing the series connected TC unit type ferroelectric RAM according to the thirteenth embodiment of the present invention;

FIGS. 50A and 50B are different sectional views of a cell array area of a series connected TC unit type ferroelectric RAM according to a fourth embodiment of the present invention;

FIGS. 51A and 51B are different sectional views of a cell array area of a series connected TC unit type ferroelectric RAM according to a fifteenth embodiment of the present invention; and

FIGS. 52A and 52B are different sectional views of a cell array area of a series connected TC unit type ferroelectric RAM according to a sixteenth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 3A to 3F show a method for manufacturing a series connected TC unit type ferroelectric RAM according to a first embodiment of the present invention, in the order of steps.

First, as shown in FIG. 3A, a lower electrode 32, a ferroelectric film 33, and an upper electrode 34 are sequentially deposited, by means of the CVD or sputtering process, on an interlayer insulating film (SiO.sub.2) 31 on a silicon semiconductor substrate (not shown) having elements such as switching transistors formed thereon. The lower electrode 32 composes, for example, one Pt film layer but may comprise one film layer containing at least one metal selected from IrO.sub.x, Ru, Ti, Al, Sr, Re, Mg, La, and Ca or a plurality of film layers containing different metals.

The lower electrode 32 has a thickness of, for example, 100 nm. The ferroelectric film 33 composes, for example, SBT but may comprise a lead zirconate titanate (PZT: PbZr.sub.1-x Ti.sub.x O.sub.3), or STB or BTO of a composite provskite structure. The ferroelectric film 33 has a thickness of, for example. 150 nm. Furthermore, like the lower electrode 32, the upper electrode 34 comprises, for example, one Pt film layer but may composes one film layer containing at least one metal selected from IrO.sub.x, Ru, Ti, Al, Sr, Re, Mg, La, and Ca or a plurality of film layers containing different metals. The upper electrode 34 has a thickness of, for example, 100 nm.

Then, as shown in FIG. 3B, an etching resist mask 35 having a predetermined pattern shape is formed on the upper electrode 34. A hard mask composing W.sub.x N.sub.y, Ti.sub.x N.sub.y, SiO.sub.2, Al.sub.2 O.sub.3, alumina, or a combination thereof may be formed instead of the resist mask 35.

Subsequently, as shown in FIG. 3C, the upper electrode 34 and the ferroelectric film 33 are etched by means of a dry etching process, for example, the RIE (Reactive Ion Etching) process using the mask 35, to leave a pair of laminate structures 36 on the lower electrode 32, the structures composing the upper elec