Semiconductor device and its manufacturing method Number:6,770,974 from the United States Patent and Trademark Office (PTO) owispatent The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film.As a result, when the smoothing film is formed, at least the dielectric film does not sustain damage and so a capacitance element having less fluctuation in its characteristics and high reliability can be obtained.<H manufacturing, Semiconductor, Semiconductor, d, 6770974.html, Patent, pto, 6770974

Title: Semiconductor device and its manufacturing method

Abstract: The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film.As a result, when the smoothing film is formed, at least the dielectric film does not sustain damage and so a capacitance element having less fluctuation in its characteristics and high reliability can be obtained.

Patent Number: 6,770,974 Issued on 08/03/2004 to Ejiri

Inventors: Ejiri; Hirokazu (Tokyo, JP)
Assignee: Sony Corporation (Tokyo, JP)

Appl. No.: 10/069,901

Filed: July 1, 2002

PCT Filed: June 29, 2001

PCT No.: PCT/JP01/05663

PCT Pub. No.: WO02/03458

PCT Pub. Date: January 10, 2002

Foreign Application Priority Data


Jun 30, 2000 [JP]			2000-199309

Current U.S. Class: 257/758 ; 257/750; 257/763; 257/764; 257/765; 257/773; 257/774; 257/E21.011; 257/E27.048

Current International Class: H01L 27/08 (20060101); H01L 21/02 (20060101)

Field of Search: 257/758,750,763-764,773,774,765

References Cited [Referenced By]

U.S. Patent Documents


6255737	July 2001	Hashimoto
6358837	March 2002	Miller et al.
6384481	May 2002	Hussein et al.
6433435	August 2002	Lin et al.

Foreign Patent Documents


4-372175	Dec., 1992	JP
05-095048	Apr., 1993	JP
11-274409	Oct., 1999	JP
11-317498	Nov., 1999	JP
2001-185687	Jul., 2001	JP

Primary Examiner: Clark; Jasmine
Attorney, Agent or Firm: Sonnenschein, Nath & Rosenthal LLP

Claims

What is claimed is:

1. A semiconductor device characterized by comprising: a lower electrode that is formed on a semiconductor substrate through a first insulation film and has a recess form section in which the surface of its periphery lies on a higher level than the surface of its center; an upper electrode that is formed on the center of the lower electrode through a dielectric film, the surface of which lies on a lower level than the surface of the periphery of the lower electrode; and a second insulation film that fills a recess of the lower electrode having the recess form section.

2. A semiconductor device according to claim 1, characterized in that: a third insulation film is formed on the periphery of the lower electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film; and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

3. A semiconductor device according to claim 1, characterized in that a dummy layer provided below the periphery of the lower electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

4. A semiconductor device according to claim 2, characterized in that a dummy layer provided below the periphery of the lower electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

5. A semiconductor device characterized by comprising: a lower electrode formed on a semiconductor substrate through a first insulation film; a dummy electrode having the surface higher than the surface of the lower electrode; an upper electrode formed on the lower electrode through a dielectric film, the surface of which lies on a level lower than the top surface of the dummy electrode; and a second insulation film that fills a recess surrounded by the dummy electrode.

6. A semiconductor device according to claim 5, characterized in that: a third insulation film is formed on the dummy electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film; and a second wiring layer that is connected to the lower electrode through a second via-hole opened in the inter-layer insulation film.

7. A semiconductor device according to claim 5, characterized in that a dummy layer provided below the dummy electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

8. A semiconductor device according to claim 5, characterized in that a dummy layer provided below the dummy electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

9. A semiconductor device characterized by comprising: a lower electrode that is formed on a semiconductor substrate through a first insulation film and has a recess form section in which the surface of its periphery lies on a level higher than the surface of its center; an upper electrode that is formed on the center of the lower electrode through a dielectric film and has the surface lower in level than the surface of the periphery of the lower electrode; and a second insulation film that fills a recess of the lower electrode having a recess form section and also covers the surface of the upper electrode.

10. A semiconductor device according to claim 9, characterized in that: a third insulation film is formed on the periphery of the lower electrode and the second insulation film to make an inter-layer insulation film; a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film; and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

11. A semiconductor device according to claim 9, characterized in that a dummy layer provided below the periphery of the lower electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

12. A semiconductor device according to claim 10, characterized in that a dummy layer provided below the periphery of the lower electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

13. A semiconductor device characterized by comprising: a lower electrode formed on a semiconductor substrate through a first insulation film; a dummy electrode that is formed on the periphery of the lower electrode and has the surface higher in level than the surface of the lower electrode; an upper electrode that is formed on the lower electrode through a dielectric film and has the surface lower in level than the top surface of the dummy electrode; and a second insulation film that fills a recess surrounded by the dummy electrode and also covers the surface of the lower electrode and upper electrode.

14. A semiconductor device according to claim 13, characterized in that: a third insulation film is formed on the dummy electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film; and a second wiring layer that is connected to the lower electrode through a second via-hole opened in the inter-layer insulation film.

15. A semiconductor device according to claim 13, characterized in that the dummy layer provided below the dummy electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

16. A semiconductor device according to claim 14, characterized in that the dummy layer provided below the dummy electrode for making a level difference is formed out of a layer of the same material as that of an electrode or a resistance layer of another element.

17. A method of fabricating a semiconductor device characterized by comprising the steps of: forming a dummy layer having a predetermined thickness for making a level difference on the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; forming a lower electrode that has a recess form section in which the surface of its periphery lies on a level higher than the surface of its center, on the predefined area of forming the capacitance element, by piling a conductor film on the first insulation film and the dummy layer and then patterning the conductor film; forming an upper electrode on the center of the lower electrode through a dielectric film, the surface of which lies on a level lower than the surface of the periphery of the lower electrode; and forming a second insulation film on the whole surface of a base body to fill a recess of the lower electrode having the recess form section.

18. A method of fabricating a semiconductor device according to claim 17, characterized by further comprising the steps of: forming a third insulation film on the whole surface of the base body including the periphery of the lower electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also opening a second via-hole in the inter-layer insulation film on the periphery of the lower electrode; and forming a first wiring layer that is connected to the upper electrode through the first via-hole and also forming a second wiring layer that is connected to the periphery of the lower electrode through the second via-hole.

19. A method of fabricating a semiconductor device according to claim 17, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

20. A method of fabricating a semiconductor device according to claim 18, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

21. A method of fabricating a semiconductor device characterized by comprising the steps of: forming a dummy layer having a predetermined thickness for making a level difference, around a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; forming a lower electrode in the predefined area of forming a capacitance element by piling a conductor film on the first insulation film and the dummy layer, thereafter patterning the conductor film, and also forming a dummy electrode that covers the dummy layer and has the surface higher than the surface of the lower electrode, around the predefined area of forming a capacitance element; forming an upper electrode on the lower electrode through a dielectric film, the surface of which lies on a level lower than the top surface of the dummy electrode; and forming a second insulation film on the whole surface of a base body to fill a recess surrounded by the dummy electrode.

22. A method of fabricating a semiconductor device according to claim 21, characterized by further comprising the steps of: forming a third insulation film on the whole surface of the base body including the dummy electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also opening a second via-hole in the inter-layer insulation film on the lower electrode; and forming a first wiring layer that is connected to the upper electrode through the first via-hole and also forming a second wiring layer that is connected to the lower electrode through the second via-hole.

23. A method of fabricating a semiconductor device according to claim 21, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

24. A method of fabricating a semiconductor device according to claim 22, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

25. A method of fabricating a semiconductor device characterized by comprising the steps of: forming a dummy layer having a predetermined thickness for making a level difference on the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; forming a lower electrode having a recess form section in which the surface of its periphery lies on a level higher than the surface of its center, in a predefined area of forming a capacitance element, by piling a conductor film on the first insulation film and the dummy layer and then patterning the conductor film; foaming an upper electrode, the surface of which lies on a level lower than the surface of the periphery of the lower electrode, on the center of the lower electrode through a dielectric film; and forming a second insulation film on the whole surface of a base body to fill a recess of the lower electrode having a recess form section and also cover the surface of the upper electrode.

26. A method of fabricating a semiconductor device according to claim 25, characterized by further comprising the steps of: forming a third insulation film on the whole surface of the base body including the periphery of the lower electrode and the second insulation film to make an inter-layer insulation film; opening a first via-hole in the inter layer insulation film on the upper electrode and also opening a second via-hole in the inter-layer insulation film on the periphery of the lower electrode; and forming a first wiring layer that is connected to the upper electrode through the first via-hole and also forming a second wiring layer that is connected to the periphery of the lower electrode through the second via-hole.

27. A method of fabricating a semiconductor device according to claim 25, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

28. A method of fabricating a semiconductor device according to claim 26, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

29. A method of fabricating a semiconductor device characterized by comprising the steps of: forming a dummy layer having a predetermined thickness for making a level difference around a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; forming a lower electrode in the predefined area of forming a capacitance element by piling a conductor film on the first insulation film and the dummy layer, thereafter patterning the conductor film, and also forming a dummy electrode that covers the dummy layer and has the surface higher than the surface of the lower electrode, around the predefined area of forming a capacitance element; forming an upper electrode, the surface of which lies on a level lower than the top surface of the dummy electrode, on the lower electrode through a dielectric film; and forming a second insulation film on the whole surface of a base body to fill a recess surrounded by the dummy electrode and also cover the surface of the lower electrode and upper electrode.

30. A method of fabricating a semiconductor device according to claim 29, characterized by further comprising the steps of: forming a third insulation film on the whole surface of the base body including the dummy electrode and the second insulation film to make an inter-layer insulation film opening a first via-hole in the inter-layer insulation film on the upper electrode and also opening a second via-hole in the inter-layer insulation film on the lower electrode; and forming a first wiring layer that is connected to the upper electrode through the first via-hole and also forming a second wiring layer that is connected to the lower electrode through the second via-hole.

31. A method of fabricating a semiconductor device according to claim 29, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of an electrode and a resistance layer of another element.

32. A method of fabricating a semiconductor device according to claim 30, characterized in that the step of forming the dummy layer for making a level difference is combined with a step of forming an electrode or a resistance layer of another element.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and its fabricating method. Particularly, it relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate and a method of fabricating the device.

BACKGROUND ART

A conventional process for fabricating LSI (Large-scale Integrated Circuit) where a capacitance element is formed on a semiconductor substrate will be described with reference to schematic sectional process diagrams of FIG. 39 to FIG. 41.

To start with, as shown in FIG. 39, a first insulation film 12 and a second insulation film 16 which are made of SiO.sub.2 film or the like are piled in turn on a semiconductor substrate 10.

Subsequently, using the sputtering method for example, on the second insulation film 16 are piled a Ti layer, a TiON layer, a Ti layer, an Al--Si layer and a TiN layer in turn from below to form a TiN/Al--Si/Ti/TiON/Ti lamination film.

Subsequently, using CVD (Chemical Vapor Deposition) method for example, on the TiN/Al--Si/Ti/TiON/Ti lamination film is piled a dielectric film of SiO.sub.2, SiN, Ta.sub.2 O.sub.5 and the like. Further, using the sputtering method for example, on the dielectric film is piled a conductor layer of a Ti layer, a TiN layer or the like.

Then, through the photolithographing process and RIT (Reactive Ion Etching) process, these piled conductor layer and dielectric film are selectively removed by etching into a predetermined pattern to form an upper electrode 22 of Ti, TiN and the like on the TiN/Al--Si/Ti/TiON/Ti lamination film through a dielectric film 20 of SiO.sub.2 SiN, Ta.sub.2 O.sub.5 or the like.

Subsequently, through the photolithographing process and RIE process, the TiN/Al--Si/Ti/TiON/Ti lamination film 18 is selectively removed by etching into a predetermined pattern to form a lower electrode 18d of the TiN/Al--Si/Ti/TiON/Ti lamination film.

In this way, a capacitance element comprised of the upper electrode 22 and the lower electrode 18d which sandwich the dielectric film 20 between them is formed.

Subsequently, using the plasma CVD method for example, which uses TEOS (tetraethoxy silane; Si(OC.sub.2 H.sub.5).sub.4) as raw materials, a SiO.sub.2 film is piled on the whole surface of a base body including the upper electrode 22 and lower electrode 18d. After the SiO.sub.2 film is further coated with SOG (Spin On Glass) film, a smoothing process that etches back these SOG film and SiO.sub.2 film is performed. In other words, unevenness of the surface of the base body is smoothed by filling with a smoothing insulation film 24 formed of the SiO.sub.2 film and SOG film.

Note that, on this occasion, because the surface of the upper electrode 22 formed on the lower electrode 18d lies on a higher level than the surface of the lower electrode 22, the surface of the upper electrode may have sometimes been in a exposed state.

Next, as shown in FIG. 40, using the plasma CVD method for example, an insulation film 26 made of, e.g. SiO.sub.2 film is piled on the whole surface of the base body including the upper electrode 22 and the smoothing insulation film 24. An inter-layer insulation film 27 is thus formed by the smoothing insulation film 24 and insulation film 26.

Subsequently, using the photolithographing process and the dry etching method, the inter-layer insulation film 27 on the upper electrode 22 is selectively removed by etching and the inter-layer insulation film 27 on the lower electrode 18d is also selectively removed by etching to open a first via-hole 28d and a second via-hole 28e. At this time, in order to reduce a contact resistance, TiN in the surface of the lower electrode 18d may sometimes be removed.

Next, as shown in FIG. 41, after an Al-alloy layer is piled on the whole surface of the base body using the sputtering method for example, the Al-alloy layer is processed using the photolithographing process and the dry etching method to form a first Al-alloy upper layer wiring layer 30d and a second Al-alloy upper layer wiring layer 30e that are connected to the upper electrode 22 and the lower electrode 18d through the first and second via-holes 28d and 28e, respectively.

However, in the conventional process of forming a capacitance element, when the smoothing process to smooth unevenness of the surface of the base body by filling with the smoothing insulation film 24 formed of the SiO.sub.2 film and SOG film is performed after a capacitance element comprised of the upper electrode 22 and lower electrode 18d that sandwich the dielectric film 20 between them is formed, because the surface of the upper electrode 22 formed on the lower electrode 18d lies on a higher level than the surface of lower electrode 18d, the upper electrode 22 and further, even the dielectric film 20 lying thereunder is subjected to etching by the etch-back in the smoothing process. That is to say, in the smoothing process, the upper electrode 22 and further the dielectric film 20 lying thereunder sustain damage.

Therefore, there is a problem in which characteristics of a capacitance element such as a capacitance value fluctuate or its reliability deteriorates, so that it is impossible to obtain such a capacitance element that has satisfactory characteristics and high reliability.

Moreover, when the first and second via-holes 28d and 28e are opened so as to form the first and second Al-alloy upper layer wiring layers 30d and 30e connected respectively to the upper electrode 22 and lower electrode 18d of a capacitance element, the film thickness of inter-layer insulation film 27 on the upper electrode 22 to be etched for opening the first via-hole 28d is thicker than the film thickness of inter-layer insulation film 27 on the lower electrode 18d to be etched for opening the second via-hole 28e. Thus, when the first and second via-holes 28d and 28e are both intended to be opened satisfactorily, excess over-etching on the surface of upper electrode 22 will inevitably take place. As a result, the upper electrode 22 or the dielectric film 20 lying thereunder will sustain damage due to the over-etching.

Consequently, this point also raises the problem in which the characteristics of capacitance element such as a capacitance value fluctuate or its reliability deteriorates, thus making it impossible to obtain such a capacitance element that has satisfactory characteristics and high reliability.

Furthermore, the following problem is also raised.

That is, in a conventional capacitance element, when comparison is made between distances from an area where the upper electrode 22 and lower electrode 18d are opposed to each other, which effectively functions as a capacitance element, to the first Al-alloy upper layer wiring layer 30d and to the second Al-alloy upper layer wiring layer 30e, the distance on the lower electrode side generally tends to be longer than that on the upper electrode side. As a result, the difference between their impedances occurs, thereby posing another problem of further adding to asymmetry in its characteristics.

When comparison is made between the first and second via-holes 28d and 28e in the conventional capacitance element, the depth of the second via-hole 28e on the lower electrode side is deeper than the depth of the first via-hole 28d on the upper side electrode side. This further increases the conventional asymmetry of its characteristics.

SUMMARY OF THE INVENTION

The present invention was made in view of the foregoing points at issue. An object of the present invention is to provide a semiconductor device and its fabricating method capable of preventing the fluctuation in characteristics such as capacitance value or deterioration of reliability by damage caused to the upper electrode or dielectric film during the process of fabricating a capacitance element, and further suppressing an increase of asymmetry in characteristics, thereby allowing a capacitance element with satisfactory characteristics and high reliability to be implemented.

A semiconductor device according to the present invention comprises: a lower electrode that is formed on a semiconductor substrate through a first insulation film and has a recess form section in which the surface of its periphery lies on a higher level than that of its center; an upper electrode that is formed on the center of the lower electrode through a dielectric film the surface of which lies on a lower level than that of the periphery of lower electrode; and a second insulation film which fills a recess of the lower electrode having a recess form section.

It should be noted that "the surface lies on a higher level" or "the surface lies on a lower level" used herein is wording to express a level of surface's height with respect to a flat plane of the top or bottom surface of a semiconductor substrate. This definition is hereinafter applied as well.

The present invention further comprises, in the above semiconductor device, an inter-layer insulation film that is formed as a third insulation film in the periphery of lower electrode, the upper electrode and the second insulation film, a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film, and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

A semiconductor device according to the present invention comprises: a lower electrode formed on a semiconductor substrate through a first insulation film; a dummy electrode formed around the lower electrode and having the surface higher than that of the lower electrode; an upper electrode that is formed on the lower electrode through a dielectric film the surface of which lies on a lower level than the top surface of the dummy electrode; and a second insulation layer that fills a recess surrounded by the dummy electrode.

It should be noted that "a dummy electrode having the surface higher than that of the dielectric film" as described above means that the top surface of the dummy electrode is higher than the surface of the lower electrode with a flat plane of the top or bottom surface of a semiconductor substrate as a reference. A description "the top surface of the dummy electrode" means the uppermost surface of surfaces of the dummy electrode. This definition is hereinafter applied as well.

The present invention further comprises, in the above semiconductor device, an inter-layer insulation film that is formed as a third insulation film on the dummy electrode, the upper electrode and the second insulation film, a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film, and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

A semiconductor device according to the present invention comprises: a lower electrode that is formed on a semiconductor substrate through a first insulation film and has a recess form section in which the surface of its periphery lies on a higher level than that of its center; an upper electrode that is formed on the center of the lower electrode through a dielectric film the surface of which lies on a lower level than that of the periphery of lower electrode; and a second insulation film which fills a recess of the lower electrode having a recess form section and at the same time, covers the surface of the upper electrode.

The present invention further comprises, in the above semiconductor device, an inter-layer insulation film that is formed as a third insulation film in the periphery of lower electrode, the upper electrode and the second insulation film, a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film, and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

A semiconductor device according to the present invention comprises: a lower electrode formed on a semiconductor substrate through a first insulation film; a dummy electrode formed around the lower electrode and having the surface higher than that of the lower electrode; an upper electrode formed on the lower electrode through the dielectric film and the surface of which lies on a lower level than the top surface of the dummy electrode; and a second insulation layer that fills a recess surrounded by the dummy electrode and at the same time, covers the surfaces of the lower and upper electrodes.

It should be noted that "a dummy electrode having the surface higher than that of the lower electrode" as described above means that the top surface of the dummy electrode is higher than the surface of the lower electrode with a flat plane of the top or bottom surface of a semiconductor substrate as a reference. A description "the top surface of the dummy electrode" means the uppermost surface of surfaces of the dummy electrode. This definition is hereinafter applied as well.

The present invention further comprises, in the above semiconductor device, an inter-layer insulation film that is formed as a third insulation film on the dummy electrode, the upper electrode and the second insulation film, a first wiring layer that is connected to the upper electrode through a first via-hole opened in the inter-layer insulation film, and a second wiring layer that is connected to the periphery of the lower electrode through a second via-hole opened in the inter-layer insulation film.

In the aforementioned semiconductor device, a dummy layer for making a level difference is provided below the periphery of the lower electrode, whereby the lower electrode is formed so as to have a recess form section.

Also, in the above semiconductor device, a dummy layer for making a level difference is provided below the dummy electrode, whereby the dummy electrode is formed so as to lie on a level higher than the lower electrode.

Such a dummy layer for making a level difference can be formed of the same material as that of an electrode or a resistance layer of other element in a semiconductor device. The dummy layer for making a level difference can also be formed of an insulation layer.

According to a semiconductor device of the present invention, because it comprises a lower electrode having a recess form section in which the surface of its periphery lies on a higher level than the surface of its center, and an upper electrode formed on the center of the lower electrode through a dielectric film the surface of which lies on a lower level than that of the periphery of lower electrode, namely, because the surface of dielectric film on the center of lower electrode with a recess form section is lower than that of the periphery of lower electrode, when the second insulation film serving as a smoothing insulation film on the whole surface of base body is formed, even if the smoothing process of etching back an insulation film or the like piled on the whole surface of base body is executed, the periphery of lower electrode forms an etching stopper which can prevent the dielectric film from sustaining damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

Moreover, in a semiconductor device according to the present invention, the third insulation film is formed on the periphery of lower electrode, the upper electrode and the second insulation film to make an inter-layer insulation film; the first wiring layer connected to the upper electrode through the first via-hole opened in the inter-layer insulation film on the upper electrode being formed; and the second wiring layer connected to the periphery of lower electrode through the second via-hole opened in the inter-layer insulation film on the periphery of lower electrode being formed. Thus, the film thickness of inter-layer insulation film on the upper electrode to be etched for opening the first via-hole is approximately equal to that of inter-layer insulation film on the periphery of lower electrode to be etched for opening the second via-hole. Therefore, when the first and second via-holes are opened, it is possible to prevent the dielectric film under the upper electrode from suffering damage due to an excess overetching to the surface of upper electrode. Consequently, it is possible to obtain a capacitance element which, in addition to the above advantage, has still less fluctuation in its characteristics and higher reliability. Furthermore, in comparing the first via-hole with second via-hole, the depth of the second via-hole opened on the periphery of lower electrode is approximately equal to the depth of the first via-hole opened on the upper electrode. Thus, of the distances from an area where the upper and lower electrodes are opposed to each other and which effectively functions as a capacitance element to the first and second wiring layers, the distance on the lower electrode side which generally tends to be longer than that on the upper electrode side can be shortened. Therefore, it is possible to reduce the difference of their impedances to suppress an increase of asymmetrical characteristics of a capacitance element and thus improve symmetry of characteristics thereof.

A semiconductor device according to the present invention comprises a lower electrode, a dummy electrode formed around the lower electrode and having the surface higher than that of the lower electrode, and an upper electrode formed on the lower electrode through a dielectric film, wherein the surface of the dielectric film on the lower electrode is lower than the top surface of the dummy electrode around the lower electrode. Thus, when the second insulation film serving as a smoothing insulation film is formed on the whole surface of base body, even if a smoothing process to etch back the insulation film piled on the whole surface of base body is performed the dummy electrode becomes an etching stopper and the dielectric film can be prevented from sustaining damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

A semiconductor device according to the present invention comprises a lower electrode having a recess form section in which the surface of its periphery is on a higher level than that of its center, and an upper electrode formed on the center of the lower electrode through a dielectric film and having the surface lower than that of the periphery of lower electrode. In other words, the surface of upper electrode on the center of lower electrode having a recess form section is lower than that of the periphery of lower electrode. Thus, when the second insulation film serving as a smoothing insulation film is formed on the whole surface of base body, the surface of the upper electrode is always in a state covered by the second insulation film. As a result, even if a smoothing process to etch back the insulation film piled on the whole surface of base body is executed, together with the fact that the periphery of lower electrode acts as a etching stopper, it is possible to prevent the upper electrode and further the dielectric film thereunder from suffering damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

Moreover, a semiconductor device according to the present invention further comprises an inter-layer insulation film formed as a third insulation film on a second insulation film covering the periphery of lower electrode and the surface of upper electrode, a first wiring layer connected to the upper electrode through a first via-hole opened in the inter-layer insulation film on the upper electrode, and a second wiring layer connected to the periphery of lower electrode through a second via-hole opened in the inter-layer insulation film on the periphery of lower electrode. Thus, the film thickness of inter-layer insulation film on the upper electrode to be etched for opening a first via-hole is thicker than that of inter-layer insulation film on the periphery of lower electrode to be etched for opening a second via-hole. Consequently, when the first and second via-holes are opened, it is possible to prevent the upper electrode and further a dielectric film thereunder from sustaining damage due to excess overetching to the surface of upper electrode. Therefore, it is possible to obtain a capacitance element which, in addition to the above advantage, has still less fluctuation in its characteristics and high reliability.

Furthermore, in comparing the first via-hole with second via-hole, the depth of the second via-hole opened on the periphery of lower electrode is shallower than that of the first via-hole opened on the upper electrode. Thus, of distances from an area where the upper electrode and lower electrode are opposed to each other and which functions effectively as a capacitance element to the first and second wiring layers, the distance on the lower electrode side which generally tends to be longer than that on the upper electrode side is shortened. This makes the difference in their impedances small to suppress an increase of asymmetry in characteristics of a capacitance element, thereby allowing symmetry in characteristics of the capacitance element to be improved.

A semiconductor device according to the present invention comprises a lower electrode, a dummy electrode formed around the lower electrode and having the surface higher than that of the lower electrode, and an upper electrode formed on the lower electrode through a dielectric film, wherein the surface of upper electrode on the lower electrode is lower than the top surface of the dummy electrode around the lower electrode. Thus, when the second insulation film serving as a smoothing insulation film is formed on the whole surface of a base body, the second insulation film makes it possible to cover the surface upper electrode easily. Therefore, even if a smoothing process to etch back the insulation film piled on the whole surface of the base body is executed, it is possible to prevent the upper electrode and further the dielectric film thereunder from sustaining damage as a result of the surface of upper electrode being etched, together with the fact that the dummy electrode acts as a etching stopper. Consequently, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

In a case where, in the above semiconductor device according to the present invention, the dummy layer for making a level difference provided below the periphery of lower electrode is formed of the same material as those of electrodes or resistance layers of other elements in the semiconductor device, simplification of its fabrication can be realized. Also, in the case where the dummy layer for making a level difference provided below the dummy electrodes is formed of the same conductor layer as are wiring layers of other elements in the semiconductor device, its fabrication can be simplified.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; piling a conductor film on these first insulation film and dummy layer and then patterning the conductor film so as to form a lower electrode with a recess form section in which the surface of its periphery lies on a higher level than the surface of its center, in the predefined area of forming a capacitance element; forming an upper electrode through a dielectric film the surface of which lies on a lower level than that of the periphery of lower electrode; and forming a second insulation film on the whole surface of a base body to fill a recess of the lower electrode having a recess form section.

A method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of a base body including the periphery of the lower electrode, the upper electrode and the second insulation film to form an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also forming a second via-hole in the inter-layer insulation film on the periphery of the lower electrode; and forming a first wiring layer connected to the upper electrode through the first via-hole and also forming a second wiring layer connected to the periphery of the lower electrode through the second via-hole.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; piling a conductor film on these first insulation film and dummy layer and then patterning the conductor film so as to form a lower electrode in the predefined area of forming a capacitance element and forming a dummy electrode in the periphery of the predefined area of forming the capacitance element as covers the dummy layer and has a surface higher than the surface of the lower electrode; and forming an upper electrode on the lower electrode through the dielectric film the surface of which lies on a lower level than the top surface of the dummy electrode; and forming a second insulation film on the whole surface of a base body to a recess the periphery of which is surrounded by the dummy electrode.

A method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of the base body including the dummy electrode, the upper electrode and the second insulation film to form an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also forming a second via-hole in the inter-layer insulation film in the lower electrode; and forming a first wiring layer connected to the upper electrode through the first via-hole and also forming a second wiring layer connected to the lower electrode through the second via-hole.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference around a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; piling a conductor film on these first insulation film and dummy layer and then patterning the conductor film so as to form a lower electrode with a recess section form the surface of which lies on a higher level than the surface thereof in the predefined area of forming the capacitance element; forming an upper electrode, whose surface lies on a lower level than the surface of the periphery of the lower electrode, on the central part of the lower electrode through a dielectric film; and forming a second insulation film on the whole surface of a base body to fill a recess section form of the lower electrode to cover the surface of the upper electrode.

A method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of the base body including the dummy electrode and the second insulation film to form an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also opening a second via-hole in the inter-layer insulation film on the lower electrode; and forming a first wiring layer connected to the upper electrode through the first via-hole and also forming a second wiring layer connected to the lower electrode through the second via-hole.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; piling a conductor film on these first insulation film and dummy layer and then patterning the conductor film so as to form a lower electrode in the predefined area of forming a capacitance element and forming a dummy electrode in the periphery of the predefined area of forming the capacitance element as covers the dummy layer and has a surface higher than the surface of the lower electrode; and forming an upper electrode the surface of which lies on a lower level than the top surface of the dummy electrode, on the lower electrode through the dielectric film; and forming a second insulation film on the whole surface of a base body to fill a recess the periphery of which is surrounded by the dummy electrode and also cover the surfaces of the lower and upper electrodes.

A method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of the base body including the dummy electrode, the upper electrode and the second insulation film to form an inter-layer insulation film; opening a first via-hole in the inter-layer insulation film on the upper electrode and also forming a second via-hole in the inter-layer insulation film in the lower electrode; and forming a first wiring layer connected to the upper electrode through the first via-hole and also forming a second wiring layer connected to the lower electrode through the second via-hole.

In the above described method of fabricating a semiconductor device, the process of forming the dummy layer for making a level difference can be combined with the process of forming electrodes or resistance layers of other elements in the semiconductor device. The dummy layer for making a level difference can be formed of an insulation layer.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; patterning a conductor film piled on the dummy layer to form a lower electrode with a recess form section in which the surface of its periphery lies on a higher level than the surface of its center in a predefined area of forming a capacitance element; and forming an upper electrode on the center of lower electrode through a dielectric film the surface of which lies on a lower level than the surface of periphery of lower electrode. Thus, when the second insulation film serving as a smoothing insulation film is formed, even if a smoothing process to etch back the insulation film piled on the whole surface of a base body is executed, the periphery of lower electrode acts as an etching stopper, thereby allowing the dielectric film to be prevented from suffering damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

Moreover, a method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of the base body including the periphery of the lower electrode, the upper electrode and the second insulation film to form an inter-layer insulation film; and then forming a first wiring layer connected to the upper electrode through the first via-hole opened in the inter-layer insulation film on the upper electrode and also forming a second wiring layer connected to the periphery of lower electrode through the second via-hole opened in the inter-layer insulation film on the periphery of lower electrode. Thus, the film thickness of the inter-layer insulation film on the upper electrode to be etched for opening the first via-hole becomes approximately equal to the film thickness of the inter-layer insulation film on the periphery of lower electrode to be etched for opening the second via-hole. Therefore, when the first and second via-holes are opened, it is possible to prevent the dielectric film under the upper electrode from sustaining damage due to an excess overetching to the surface of the upper electrode. Consequently, it is possible to obtain a capacitance element having in addition to the above advantage, still less fluctuation in its characteristics and higher reliability.

In comparing the first via-hole with the second via-hole, the depth of the second via-hole opened on the lower electrode becomes approximately equal to the depth of the first via-hole opened on the upper electrode. Thus, of distances from an area where the upper and lower electrodes are opposed to each other and which effectively functions as a capacitance element to the first and second wiring layers, the distance on the lower electrode side which generally tends to be longer than that on the upper electrode side is shortened. This makes the difference in their impedances decrease to thereby suppress an increase of asymmetry in characteristics of a capacitance element and improve symmetry in characteristics of the capacitance element.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; patterning thereafter a conductor film piled on these first insulation film and dummy layer to form a lower electrode in a predefined area of forming a capacitance element and also form a dummy electrode that covers the dummy layer and has the surface higher than that of the lower electrode around the predefined area of forming a capacitance element; and forming an upper electrode on the lower electrode through a dielectric film the surface of which lies on a lower level than the top surface of the dummy electrode. Thus, when a second insulation film serving as a smoothing insulation film is formed, even if a smoothing process to etch back an insulation film piled up all over the base body is executed, the dummy electrode acts as an etching stopper, whereby it is possible to prevent the dielectric film from sustaining damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference in the periphery of a predefined area of forming a capacitance element on a semiconductor substrate through a first insulation film; patterning a conductor film piled on these first insulation film and dummy layer to form a lower electrode with a recess form section in which the surface of its periphery lies on a higher level than the surface of its center; and forming an upper electrode the surface of which lies on a lower level than the surface of the periphery of lower electrode on the center of lower electrode through a dielectric film, whereby it is possible to easily materialize covering the surface of upper electrode by a second insulation film formed on the whole surface of a base body. Thus, when the second insulation film serving as a smoothing insulation film is formed, even if a smoothing process to etch back the insulation film piled on the whole surface of the base body, the periphery of lower electrode becomes an etching stopper, thereby making it possible to avoid that the surface of upper electrode is etched to cause damage to the upper electrode and further the dielectric film thereunder. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

Moreover, a method of fabricating a semiconductor device according to the present invention further comprises the steps of: forming a third insulation film on the whole surface of a base body including the periphery of the lower electrode and the second insulation film covering the surface of the upper electrode to form an inter-layer insulation film; and thereafter forming a first wiring layer connected to the upper electrode through a first via-hole opened in the inter-layer insulation film on the upper electrode and also forming a second wiring layer connected to the periphery of lower electrode through a second via-hole opened in the inter-layer insulation film on the periphery of lower electrode. As a result, the film thickness of the inter-layer insulation film on the upper electrode to be etched for opening the first via-hole becomes thicker than that of the inter-layer insulation film on the periphery of lower electrode to be etched for opening the second via-hole. Thus, when the first and second via-holes are opened, it is possible to prevent the upper electrode and further the dielectric film thereunder from suffering damage due to an excess overetching to the surface of upper electrode. Therefore, it is possible to obtain a capacitance element having, in addition to the above advantage, still less fluctuation in its characteristics and higher reliability.

Also, in comparing the first via-hole with the second via-hole, the depth of the second via-hole opened on the lower electrode becomes shallower than that of the first via-hole opened on the upper electrode. Thus, of distances from an area where the upper and lower electrodes are opposed to each other and which functions effectively as a capacitance element to the first and second wiring layers, the distance on the lower electrode side which generally tends to be longer is made shorter. Therefore, it is possible to reduce the difference in their impedances and suppress an increase of asymmetry in characteristics of a capacitance element, thereby allowing symmetry in characteristics of the capacitance element to be improved.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: forming a dummy layer with a predetermined thickness for making a level difference around a predetermined area of forming a capacitance element on a semiconductor substrate through a first insulation film; patterning thereafter a conductor film piled on these first insulation film and dummy layer to form a lower electrode in the predefined area of forming a capacitance element and also form a dummy electrode that covers the dummy layer and has the surface higher than the surface of lower electrode around the predefined area of forming a capacitance element; and forming an upper electrode the surface of which lies on a lower level than the top surface of the dummy electrode, on the lower electrode through a dielectric film. As a result, it is possible to easily materialize covering the surface of upper electrode by a second insulation film formed on the whole surface of a base body. Thus, when the second insulation film serving as a smoothing insulation film is formed, even if a smoothing process to etch back the insulation film piled on the whole surface of the base body is executed, the dummy electrode becomes an etching stopper and so it is possible to prevent the upper electrode and further the dielectric film thereunder from sustaining damage. Therefore, it is possible to obtain a capacitance element having less fluctuation in its characteristics and high reliability.

In the above method of fabricating a semiconductor device according to the present invention, by combining the process of forming the dummy layer for making a level difference with a process of forming an electrode or a resistance layer of another element in a semiconductor device, it is possible to aim at simplifying its fabrication process.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic sectional diagram showing a capacitance element according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional process diagram (No.1) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 3 is a schematic sectional process diagram (No.2) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 4 is a schematic sectional process diagram (No.3) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 5 is a schematic sectional process diagram (No.4) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 6 is a schematic sectional process diagram (No.5) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 7 is a schematic sectional process diagram (No.6) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 8 is a schematic sectional process diagram (No.7) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 9 is a schematic sectional process diagram (No.8) for explaining the method of fabricating the capacitance element shown in FIG. 1.

FIG. 10 is a schematic sectional diagram showing a capacitance element according to a second embodiment of the present invention.

FIG. 11 is a schematic sectional process diagram (No.1) for explaining the method of fabricating the capacitance element shown in FIG. 10.

FIG. 12 is a schematic sectional process diagram (No.2) for explaining the method of fabricating the capacitance element shown in FIG. 10.

FIG. 13 is a schematic sectional diagram showing a capacitance element according to a third embodiment of the present invention.

FIG. 14 is a schematic sectional process diagram (No.1) for explaining the method of fabricating the capacitance element shown in FIG. 13.

FIG. 15 is a schematic sectional process diagram (No.2) for explaining the method of fabricating the capacitance element shown in FIG. 13.

FIG. 16 is a schematic sectional process diagram (No.3) for explaining the method of fabricating the capacitance element shown in FIG. 13.

FIG. 17 is a schematic sectional process diagram (No.4) for explaining the method of fabricating the capacitance element