Semiconductor devices, circuit substrates and electronic devices Number:6,800,894 from the United States Patent and Trademark Office (PTO) owispatent Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films 12 and 22, floating gates 14 and 24, dielectric films 16 and 26, control gates 18 and 28 on first and second memory cell areas 10 and 20 formed mutually adjacent to each other on a semiconductor substrate 30, a plurality of impurity area formation steps of forming sources and drains 32, 34, 36 and 38 on the first and second memory cell areas 10 and 20, and forming a connecting area 40 capable of forming an electric connection between one 32 of the source and drain of the first memory cell area 10 and one 36 of the source and drain of the second memory cell area 20. The connecting area 40 is formed to have a lower electric resistance than impurity areas 42 and 44 formed in one of the of impurity area formation steps.<H Semiconductor, electronic, Semiconductor, d, 6800894.html, Patent, pto, 6800894

Title: Semiconductor devices, circuit substrates and electronic devices

Abstract: Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films 12 and 22, floating gates 14 and 24, dielectric films 16 and 26, control gates 18 and 28 on first and second memory cell areas 10 and 20 formed mutually adjacent to each other on a semiconductor substrate 30, a plurality of impurity area formation steps of forming sources and drains 32, 34, 36 and 38 on the first and second memory cell areas 10 and 20, and forming a connecting area 40 capable of forming an electric connection between one 32 of the source and drain of the first memory cell area 10 and one 36 of the source and drain of the second memory cell area 20. The connecting area 40 is formed to have a lower electric resistance than impurity areas 42 and 44 formed in one of the of impurity area formation steps.

Patent Number: 6,800,894 Issued on 10/05/2004 to Furuhata

Inventors: Furuhata; Tomoyuki (Sakata, JP)
Assignee: Seiko Epson Corporation (Tokyo, JP)

Appl. No.: 09/459,305

Filed: December 10, 1999

Foreign Application Priority Data


Dec 11, 1998 [JP]			10-352498
Aug 26, 1999 [JP]			11-239380

Current U.S. Class: 257/315 ; 257/316; 257/317; 257/321; 257/E21.682; 257/E21.688; 257/E27.081; 257/E27.103

Field of Search: 257/314-317,321 438/257,263,264,266

References Cited [Referenced By]

U.S. Patent Documents


5297082	March 1994	Lee
5326999	July 1994	Kim et al.
5394001	February 1995	Yamaguchi et al.
5523249	June 1996	Gill et al.
5553018	September 1996	Wang et al.
5568422	October 1996	Fujiwara
5661057	August 1997	Fujiwara
5675161	October 1997	Thomas
5780341	July 1998	Ogura
6015725	January 2000	Hirayama
6027971	February 2000	Cho et al.

Other References

US. application Ser. No. 09/155,357. .
U.S. application Ser. No. 09/273,500..

Primary Examiner: Tran; Thien F
Attorney, Agent or Firm: Konrad Raynes & Victor, LLP Raynes; Alan S.

Claims

What is claimed is:

1. A semiconductor device comprising: tunnel insulating films, floating gates, dielectric films and control gates, all of which are laminated on first and second cell areas on a semiconductor substrate; sources and drains formed in the first and second cell areas at positions in contact with a common plane defined by a surface of the semiconductor substrate; a groove in the semiconductor substrate at a position between the first and second cell areas; and a connecting area extending under the groove within the semiconductor substrate, the connecting area electrically connecting one of the source and drain of the first cell area with one of the source and drain of the second cell area, wherein the connecting area has an electric resistance which is lower than at least one of the sources and drains of the first and second cell areas.

2. The semiconductor device according to claim 1, wherein an impurity concentration of the connecting area is the same as an impurity concentration of one of the sources and drains of the first and second cell areas, and is higher than an impurity concentration of the other of the sources and drains of the first and second cell areas.

3. The semiconductor device according to claim 1, wherein an impurity concentration of the connecting area is higher than impurity concentrations of all the sources and drains of the first and second cell areas.

4. The semiconductor device according to claim 1, wherein at least one part of the connecting area has almost the same impurity depth and almost the same impurity concentration of one of a source/drain area and an off-set area of MOS transistor forming a surrounding circuit of the first and second memory cell areas.

5. The semiconductor device according to claim 1, wherein the groove has a depth, and at least part of the connecting area has an impurity depth that is offset from that of the adjacent source/drain regions by the depth of the groove.

6. A circuit substrate equipped with the semiconductor device according to claim 1.

7. An electronic device comprising a circuit substrate according to claim 6.

8. A semiconductor device comprising: a semiconductor substrate including first and second memory cell areas; the first memory cell area including a first horizontal field effect transistor comprising a first tunnel insulating film in contact with the semiconductor substrate, a first floating gate in contact with the first tunnel insulating film, a first dielectric layer in contact with the floating gate, a first control gate in contact with the first dielectric layer, and first source/drain regions extending into the semiconductor substrate; the second memory cell area including a second horizontal field effect transistor comprising a second tunnel insulating film in contact with the semiconductor substrate, a second floating gate in contact with the second tunnel insulating film, a second dielectric layer in contact with the second floating gate, a second control gate in contact with the second dielectric layer, and second source/drain regions extending into the semiconductor substrate; the first source/drain regions and the second source/drain regions each including an upper surface that extends along a common plane; a groove located in the semiconductor substrate at a position between the first and second memory cell areas; and a connecting area electrically connecting one of the first source/drain regions with one of the second source/drain regions, wherein the connecting area has an electric resistance which is lower than any of the first and second source/drain regions, wherein the connecting area extends under the groove in the semiconductor substrate.

9. The semiconductor device according to claim 8, wherein no portion of the first and second floating gates, no portion of the first and second dielectric layers, and no portion of the first and second control gates is positioned within the groove.

10. A semiconductor device comprising: a semiconductor substrate including first and second memory cell areas; the first memory cell area including a first field effect transistor comprising a first tunnel insulating film in contact with the semiconductor substrate, a first floating gate in contact with the first tunnel insulating film, a first dielectric layer in contact with the first floating gate, a first control gate in contact with the first dielectric layer, and first source/drain regions extending into the semiconductor substrate; the second memory cell area including a second field effect transistor comprising a second tunnel insulating film in contact with the semiconductor substrate, a second floating gate in contact with the second tunnel insulating film, a second dielectric layer in contact with the second floating gate, a second control gate in contact with the second dielectric layer, and second source/drain regions extending into the semiconductor substrate; a connecting area electrically connecting one of the first source/drain regions with one of the second source/drain regions, wherein the connecting area has an electric resistance which is lower than that of the first source/drain regions and lower than that of the second source/drain regions, and wherein an impurity concentration of the connecting area is higher than impurity concentrations of the first source/drain regions and higher than impurity concentrations of the second source/drain regions; and a groove in the semiconductor substrate above at least a portion of the connecting area, wherein no portion of the first and second floating gates is positioned within the groove.

11. A semiconductor device according to claim 10, further comprising an interlayer dielectric layer on the first and second field effect transistors, wherein the interlayer dielectric layer on the first and second field effect transistors also extends into the groove.

12. A semiconductor device according to claim 10, wherein the groove comprises an etched groove having sidewalls and a lower surface.

13. A semiconductor device according to claim 10, wherein the groove includes sidewalls and a lower surface, wherein the sidewalls are orthogonal to the lower surface.

14. A semiconductor device comprising: first and second field effect transistors spaced apart from each other, each having source/drain regions in a semiconductor substrate; a groove extending into the semiconductor substrate at a position between the first and second field effect transistors; the first and second field effect transistors each including a floating gate structure, wherein the floating gate structure of the first and second transistors is positioned a distance away from the groove; and a conducting region connecting a source/drain of the first field effect transistor to a source/drain of the second field effect transistor, the conducting region being positioned below the groove and the conducting region having a lower resistance than at least one of the source/drain regions.

15. A semiconductor device according to claim 14, further comprising an insulating material in contact with the semiconductor substrate in the groove.

16. A semiconductor device according to claim 14, further comprising at least an insulating film above the source/drain regions, wherein at least a portion of ends of the conducting region is in direct contact with the insulating film.

17. A semiconductor device according to claim 14, wherein the conducting region has a lower resistance than any of the source/drain regions.

18. A semiconductor device according to claim 17, further comprising an interlayer dielectric layer on the first and second field effect transistors, wherein the interlayer dielectric layer on the first and second field effect transistors also extends into the groove.

19. A semiconductor device according to claim 17, further comprising an interlayer dielectric layer on the first and second field effect transistors, wherein the interlayer dielectric layer on the first and second field effect transistors also extends into the groove.

20. A semiconductor device according to claim 17, wherein the groove comprises an etched groove having sidewalls and a lower surface.

21. A semiconductor device according to claim 17, wherein the groove includes sidewalls and a lower surface, wherein the sidewalls are orthogonal to the lower surface.

22. A semiconductor device comprising: first and second field effect transistors spaced apart from each other, each having source/drain regions in a semiconductor substrate; a groove extending into the semiconductor substrate at a position between the first and second field effect transistors; and a conducting region connecting a source/drain of the first field effect transistor to a source/drain of the second field effect transistor, the conducting region being positioned below the groove and the conducting region having a lower resistance than any of the source/drain regions; wherein the groove has a depth, and at least part of the connecting area has an impurity depth that is offset from that of the adjacent source/drain regions by the depth of the groove.

23. A semiconductor device comprising: first and second memory cell means for storing data, the first and second memory cell means including source/drain regions formed in a semiconductor substrate; a groove extending into the semiconductor substrate at a position between the first and second memory cell means; and connecting means positioned under the groove for electrically connecting the first and second memory cell means, the connecting means having a resistance lower than that of the source/drain regions; wherein the first and second memory cell means each include a floating gate structure, wherein the floating gate structure of the first and second memory cell means is positioned a distance away from the groove.

24. A semiconductor device comprising: tunnel insulating films, floating gates, dielectric films and control gates, all of which are laminated on first and second cell areas on a semiconductor substrate; sources and drains formed in the first and second cell areas at positions in contact with a common plane defined by a surface of the semiconductor substrate; a groove in the semiconductor substrate at a position between the first and second cell areas; and an impurity area extending under the groove within the semiconductor substrate, the impurity area electrically connecting one of the source and drain of the first cell area with one of the source and drain of the second cell area, wherein the impurity area has an electric resistance which is lower than any one of the sources and drains of the first and second cell areas; and wherein at least a portion of ends of the impurity area are in contact with the tunneling insulating films.

25. A semiconductor device according to claim 24, further comprising an interlayer dielectric layer on the control gates on the first and second cell areas, wherein the interlayer dielectric layer on the control gates also extends into the groove.

26. A semiconductor device according to claim 24, wherein the groove comprises an etched groove having sidewalls and a lower surface.

27. A semiconductor device according to claim 24, wherein the groove includes sidewalls and a lower surface, wherein the sidewalls are orthogonal to the lower surface.

28. A semiconductor device comprising: a semiconductor substrate including first and second memory cell areas; the first memory cell area including a first field effect transistor comprising a first tunnel insulating film in contact with the semiconductor substrate, a first floating gate in contact with the first tunnel insulating film, a first dielectric layer in contact with the first floating gate, a first control gate in contact with the first dielectric layer, and first source/drain regions extending into the semiconductor substrate; the second memory cell area including a second field effect transistor comprising a second tunnel insulating film in contact with the semiconductor substrate, a second floating gate in contact with the second tunnel insulating film, a second dielectric layer in contact with the second floating gate, a second control gate in contact with the second dielectric layer, and second source/drain regions extending into the semiconductor substrate; the first source/drain regions and the second source/drain regions each including an upper surface that extends along a common plane; a groove located in the semiconductor substrate at a position between the first and second memory cell areas; an impurity area electrically connecting one of the first source/drain regions with one of the second source/drain regions, wherein the impurity area has an electric resistance which is lower than that of the first source/drain regions and lower than that of the second source/drain regions, wherein the impurity area extends under the groove in the semiconductor substrate, wherein the impurity area also includes first and second end regions that extend adjacent to sides of the grooves; and wherein the first end region is in contact with the first tunneling insulating film and the second end region is in contact with the second tunnel insulating film.

29. A semiconductor device according to claim 28, wherein the groove comprises an etched groove having sidewalls and a lower surface.

30. A semiconductor device according to claim 28, wherein the groove includes sidewalls and a lower surface, wherein the sidewalls are orthogonal to the lower surface.

Description

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and methods of manufacturing semiconductor devices, including various circuits and electronic devices.

BACKGROUND

As a semiconductor device, there has been widely used a memory such as a flash memory which is comprised of floating gate and control gate. A memory cell serving as a smallest unit may include a tunnel oxide film (a first insulating film) formed by oxidizing the surface of a semiconductor substrate, a floating gate (a first poly-silicon film) formed on the tunnel oxide film, a dielectric film (a second insulating film) formed on the floating gate, and a control gate (a second poly-silicon film) formed on the dielectric film. Further, a semiconductor substrate is formed with a source area and a drain area under the tunnel oxide film, and the two areas are located on such positions that the floating gate is interposed therebetween. One (a first impurity area) of the source area and the drain area is connected through a connecting area (a third impurity area) to one (a second impurity area) of the source area and the drain area of an adjacent area.

Here, there is a problem that can be described as follows, i.e., if the third impurity area is formed at the same time as the above first and second impurity areas in accordance with a depth and a impurity concentration required by the first and second impurity areas, the resistance of the connecting area (the third impurity area) will become high, hence retarding the transmission of a signal.

SUMMARY

Certain embodiments relate to a method of manufacturing a semiconductor device, including a laminating step including forming tunnel insulating films, floating gates, dielectric films and control gates on first and second cell areas, the first and second cell areas being formed mutually adjacent to each other on a semiconductor substrate. A plurality of impurity area formation steps are carried out for forming sources and drains on the first and second cell areas. The method also includes forming an electric connection between one of the source and drain of the first cell area and one of the source and drain of the second cell area. The electrical connection may flow through a connecting area formed to have a lower electric resistance than impurity areas formed in one of the plurality of impurity area formation steps.

Other embodiments relate to a semiconductor device including tunnel insulating films, floating gates, dielectric films and control gates, all of which are formed on first and second cell areas on a semiconductor substrate. Sources and drains are formed on the first and second cell areas, and a connecting area is formed that is capable of electrically connecting one of the source and drain of the first cell area with one of the source and drain of the second cell area. The connecting area is formed to have an electric resistance which is lower than any one of the sources and drains of the first and second cell areas.

Other embodiments relate to a method for manufacturing a semiconductor device, including forming first and second field effect transistors, each having source/drain regions, and forming a conducting region connecting a source/drain region of the first field effect transistor to a source/drain region of the second field effect transistor, wherein the conducting region is formed to have a lower resistance than at least one of the source/drain regions.

Other embodiments relate to a semiconductor device including first and second field effect transistors, each having source/drain regions, and a conducting region connecting a source/drain of the first field effect transistor to a source/drain of the second field effect transistor, the conducting region having a lower resistance than at least one of the source/drain regions.

Still other embodiments relate to a semiconductor device including first and second memory cell means for storing data, the first and second memory cell means including source/drain regions. The device also includes connecting means for electrically connecting the first and second memory cell means, the connecting means having a resistance lower than that of the source/drain regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain embodiments of the invention are described with reference to the accompanying drawings which, for illustrative purposes, are schematic and not necessarily drawn to scale.

FIG. 1 is a view illustrating a semiconductor device made according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a semiconductor device made according to the first embodiment of the present invention.

FIG. 3 is a view illustrating a semiconductor device made according to the first embodiment of the present invention.

FIG. 4 is a view illustrating a circuit of a semiconductor device made according to the first embodiment of the present invention.

FIG. 5 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 12A is a view illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 12B is a view illustrating a method of manufacturing a semiconductor device according to an alternative embodiment of the present invention.

FIG. 13 is a view illustrating a semiconductor device made according to another embodiment of the present invention.

FIG. 14 is a view illustrating a method of manufacturing a semiconductor device as in FIG. 13 according to an embodiment of the present invention.

FIG. 15 is a view illustrating a method of manufacturing a semiconductor device according to still another embodiment of the present invention.

FIG. 16 is a view illustrating a method of manufacturing a semiconductor device according to an additional embodiment of the present invention.

FIG. 17 is a view illustrating an additional step in a method of manufacturing a semiconductor device as in claim 16.

FIG. 18 is a view illustrating a circuit substrate equipped with a semiconductor device made according to an embodiment of the present invention.

FIG. 19 is a view illustrating an electronic device having a circuit substrate equipped with a semiconductor device according to an embodiment of the present embodiment.

FIG. 20 is a view illustrating a modified example according to an embodiment of the present invention.

FIG. 21 is a view illustrating another modified example according to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain embodiments of the present invention provide a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method of manufacturing such a semiconductor device, a circuit substrate and an electronic device.

A method of manufacturing a semiconductor device according to certain embodiments of the present invention includes a laminating step of forming tunnel insulating films, floating gates, dielectric films and control gates on first and second cell areas which are formed mutually adjacent to each other on a semiconductor substrate; and several times of impurity area formation steps for forming sources and drains on the first and second cell areas, and forming an electric connection between one of the source and drain of the first cell area on one hand and one of the source and drain of the second cell area on the other, wherein a connecting area is formed having a lower electric resistance than impurity areas formed in one of the several times of impurity area formation steps.

With the use of certain embodiments of the present invention, since there is a low electric resistance of the connecting area connecting together the first and second cell areas, it is possible to prevent a retardation of signal transmission. Here, in order to reduce the electric resistance, there may be various methods which can be used to increase the concentration of an impurity in the connecting area, or to enlarge the connecting area.

According to certain embodiments, a groove is formed in the connecting area on the surface of the semiconductor device. When the groove is formed, although the shape of the connecting area will be deformed, the use of the present invention makes it possible to reduce the electric resistance.

In addition, according to certain embodiments, the laminating step may include a step of forming a first insulating film on the surface of the semiconductor substrate; and a step of forming a first electrically conductive film on the first insulating film, and etching the first electrically conductive film corresponding to the first and second cell areas, thereby partially exposing the first insulating film in a groove formation area. These embodiments may also include a step of forming a second insulating film on the exposed portions of the first insulating film and on the first electrically conductive film; a step of forming a second electrically conductive film on the second insulating film; a step of etching the second electrically conductive film corresponding to the control gates; a step of etching the second insulating film corresponding to the dielectric film, and etching, in the groove formation area, the first insulating film to partially expose the surface of the semiconductor substrate; a step of etching the first electrically conductive film corresponding to the floating gates, and etching the exposed portions of the surface of the semiconductor substrate so as to form the groove.

When the semiconductor device is manufactured with the use of the above steps, the groove is formed in the connecting area.

According to certain embodiments for manufacturing a semiconductor device, the several times of impurity area formation steps may comprise a step of injecting a first impurity into an area containing the connecting area, a step of injecting a second impurity into an area for the formation of source and drain of the first and second cell areas.

With the use of the above method, the injection of an impurity for forming the source and drain is carried out separately from the injection of an impurity for forming the connecting area. Therefore, it is possible to inject the impurities under optimum conditions, thus making it easy to reduce the electric resistance of the connecting area.

According to certain embodiments for manufacturing a semiconductor device, the first impurity may be injected with a patterned resist serving as a mask; and the second impurity may be injected with the control gates, the dielectric films and the floating gates serving as masks.

Since the first impurity is used to form the connecting area, it is preferred that the sources and drains should not be laid one upon another. For this reason, it is preferred that the first impurity is injected with a patterned resist serving as a mask. On the other hand, in certain preferred embodiments, since the second impurity is used to form the sources and drains, it is desired that the impurity should not form a continuous layer under the floating gate. For such a reason, what is desired is only to use as masks the floating gates and layers laminated above the floating gates, without a necessity of patterning the resist.

According to certain embodiments for manufacturing a semiconductor device, the first impurity may be injected from an end portion of an area right under the floating gate of the first cell area to a portion in front of an area right under the floating gate of the second cell area. According to other embodiments, the first impurity may be injected in an area away from an area right under the floating gates of the first and second cell areas. In addition, according to certain embodiments, the first impurity may be injected into an area containing an end portion of an area right under the floating gates of the first and second cell areas.

In another aspect of certain embodiments, a dosing amount of the first impurity may be higher than a dosing amount of the second impurity. In this way, the impurity concentration of the connecting area may be increased, thereby reducing the electric resistance.

In addition, according to certain embodiments, the first and second impurities may be injected with the use of an ion injection technique, and an energy for injecting the first impurity may be larger than an energy for injecting the second impurity. In this way, since the connecting area may be formed with a great depth, its cross sectional area will be increased, thereby reducing its electric resistance.

According to another aspect of certain embodiments, the step of injecting the first impurity may be carried out at the same time when carrying out the step of forming one of a source/drain area and an off-set area of MOS transistor forming a surrounding circuit of the first and second memory cell areas. In this way, it is possible to inject the first impurity at the same time when forming the surrounding circuit.

In addition, according to certain embodiments, the connecting area is formed close to one of the source and drain of the first cell area, and also close to one of the source and drain of the second area. In addition, the impurity area formation steps may comprise: a step of injecting the first impurity into a source and drain formation area of the first cell area and into the connecting area; and a step of injecting the second impurity into a source and drain formation area of the second cell area and into the connecting area.

With the use of the above method, the source and the drain of the first cell area may be formed by the first impurity, the source and the drain of the second cell area may be formed by the second impurity. Further, with the connecting area, since the first and the second impurities are repeatedly injected thereinto, its impurity concentration will be increased, thus reducing its electric resistance.

Certain embodiments also relate to a semiconductor device including: (1) tunnel insulating films, floating gates, dielectric films and control gates, all of which are laminated on the first and second cell areas on the semiconductor substrate; (2) sources and drains formed on the first and second cell areas; and (3) a connecting area capable of electrically connecting one of the source and drain of the first cell area with one of the source and drain of the second cell area, wherein the connecting area has an electric resistance which is lower than any one of the sources and drains of the first and second cell areas.

With the use of the above embodiment, since there is a low electric resistance of the connecting area connecting together the first and second cell areas, it is possible to prevent a retardation of signal transmission. Here, in order to reduce the electric resistance, there may be various constitutions which can be used to increase the concentration of an impurity in the connecting area, or to enlarge the connecting area.

In certain embodiments, the semiconductor device may include a groove formed in the connecting area on the surface of the semiconductor substrate. When the above groove is formed, although the shape of the connecting area will be deformed, the use of the present invention makes it possible to reduce the electric resistance.

In another aspect of certain embodiments of the semiconductor device, an impurity concentration of the connecting area may be the same as an impurity concentration of one of the sources and drains of the first and second cell areas, but may be higher than an impurity concentration of the other of the sources and drains of the first and second cell areas.

In another aspect of certain embodiments, the impurity concentration of the connecting area is higher than the impurity concentrations of all the sources and drains of the first and second cell areas.

In another aspect of certain embodiments of the semiconductor device, at least one part of the connecting area may have almost the same impurity depth and almost the same impurity concentration of one of a source/drain area and an off-set area of MOS transistor forming a surrounding circuit of the first and second memory cell areas.

A circuit substrate according to the present invention may be equipped with the above semiconductor device. In addition, an electronic device according to the present invention may include the above circuit substrate.

Several preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIGS. 1 to 3 are views illustrating a semiconductor device made according to a first embodiment of the present invention. FIG. 1 is a cross sectional view taken along line I--I shown in FIG. 2. FIG. 3 is also a cross sectional view taken along line III--III shown in FIG. 2.

The semiconductor device according to the embodiment of FIGS. 1-3 is an electrically writable memory (ROM: Read Only Memory) which is fabricated so that recorded data is electrically erasable. Alternatively, it is also possible to employ in certain embodiments of the present invention other types of structures such as an ultraviolet light erasing type of a ROM whose data can be erased by irradiation using an ultraviolet light, i.e., employ an EPROM (Electrically Programmable ROM). Such type of semiconductor device is a non-volatile semiconductor storing device. A smallest unit for storing information may be a memory cell, and a plurality of memory cells may be arranged to form a memory array. In this case, a plurality of memory cells are allowed to be arranged in a correct order, so as to form a plurality of rows and a plurality of columns. The following descriptions will be given only to a first memory cell and a second memory cell which are located adjacent to each other.

As shown in FIG. 1, the semiconductor device embodiment has a first memory cell area 10 and a second memory cell area 20. In the first memory cell area 10, there is provided a tunnel insulating film 12, a floating gate 14, a dielectric film 16 and a control gate 18, which are laminated or formed successively on a semiconductor substrate 30 in an order from below. In the second memory cell area 20, there is provided a tunnel insulating film 22, a floating gate 24, a dielectric film 26 and a control gate 28, which are laminated or formed successively on a semiconductor substrate 30 in an order from below.

As shown in FIG. 3, the control gates 18 and 28 are formed in a continuous manner and are electrically connected with each other. The floating gates 14 and 24 are separated from each other by an embedded insulating film 62, so that they are not electrically connected with each other. The embedded insulating film 62 may be formed using a LOCOS (Local Oxidation of Silicon) method.

The tunnel insulating films 12, 22 and the dielectric films 16, 26 are all electrically insulating films. When the tunnel films 12 and 22 are formed by an oxide film, they are referred to as tunnel oxide film. When the semiconductor substrate 30 is a silicon wafer, the tunnel films 12 and 22 may be formed by using a film of silicon oxide. Further, the dielectric films 16 and 26 may be formed by using an ONO film which is obtained by forming a film of silicon nitride between films of silicon oxide. The floating gates 14, 24 and the control gates 18, 28 are all electrically conductive films. Here, the electrically conductive film may be either a conductor or a semiconductor.

In the first memory cell area 10, there are formed one 32 and the other 34 of a source and a drain (hereinafter referred to as source/drain 32, 34). In more detail, the source/drain 32, 34 are formed in an area containing a plane in which the tunnel insulating film 12 of the semiconductor substrate 30 has been formed, or they are formed close to such a plane. Further, the source/drain 32, 34 are formed below the tunnel insulating film 12, located at positions having the floating gate 14 interposed therebetween. Also, the source/drain 32, 34 are formed extending to a part of an end portion of an area under the floating gate 14. The source/drain 32, 34 are separated from each other by the material of the semiconductor substrate 30.

In the second memory cell area 20, there are formed one 36 and the other 38 of a source and a drain (hereinafter referred to as source/drain 36, 38). In more detail, the source/drain 36, 38 are formed in an area containing a plane in which the tunnel insulating film 22 of the semiconductor substrate 30 has been formed, or they are formed close to such a plane. Further, the source/drain 36, 38 are formed below the tunnel insulating film 22, located at positions having the floating gate 24 interposed therebetween. Also, the source/drain 36, 38 are formed extending to a part of an end portion of an area under the floating gate 24. Nevertheless, the source/drain 36, 38 are separated from each other by virtue of the material of the semiconductor substrate 30.

Elements 32, 36 of the sources and the drains in the first and second memory cell areas 10, 20 are electrically connected each other by way of a connecting area 40. As illustrated in FIG. 1, the connecting area 40 is comprised of at least one portion of the first impurity area 42 and at least one portion of the second impurity area 44. In FIG. 1, there is indicated an example in which the entire area of the first impurity area 42 and a partial area of the second impurity area 44 are laid one upon another.

The second impurity area 44 is formed extending from an area containing an element 32 of the source and the drain in the first memory cell area 10, to an area containing an element 36 of the source and the drain in the second memory cell area 20. Further, the second impurity area 44 also contains one portion of the connecting area 40, which is formed between the elements 32, 36 of the sources and the drains in the first and second memory cell areas 10, 20.

As illustrated in FIG. 1, the first impurity area 42 is allowed to partially cover the second impurity area 44. At this time, in the mutually laminated area, since the impurity concentration will become high, an electrical resistance will become low. Further, the first impurity area 42 is also allowed to form in a position deeper than the second impurity area 44. At this moment, since the connecting area 40 is formed deeper than the elements 32, 36 of the sources and the drains, its cross section is large, so that its electric resistance is low. Alternatively, the impurity concentration of the first impurity area 42 is allowed to be higher than that of the second impurity area 44. In this case, the electric resistance of the connecting area 40 will become low.

At a position higher than at least one portion of the connecting area 40, there is formed a groove 46. Such groove 46 is located between the tunnel insulating films 12 and 22, and is formed on the surface of the semiconductor substrate 30. In practice, the groove 46 may be formed in a semiconductor device manufacturing process according to the present embodiment, and its details will be described below. Further, in the present embodiment, since the groove 46 is formed, a possible deformation of the connecting area 40 will not cause a reduced electric resistance owning to the above structure.

Namely, if an impurity area is formed on the surrounding area of the groove 46 at the same depth and with the same impurity concentration as at least one of the sources/drains 32, 34, 36, 38, the groove 46 will cause the impurity area to deform and can make its electrical resistance to become higher than that of any one of the sources/drains 32, 34, 36, 38. For this reason, in the present embodiment, at least one of the depth and the impurity concentration of the connecting area 40 should be made deeper or higher than at least any one of the sources/drains 32, 34, 36, 38, thereby inhibiting the electric resistance to a low value.

The above tunnel insulating films 12 and 22, the floating gates 14 and 24, the dielectric films 16 and 26, the control gates 18 and 28, are all covered by an interlayer insulating film 48. The interlayer insulating film 48 is an electrically insulating film which may be a film of silicon oxide or the like.

Above the elements 34, 38 of the sources and the drains in the first and second memory cell areas 10, 20, there are formed contact holes 50 and 52 passing through the tunnel insulating films 12, 22 and the interlayer insulating film 48. Thus, electrodes 54 and 56 are allowed to be electrically connected to the elements 34, 38 of the sources and the drains by way of the contact holes 50, 52. Further, a first and a second bit lines BL1 and BL2 are integrally formed with the electrodes 54 and 56.

FIG. 4 is a view indicating some circuit portions of a semiconductor device made according to an embodiment to which the present invention has been applied. In the drawing, there are indicated a plurality of memory cells 1 to 4 forming a part of a memory array. Here, the memory cells 1, 2 may be deemed to be equivalent to the memory cell areas 10 and 20 shown in FIG. 1, so that identical portions will be indicated by the identical reference numerals. A description of the memory cells 1 and 2 is as follows.

The memory cells 1, 2 are connected to the bit lines BL1 and BL2 shown in FIG. 1, further connected to a word line WL. The word line WL is also connected to the control gates 18, 28 of the memory cells 1, 2. The source/drain 32, 36 of the memory cells 1, 2 are connected by virtue of a source line SL. However, the source/drain 32, 36 and the source line SL are formed by virtue of the second impurity area 44 shown in FIG. 1. Since the second impurity area 44 contains the groove 46, a resistance R may be formed in connection with the source line SL. Further, in an area containing the groove 46, since there is formed a connecting area 40 shown in FIG. 1, both ends of the resistance R may be directly connected with another resistance R' (R'<R). Therefore, it is possible to obtain a relatively low resistance as compared with the resistance R, thus preventing a retardation of signal transmission.

A semiconductor device formed according to the present embodiment, having the above constitution, will be described as to its operation in the following.

A write operation on the memory cells 1, 2 will be described as follows. At first, a high voltage VcH (for example 12 V) is applied to the control gates 18, 28 through the word line WL. Preferably, at the same time, another high voltage VcH (for example 5.5 V) is applied to those elements performing the write operation, which elements are among the source/drain (in this case, it relates only to drains) 34 and 38 of the memory cells 1, 2. Such high voltage VdH is applied through the bit lines BL1 and BL2. Preferably, at the same time, the source line SL is set at a low potential VsL (for example, an earth potential). At this moment, since there is provided a resistance R' (connecting area 40), it is possible to set the source line SL at a low potential, within a short time period.

In this way, among the source/drain 34 and 38, an electric current will flow from the elements having received the high voltage VdH along a direction of the source line SL. At this moment, electrons (which may also be called hot electrons) are injected into the floating gates 14, 24 from the source line SL. As a result, a threshold voltage Vth of the transistor formed by the memory cells 1 and 2 will be higher than a standard voltage Vcc (for example, 5 V). If the threshold voltage Vth is not higher than the standard voltage Vcc, information will be written into the memory. On the other hand, if the threshold voltage Vth is lower than the standard voltage Vcc, information will not be written into the memory.

Next, a readout operation on the memory cells 1, 2 will be explained in the following. At first, a high voltage VcH (for example, 5 V) is applied to the control gates 18, 28 through the word line WL. At this time, a portion just effecting a write operation among the memory cells 1 and 2, has a higher threshold voltage Vth than the standard voltage Vcc, a transistor formed by the memory cells 1 and 2 will become OFF. On the other hand, a portion not effecting a write operation among the memory cells 1 and 2, has a lower threshold voltage Vth than the standard voltage Vcc, a transistor formed by the memory cells 1 and 2 will become ON. For instance, if source line SL, bit lines BL1 and BL2 are set at predetermined different potentials, and if electric current flowing through the bit lines BL1 and BL2 are detected, it is possible to detect the ON or OFF of the transistor, thereby detecting whether or not a write operation is being effected. Even at this time, since there is provided a resistance R' (connecting area 40), it is allowed to set the source line SL at a predetermined potential, within a short time period.

Next, an erase operation to be performed on the memory cells 1 and 2 will be described in the following. Namely, a high voltage VsH (for example, 5 V) is applied to the source line SL. Preferably, at the same time, at least a low voltage VcL (for example, -7 V) which is lower than a ground potential, is applied to the control gates 18, 28 through the word line WL. Preferably, at the same time, among the source/drain 34, 38 of the memory cells 1, 2, a portion just effecting an erase operation (in general, data on the entire area is erased) is maintained at a floating state (open) through the bit lines BL1 and BL2.

In this way, electrons will be drawn from the floating gates and caused to move in a direction along the source line SL. Then, since the threshold voltage Vth becomes lower than the standard voltage Vcc, the area will be changed to a state where no write operation is being conducted, thereby completing the erase operation.

Next, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described in the following with reference to FIGS. 5 to 12A.

At first, as shown in FIG. 5, a first insulating film 112 is formed on the surface of the semiconductor substrate 30, followed by forming thereon an electrically conductive film 114. Here, a material forming the first insulating film 112 has an electrically insulating property. It is possible that the first insulating film 112 may be obtained by forming an oxide film on the surface of the semiconductor substrate 30 with the use of a method such as a thermal oxidizing method. If the semiconductor substrate 30 is formed by a silicon, the first insulating film 112 may be a film of silicon oxide. The thickness of the first insulating film 112 is preferred to be 7 to 10 nm. Further, the first insulating film 112 may be etched so as to become tunnel insulating films 12 and 22. When the first insulating film 112 is a film of silicon oxide, the tunnel insulating films 12 and 22 will be tunnel oxide films.

A material forming the first electrically conductive film 114 may contain not only an electrically conductive material but also a semiconductor such as silicon. In fact, it is possible that the first electrically conductive film 114 may be obtain by forming a silicon film on the first insulating film 112, with the use of a CVD method. Here, the thickness of the first electrically conductive film 114 is preferred to be 100 to 200 nm. The first electrically conductive film 114 may be etched so as to form the floating gates 14, 24.

Next, as shown in FIG. 6, the first electrically conductive film 114 is selectively removed by means of an etching treatment which is conducted at or on an area in the vicinity of the first and second memory cell areas 10 and 20, and a second insulating film 116 is formed on the first electrically conductive film 114. In practice, the etching treatment performed on the first electrically conductive film 114 may be accomplished with the use of a technique such as photolithography. Further, the etching treatment utilized here is a selective etching treatment, and is used for etch-treating the first electrically conductive film 114, but under a condition in which the first insulating film 112 will not be etched.

The second insulating film 116 is formed on the remaining portions not etched during the etching treatment conducted on the first electrically conductive film 114, also on the first insulating film 112 exposed by partially etching the first electrically conductive film 114. The second insulating film 116 may be formed by laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film. In such a case, the second insulating film 116 may be an ONO film. Here, the silicon oxide film may be formed with the use of either a CVD method or a thermal oxide film formation method. The silicon nitride film may be formed by a CVD method.

Next, as shown in FIG. 7, a second electrically conductive film 118 is formed on the second insulating film 116. A material forming the second electrically conductive film 118 may contain not only an electrically conductive material but also a semiconductor such as silicon. It is possible that the second electrically conductive film 118 may be obtained by forming a silicon film on the second insulating film 116, with the use of a method such as CVD method. Here, the thickness of the second electrically conductive film 118 is preferred to be about 200 to 400 nm. As another example serving as the second electrically conductive film 118, it is allowed to form a structure which includes a silicon film having a preferred thickness of 80 to 200 nm, and a silicide layer containing WSi.sub.2, MoSi.sub.2, CoSi.sub.2, TiSi.sub.2, etc., having a preferred thickness of 80 to 200 nm.

Then, a patterned resist 120 may be formed on the second electrically conductive film 118. The resist 120 is patterned in a manner such that it can cover up the surface of the second electrically conductive film 118 in an area corresponding to the control gates 18 and 28.

Next, the resist 120 is used as a mask and the second electrically conductive film 118 is selectively etched, thereby forming control gates 18, 28, as shown in FIG. 8. Here, an etching method used is a selective etching treatment, so that the second insulating film 116 will not be etched.

Subsequently, the resist 120 and the control gates 18 and 28 are used as masks to selectively etch the second insulating film 116. With the use of such an etching treatment, only the portions under the control gates 18 and 28 on the second insulating film 116 are allowed to remain, while other portions will be removed. As a result, as shown in FIG. 9, dielectric films 16 and 26 can thus be formed. Further, since the etching treatment will also remove the portions formed on the first insulating film 112 of the second insulating film 116, the first insulating film 112 can be partially exposed. Such exposed portions will later become the first and the second memory cell areas 10 and 20.

The etching method suitable for use in the process is a selective etching method. However, in a case where the first insulating film 112 and the second insulating film 116 have the same properties, for example, when they are all oxide films, the second insulating film 116 together with the first insulating film 112 will be etched at the same time. Namely, the second insulating film 116 is removed so that the exposed portions of the first insulating film 112 will be etched. In this way, a portion of the surface of the semiconductor substrate 30 may be exposed between the first and the second memory cell areas 10 and 20. Further, the first insulating film 112 is etched, thereby forming the tunnel insulating films 12 and 22.

Next, the resist 120 and the control gates 18, 28 are used as masks to selectively etch the first electrically conductive film 114. With the use of the etching treatment, only the portions under the dielectric films 16, 26 on the first electrically conductive film 114 are allowed to remain, while other portions will be removed. As a result, as shown in FIG. 10, floating gates 14 and 24 will be formed.

An etching method suitable for use in the process is a selective etching method. However, in a case where the first electrically conductive film 114 and the semiconductor substrate 30 have the same properties, for example, when the first electrically conductive film 114 is formed by silicon, the first electrically conductive film 114 together with the semiconductor substrate 30 will be etched at the same time. Namely, as shown in FIG. 9, a portion exposed between the first and the second memory cell areas 10 and 20 on the surface of the semiconductor substrate 30, will be etched. In this way, a groove 46 can be formed on the surface of the semiconductor substrate 30 between the first and the second memory cell areas 10 and 20. However, it is also possible that the depth of the groove 46 may be made to be about 100 to 300 nm.

Next, the resist 120 is removed, and then, as shown in FIG. 11, another resist 130 having another pattern is formed thereon. The resist 130 should preferably be formed at least away from the groove 46 which has been formed on the semiconductor substrate 30. Further, the resist 130 is preferred to be formed not only away from the groove 46 but also away from the surrounding areas. Thus, it is preferred that at least the groove 46 is exposed, while the areas other than the groove 46 are covered by the resist 130. It is even more preferred that the groove 46 and the surrounding areas near the groove 46 are exposed, while other areas further from the groove 46 are covered by the resist 130, as illustrated, for example, in FIG. 11.

The resist 130 is used as a mask, and a first impurity 140 is injected on to the surface of the semiconductor substrate 30. For example, with the use of an ion injection technique, it is preferred to inject phosphorus ions with an energy of 40 to 120 keV and a preferred dosing amount of 1.times.10.sup.14 to 6.times.10.sup.15 /cm.sup.2. Alternatively, either phosphorus ions or arsenic ions are injected with a preferred energy of 30 to 80 keV and a dosing amount of 1.times.10.sup.15 to 6.times.10.sup.15 /cm.sup.2. Further, alternatively, both of the above phosphorus ions and arsenic ions are injected under the above conditions. The above ions may serve as an example of the first impurity 140. After injection of the first impurity 140, an annealing treatment may be conducted so as to form the first impurity area 42. The first impurity area 42 is, for example, an N.sup.+ type area. It is possible that the depth of the first impurity area 42 may be about 200 to 600 nm, the impurity concentration thereof may be about 1.times.10.sup.18 to 1.times.10.sup.21 /cm.sup.3. The preferred conditions for performing an annealing treatment for the first impurity area 42 involve an atmosphere of N.sub.2 or N.sub.2 /O.sub.2, a treating temperature of about 900 to 950.degree. C., and a treating time of about 30 to 180 minutes.

Next, the resist 130 is removed, and as shown in FIG. 12A, the floating gates 14 and 24 are used as masks so that the second impurity 150 is injected on to the surface of the semiconductor substrate 30. For example, with the use of an ion injection technique, it is preferred to inject phosphorus ions with an energy of 40 to 120 keV and a preferred dosing amount of 5.times.10.sup.12 to 5.times.10.sup.14 /cm.sup.2. Alternatively, either phosphorus ions or arsenic ions are injected with an energy of 30 to 80 keV and a dosing amount of 1.times.10.sup.15 to 6.times.10.sup.15 /cm.sup.2. Further, alternatively, both of the above phosphorus ions and arsenic ions are injected under the above conditions. The above ions may serve as an example of the second impurity 150.

Although the floating gates 14 and 24 can serve as masks, the second impurity 150 can also get into the end portions under the floating gates 14 and 24. After injection of the impurity 150, an annealing treatment may be conducted for the second impurity area 44. The second impurity area 44 is, for example, an N.sup.+ type area. It is possible that the depth of the second impurity area 44 may preferably be about 100 to 400 nm, the impurity concentration thereof may preferably be made 1.times.10.sup.17 to 1.times.10.sup.21 /cm.sup.3.

The second impurity area 44 may be used to form the sources/drains 32, 34, 36, 38 of the first and the second memory cells 10, 20, and be connected with the source/drain 32, 34. However, since the second impurity area 44 is formed with a groove 46 on areas in connection with the source/drain 32 and 36, the areas surrounding the groove 46 will have a high electric resistance.

In the present embodiment, at least the areas directly under the groove 46, preferably, the areas under the groove 46 and its surrounding areas, contain the first impurity area 42 formed therein. Therefore, some deformed portions occurred due to the groove 46 on the second impurity area 44 may be compensated by the first impurity area 42. As a result, since the surrounding areas adjacent to the groove 46 are connected with one another by virtue of the first and the second impurity areas 42 and 44, it is possible that the electric resistance may be reduced. In this way, the connecting area 40 may be formed by virtue of at least a part of the first impurity area 42, and at least a part of the second impurity area 44. The electric resistance of the connecting area 40 will be lower than that of the deformed portions occurred due to the groove 46 of the second impurity area 44.

Here, if an energy for injecting the first impurity 140 is made larger than an energy for injecting the second impurity 150, it is possible that the first impurity area 42 may be made deeper than the second impurity area 44, as illustrated in FIG. 12A. In such a case, if the connecting area 40 is made deeper than the second impurity area 44, it is sure to reduce the electric resistance.

Further, if the dosing amount of the first impurity 140 is made larger than the dosing amount of the second impurity 150, since the impurity concentration of the first impurity area 42 will be increased, it is sure to reduce the electric resistance of the connecting area 40.

Alternatively, it is also possible that a first impurity area 42A may be formed by being laid on the deformed portions occurred due to the groove 46 on the second impurity area 44, so that the first impurity area 42A and the second impurity area 44 overlap one another and extend about the same depth into the substrate 30, as illustrated in FIG. 12B. In such a case, the impurity concentration of the deformed