Semiconductor device having two-layered charge storage electrode Number:6,806,132 from the United States Patent and Trademark Office (PTO) owispatent A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.<H Semiconductor, electrode, Semiconductor, d, 6806132.html, Patent, pto, 6806132

Title: Semiconductor device having two-layered charge storage electrode

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Patent Number: 6,806,132 Issued on 10/19/2004 to Mori, et al.

Inventors: Mori; Seiichi (Tokyo, JP); Noguchi; Mitsuhiro (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba (Tokyo, JP)

Appl. No.: 10/728,818

Filed: December 8, 2003

Foreign Application Priority Data


Oct 30, 2000 [JP]			P2000-331407
Oct 22, 2001 [JP]			P2001-324141

Current U.S. Class: 438/221 ; 257/314; 257/E29.129; 438/197; 438/253; 438/257

Field of Search: 438/197,253,257 257/314

References Cited [Referenced By]

U.S. Patent Documents


6153472	November 2000	Ding et al.
6153494	November 2000	Hsieh et al.
6171909	January 2001	Ding et al.
6310374	October 2001	Satoh et al.
6342715	January 2002	Shimizu et al.
6391722	May 2002	Koh
6479858	November 2002	Krivokapic

Foreign Patent Documents


H10-335497	Dec., 1998	JP
11-87543	Mar., 1999	JP
H11-261038	Sep., 1999	JP

Primary Examiner: Nelms; David
Assistant Examiner: Tran; Mai-Huong
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This is a Divisional of prior application No. 09/984,599, filed Oct. 30, 2001.

This application is based upon and claims the benefit of priority from prior Japanese Patent Applications P2000-331407 and P2001-324141 filed on Oct. 30, 2000 and Oct. 22, 2001; the entire contents of which are incorporated by reference herein.

Claims

What is claimed is:

1. A manufacturing method of a nonvolatile memory comprising: sequentially forming a first insulation film, a first floating gate film, and a cap on a semiconductor substrate; etching the first insulation film, the first floating gate film, and the cap on the same pattern; filling a second insulation film in the pattern; removing the cap; and forming a second floating gate film on a side face of the second insulation film and a top face of the first floating gate film, and a top face at an outer side of the second floating gate is higher than a top face at an inner side of the second floating gate.

2. The manufacturing method of a nonvolatile memory as claimed in claim 1, wherein after said forming the second floating gate film, the second insulation film is etched.

3. The manufacturing method of a nonvolatile memory as claimed in claim 1, wherein, in said forming the second floating gate film, the second floating gate film is disposed as one body on the first floating gate film.

4. The manufacturing method of a nonvolatile memory as claimed in claim 1, further comprising: forming a fourth insulation film on the second floating gate film and on the second insulation film; and forming a fourth conductor film on the fourth insulation film.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device having trench-type isolation regions, a floating gate, and a control gate. More particularly, the present invention relates to capacitive coupling between a floating gate and a control gate.

A nonvolatile semiconductor storage device is composed of nonvolatile memory cells. These nonvolatile memory cells each have a floating gate and a control gate. Potential of the floating gate is controlled by capacitive coupling between the floating gate and the control gate. As the capacitive coupling between the control gate and the floating gate increases, the voltage of the control gate can be lowered. In order to increase the capacitive coupling, the area where the control gate is proximal to the floating gate is increased as follows. The floating gate has a two-layered structure made of a polycrystalline silicon (Si) film in the first layer and polycrystalline silicon at a second layer. The polycrystalline silicon film of the first layer is formed by self-alignment with trench-type isolation regions. The polycrystalline silicon film of the second layer is formed onto the polycrystalline silicon film of the first layer and the trench type isolation regions. An insulation film is formed onto the polycrystalline silicon of the second layer. A control gate is formed onto this insulation film.

However, this cell structure requires a space, an isolation width "Wt" of the memory cell, for separating the polycrystalline silicon of the second layers. In addition, this cell structure requires a space, as an alignment margin, during lithography steps.

In this cell structure, in order to increase the capacitive coupling between the floating gate and the control gate, it is effective to increase the film thickness of the floating gate. When the film thickness of the floating gate is increased, capacitive coupling C2 in the floating gate between cells increases. When the capacitive coupling C2 increases, the cell threshold voltage is susceptible to modulation corresponding to the state of data in adjacent cells.

SUMMARY OF THE INVENTION

A semiconductor device in accordance with embodiments of the present invention includes a semiconductor substrate including plural trenches on a surface, first and second insulators placed in the trench and upper portions of side faces of the first and second insulators are higher than the surface of the substrate, a third insulation film disposed on the surface of the substrate, one end of the third insulation film contacts with the first insulator, and the other end of the third insulation film contacts with the second insulator, a first conductor disposed on a surface of the third insulation film, one end face of the first conductor contacts with the first insulator, and the other end face of the first conductor contacts with the second insulator, a second conductor disposed at a vicinity of the one end face of the first conductor, a third conductor disposed at a vicinity of the other end face of the first conductor, a fourth insulation film contacting with a first side face of the second conductor and a second side face of the third conductor and contacting with a top face of the first conductor, and a fourth conductor disposed on the fourth insulation film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view showing a semiconductor device in accordance with a first embodiment;

FIG. 1B is a sectional view taken along line I--I in FIG. 1A;

FIG. 2A is a sectional view taken along line II--II in FIG. 1A;

FIG. 2B is a sectional view taken along line III--III in FIG. 1A;

FIG. 3A to FIG. 4C are sectional views each showing a semiconductor device in accordance with the first embodiment by manufacturing process;

FIG. 4C is a sectional view taken along line I--I in FIG. 5;

FIG. 5 is a upward perspective view showing a semiconductor device shown in FIG. 4C;

FIG. 6 is a sectional view showing a semiconductor device in accordance with a first modified example of the first embodiment;

FIG. 7 is a sectional view showing a semiconductor device in accordance with a second modified example of the first embodiment;

FIG. 8A and FIG. 8B are sectional views each showing a semiconductor device in accordance with a second embodiment;

FIG. 9A and FIG. 9B are sectional views each showing detailed parts of a comparative example of the semiconductor device in accordance with the second embodiment;

FIG. 10 is a view illustrating an effect of capacitive coupling reduction in floating gate obtained by the semiconductor device in accordance with the first and second embodiments;

FIG. 11A is a sectional view showing a semiconductor device in accordance with a third embodiment;

FIG. 11B is a sectional view showing a semiconductor device in accordance with a first modified example of the third embodiment;

FIG. 11C is a sectional view showing a semiconductor device in accordance with a second modified example of the third embodiment;

FIG. 11D is a sectional view showing a semiconductor device in accordance with a third modified example of the third embodiment;

FIG. 12A to FIG. 12D are sectional views each showing a semiconductor device in accordance with the third embodiment by manufacturing process;

FIG. 13A to FIG. 13D are sectional views each showing a semiconductor device in accordance with a first modified example. of the third embodiment by manufacturing process;

FIG. 14A to FIG. 14C are sectional views each showing a semiconductor device in accordance with a second modified example of the third embodiment by manufacturing process;

FIG. 15A is an upward perspective view showing a semiconductor device in accordance with a fourth embodiment;

FIGS. 15B and 15C are sectional views of a fourth embodiment of the present invention showing the dummy cell and periphery circuit separate from each other;

FIG. 16A to FIG. 20D is sectional views each showing a semiconductor device in accordance with the fourth embodiment by manufacturing process.

FIG. 16A, FIG. 16C, FIG. 17A, FIG. 17C, FIG. 18A, FIG. 18C, FIG. 19A, FIG. 19C, FIG. 20A and FIG. 20C are sectional views each showing a memory cell region.

FIG. 16B, FIG. 16D, FIG. 17B, FIG. 17D, FIG. 18B, FIG. 18D, FIG. 19B, FIG. 19D, FIG. 20B, and FIG. 20D are sectional views each showing a peripheral circuit region.

FIG. 21A and FIG. 21B are sectional views each showing a comparative example of the semiconductor device in accordance with the fourth embodiment. FIG. 21A is a sectional view taken along line I--I in FIG. 21C. FIG. 21B is a sectional view taken along line VI--VI in FIG. 21C.

FIG. 21C is a top view showing a comparative example of semiconductor device according to the fourth embodiment.

FIG. 22A is an upward perspective view showing a semiconductor device in accordance with a modified example of the fourth embodiment;

FIG. 22B is a sectional view taken along line I--I in FIG. 22A;

FIG. 22C is a sectional view taken along line VI--VI in FIG. 22A;

FIG. 23A to FIG. 23D are sectional views each showing a semiconductor device in accordance with a modified example of the fourth embodiment by manufacturing process;

FIG. 23A and FIG. 23C are sectional views each showing a memory cell region; and FIG. 23B and FIG. 23D are sectional views each showing a peripheral circuit region.

DETAILED DESCRIPTION OF EMBODIMENTS

Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.

First Embodiment

A semiconductor device in accordance with a first embodiment of the present invention has the following features, as shown in FIG. 1A to FIG. 2B. A semiconductor substrate 1 has plural trenches on a surface. Isolation regions 21 to 24 are placed in the trenches. Side faces of the isolation regions 21 to 24 each extend to a position that is higher than a surface of the substrate 1. Tunnel oxide films 31 to 33 are provided on the surface of the substrate 1. Both ends of the tunnel oxide films 31 to 33 each come into contact with the isolation regions 21 to 24.

First conductors 41 to 43 are provided on the surface of the tunnel oxide films 31 to 33. Both end faces of the first conductors 41 to 43 come into contact with the isolation regions 21 to 24. Second conductors 51, 53, and 55 are provided in the vicinity of one end face of the first conductor. First side faces of the conductors 51, 53, and 55 come into contact with the isolation regions 21 to 24. Third conductors 52, 54, and 56 are provided on the surfaces of the first conductors 41 to 43. The third conductors 52, 54, and 56 are provided in the vicinity of the, other end face of the first conductor. First side faces of the third conductors 52, 54, and 56 each come into contact with the isolation regions 21 to 24. The floating gate is composed of: the first conductors 41 to 43; the second conductors 51, 53, and 55; and the third conductors 52, 54, and 56.

An insulation film 6 comes into contact with a second side face of each of the second conductors 51, 53, and 55. The insulation film 6 comes into contact with the first side face of each of the third conductors 52, 54, and 56. The insulation film 6 comes into contact with the surface of each of the first conductors 41 to 43. An conductor that is a control gate 7 is provided on the insulation film 6.

In the following embodiments, a charge storage region that is an electrode responsible for charge storage is expressed as a floating gate electrode as usual. The floating gate electrode can hold a charge during a hold time in accordance with use, for example, for 10 years for nonvolatile memory use, and for about 1 second for nonvolatile memory use.

Source/drain regions 81 to 87 are disposed in the vicinity of the surface of the semiconductor substrate 1. The conductor type of the source/drain regions 81 to 87 differs from that of the substrate 1 below the floating gate electrodes 41 to 43. Further, as shown in FIG. 1A, a plurality of trench type isolation regions 21 to 24 are disposed in parallel in a longitudinal direction, and a plurality of control gates 7 and 27 are disposed in parallel in a transverse direction, whereby a number of nonvolatile memory cells can be integrated on the substrate 1.

A floating gate electrode is structured in two-layered manner. The first layer corresponds to first conductors 41 to 43. The second layer corresponds to second and third conductors 51 to 56. The second and third conductors are electrically connected to the first conductors. The first to third conductors 42, 53, and 54 serve as one floating gate electrode.

The pattern of the trench type isolation regions 21 to 24 is an inverted pattern of that of the first conductors 41 to 43. The first conductors 41 to 43 are separated by self-alignment in accordance with the trench type isolation regions 21 to 24. The second and third conductors 51 to 56 are provided on the side faces of the isolation insulation films 21 to 24, on the ends of the first conductors 41 to 43, as sidewalls of the isolation insulation films 21 to 24. The side faces of the second and third conductors 51 to 56 are disposed under the control gate 7 and adjacent to the protrusive portions.

A flash memory cell that is a nonvolatile memory cell has floating gates 42, 53, and 54 and a control gate 7. When the fined flash memory cells is developed, it is necessary to maintain the size of capacitive coupling between each of the floating gates 42, 53, and 54 and the control gate 7. In accordance with the first embodiment, the amount of capacitive coupling between the control gate 7 and each of the floating gates 42, 53, and 54 can be increased. Thereby improving the performance of the memory cells. There are two reasons for this higher density and increase in capacitance being achievable. The first reason is that an active region and a first conductor 42 are provided to the trench isolation regions 22 and 23 in a self-aligned manner. The second reason is that the second and third conductors 53 and 54 that form the side walls of the trench type isolation regions 22 and 23 are provided to both ends of the first conductor 42, i.e., the side faces of the trench type isolation regions 22 and 23. An increased density can be achieved by the multiple self-alignment structure. The side face areas of the second and third conductors 53 and 54 can be increased, thus increasing capacitive coupling.

The side face of the second conductor 51 comes into contact with the first isolation region 21. The side face of the third conductor 52 comes into contact with the second isolation region 22. This contact between the conductors 51 and 52 and the isolation regions 21 and 22 is formed in a self-aligned manner.

In addition, as shown in FIG. 2A and FIG. 10, the film. thickness of the first conductors 42 and 44 or 71 to 74 is relatively thin. In addition, the film thicknesses of the second and third conductors 53 and 54 are also thin. Due to this, the parasitic capacity C1 among floating gate electrodes in the adjacent cells 61 to 64 can be reduced. Then, threshold voltage interference caused between cells via the parasitic capacity C1 can be reduced.

Hereinafter, a method of manufacturing a semiconductor device in accordance with a first embodiment will be described.

(1) First, as shown in FIG. 3A, a trench section 10 is formed in place of the isolation regions 22 and 23. The trench section 10 and the first conductors 41 to 43 and active region 1 are processed in a self-aligned manner. The first conductors 41 to 43 are not arranged laterally along the active region 1.

Insulation films 31 to 33 are silicon oxide films or silicon oxynitride films are formed on a p-type silicon (Si) substrate 1. These silicon oxide films or silicon oxynitride films act as tunnel oxide films of nonvolatile memory cells. The film thicknesses of these silicon oxide films are within a range of 3 nm to 15 nm. The film thicknesses of these silicon oxide films are for example about 10 nm. First conductors 41 to 43 are polycrystalline silicon (Si) films deposited on the insulation films 31 to 33. The film thicknesses of the first conductors 41 to 43 are within a range of 10 nm to 500 nm. The film thicknesses of the first conductors 41 to 43 are for example about 30 nm. Caps 91 to 93 that silicon nitride films deposited above the first conductors 41 to 43. The film thicknesses of the caps 91 to 93 are within a range of 3 nm to 500 nm. The film thicknesses of the caps 91 to 93 are for example about 100 nm. The heights of the second and third conductors 51 to 56 correspond to the film thicknesses of the caps 91 to 93, and are substantially equal to each other. That is, as the film thicknesses of the caps 91 to 93 increases, the heights of the second and third conductors 51 to 56 are also increased.

Now, trenches 10 are grooved in each of the regions that are referred to as the isolation regions 21 to 24 by lithography steps and etching. Specifically, the caps 91 to 93, first conductors 31 to 33, and silicon substrate 1 are sequentially etched. The isolation trenches 10, first conductors 41 to 43, and caps 91 to 93 are formed in a self-aligned manner. The depth of trenches 10 in the silicon substrate 1 is within a range of 50 nm to 1000 nm. The depth of trenches 10 in the silicon substrate 1 is for example about 300 nm. After grooving trenches 10, a thin silicon oxide film is formed as required in accordance with a thermal oxidization technique. The film thickness of this silicon oxide film is within a range of 3 nm to 20 nm. The film thickness of this silicon oxide film is for example about 10 nm.

In this manner, cell minuteness has been enhanced. In addition, the first conductors 41 to 43 are not formed so as to cover the corner portions of the active region. Electric field concentration at the corner portion of the active region does not occur. Deviation in memory cell characteristics due to this electric field concentration can thereby be suppressed.

(2) Next, each of the isolation regions 21 to 24 is placed up with an insulation film in accordance with an HDP (High Density Plasma Deposition) technique. As shown in FIG. 3B, after depositing this insulation film, insulation films 21 to 24 are polished down to the top faces of the caps 91 to 93 in accordance with a method such as CMP (Chemical Mechanical Polishing). The insulation films 21 to 24 are flattened. The isolation regions 21 to 24 are each filled up to the end of the first conductor in a self-alignment manner.

(3) As shown in FIG. 3C, caps 91 to 93 are removed. This produces trench portions 11 surrounded by the isolation regions 21 to 24. If the caps 91 to 93 are silicon nitride films, a chemical solution made of a heated (hot) phosphate (H.sub.3 PO.sub.4) is used. Only the caps 91 to 93 can be easily removed by etching, using this chemical solution.

(4) As shown in FIG. 4A, a thin conductor film 5 is deposited on the exposed faces of each of the isolation regions 21 to 24. This thin conductor film 5 is made of a polycrystalline silicon. This thin conductor film 5 is used to form the second and third conductors 51 to 56.

(5) As shown in FIG. 4B, the conductor film 5 is etched back. The second and third conductors 51 to 56 are formed on the side faces of the isolation regions 21 to 24. In this etching back process, the insulator film 5 formed on each of the isolation regions 21 to 24 that exist between cells is removed in a self-aligned manner. The second and third conductors 51 to 56 can be separated into cells. For example, the second conductor 53 and the third conductor 52 are separated from each other. The first conductors 41 to 43 and the second and third conductors 51 to 56 are electrically connected with each other on the bottom faces of the conductors 51 to 56. Even if a thin insulation film exists between the first and second conductors 41 and 51, the first and second conductors 41 and 51 are still capacitively-coupled with each other. Therefore, even in the case where an insulation film exists, the memory cell operates in the same way as it would were it electrically connected.

(6) As shown in FIG. 4C and FIG. 5, an insulation film 6 is formed between each of the floating gates 42, 53, and 54 and the control gate 7. The insulation film 6 is formed on the side face of each of the second and third conductors 51 to 56. The insulation film 6 is formed on the top face of each of the second and third conductors 51 to 56, first conductor, and isolation regions 21 to 24. The insulation film 6 is formed on the inner wall of the trench sections 11. For the insulation film 6, a three-layered structure made of a silicon oxide film, a silicon nitride film, and a silicon oxide film, a so-called ONO film is used.

(7) As shown in FIG. 1B, the control gate 7 is deposited above the insulation film 6. The control gate 7 is filled up in a trench sections 11. The control gate 7 is deposited in proximity to the side face of each of the second and third conductors 51 to 56. The second and third conductors 51 to 56 and the control gate 7 each have a large coupling capacitance.

(8) As shown in FIG. 1A, the control gate materials 7 and 27 are formed in a striped shape by lithography steps and etching. This etching uses the same mask or the etched control gate materials 7 and 27 are used as masks. Further, the isolation regions 21 to 25 are used as masks, and the first to third conductors 42 and 44 and the like are etched as shown in FIG. 2A and FIG. 2B. In this etching, as shown in FIG. 1B, it is preferable that the control gate 7, the second and third conductors 56 and the like, and the insulation film 6 each having thickness H1 equal to each other are etched at the same etching-rates at the same time. In this etching, etching condition with high deposition rates of absorbates may be selected. In addition, a second modified example of the first embodiment as described later, may be employed. In this manner, even if etching rates are different from each other depending on the material, a good etching shape can be obtained.

Lastly, the isolation regions 21 to 24 or the control gate materials 7 and 27 are used as masks, and ion implantation is carried out for the substrate 1. The implanted impurities are activated. In this manner, source/drain regions 81 to 87 are formed.

In a manufacturing method in accordance with the first embodiment, lithography and etching steps are not required for separating a generally used floating gate. An alignment margin, i.e. overlay in an active region for the floating gates 41 to 43 is not required. The isolation regions 21 to 24 and the active region can be formed in a self-aligned manner. In this manner, cell-minuteness can be enhanced. As shown in FIG. 1B, the transverse width of a cell can be scaled down to be twice that of a minimum design dimension F. This is because the width and interval of the isolation region 23 and the like can be set to F, respectively. In a semiconductor integrated circuit using a high voltage, its isolation space can be reduced down to F. The chip area for this semiconductor integrated circuit can be reduced. Thereby, the manufacturing cost of this semiconductor integrated circuit can be reduced.

In addition, the second and third conductors 51 to 56 are formed to both ends of the first conductors 41 to 43, as sidewalls of the isolation regions 21 to 24 in a self-aligned manner. The film thickness of the first to third conductors can be decreased. Thus, the parasitic capacitance C1 between floating gate electrodes and the adjacent cells can be reduced. Thereby, reducing interference the threshold voltage between cells caused by this parasitic capacittance. In this way, the minuteness of the flash memory can be enhanced, while maintenance of the capacitive coupling between each of the floating gates 41 to 43 and the like and the control gate 7 is achieved.

First Modified Example of First Embodiment

As shown in FIG. 6, capacitive coupling between a floating gate and a control gate can be increased by increasing the height H2. In order to increase the height H2, the film thickness of a cap 91 and the like are principally increased. The height H2 is substantially equal to the film thickness of the cap 91 and the like. There is no need to increase the film thickness of the conductor 41 in order to increase the coupling capacitance. When the height H2 is increased, the parasitic capacitance C1 between the floating gates increases. However, the increment of the parasitic capacitance C1 with the height H2 is increased, is smaller than that of the increase of capacitance between each of the floating gates 41, 51, and 52 and the control gate 7.

Second Modified Example of First Embodiment

In the first embodiment, the side face of the second floating gate 51 and the like provided at the side face of each of the isolation regions 21 to 24 are perpendicular to the surface of the substrate 1. In such a case, where these faces are vertically parallel to each other, the control gates 7 and 27 are formed in a striped shape, as shown in FIG. 1A, by means of RIE (Reactive Ion Etching). When this etching is carried out, the control gate 7 and the floating gates 51 and 52 are processed to be etched continuously using the same mask in a self-aligned manner. At this time, a vertical insulation film 6 between the side face of each of the floating gates 51 and 52 and the side face of the control gate 7 is difficult to remove. The unremoved insulation film 6 acts as a mask, and when etching of the first electric conducting film 41 at the lower layer etching residue can occur. This etching residue produces electrical shorts between the floating gates in the adjacent cells. This etching residue causes malfunction of the semiconductor device thus, reducing the yield.

In accordance with a second modified example of the first embodiment, as shown in FIG. 7, the sectional shapes of the second and third conductors 151 to 156 are formed in a tapered shape. The processing facility of the insulation film 16 during etching is enhanced by this shape. The secondhand third conductors are formed in a downward tapered shape, whereby the insulation film 16 is diagonally disposed. Even by means of anisotropic etching such as RIE, the insulation film 16 can be easily removed with a small amount of etching. This downward tapered shape can be achieved by changing the etching condition for separating the second and third conductors 151 to 156 from each other (for example, by lowering a substrate temperature) during etching.

Second Embodiment

In the first embodiment, only the inner faces of trench 11 of each of the second and third conductors 51 to 56 are proximal to the control gate 7. In a second embodiment, as shown in FIG. 8B, the outer faces of the trench 11 of each of the second and third conductors 51 to 56 are proximal to the control gate 7 as well. In a semiconductor device of the second embodiment, the capacitive coupling between each of the second and third conductors 51 to 56 and the control gate 7 can be increased more than in the semiconductor device of the first embodiment.

The manufacturing method is identical to that in accordance with the first embodiment with respect to the steps (1) to (5), as shown in FIG. 4B. Next, as shown in FIG. 8A, for example, the isolation regions (STI) 21 to 24 are etched back in accordance with a wet etching technique. The subsequent steps are identical to the step (6) on wards of the first embodiment, as shown in FIG. 4C. That is, as shown in FIG. 8B, the insulation film 6 is formed on the first conductors 41 to 43 and the second and third conductors 51 to 56. Further, an electric conducting film that is a control gate 7 is formed on the insulation film 6. By using such a structure, both side faces of the second and third conductors 51 to 56 can be coupled with the control gate capacitively. When the height of the second and third conductors 51 to 56 is identical to those of first embodiment, the capacitive coupling in accordance with the second embodiment is larger than that in the first embodiment. In addition, in order to obtain capacitive coupling in size equal to that of the first embodiment, the height of the second floating gate 51 in the second embodiment can be smaller than that of the first embodiment.

The height of the top face of the isolation regions 21 to 24 are each defined to be larger than that of the top face of the polycrystalline silicon film of the first conductors 41 to 43 each. In this manner, a short circuit between the control gate 7 and the control gate 27 shown in FIG. 1A and FIG. 2A can be prevented.

In contrast to this embodiment, as shown in FIG. 9A, a disadvantage will be given with respect to a case in which the height of the top face of the isolation region 22 is smaller than that of the top face of a first conductor 41. In this case, the control gate 7 is provided at a position that is lower than the height of the top face of the first conductor 41. Then, the control gate 7 is provided downwardly of a third conductor 52 as in a region 116. This is because the third conductor 52 is spread in the isolation region 22 more significantly than the first conductor 41. The third conductor 52 is disposed over the isolation region 22. This spreading occurs during preprocessing of the step of depositing the third conductor 52 on the first conductor 41. In this preprocessing, a native oxide film on the first conductor 41 is removed by etching. At this time, an exposed isolation region 22 is also etched, and the interval between the isolation regions 21 and 22 is increased.

Then, in the structure shown in FIG. 9A, the control gate 7 and the control gate 27 are separated from each other. The control gate 7, the block insulation film 6, the conductor 52, and the first conductor 41 are etched substantially vertically by means of anisotropic etching. In this separation processing, the following fault occurs.

First, the control gate 7 is patterned and vertically processed. The block insulation film 6 remains unetched. A region 116 of the control gate 7 downward of the third conductor 52 also remains without being etched. This is because the third conductor 52 masks the region 116 from etchant.

Then, the block insulation film 6 is subjected to anisotropic etching. The block insulation film 114 under the third conductor 52 remains unetched. This is because the third conductor 52 masks the film 114 from etchant. The region 116 also remains unetched.

Lastly, the first conductor 41 is removed by etching. When this etching is carried out, the film 114 and region 116 may still remain unetched. This etching residue region 116 causes a short-circuit failure between the adjacent data control lines 7 and 27. This short-circuit fault was found out by the Inventor et al.

In a case where the region 116 is removed and no longer exists, with only the film 114 remaining after etching, a failure may occur. This is because, when ion implantation is carried out to form a source/drain region, the film 114 works as a mask for ion implantation. In addition, this is because, when etching is carried out to form a contact electrode in a source/drain region, the film works as an etching mask.

From the foregoing, in the second embodiment, the height of each of the isolation regions 21 to 24 at the memory cell section is controlled to be greater than that of the top face of the first floating gate 41. In this manner, the etching residue area 116 for the control gate electrode 7 does not occur.

Third Embodiment

In the first embodiment, the second and third conductors 51 to 56 are formed as sidewalls of the side faces of the isolation regions 21 to 24. The second and third conductors 51 to 56 are separated from each other in accordance with etching back steps. These etching back steps cause the following problems to occur.

First, the first and second conductors 51 to 56 which carry out the etching, are made of apolycrystalline silicon film. The first conductors 41 to 43 are provided at the lower layer of the second and third conductors 51 to 56. These first conductors 41 to 43 are also made of a polycrystalline silicon film. In the etching back steps, the first conductors 41 to 43 are also etched in order to reliably separate the second and third conductors 54 and 55 from each other. In this manner, the film thicknesses of a finish of the first conductors 41 to 43 each vary in size between and within of the semiconductor storage devices. The Inventor found the possibility that cell characteristics vary.

Next, the film thicknesses of the first conductors 41 to 43 each can be decreased in order to reduce the parasitic capacitance C1 between cells. This is because, even if the film thickness is decreased, the capacitive coupling between a control gate and a floating gate is not decreased. However, if the film thicknesses of the first conductors 41 to 43 each are decreased, the surface of the thin films 41 to 43 each is etched in the etching back steps. In this etching, a pinhole defect occurs with the thin films 41 to 43. The Inventor found the possibility of this degrading the reliability of tunnel oxide films 31 to 33 in the lower layer of the films 41 to 43.

Lastly, in FIG. 8A, the second and third conductors 51 to 56 each have an area that comes into contact with the first floating gates 41 to 43 in the lower layer. From the foregoing, the Inventor investigated the possibility that, if the heights of the second and third conductors 51 to 56 are too large, the second and third conductors 51 to 56 are released from the first conductors 41 to 43, and the released conductors fall down.

In the third embodiment, the second and third two conductors 51 and 52 of one memory cell each have an integrated structure by which they are connected to each other without being separated. In the etching back steps of separating the third and second conductors 54 and 55 from each other, a first conductor 43 is not exposed between the second and third conductors 55 and 56.

That is, a semiconductor device in accordance with the third embodiment has a semiconductor substrate 1 having plural trenches on a surface, as shown in FIG. 1A. The isolation regions 21 to 24 are placed in the trenches. The side faces of the isolation regions 21 to 24 are each provided at a position higher than the surface of the substrate 1. The tunnel oxide films 31 to 33 are provided on the surface of the substrate 1. Both ends of the tunnel oxide films 31 to 33 come into contact with the isolation regions 21 to 24. A floating gate has the first conductors 41 to 43 and the second conductors 51 to 53. The first conductors 41 to 43 are provided on the surfaces of the tunnel oxide films 31 to 33.

Both end faces of the first conductors 41 to 43 come into contact with the isolation regions 21 to 24. The second conductors 51 to 53 are provided on the surfaces of the first conductors 41 to 43. The bottoms of the second conductors 51, 53, and 55 come into contact with the first conductors 41 to 43. Both ends of the second conductors 51, 53, and 55 are higher than the center. The heights at both ends of these conductors are each substantially equal to the height of the top face of the isolation region. The insulation film 6 between the floating gate and the control gate comes into contact with the surfaces of the second conductors 51 to 53. The insulation film 6 is provided on the top faces of the isolation regions 21 to 24. The control gate 7 is provided on the insulation film 6.

The floating gate is laminated in two layers made of the first conductors 41 to 43 and the second conductors 51 to 53. In the second conductors 51 to 53 in accordance with the third embodiment, while the second and third conductors 51 and 52 in accordance with the first and second embodiments are integrally coupled with each other on the first conductors 41 to 43. In the conductors 41 to 43 and 51 to 53, the thickness is defined to be small, whereby the parasitic capacitance C1 between the floating gates of the adjacent memory cells can be reduced without decreasing the capacitance between the floating gate and the control gate.

Now, a method of manufacturing a semiconductor device in accordance with a third embodiment will be described here.

The manufacturing method used is substantially identical to that described with reference to FIG. 3A to FIG. 4A in accordance with the first embodiment. That is, the trench sections 10, the first conductors 41 to 43, and the active region are processed in a self-aligned manner.

(1) As shown in FIG. 3A, on a p-type silicon (Si) substrate 1, silicon oxide films or silicon oxynitride films 31 to 33 (SiO.sub.2) are formed, by thermal oxidization. These silicon oxide films or silicon oxynitride films 31 to 33 are produced as a tunnel oxide film of a nonvolatile memory cell. The film thickness of the silicon oxide films or silicon oxynitride films 31 to 33 each is within a range of 3 nm to 15 nm. The film thickness of the silicon oxide films or silicon oxynitride films 31 to 33 each is for example about 10 nm. Subsequently, a polycrystalline silicon (Si) film is formed as part of the first conductors 41 to 43 of a floating gate on the silicon oxide films 31 to 33. The film thickness of the first conductors 41 to 43 each is within a range of 10 nm to 500 nm. The film thickness of the first conductors 41 to 43 each is for example about 30 nm. Further, a silicon nitride film that serves as the caps 91 to 93 is deposited on each of the first conductors 41 to 43. The film thicknesses of the cap materials 91 to 93 each are within a range of 3 nm to 500 nm. The film thicknesses of the cap materials 91 to 93 are for example about 120 nm.

Next, the trenches 10 are grooved in the regions that are defined as the isolation regions 21 to 24 by means of photolithography and etching. Specifically, the caps 91 to 93, the first conductors 41 to 43, and the silicon substrate 1 are etched in sequence in the regions that are defined as the isolation regions 21 to 24. As shown in FIG. 3A, the trenches 10, the first conductors 41 to 43, and the caps 91 to 93 can be formed in a self-aligned manner. In this form, cell minuteness can be enhanced, and a variation in memory cell characteristics caused by the effects of electric field concentration can be suppressed because no floating gate is formed to cover the corner portions of the active regions. The depth of the trenches 10 in the silicon substrate 1 is within a range of 50 nm to 1000 nm. The depth of the trenches 10 in the silicon substrate 1 is about 300 nm, for example. After forming the trenches 10 for isolation, a thin silicon oxide film is formed on an exposed face between the substrate 1 and the first conductor by a thermal oxidization technique as required. The film thickness of this thin silicon oxide film is within a range of 3 nm to 20 nm. The film thickness of this thin silicon oxide film is for example about 5 nm.

Next, an insulation film is placed in the trenches 10, for example, by a HDP (High Density Plasma) technique. After an filler material has been deposited, the insulation film is polished and flattened up to the top face of the caps 91 to 93 by a method such as CMP (Chemical Mechanical Polish technique. As shown in FIG. 3B, the isolation regions 21 to 24 are placed at the ends of the floating gates 41 to 43 in a self-aligned manner As shown in FIG. 3B, the isolation regions 21 to 24 are filled up to the ends of the floating gates 41 to 43 in a self-aligned manner. Next, as shown in FIG. 3C, the cap materials 91 to 93 are removed. In this manner, the trench sections 11 surrounded by the isolation regions 21 to 24 is formed. Next, a thin polycrystalline silicon film 5 produced as the second conductors 51 to 53 of a floating gate electrode is deposited. The film thickness of this polycrystalline silicon film 5 is within a range of 3 nm to 250 nm. The film thickness of this polycrystalline silicon film 5 is for example about 20 nm. The above manufacturing method is basically identical to that in the first embodiment.

Next, as shown in FIG. 12A, for example, a photoresist 76 is fully coated on the polycrystalline silicon film 5. As shown in FIG. 12B, a resist 76 is etched back. In this manner, a polycrystalline silicon film 5 positioned on the isolation regions 21 to 24 is exposed. The etched back resists 77 to 79 are placed into the trenches 11. As shown in FIG. 12C, for example, the polycrystalline silicon film 5 on the isolation regions 21 to 24 are removed by means of etching back using an RIE technique. The second conductors 51 to 53 of the floating gate electrode are formed. As shown in FIG. 12D, the resists 77 to 79 are removed.

Lastly, the insulation film 6 between the floating gate and the control gate is formed on each of the second conductors 51 to 53 and the isolation regions 21 to 24. Then, as shown in FIG. 11A, a polycrystalline silicon film produced as the control gate 7 is deposited.

First Modified Example of Third Embodiment

In a semiconductor device in accordance with a first modified example of the third embodiment, as shown in FIG. 11B, the heights of the top face of the isolation regions 21 to 24 lower than that of the tops of the second conductors 51 to 53. The heights of the top faces of the isolation regions 21 to 24 are each equal to or greater than that of the tops of each of the second conductors 51 to 53. Therefore, etching residue, as shown in FIG. 9, does not occur. The control gate 7 disposed over the isolation regions 21 to 24 and the second conductors 51 to 53 are proximal to each other via the insulation film 6. That is, at a side face portion at the outside of the second conductors 51 to 53, the second conductors 51 to 53 are proximal to each other via the control gate 7 and insulation film 6. In this manner, in the first modified example of the third embodiment, the capacitive coupling between the control gate 7 and each of the floating gates 51 to 53 can be increased more significantly as compared with the third embodiment.

Now, a method of manufacturing a semiconductor device in accordance with the first modified example of the second embodiment will be described. The steps executed until the second conductor 5 shown in FIG. 4A is deposited are identical to those in accordance with the first and third embodiments. Next, as shown in FIG. 13A, a silicon oxide 120 is deposited by the CVD technique. As shown in FIG. 13B, the silicon oxide film 120 is etched back. A second conductor 5 over the isolation regions 21 to 24 is exposed. The silicon oxide films 121 to 123 are filled into the trenches 11. At this time, it is desirable that the residual film thickness "d" of the silicon oxide films 121 to 123 of the trench 11 is less than the etching depth of the isolation regions 21 to 24 as will be shown in FIG. 13D.

Next, as shown in FIG. 13C, the second conductor 5 provided on the isolation regions 21 to 24 is removed by means of the CMP technique or etching back technique. The second conductor 5 is separated from the second conductors 51 to 53. In accordance with the CMP technique, the height of the second conductor remaining on the side face of the trenches 11 can be precisely controlled.

Next, as shown in FIG. 13D, the silicon oxide films 121 to 123 and the isolation regions 21 to 24 are etched. By means of this etching, the silicon oxide films 121 to 123 in the trenches 11 are removed. The top face of the second conductor is exposed. Then, the isolation regions 21 to 24 are etched to a desired depth. At this time, if the residual film thickness "d" of the silicon oxide films 121 to 123 are each less than the desired depth, the silicon oxide films 121 to 123 can be removed at the same time as when the isolation regions 21 to 24 are etched. By means of this etching, fin shaped protrusions are exposed in parallel pairs on the outer sides of each of the second conductors 51 to 53. The entire bottom faces of the second conductors 51 to 53 come into contact with the entire top faces of the first conductors 41 to 43, and thus, the protrusion is sturdy and difficult to knock down.

Lastly, as shown in FIG. 11B, the insulation film 6 is formed on the isolation regions 21 to 24 and each of the second conductors 51 to 53. A polycrystalline silicon film produced as the control gate 7 is deposited on the insulation film 6.

Second Modified Example of Third Embodiment

In a semiconductor device in accordance with a second modified example of the third embodiment, as shown in FIG. 1C, second conductors 57 to 59 are disposed on the isolation regions 124 to 127. In this manner, the area opposite the floating gates 57 to 59 and the insulation film 6 of the control gate 7 can be defined as larger than a semiconductor device in accordance with the third embodiment. In the second modified example of the third embodiment, the capacitive coupling between the control gate 7 and each of the floating gates 57 to 59 can be increased more significantly as compared with that in the third embodiment.

Now, a method of manufacturing a semiconductor device in accordance with a second modified example of the third embodiment will be described. The steps executed until up the cap materials 91 to 93 shown in FIG. 3C are removed are identical to those in accordance with the first and third embodiments. Next, as shown in FIG. 14A, the isolation regions 124 to 127 are etched by means of isotropic etching such as wet etching. By means of this etching, the isolation regions 124 to 127 are retracted. The isolation regions 124 to 127 laterally placed on the first conductors 41 to 43 are removed as well. The width of the trenches 11 is increased.

Next, as shown in FIG. 14B, a second conductor 5 is formed as a film on the isolation regions 124 to 127 and the first conductors 41 to 43. In particular, the second conductor 5 is formed as a film on the first conductors 41 to 43 as well. The subsequent manufacturing method is identical to that in accordance with the third embodiment shown in FIG. 12A to FIG. 12D. That is, as shown in FIG. 14C, when the second conductors 57 to 59 inside of the trenches 11 are protected with the photo resists 77 to 79, the second conductors 57 to 59 are divided. In accordance with such steps, a shape in which the second conductors 57 to 59 are extended on the isolation regions 124 to 127 can be formed.

Third Modified Example of Third Embodiment

A semiconductor device in accordance with a third modified example of the third embodiment has characteristics in accordance with the first modified example of the third embodiment and in accordance with the second modified example of the third embodiment, as shown in FIG. 11D. The side faces outside of the second conductors 57 to 59 are opposite to each other via the control gate and insulation material 6. In addition, the second conductors 57 to 59 are disposed on the isolation regions 124 to 127, and extend to the isolation regions 124 to 127.

The height of the top face of the isolation regions 124 to 127 is less than that of the top part of the second conductors 57 to 59 each. Then, the height of the top face of the isolation regions 124 to 127 are each equal to or greater than the bottom part of each of the second conductors 57 to 59. Therefore, the etching residue 116 shown in FIG. 9 does not occur. The control gate 7 is disposed over the isolation regions 124 to 127 and the second conductors 57 to 59 are opposite to each other via the insulation film 6. In this manner, in the third modified example of the third embodiment, the capacitive coupling between the control gate 7 and each of the floating gates 57 to 59 can be increased more significantly as compared with the third embodiment. A method of manufacturing a semiconductor device of a third modified example of the third embodiment is based on those of the first and second modified examples of the third embodiment.

Fourth Embodiment

A fourth embodiment describes the third modified example, in particular, of the third embodiment in more detail. The semiconductor device in accordance with the fourth embodiment is a nonvolatile semiconductor storage device with a NAND structure. The semiconductor device in accordance with the fourth embodiment is characterized in that the step difference between a region between a memory cell region and a peripheral circuit region and an upper face of the control gate electrode 7 in a memory cell region is small. In the fourth embodiment, insulation films 101 and 102 shown in FIG. 15B can be regarded as isolation regions 124 to 127 as well. In this manner, the shapes of the isolation regions 101, 102, 124, and 127 shown in FIG. 15B are considered to be identical to those of the isolation regions 124 to 127 in the third modified example of the third embodiment shown in FIG. 11D.

A memory cell region is shown in the left section of FIG. 15A and in FIG. 15B. The periphery circuit region is shown in the right section of FIG. 15A and in FIG. 15C. The control gates 28, 7, and 27 having widths equal to each other are disposed in a transverse direction in parallel at equal intervals in the memory cell region. The isolation regions 124 to 127 are disposed in a longitudinal direction in parallel downward of the control gates 28, 7, and 27 in FIG. 15A. In a memory cell region, the isolation regions 124 to 127 have widths equal to each other, and are disposed at equal intervals, for example. This placement makes the breakdown voltages of isolations uniform. This placement makes the channel conductance of cells uniform. This placement makes the transport characteristic of cells uniform. The source/drain regions 81 to 87 of the memory cells 162 and 163 and the dummy cell 161 are disposed in a region in which the control gates 28, 7,and 27 and the isolation regions 124 to 127 are not disposed. A source/drain region 88 of a periphery circuit 164 is provided in a region in which the control gates 28, 7, and 27 and the isolation region 124 are not disposed.

The bottom face of the control gate electrode 7 formed over the isolation regions 124 to 127 is disposed upward of a stacked direction than the top face of the first conductors 41 to 43. The maximum distance between the two outer side faces of the second conductor 58 is greater than that between two end faces of the first conductor 42. The lower face of the second conductors 58 and 59, i.e., the lower end of the outer side face is provided further down from the top face of the first conductors 42 and 43. The second conductors 58 and 59 are linked as one body on the first conductors 42 and 43. A distance between the two outer side faces of the second conductors 58 and 59 is reduced toward the top part of this side face. The control gate electrode 7 is opposed to the top face and side face of the second conductors 58 and 59 via the block insulation film 6. An isolation region 125 comes into contact with a second conductor 57. An isolation region 124 also comes into contact with the second conductor 57. The isolation region 124 is larger in width than the isolation region 125. The height of the top face of the isolation region 124 is larger than that of the top face of the isolation region 125.

A dummy cell 161 is formed between a memory cell array that consists of a plurality of memory cells 162 and 163 and a periphery circuit 164. The dummy cell 161 stabilizes an operation or process controllability of the memory cells 162 and 163. The dummy cell 161 has a structure that is substantially identical to the memory cells 162 and 163, and is formed adjacent to the memory cells 162 and 163. The number of dummy cells 161 may be formed in plurality, of course, without being limited to one. In addition, for the purpose of convenience to display signs clearly, the dummy cell 161 and the periphery circuit 164 are displayed separately from each other in FIG. 15B and FIG. 15C. The dummy cell 161 and peripheral-circuit 164 are formed continuously using a common isolation region 124. The peripheral circuit 164 denotes a device that serves as a MIS transistor except the memory cells 162 and 163.

The impurity concentration of boron (B) of the p-type silicon substrate 1 is within the range of 10.sup.14 cm.sup.-3 to 10.sup.19 cm.sup.-3 . On the p-type silicon substrate 1, for example, there are provided gate insulation films 31 to 33 and 35 that are a silicon oxide film or oxynitride film with 3 nm to 15 nm in thickness, for example. First conductors 41 to 43 and 141 that consist of polycrystalline silicon are provided on the gate insulation films 31 to 33 and 35. The first conductors 42 and 43 serve as a first charge storage layer of the floating gates of the memory cells 163 and 162. To the first conductors 41 to 43 and 141, for example, phosphor (P) or arsenic (As) are introduced within a range of 10.sup.18 cm.sup.-3 to 10.sup.21 cm.sup.-3. The thickness of the first conductors 41 to 43 and 141 is within a range of 10 nm to 500 nm. In addition, the gate insulation films 31 to 33 and 35 and the first conductors 41 to 43 and 141 are provided on a fully leveled plane. In this manner, a variation between cells in electrical characteristics of the memory cells 162 and 163 can be made uniform. A floating gate sidewall oxide film 101 is provided on the side face of the first conductors 41 to 43 and 141.

The second conductors 57 to 59 and 157 are provided on the first conductors 41 to 43 and 141 and the float gate sidewall oxide film 101. The second conductors 57 to 59 and 157 are polycrystalline silicon introduced within a range of 10.sup.18 cm.sup.-3 to 10.sup.21 cm.sup.-3 in impurity concentration where phosphor or arsenic is defined as impurities. The thicknesses of the second conductors 57 to 59 are within the range of 3 nm to 500 nm. Preferably, the thicknesses of the second conductors 57 to 59 are each smaller than half of the thicknesses of each of the first conductors 41 to 43, and within a range of 3 nm to 100 nm. Further, with in this range, capacitive coupling between the control gates is not reduced. In addition, the resistance component is hardly increased, leading to the result that a data readout time or write time is significantly increased. On the contrary, a capacitive coupling between cells can be decreased.

The second conductors 57 to 59 come into contact with the top part of the side face and the full face of the top face of each of the first conductors 41 to 43. That is, the second conductors 57 to 59 cover the top face and side face of the first conductors 41 to 43. In addition, the second conductors 57 to 59 are integrated as one body unlike the conductors 51 and 52 shown in FIG. 1B. In this manner, the second conductors 57 to 59 and the first conductors 41 t 43 come into intimate contact with each other in a larger area. Thus, the peeling off caused by the internal stress of the second conductors 57 to 59 and by the external force relevant to the second conductors 57 to 59 can be prevented.

The second conductors 58 to 59 each serve as a second charge storage layer of a floating gate of each of the memory cells 162 and 163. The top faces of the outer sides of the second conductors 58 and 59 are each higher than the top faces of the inside of the second conductors 58 and 59. The second conductors 58 and 59 are formed in a form of an uppercase letter H. The second conductors 58 and 59 have a first side face on the outside right and a second side face on the outside left. The second conductors 58 and 59 have a third side face on the inside left and a fourth side face on the inside left. The lower part of the first and second side face at the outside of the second conductors 58 and 59 comes into contact with the isolation regions 125 to 127. The block insulation film 6 is provided on the first, second, third and fourth side face. The block insulation film 6 is provided on the top face of inside of each of the second conductors 58 and 59. The block insulation film 6 is provided on each of the upper face inside of the second conductors 58 and 59. The control gate 7 is provided on this insulation film 6. The block insulation film 6 is formed of a silicon oxide film, an oxynitride film or a stacked film (ONO film) that consists of a silicon oxide film/a silicon nitride film/a silicon oxide film. The thickness of the silicon oxide film or the oxynitride film is within a range of 5 nm to 30 nm. The thickness of a silicon oxide film/a silicon nitride film/a silicon oxide film of the ONO film is within a range of 2 nm to 100 nm in thickness, respectively. The control gate 7 is made of polycrystalline silicon introduced within a range of 10.sup.17 cm.sup.-3 to 10.sup.21 cm.sup.-3 in impurity concentration, where phosphor arsenic or boron is defined as impurities. In addition, the control gate 7 may be structured to be stacked with tungsten silicide (WSi) and polycrystalline silicon. In addition, the control gate may be structured to be stacked with nickel silicide (NiSi), molybdenum silicide (MoSi), titanium silicide (TiSi), cobalt silicide (CoSi), and polycrystalline silicon. The thickness of the control gate 7 is within a range of 10 nm to 500 nm. The block insulation film 6 and control gate 7 positioned over the isolation regions 125 to 127 are formed over the top faces of the first isolation regions 125 to 127. Similarly, the block insulation film 6 and control gate 7 positioned upward of the isolation regions 125 to 127 are formed over the lowest face of the second conductors 58 and 59. That is, the height H shown in FIG. 15B is obtained as a positive value. In this manner, an etching residue 116 of the control gate 7 described in FIG. 9 is not generated.

On the silicon substrate 1, the isolati