Title: Semiconductor device and manufacturing the same
Abstract: A semiconductor device is designed to resist warpage of a heat sink with an inexpensive construction. The device comprises a heat sink, a pair of screwing pieces having inner end portions connected to ends of the heat sink and outer end portions formed with through spaces for screwing, a semiconductor chip fixed to a main surface of the heat sink, a seal covering a back side of the heat sink and partially covering the paired screwing pieces, first and second leads having outer end portions projecting from the seal member and inner end portions within the seal member near respective side faces of the heat sink, and conductive wires electrically connecting the leads and predetermined electrodes of a semiconductor chip.
Patent Number: 6,847,112 Issued on 01/25/2005 to Ito
| Inventors:
|
Ito; Mamoru (Tamamura, JP)
|
| Assignee:
|
Renesas Technology Corp. (Tokyo, JP)
|
| Appl. No.:
|
318018 |
| Filed:
|
December 13, 2002 |
Foreign Application Priority Data
| Feb 06, 2002[JP] | 2002-029598 |
| Current U.S. Class: |
257/712; 257/666; 257/675; 257/704; 257/706; 257/720 |
| Intern'l Class: |
H01L 023/34; H01L023/12 ; 692-693 |
| Field of Search: |
257/704,706-707,712,717-718,719-720,723,730-731,796,787,675-676,666,685,690
|
References Cited [Referenced By]
U.S. Patent Documents
| 5907474 | May., 1999 | Dolbear.
| |
| 2002/0025606 | Feb., 2002 | Kurihara et al.
| |
Primary Examiner: Pham; Long
Assistant Examiner: Nguyen; Dilinh
Attorney, Agent or Firm: Miles & Stockbridge P.C.
Claims
What is claimed is:
1. A semiconductor device comprising:
heat sink formed of a metallic plate;
a pair of screwing pieces having respective inner end portions connected
respectively to the heat sink, the screwing pieces further having outer
end portions formed with through spaces for screwing;
one or plural semiconductor chips fixed to the main surface of the heat
sink;
a seal member, the seal member covering a main surface portion of the heat
sink and also covering the inner end portions of the screwing pieces;
a first lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
electrically connected to the semiconductor chip;
a second lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
electrically connected to the semiconductor chip; and
wherein the heat sink and the screwing pieces are constituted by respective
discrete pieces;
a thickness of the heat sink is larger than thickness of the screwing
pieces; and
the screwing pieces are more easily deformed than the heat sink.
2. A semiconductor device according to claim 1, wherein the heat sink and
the screwing pieces are connected with each other using screws, or by
welding or soldering, or with rivets.
3. A semiconductor device according to claim 1, wherein the seal member is
formed by transfer molding, and side portions of the seal member which
side portions overlap the screwing pieces are partially recessed inwards
of the seal member.
4. A semiconductor device according to claim 1, wherein the inner end
portions of the first and second leads are respectively formed with
engaging portions for engagement with a resin which constitutes the seal
member.
5. A semiconductor device according to claim 1, wherein the first lead or
the second lead is partially formed with a polarity identifying portion.
6. A semiconductor device according to claim 1, wherein the inner ends of
the first and second leads are positioned respectively in regions diverted
from the heat sink.
7. A semiconductor device according to claim 1, wherein the inner ends of
the first and second leads are positioned inside the heat sink with
respect to side edges of the heat sink and are electrically isolated from
the heat sink.
8. A semiconductor device according to claim 7, wherein the heat sink and
the inner end portions of the first and second leads overlap each other
through insulating spacers.
9. A semiconductor device according to claim 8, wherein the seal member is
formed by transfer molding, side portions of the seal member which side
portions overlap the screwing pieces are partially recessed inwards of the
seal member, and the spacers are respectively provided with through spaces
including regions corresponding to the recesses.
10. A semiconductor device according to claim 7, wherein in the seal
member, the one or plural semiconductor chips and the wires are covered
with an undercoat resin higher in heat resistance than a resin which
constitutes the seal member.
11. A semiconductor device according to claim 1, wherein Au plating film
having a thickness of about 0.2 .mu.m or less is formed on surfaces of the
leads, while thicker Au plating film is formed on the main surface of the
heat sink.
12. A semiconductor device according to claim 1, wherein upper electrodes
of the same function formed on all the semiconductor chips are arranged in
lines in a first direction, while the wires extend in a second direction
intersecting the first direction.
13. A semiconductor device according to claim 1, wherein the seal member is
formed of an insulating resin, the wires are aluminum wires, the
electrodes on the semiconductor chips are aluminum electrodes, and a pn
junction temperature in operation of conductive layers formed in the one
or plural semiconductor chips is 150.degree. C. or higher.
14. A semiconductor device according to claim 1,
wherein a semiconductor chip with a field effect transistor formed thereon
and semiconductor chips with capacitors formed thereon are fixed to the
main surface of the heat sink in such a manner that the capacitor-formed
semiconductor chips are positioned on both sides in the gate-drain
direction of the field effect transistor-formed semiconductor chip,
wherein a drain electrode on an upper surface of the field effect
transistor and an upper electrode of one of the semiconductor chips with
capacitors formed thereon are connected with each other through a
plurality of the wires, and the upper electrode and the first lead are
connected with each other through a plurality of the wires, and
wherein a gate electrode on the upper surface of the field effect
transistor and an upper electrode of another capacitor-formed
semiconductor chip are connected with each other through a plurality of
the wires, and the upper electrode and the second lead are connected with
each other through a plurality of the wires, to constitute a high
frequency power amplifier for a base station.
15. A semiconductor device according to claim 1, including plural sets of
the first and second leads and plural sets of the semiconductor chips
whose electrodes are connected to the leads directly or indirectly through
wires.
16. The semiconductor device of claim 1, wherein each of the screwing
pieces has a bent portion, the bent portion serving as a buffer portion
adapted to deform under a stress.
17. A semiconductor device comprising:
heat sink formed of a flat metallic plate having a high thermal
conductivity;
a pair of screwing pieces having respective inner end portions connected
respectively to right and left ends of the heat sink on a main surface
side of the heat sink, the screwing pieces further having outer end
portions formed with through spaces for screwing;
one or plural semiconductor chips fixed to the main surface of the heat
sink;
a seal member formed of an insulating resin, the seal member covering the
main surface of the heat sink and also covering the inner end portions of
the screwing pieces;
a first lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
whose inner end is arranged near one side face of the heat sink;
a second lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
whose inner end is arranged near another side face of the heat sink; and
a plurality of conductive wires for electrically connecting between the
leads and predetermined electrodes of said predetermined semiconductor
chip, or between the leads and predetermined electrodes of said
predetermined semiconductor chip and also between predetermined electrodes
of said predetermined semiconductor chip and predetermined electrodes of
said predetermined semiconductor chip,
wherein the heat sink is formed of a thick material difficult to deform,
while the screwing pieces are constituted of a flexible material easy to
deform.
18. A semiconductor device comprising:
heat sink formed of a flat metallic plate having a high thermal
conductivity;
a pair of screwing pieces having respective inner end portions connected
respectively to right and left ends of the heat sink on a main surface
side of the heat sink, the screwing pieces further having outer end
portions formed with through spaces for screwing;
one or plural semiconductor chips fixed to the main surface of the heat
sink;
a seal member formed of an insulating resin, the seal member covering the
main surface of the heat sink and also covering the inner end portions of
the screwing pieces;
a first lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
whose inner end is arranged near one side face of the heat sink;
a second lead having an outer end portion projecting from the seal member
and an inner end portion which is positioned within the seal member and
whose inner end is arranged near another side face of the heat sink; and
a plurality of conductive wires for electrically connecting between the
leads and predetermined electrodes of said predetermined semiconductor
chip, or between the leads and predetermined electrodes of said
predetermined semiconductor chip and also between predetermined electrodes
of said predetermined semiconductor chip and predetermined electrodes of
said predetermined semiconductor chip,
wherein each of the screwing pieces has a bent portion at an intermediate
portion thereof projecting from the seal member and then extends so that a
back side thereof is positioned on a plane on which a back side of the
heat sink is positioned, or on a plane close to said plane, the bent
portion serving as a buffer portion adapted to deform under a stress.
19. A semiconductor device comprising:
a heat sink formed of a flat metallic plate;
a frame fixed to a main surface of the heat sink, the frame having a
frame-shaped ceramic laminate structure with wiring lines provided at
predetermined positions;
a plurality of leads projecting outside the frame, the plural leads being
connected electrically and mechanically at respective inner end portions
to predetermined wiring lines of the frame;
one or plural semiconductor chips fixed to the main surface of the heat
sink;
a plurality of conductive wires for electrically connecting the leads to
the one or plural semiconductor chips;
a metallic cap which is fixed to the frame so as to cover the one or plural
semiconductor chips and the wires and seal the frame,
wherein the metallic cap has a first portion and a second portion extended
outside the heat sink;
the first and second portions have bent portions; and
the first and second portions have through spaces for screwing.
20. A semiconductor device according to claim 19,
wherein a semiconductor chip with a field effect transistor formed thereon
and semiconductor chips with capacitors formed thereon are fixed to the
main surface of the heat sink in such a manner that the capacitor-formed
semiconductor chips are positioned spacedly on both sides of the field
effect transistor-formed semiconductor chip,
wherein a drain electrode on an upper surface of the field effect
transistor and an upper electrode of one of the semiconductor chips with
capacitors formed thereon are connected with each other through a
plurality of the wires, and the upper electrode and a first of the leads
are connected with each other through a plurality of said wires, and
wherein a gate electrode on the upper surface of the field effect
transistor and an upper electrode of another capacitor-formed
semiconductor chip are connected with each other through a plurality of
the wires, and the upper electrode and a second of the leads are connected
with each other through a plurality of the wires, to constitute a high
frequency power amplifier for a base station.
21. The semiconductor device of claim 19, wherein there are a plurality of
semiconductor chips, and the plurality of semiconductor chips are
interconnected.
Description
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of
manufacturing the same. Particularly, the invention is concerned with a
technique which is effectively applicable to a manufacturing technique for
a high frequency power amplifier (high frequency power amplifier module)
for a base station in a radio communication system such as a cellular
communication system.
SUMMARY OF THE INVENTION
In a radio communication system such as a cellular communication system, a
portable telephone set (a portable terminal) is connected to a base
station adjacent to a telephone network by a speaker's operation of the
telephone set, then is connected successively to a single or plural base
stations, and finally a portable terminal of the party being called is
called (originating a call), thereafter the portable telephone set assumes
a state which permits talking with the called party. In this case, the
base station amplifies the received signal and transfers the
thus-amplified signal. Such an amplification is performed by means of a
high frequency power amplifier for a base station.
Having made studies about the cost reduction of a high frequency power
amplifier for a base station, the present inventor reviewed a sealing
structure (package structure) as a main cause of high cost.
FIGS. 28 to 39 illustrate a semiconductor device (hereinafter referred to
as the "studied semiconductor device") which the present inventor had
studied prior to the present invention. The studied semiconductor device
is a high frequency power amplifier (a high frequency power amplifier
module). FIG. 28 is a plan view of the studied semiconductor device, FIG.
29 is a side view thereof, FIG. 30 is a plan view thereof with a cap
removed, and FIG. 31 is a schematic sectional view of the studied
semiconductor device shown in FIG. 30.
A semiconductor device 70 is manufactured using a rectangular substrate 71.
The substrate 71 is formed of a metal (e.g., CuMo plate) which is superior
in thermal conductivity so that heat generated from a semiconductor chip
is transferred promptly to an installed radiation board or mounting
substrate, thus serving also as a heat sink.
A quadrangular frame 72 is fixed by bonding (silver soldering) centrally
onto the substrate, or heat sink, 71, the frame 72 having a width smaller
than the width of the heat sink 71 and having a length shorter than long
sides of the heat sink 71. The heat sink 71 serves as a source electrode.
Screwing grooves 73 are formed centrally of both ends of the heat sink 71
at positions spaced apart from the frame 72.
As shown in FIG. 31, the frame 72 comprises a frame-shaped ceramic base 74
and two frame-shaped ceramic sleeves 75 superimposed successively on the
ceramic base 74. A metallized surface layer 75a (the dotted region in
FIGS. 28 and 30) is formed on the surface of the upper ceramic sleeve 75.
Along the width of the heat sink 71 the ceramic sleeves 75 are superimposed
one on the other at the same width as the width of the ceramic base 74 so
that their inner and outer wall surfaces are in registration with the
ceramic base, while in the long sides of the heat sink 71 the ceramic
sleeves 75 are smaller in width than the ceramic base 74 and the surface
of the ceramic base is exposed to both inside and outside of the ceramic
sleeves 75.
On the surface of the ceramic base 74 extending along the long sides of the
heat sink 71 there is formed an electrically conductive metallized layer
76. Consequently, the metallized layer 76 is exposed to the surface
portions of the ceramic base 74 inside and outside the ceramic sleeves 75.
The metallized layer portions located inside the ceramic sleeves 75 serve
as bonding posts 76a for wire connection, while the metallized layer
portions located outside the ceramic sleeves 75 serve as lead connecting
portions 76b for lead connection.
An inner end of a drain lead 77 formed of a broad metallic plate is fixed
to the lead connecting portion 76b extending along one long side of the
heat sink 71, and an inner end of a gate lead 78 formed of a broad
metallic plate is fixed to the lead connecting portion 76b extending along
the other long side of the heat sink 71. One corner of the drain lead 77
is cut off obliquely, serving as an electrode index 77a for recognition of
a drain electrode (see FIG. 28). The metallic plates which constitute the
drain lead 77 and the gate lead 78 are formed of Kovar or Fe--Ni alloy,
having such characteristics as thermal expansion coefficient and thermal
expansion coefficient difference of ceramic being small and has a
resistance to a high temperature in silver soldering.
On an upper surface of the heat sink 71 located inside the frame 72 there
are fixed a capacitor chip 79, an SiMOSFET chip 80, and a capacitor chip
81 side by side from the drain lead 77 toward the gate lead 78. In the
capacitor chips 79 and 81, an oxide film (SiO.sub.2 film) is formed on a
silicon substrate and an electrode is formed thereon to afford a
predetermined capacitance. The silicon substrate serves as one electrode,
while the electrode on the oxide film serves as the other electrode. These
chips are fixed by AuSi eutectic, which is satisfactory in heat radiating
property and electric conductivity and high in reliability, to the heat
sink 71 formed of a metallic plate, so that there is ensured an electric
contact between the substrate-side electrode of each chip and the heat
sink 71 and there is obtained a satisfactory heat radiating property.
As shown in FIG. 30, one end of each conductive wire 82 is connected to a
drain electrode 80d on the SiMOSFET chip 80, while an opposite end thereof
is connected to an upper electrode 79a of the capacitor chip 79 at a
position close to the drain lead 77. Likewise, one end of each conductive
wire 83 is connected to the upper electrode 79a of the capacitor chip 79,
while an opposite end thereof is connected to the bonding post 76a which
is connected electrically to the drain lead 77. Further, one end of each
conductive wire 84 is connected to one end of a gate electrode 80g on the
SiMOSFET 80, while an opposite end thereof is connected to an upper
electrode 81a of the capacitor chip 81 located close to the gate lead 78.
One end of each conductive wire 85 is connected to the upper electrode 81a
of the capacitor chip 81, while an opposite end thereof is connected to
the bonding post 76a which is electrically connected to the gate lead 78.
The wires 81 to 85 are formed of aluminum wires. As to the wires connected
to drain and gate electrodes, there is adopted a structure wherein plural
wires are connected in parallel to ensure current capacity and high
frequency characteristic (see FIG. 30).
As shown in FIG. 28, a cap 87 is fixed to the frame 72. The cap 87 is
formed of a ceramic plate. As shown in FIG. 29, in a peripheral portion on
a back side of the cap 87, a plating film 87a is formed of AuSn in a frame
shape correspondingly to the ceramic sleeves 75, and the ceramic sleeves
75 are fixed through the plating film 87a. That is, the cap 87 is fixed to
the frame 72 hermetically (hermetic seal structure) through AuSn alloy.
Along a side face of the frame 72 there is formed a side metallized layer
76d, as indicated with dots in FIG. 29. The side metallized layer 76d
provides an electric connection between the heat sink 71 serving as a
source electrode and the surface metallized layer 75a, placing the surface
metallized layer 75a at an equal potential to the source electrode.
Exposed portions of the heat sink 71, drain lead 77, gate lead 78, surface
metallized layer 75a, side metallized layer 7d, and metallized layer 76
are wholly plated with Au.
It is difficult to reduce the manufacturing cost of such a semiconductor
device. More particularly, (1) a heat sink made of CuMo is closely similar
in thermal expansion coefficient to a semiconductor chip formed of a
ceramic material or Si and exhibits a package stress diminishing effect;
besides, it is superior in heat radiating property, so it becomes possible
to ensure a stable operation of the associated semiconductor device.
However, the material cost is high and machining is troublesome, leading
to an increase of cost. In the structure of the semiconductor device,
moreover, the size of the heat sink used is large and hence an increase of
cost results.
(2) Thick gold plating is needed for ensuring a required heat resistance in
AuSi eutectic chip bonding, but a selective gold plating is difficult and
there must be adopted a whole-surface plating method, with consequent
increase of cost. It is necessary that the gold plating be performed to a
thickness sufficient to ensure such a heat resistance as prevents the
occurrence of discoloration of plating due to heating in chip bonding. For
AuSi eutectic, in which heating is made to about 430.degree. C., a plating
thickness of 2 .mu.m or more is needed, constituting one of causes of an
increased cost.
(3) AuSn sealing work costs high. Besides, there is obtained a package of a
hollow structure and a hermetic seal structure, so it becomes necessary to
conduct a hermetic seal leak inspection and a movable dust particle
inspection (dust particle inclusion inspection) as additional works, thus
resulting in that the inspection cost further increases.
In more particular terms, since reliability depends on whether hermetic
seal performance is good or not, it is necessary to conduct a hermetic
seal leak inspection, which causes an increase of the assembling cost.
Moreover, the management of oxygen control is important for ensuring a
high hermetic seal performance, which causes deterioration of the sealing
work efficiency and hence an increase of the assembling cost.
Further, if a hollow package is sealed with electrically conductive dust
particles mixed therein, the dust particles move around the interior of
the package under vibrations imparted to the package from the exterior. If
the moving dust particles span the electrodes, there is a fear that an
electrically semi-shorting defect may result, thus requiring the dust
particle inclusion inspection as an essential condition.
On the other hand, a review of the semiconductor device 70 from the
standpoint of electrical characteristics has revealed that the following
problems are involved therein.
In the case of a base station for mobile telephone, the frequency is about
0.8 to about 2.1 GHz and an output as large as 60 to 250 W is required as
the output of a final-stage power amplifying FET. A supply voltage of an
amplifier which uses MOSFET (Metal Oxide Semiconductor
Field-Effect-Transistor) made of Si as FET for output is about 28V, so in
the case of an FET with an output of 125 W and a drain efficiency of about
50%, an average current is about 9A and a peak current reaches 27A which
is about three times as large as the average current.
Since such a large current is handled, it is necessary to use a large-sized
FET chip with a gate width of 20 cm or so, and input and output
capacitances become as large as nearly 150 PF and 80 PF, respectively,
resulting in the device being very low in impedance ACwise. For this
reason, a high frequency loss increases at a frequency band of 1.5 GHz or
higher. For avoiding this inconvenience, an internal matching circuit is
included between FET chip and package electrode leads to increase the
impedance of the lead portions.
FIG. 32 is an equivalent circuit diagram in which internal matching
circuits are provided on an input side (gate side) and an output side
(drain side), respectively. Between a gate electrode 80g of SiMOSFET chip
80 and an input terminal Pin is formed an input matching circuit by
inductances L1, L2 of wires 85, 84, capacitance C1 of the capacitor chip
81, and input capacitance Ciss of SiMOSFET chip 80.
Further, between a drain electrode 80d of SiMOSFET chip 80 and an output
terminal Pout is formed an output matching circuit by inductances L3, L4
of wires 82, 83, capacitance C2 of the capacitor chip 79, and output
capacitance Coss of SiMOSFET 80. A source electrode 80s for the drain
electrode 80d, as well as one terminals of the capacitors, are connected
to ground (GND).
With the input matching circuit, an impedance of several ten ohms is
converted to a low impedance of 1 ohm or less, while with the output
matching circuit, an impedance of 1 ohm or less is converted to an
impedance of several ten ohms, thus permitting an efficient power
amplification.
The wires 82 to 85 serve as appropriate inductances for a desired frequency
characteristic and the wire length (wire loop shape) is designed so as to
form an internal matching circuit.
However, for forming the internal matching circuit it becomes necessary to
ensure an additional space for the capacitor chips 79 and 81, which is
disadvantageous to the needs for the reduction of size, and it is also
necessary to perform a wire bonding work many times in a uniform loop
shape, which causes a deteriorated yield in assembly.
Now, with reference to FIG. 33, a description will be given about a
sectional structure of SiMOSFET 80 and a current path thereof. FIG. 33
illustrates a section and current path of a horizontal type SiMOSFET chip
used for high frequency power amplification.
The horizontal SiMOSFET has a p.sup.+ silicon substrate 90 of a high
concentration and a p.sup.- epitaxial layer 91 of a low concentration
which is formed on the p.sup.+ silicon substrate 90 for obtaining a
required voltage proof. In a surface portion of the p.sup.- epitaxial
layer 91 are formed a channel-forming p layer 92 and a drain n.sup.+ layer
93 of a high concentration which is located at a position spaced a
predetermined distance from the channel-forming p layer 92. Further, an
n.sup.- drain offset layer 94 of a low concentration is formed in the
surface layer portion of the p.sup.- epitaxial layer 91 from the drain
n.sup.+ layer 93 up to the channel forming p layer 92.
The channel-forming p layer 92 is formed relatively deep and a
source-forming n.sup.+ layer 95 of a high concentration is formed on the
left-hand side of a surface portion of the channel-forming p layer 92. The
region from the left end of the source-forming high concentration n.sup.+
layer 95 up to the pn junction formed of both channel-forming p layer 92
and n.sup.- drain offset layer 94 serves as a channel-forming region.
A p.sup.+ through diffusion layer 96 of a high concentration is formed
throughout a depth extending from the left end of the source-forming high
concentration n.sup.+ layer 95, past the p.sup.- epitaxial layer 91, up to
a surface portion of the p.sup.+ silicon substrate 90. An insulating film
(oxide film 97 is formed selectively on the surface of the p.sup.-
epitaxial layer 91. The insulating film 97 extends from an intermediate
position of the source-forming high concentration n.sup.+ layer 95 up to
an intermediate position of the drain n.sup.+ layer 93. At the right end
of the insulating film 97 a drain electrode 80d is formed on the drain
n.sup.+ layer 93, and at the left end of the insulating film 97 a source
wiring line 80sa is formed from the source-forming high concentration
n.sup.+ layer 95 onto the p.sup.+ through diffusion layer 96.
At a position deviated from the channel forming region, a source field
plate 98 is provided on the insulating film 97 which overlies the n.sup.-
drain offset layer 94. The source field plate 98 is fixed at a source
potential and is improved in drain voltage proof by relaxing an electric
field.
The insulating film 97 is thinned at its portion opposed to the
channel-forming region, which thinned portion serves as a gate insulating
film (oxide film) 97a. A gate electrode 80g is formed on the gate
insulating film 97a and is electrically connected to a gate wiring line
80ga which extends onto the insulating film 97.
By a high accuracy by both ion implantation technique and diffuison
technique, p- and n-type diffusion layers (regions) are formed, whereby an
n-channel enhancement type MOSFET is formed.
In such a device structure, a thick-line arrow shown in FIG. 33 represents
a current path, along which an electrode current 99 flows through the
drain electrode 80d, drain n.sup.+ layer 93, n.sup.- drain offset layer
94, channel-forming p layer 92, source-forming high concentration n.sup.+
layer 95, source wiring line 80sa, p.sup.+ through diffusion layer 96, and
p.sup.+ silicon substrate 90, and reaches the source electrode 80s.
Current control is made by increasing or decreasing the gate potential, but
since the horizontal FET is an enhancement type, it has a structure such
that the drain current increases with an increase in gate potential and is
cut off as the gate potential approaches 0V. Thus, there accrues an
advantage that a minus power supply for gate bias which is necessary for a
depletion type GaAsFET can be omitted and that therefore it is easy to
implement a set circuit configuration.
The conventional high frequency power amplification using the horizontal
FET is approximately class B amplification, in which a power component
based on ON/OFF switching operation of a specified frequency is
accumulated in a tank circuit constituted by both inductor and capacitor
and a high frequency power is taken out by a matching circuit. Therefore,
the higher the drain voltage and the larger the drain current capable of
being flowed, the higher the output obtained in FET concerned, but for
following up a high frequency operation it is necessary that the
capacitance be small and mutual inductance (Gm) be large, so there is made
such a chip design as affords high voltage proof, low capacitance, and
high Gm. For attaining low capacitance and high Gm of FET chip,
microminiaturization of gate length is necessary and is now a trend in
FETs for high frequency amplification.
As a great factor of obstructing the attainment of high Gm there is
mentioned source resistance. If an apparent Gm observed in an actual FET
is assumed to be Gm' (exteriorly measurable Gm), Gm' can be represented by
the following relationship between true Gm (=Gmint) and source resistance
(=Rs):
Gm'=(Gmint)/(1+Rs.times.Gmint) (1)
Thus, for improving the performance of FET, the resistance diminishing
processings subsequent to the formation of source n layer (source-forming
high concentration n.sup.+ layer 95) shown in terms of the foregoing
current path are important, and the decrease of contact resistance between
the source electrode (=Si substrate) and the heat sink is an important
subject in the assembling process. More particularly, the AuSi eutectic
chip bonding method is suitable, including the point of high heat
radiating performance, and is applied while imposing such a condition as
does not develop voids in AuSi eutectic.
Now, with reference to FIGS. 34 and 35, a description will be given below
about problems involved in space margin which are an obstructing factor
against the reduction in size of a heat sink as an expensive component.
FIG. 34 is a side view as seen from a side face of the package for
explaining a space margin which is necessary for chip bonding of the
SiMOSFET 80. For chip bonding, the SiMOSFET chip 80 is chucked and
conveyed by a chip bonding collet 100 and is pushed and scrubbed against a
predetermined portion of the heat sink 71 heated to about 430.degree. C.
(Au foil now shown is affixed beforehand to the chip bonding portion of
the heat sink to facilitate the formation of AuSi eutectic), allowing AuSi
eutectic 111 to be developed for fusion-bonding.
In this case, scrubbing is necessary for preventing the generation of voids
in AuSi, and the larger the size of chip, the greater the degree of
scrubbing is needed. Since it is necessary for the collet 100 to embrace
the FET chip, the size of the collet is larger than that of the FET chip
80.
It is necessary that a space margin be ensured an amount sufficient to
prevent abutment of a collet end against the ceramic base 74 when
scrubbing width is added to the collet size. Further, it is necessary that
a positional variation margin of the frame 72, a ceramic size variation
margin, and a collet position accuracy margin be added thereto. The total
is about 1 mm.
FIG. 35 is a sectional view as seen from a package side face for explaining
the space margin of a bonding posts 76a necessary for wire bonding. In
wire bonding, with use of a wire bonding tool 113, wire 112 is
first-bonded (1st bonding) to an Al electrode (not shown) of the FET chip
80, then is second-bonded (2nd bonding) to an Al electrode (not shown) of
the capacitor chip 81 on the drain lead 77 side in the illustrated
example. Next, with an electrode (not shown) of the capacitor chip 81 as
the 1st bonding side, the wire is moved onto the bonding post 76a of the
ceramic base 74 to which the drain lead 77 is fixed, and the wire 112
formed of Al is pushed against the bonding post 76a with the bonding tool
113 and is subjected to ultrasonic compression bonding to effect 2nd
bonding. Thereafter, the bonding tool 113 is raised while allowing the
wire 112 to be clamped by the bonding tool to tear off the wire from the
2nd-bonded portion.
In this case, as shown in FIG. 35, it is necessary to ensure such a margin
as prevents abutment of an end portion of the bonding tool 113 and the
wire 112 against a ceramic sleeve 75. The larger the height of the ceramic
sleeve 75, or the obtuser the feed angle of the wire 112, the larger is
required the length of the bonding post 76a, thus obstructing the
reduction of size.
In a conventional ultrasonic Al wire bonding, the lower the Al wire feed
angle, the smaller the variations in compression-bonded shape of Al and
the higher the yield in assembly. For this reason, the lower the Al wire
feed angle, the more desirable. On the other hand, however, it is
necessary that the size of the bonding post 76a be made large. As a
result, there may occur an increase of cost due to an increase in package
size, or an increase of electrode capacitance may exert an influence on
characteristics.
Next, with reference to FIGS. 36 to 39, the following description will be
provided about the case where the semiconductor device 70 is attached to a
set radiation plate and also about problems involved therein. FIG. 36 is a
plan view of the semiconductor device 70 as screwed to a set radiation
plate and FIG. 37 is a schematic sectional view thereof.
The semiconductor device 70 is mounted in the following manner. Screws 115
are inserted into screwing grooves 73 formed in both ends of the heat sink
71 and the substrate 71 is fixed to a mounting substrate 116 with the
screws 115. The drain lead 77 and the gate lead 78 are connected to
predetermined wiring portions of the mounting substrate 116 through a
bonding material (e.g., PbSn solder). In connection with fixing the heat
sink 71 as a radiation board to the mounting substrate 116, a tightening
torque in the fixing work is prescribed for suppressing an increase in
both thermal and electrical resistances.
In actual mounting, for preventing contact imperfection caused by the
generation of an intermetallic compound between Au plating on the surfaces
of drain and gate leads 77, 78 and PbSn solder, it is necessary to perform
a work for removing Au plating from the leads before the mounting.
Generally, it is necessary to conduct a preliminary soldering work of
dipping the leads into a solder dipping vessel, allowing the Au plating to
be diffused into the solder vessel. Such wasteful labor and time are
required.
As a countermeasure the application of a selective Au plating method is
considered so as not to plate the lead portions with Au. However, unlike
the selective Au plating for such a material as a lead frame material
capable of being conveyed continuously, close to a two-dimensional
structure, masking is difficult for a ceramic package which is of a
three-dimensional structure and which is basically conveyed one by one.
Thus, the productivity of selective Au plating is low and whole-surface Au
plating costs lower than selective Au plating. Even if Au plating is
thinned for only the leads, there arises the problem of discoloration on
heating in chip bonding, so Au plating is applied thick throughout the
whole surface.
Next, problems involved in such screw mounting of the semiconductor device
will be described with reference to FIGS. 37 to 39. FIG. 37 is a schematic
sectional view of the studied semiconductor device as screwed to a
mounting substrate, FIGS. 38(a) and 38(b) are schematic diagrams showing
the semiconductor device wherein a substrate is warped in a centrally
depressed state, as well as a mounted state thereof, and FIGS. 39(a) to
39(c) are schematic diagrams showing the semiconductor device wherein a
substrate is warped in a centrally raised state, as well as a mounted
state thereof.
From the standpoint of heat radiating performance it is preferable that the
substrate (heat sink) 71 be in such a flat state as shown in FIG. 37.
However, due to a bimetal effect inducted by thermal stresses among the
metallic heat sink 71, the ceramic frame 72 fixed to the heat sink 71, and
the metallic cap 87, there actually occurs a concave warp wherein the
substrate center is recessed as in FIGS. 38(a) and 38(b) or a convex warp
wherein the substrate center is raised as in FIGS. 39(a) to 39(c). The
heat sink 71 and the frame 72 are bonded together by silver solder 117. In
these figures the ceramic portion is not bent, but actually there also is
a case where the ceramic portion is bent.
In the case where the heat sink 71 is concavely warped as in FIG. 38(a), if
the heat sink is screwed to the mounting substrate 116, as in FIG. 38(b),
the heat sink which is in a concavely warped state is corrected to the
flat side, so that a tensile stress is imposed on the frame 72 formed of a
ceramic laminate and there easily occurs a crack C.
On the other hand, in the case of such a convex warp as shown in FIG.
39(a), a compressive stress is imposed on the frame 72 formed of a ceramic
laminate due to a screwing stress as in FIG. 39(b), so the breakage of
ceramic is difficult to occur. However, as shown in FIG. 39(c), since a
gap G is formed in the heat radiation path to the mounting substrate 116,
a thermal resistance Rth increases and there arises the problem that both
reliability and heat radiating performance are deteriorated.
As a measure against such warps it is considered to use a sufficiently
thick heat sink material so as to make the heat sink difficult to warp,
and conduct the selection of a heat sink warp. In this case, however, the
material cost increases, with consequent increase in the cost of the
semiconductor device.
It is an object of the present invention to reduce the material cost,
reduce the cost of an assembling work including a sealing work, reduce the
inspection cost, and thereby reduce the semiconductor device manufacturing
cost.
It is another object of the present invention to provide a semiconductor
device in which a heat sink is difficult to warp.
The above and other objects and novel features of the present invention
will become apparent from the following description and the accompanying
drawings.
Typical inventions disclosed herein will be outlined below.
(1) A semiconductor device comprising:
a heat sink formed of a flat metallic plate having a high thermal
conductivity;
a pair of screwing pieces having respective inner end portions connected
with screws respectively to right and left ends of the heat sink on a main
surface side of the heat sink, the screwing pieces further having outer
end portions formed with through spaces for screwing;
one or plural semiconductor chips fixed to the main surface of the heat
sink;
a seal member formed of an insulating resin, the seal member covering a
back side opposite to the main surface of the heat sink and also covering
the other portions of the two screwing pieces than the outer end portions;
a first lead having an outer end portion projecting from the seal member
and further having an inner end portion which is positioned within the
seal member and whose inner end is arranged near one side face of the heat
sink;
a second lead having an outer end portion projecting from the seal member
and further having an inner end portion positioned within the seal member
and near another side face of the heat sink; and
a plurality of conductive wires for electrically connecting between the
leads and predetermined electrodes of the predetermined semiconductor
chip, or between the leads and predetermined electrodes of the
predetermined semiconductor chip and also between predetermined electrodes
of the predetermined semiconductor chip and predetermined electrodes of
the predetermined semiconductor chip.
The heat sink is formed using a thick material difficult to deform, while
the screwing pieces are formed using a flexible material easy to deform.
Each of the screwing pieces is bent in one step at an intermediate portion
thereof projecting from the seal member, then extends so that a back side
thereof is positioned on a plane on which the back side of the heat sink
is positioned, or on a plane close to the plane, the bent portion serving
as a buffer portion adapted to deform under a stress. The inner end
portions of the first and second leads are formed with engaging portions
for engagement with the resin which constitutes the seal member. The first
or the second lead is partially provided with a polarity identifying
portion. The inner ends of the first and second leads are positioned in
regions diverted from the heat sink.
A semiconductor chip with a field effect transistor formed thereon and
semiconductor chips with capacitors formed thereon are fixed to the main
surface of the heat sink in such a manner that the capacitor-formed
semiconductor chips are positioned on both sides in the gate-drain
direction of the FET-formed semiconductor chip. A drain electrode formed
on an upper surface of the field effect transistor and an upper electrode
of one of the semiconductor chips with capacitors formed thereon are
connected with each other through the plural wires, and the upper
electrode and the first lead are connected with each other through the
plural wires. Further, a gate electrode formed on the upper surface of the
field effect transistor and an upper electrode of the other capacitor
semiconductor chip are connected with each other through the plural wires,
and the upper electrode and the second lead are connected with each other
through the plural wires. In this way there is constituted a high
frequency power amplifier for a base station.
Such a semiconductor device is manufactured through the steps of:
providing a lead frame and a heat sink, the lead frame being constituted by
a metallic plate having one or more product forming portions of a
predetermined pattern, the heat sink being constituted by a flat metallic
plate of a high thermal conductivity which is fixed to the product forming
portions with screws;
fixing one or plural semiconductor chips to a main surface of the heat
sink;
superimposing the heat sink on back sides of the product forming portions
of the lead frame and fixing the heat sink to the lead frame with screws
from a main surface side of the lead frame;
connecting between electrodes of the semiconductor chips and inner end
portions of corresponding leads and also between predetermined electrodes
of predetermined semiconductor chips, using conductive wires;
covering the main surface side of the heat sink and a predetermined portion
of the lead frame with an insulating resin by one-side transfer molding to
form an insulating seal member; and
cutting off an unnecessary portion of the lead frame, allowing a back side
of the heat sink which is insulative to be exposed to a back side of the
seal member and allowing the leads to be projected from side faces of the
seal member,
the product forming portion each comprising:
a pair of screwing pieces having respective inner end portions connected
with screws respectively to right and left ends of the heat sink on the
main surface side of the heat sink, the screwing pieces further having
respective outer end portions projecting to the exterior of the seal
member, the outer end portions having respective through spaces for
screwing which are used at the time of mounting the semiconductor device;
a first lead having an inner end portion which is positioned within the
seal member and whose inner end is arranged near one side face of the heat
sink and further having an outer end portion projecting from the seal
member; and
a second lead having an inner end portion positioned within the seal member
and near another side face of the heat sink and further having an outer
end portion projecting from the seal member,
wherein in the step of cutting off the unnecessary portion of the lead
frame, or thereafter, the leads projecting from the side faces of the seal
member are bent in one step to form surface-mounted type leads.
In the above semiconductor device manufacturing method, the screwing pieces
are cut so that there remain the through spaces for screwing, and the
screwing pieces are bent in one step at intermediate portions thereof
projecting from the seal member, then extend so that back sides thereof
are each positioned on a plane on which the back side of the heat sink is
positioned or on a plane close to the plane.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective plan view showing the structure of a semiconductor
device according to an embodiment (first embodiment) of the present
invention;
FIG. 2 is a plan view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a side view thereof;
FIG. 5 is a schematic sectional view taken along line A--A in FIG. 2;
FIG. 6 is a schematic sectional view taken along line B--B in FIG. 2;
FIG. 7 is an enlarged sectional view showing a part of the semiconductor
device of the first embodiment;
FIG. 8 is a plan view of a lead frame used in manufacturing the
semiconductor device of the first embodiment;
FIG. 9 is a plan view of a substrate used in manufacturing the
semiconductor device of the first embodiment;
FIG. 10 is a side view thereof;
FIGS. 11(a) and 11(b) illustrate the substrate with semiconductor chips
fixed thereto in the manufacture of the semiconductor device of the first
embodiment;
FIG. 12 is a plan view of the lead frame with the substrate attached
thereto;
FIG. 13 is a plan view of the lead frame after the end of wire bonding in
the manufacture of the semiconductor device of the first embodiment;
FIG. 14 is a schematic diagram showing how to perform the wire bonding;
FIG. 15 is a plan view of the lead frame after the end of sealing with
resin in the manufacture of the semiconductor device of the first
embodiment;
FIG. 16 is a schematic diagram showing in what state the semiconductor
device of the first embodiment is manufactured as a device equipped with
suspension leads by cutting the lead frame selectively;
FIG. 17 is a schematic diagram showing in what state the semiconductor
device of the first embodiment is manufactured as a device not equipped
with suspension leads by cutting the lead frame selectively;
FIGS. 18(a) and 18(b) are a diagram and a graph, respectively, showing how
a gap formed between a package bottom of the semiconductor device and a
lower surface of each suspension lead, as well as thermal resistance and
package breakdown occurrence rate, are correlated with each other;
FIG. 19 is a perspective plan view showing the structure of a semiconductor
device according to another embodiment (second embodiment) of the present
invention;
FIG. 20 is a schematic sectional view thereof;
FIG. 21 is a schematic sectional view in another section of the
semiconductor device of the second embodiment;
FIG. 22 is a plan view of a spacer used in a semiconductor device according
to a modification of the second embodiment;
FIG. 23 is a schematic sectional view showing the structure of a
semiconductor device according to another modification of the second
embodiment;
FIG. 24 is a plan view of a semiconductor device according to a further
embodiment (third embodiment) of the present invention;
FIG. 25 is a front view of thereof;
FIG. 26 is a plan view of a semiconductor device according to a still
further embodiment (fourth embodiment) of the present invention;
FIG. 27 is a side view thereof;
FIG. 28 is a plan view of the studied semiconductor device which the
present inventor had studied prior to the present invention;
FIG. 29 is a side view thereof;
FIG. 30 is a plan view thereof with a cap removed;
FIG. 31 is a schematic sectional view thereof;
FIG. 32 is an equivalent circuit diagram thereof;
FIG. 33 is a schematic sectional view of an FET chip used in the studied
semiconductor device;
FIG. 34 is a schematic diagram showing a state of chip bonding in the
manufacture of the studied semiconductor device;
FIG. 35 is a schematic diagram showing a state of wire bonding in the
manufacture of the studied semiconductor device;
FIG. 36 is a plan view of the studied semiconductor device as screwed to a
set radiation board;
FIG. 37 is a schematic sectional view thereof;
FIGS. 38(a) and 38(b) are schematic diagrams showing a mounted state of the
studied semiconductor device in which a substrate is warped in a centrally
depressed state; and
FIGS. 39(a) to 39(c) are schematic diagrams showing a mounted state of the
studied semiconductor device in which a substrate is warped in a centrally
raised state.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the present invention will be described in detail
hereinunder with reference to the accompanying drawings. In all of the
drawings for illustrating the embodiments, portions having the same
functions are identified by like reference numerals, and repeated
explanations thereof will be omitted.
(First Embodiment)
FIGS. 1 to 18 are concerned with a semiconductor device according to an
embodiment (first embodiment) of the present invention, of which FIGS. 1
to 7 are concerned with the structure of the semiconductor device and
FIGS. 8 to 17 are concerned with the manufacture of the semiconductor
device. In this first embodiment, a description will be given below about
an example in which the present invention is applied to a high frequency
power amplifier (a high frequency power amplifier module) for a base
station, as a semiconductor device.
The semiconductor device of this first embodiment, i.e., a high frequency
power amplifier module for a base station, indicated at 1, has such a
structure as shown in FIGS. 1 to 7, of which FIG. 1 is a perspective plan
view, FIG. 2 is a plan view, FIG. 3 is a front view, FIG. 4 is a side
view, FIGS. 5 and 6 are schematic sectional views taken along lines A--A
and B--B in FIG. 2, and FIG. 7 is a partially enlarged sectional view.
In appearance, as shown in FIGS. 2 to 4, the semiconductor device 1 of this
embodiment comprises a flat, rectangular, seal member (package) 2 formed
of an insulating resin, a heat sink (substrate) 3 whose lower surface is
exposed to a bottom of the seal member 2, a pair of screwing pieces
(suspension leads) 4 projecting respectively from both ends (short sides)
in the longitudinal direction of the seal member 2, a first broad lead 5
and a second broad lead 6 projecting respectively from long sides of the
seal member 2. The second lead 6 serves as a gate (G) lead. The lower
surface of the heat sink 3 exposed to the bottom of the seal member 2
serves as both a heat radiating surface and a source electrode.
The seal member 2 is formed, for example, using an insulating epoxy resin
by transfer molding. The seal member 2 has a structure which covers the
four side faces of the heat sink 3 and in which a water admission path
passing the interface between the heat sink 3 and the resin is made long
to ensure a high reliability. Recesses 8 are formed centrally of short
sides of the seal member 2 and toward the center of the seal member. The
recesses 8 are draw-out traces of an upper mold for clamping the heat sink
3 and the screwing pieces 4 with upper and lower molds of a molding die
and causing the heat sink 3 to come into close contact with the lower mold
positively in transfer molding to prevent the occurrence of burrs caused
by flowing-out of resin.
The heat sink 3 and the screwing pieces 4 are formed of metal, and within
the seal member 2, an inner end portion of each screwing piece 4 is
superimposed on an upper surface of the heat sink 3 and is connected
thereto with two screws 7 (see FIG. 1), so that the heat sink 3 and the
screwing pieces 4 become equal in potential and can be used as source (S)
terminals. Semiconductor chips are fixed to the heat sink 3 and the heat
sink plays the role of dissipating the heat generated in the semiconductor
chips, therefore, the heat sink 3 is formed of a flat metallic plate
(e.g., CuMo plate) superior in thermal conductivity. Besides, the heat
sink 3 is as thick as 2 mm for example to make its deformation difficult.
On the other hand, the screwing pieces 4 are as thin as 0.15 mm for
example and are flexible so as to serve as suspension leads.
Both screwing pieces 4 have screwing grooves 9 formed in respective outer
end portions. With use of the paired screwing grooves 9 the semiconductor
device 1 is fixed with screws to a mounting substrate such as a mother
board. The inner end portions of the screwing pieces 4 are superimposed
and fixed onto the main surface (upper surface) of the heat sink 3, and
the outer end portions of the screwing pieces 4 are mounted in contact
with the mounting substrate. Therefore, as shown in FIG. 5, the screwing
pieces 4 are bent in one step at their portions projecting from the seal
member 2. The bent portions, indicated at 10, are easily deformable
portions against a stress, i.e., suspension portions.
As shown in FIG. 7, a plating film 11 is formed on the whole surface of the
heat sink 3. The plating film 11 comprises Ni plating film as undercoat
and Au plating film formed on the Ni plating film. The Ni plating film is
superior in its adhesion to CuMo which constitutes the heat sink 3. The Au
plating film is formed as th
