Title: Semiconductor device
Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n- region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n- region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
Patent Number: 6,897,493 Issued on 05/24/2005 to Takahashi, et al.
| Inventors:
|
Takahashi; Tetsuo (Hyogo, JP);
Nakamura; Katsumi (Hyogo, JP);
Minato; Tadaharu (Hyogo, JP);
Harada; Masana (Hyogo, JP)
|
| Assignee:
|
Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
|
| Appl. No.:
|
457658 |
| Filed:
|
June 10, 2003 |
Foreign Application Priority Data
| Jul 19, 1995[JP] | 7-183102 |
| Sep 14, 1995[JP] | 7-237002 |
| Oct 27, 1995[JP] | 7-280961 |
| Current U.S. Class: |
257/136; 257/135 |
| Intern'l Class: |
H01L 029/42.3 |
| Field of Search: |
257/136,135
|
References Cited [Referenced By]
U.S. Patent Documents
| 4994883 | Feb., 1991 | Chang et al.
| |
| 5360746 | Nov., 1994 | Terashima.
| |
| 5689121 | Nov., 1997 | Kitagawa et al.
| |
| 5747856 | May., 1998 | Chen et al.
| |
| 5866931 | Feb., 1999 | Buluccea et al.
| |
| Foreign Patent Documents |
| 41 30889 | Sep., 1991 | DE.
| |
| 0 050 988 | Oct., 1981 | EP.
| |
| 0 527 600 | Feb., 1993 | EP.
| |
| 0 565 349 | Apr., 1993 | EP.
| |
| 0565349 | Oct., 1993 | EP.
| |
| 3-196570 | Aug., 1991 | JP.
| |
| 5-13769 | Jan., 1993 | JP.
| |
| 05013769 | Jan., 1993 | JP.
| |
| 5-243561 | Sep., 1993 | JP.
| |
| 6-12559 | Jan., 1994 | JP.
| |
| 6-13621 | Jan., 1994 | JP.
| |
| 7-1347 | Jan., 1995 | JP.
| |
Other References
"4500 V IEGTs Having Switching Characteristics Superior to GTO", by Kitagawa,
et al., Proceedings of 1995 International Symposium of Power Devices & ICs, May
23-25, 1995, pp. 486-491.
Jun-ichi Nishizawa et al. "The MOS SIT and its Integration", Denshi Tokyo No.
27 (1988), pp 83-87.
Patent Abstracts of Japan, vol. 17, No. 276 (E-1372), May 27, 1993.
Mitsuhiko Kitagawa et al. A 4500 V Injection Enhanced Insulated Gate Bipolar
Transistor (IEGT) Operating in a Mode Similar to a Thyristor, IEDM 93, pp. 679-682.
M. Harada et al. "600 V Trench IGBT in Comparison with Planar IGBT", Proc. of
the 6th International Symposium on Power Semiconductor Devices & IC's Davos. Switzerland,
May 31-Jun. 2, 1994, pp. 411-416.
"MOS Controlled Diodes—A New Power Diode", Huang et al., Solid State Electronics,
Elsevier Science Publishers, Barking, GB, vol. 38, No. 5, May 1, 1995, pp. 977-980, XP000500477.
|
Primary Examiner: Zarabian; Amir
Assistant Examiner: Rose; Kiesha L.
Attorney, Agent or Firm: McDermott Will & Emery LLP
Parent Case Text
This applicalion is a divisional of application Ser. No. 09/862,520, filed May
23, 2001 now U.S. Pat. No. 6,693,310, which is a divisional of Ser. No. 09/222,795,
filed Dec. 30, 1998, now U.S. Pat. No. 6,265,735 which is a divisional of application
of Ser. No. 08/683,279, filed Jul. 18, 1996, now U.S. Pat. No. 5,977,570.
Claims
1. A semiconductor device in which current flows between first and second main
surfaces of an intrinsic or a first conductivity type semiconductor substrate, comprising:
a first impurity region of a second conductivity type formed on said first main
surface side of said semiconductor substrate; and
a second impurity region of the second conductivity type formed on said second
main surface of said semiconductor substrate, sandwiching, with said first impurity
region, a low concentration region of said semiconductor substrate; wherein
said semiconductor substrate includes a trench reaching said low concentration
region of said semiconductor substrate from said first main surface through said
first impurity region;
said device further comprising:
a third impurity region of the first conductivity type on said first impurity
region to be in contact with a sidewall of said trench at said first main surface
of said semiconductor substrate;
a fourth impurity region of the second conductivity type having a higher concentration
than said first impurity region, formed on said first impurity region and adjacent
to said third impurity region at said first main surface of said semiconductor
substrate;
a control electrode layer formed in said trench to oppose to said first and third
impurity regions and said low concentration region of said semiconductor substrate
with an insulating film interposed, for controlling current flowing between said
first and second main surfaces by an applied control voltage;
a first electrode layer formed on said first main surface of said semiconductor
substrate and electrically connected to said third and fourth impurity regions;
and
a second electrode layer formed on said second main surface of said semiconductor
substrate and electrically connected to said second impurity region; wherein
the following expression is satisfied where Dt represents depth of said trench
from said first main surface, Wt represents width of said trench, De represents
depth of said third impurity region from said first main surface, We represents
width of said third impurity region from one of said trenches to another of said
trenches, and Pt represents pitch of adjacent said trenches:
##EQU6##
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical power semiconductor device having
self turn-off function and to a manufacturing method thereof.
2. Description of the Background Art
First, a conventional semiconductor device will be described.
FIG. 96 is a cross sectional view schematically showing a structure of a semiconductor
device in accordance with a first prior art example. Referring to FIG. 96, the
first prior art example has an SITh (Static Induction Thyristor). The SITh includes
a pin diode porion, a p type gate region
307, a gate electrode layer
309,
a cathode electrode
311 and an anode electrode
313.
A pin diode portion has a stacked structure including a p
+, anode
region
301, an n
- region
303 and a cathode region (n
+
emitter region)
305. The p type gate region
307 is formed in n
-
region
303. Gate electrode
309 is electrically connected to p type
gate region
307. Cathode electrode
311 is electrically connected
to cathode region
305, and anode electrode
313 is electrically connected
to p
+ anode region
301, respectively.
The SITh can realize on-state by setting gate voltage applied to gate electrode
309 positive. At this time, current flows through pin diode from p
+
anode region
301 to the side of cathode region
305.
FIG. 97 is a cross sectional view schematically showing a structure of a semiconductor
device in accordance with a second prior art example. Referring to FIG. 97, the
second prior art example shows a GTO (Gate Turn-Off) thyristor. The GTO thyristor
has a p
+ anode region
351, an n
- region
353,
a p base region
355, a cathode region
357, a gate electrode
359,
a cathode electrode
361 and an anode electrode
363.
The p
+ anode region
351, n
- region
353, p
base region
355 and cathode region
357 are stacked successively.
The p type base region
355 is electrically connected to gate electrode
359.
Cathode electrode
361 is electrically connected to cathode region
357,
and anode electrode
363 is electrically connected to p
+ anode
region
351, respectively.
In this GTO thyristor also, on-state can be realized by setting the gate voltage
positive. By setting gate voltage positive, current flows through a pnpn diode
from p
+ corrector region
351 to the side of cathode region
357.
Both in the first and second prior art examples, off-state can be realized by
applying a negative voltage to the gate electrode. When a negative voltage is applied
to gate electrode
309 or
359, minority carriers (holes) remaining
in the device are extracted from gate electrode
309 or
359. Thus,
the main current is cut off.
FIG. 98 is a cross sectional view schematically showing a structure of a semiconductor
device in accordance with a third prior art example. Referring to FIG. 98, the
third prior art example shows an example of a trench IGBT (Insulated Gate Bipolar
Transistor). The trench IGBT includes a p
+ collector region
101,
n
+ buffer region
103, n
- region
105, p type
base region
107, n
+ emitter region
109, a p
+
contact region
111, a gate oxide film
115, a gate electrode layer
117, a cathode electrode (emitter)
121 and an anode electrode (collector)
123. On p
+ collector region
101, n
- region
105 is formed with n
+ buffer region
103 interposed. On
n
- region
105, n
+ emitter region
109 and p
+
contact region
111 are formed adjacent to each other with p type base region
107 interposed. On the surface where n
+ emitter region
109
is formed, there is provided a trench
413.
Trench
413 passes through n
+ emitter region
109 and
p type base region
107 and reaches n
- region
105. The
depth T
p of trench
413 from the surface is 3 to 5 μm.
Along inner wall surface of trench
413, gate oxide film
115 is
formed. Gate electrode layer
117 is formed to fill the trench
413
and with its upper end projecting from trench
413. Gate electrode layer
117 opposes to n
+ emitter region
109, p type base region
107 and n
- region
105 with gate oxide film
115 interposed.
Interlayer insulating layer
119 is formed to cover an upper end
of gate electrode layer
117. In interlayer insulating layer, there is provided
an opening which disposes the surfaces of n
+ emitter region
109
and p
+ contact region
111. Cathode electrode (emitter)
121
is formed so as to electrically connect n
+ emitter region
109
and p
+ contact region
111 through the opening. Anode electrode
(collector)
123 is formed to be electrically connected to p
+
collector region
101.
Hereinafter, the surface of the semiconductor substrate on which cathode
electrode
121 is formed will be referred to as a cathode surface or a first
main surface, and the surface where anode electrode
123 is formed will be
referred to as an anode surface or the second main surface.
A trench MOS gate structure in which gate electrode layer
117 is formed
in trench
413 with gate oxide film
115 interposed is manufactured
through the following steps.
First, in a semiconductor substrate, a relatively deep trench
413 of
about 3 to about 5 μm is formed by common anisotropic dry etching. Sacrificial
oxidation or cleaning is performed on the inner wall of trench
413. Thereafter,
a silicon thermal oxide film (hereinafter referred to as a gate oxide film)
115
is formed at a temperature from 900° C. to 1000° C. in, for example,
vapor ambient (H
2O). A polysilicon film doped with an n type impurity
such as phosphorous or a polycrystalline silicon film doped with a p type impurity
such as boron fills the trench
413. The doped polysilicon film is patterned
so that trench
413 is filled and doped polysilicon film is drawn out at
least from a porion of trench
413 to the surface of the cathode side. The
patterned doped polysilicon film is electrically connected to a gate surface interconnection
formed of a metal such as aluminum, provided entirely over the semiconductor device,
while insulated from cathode electrode
121.
The method of controlling on-state and off-state in the third prior art example
will be described.
On-state is realized by applying a positive (+) voltage to gate electrode
117 while a forward bias is applied between cathode electrode
121-anode
electrode
123, that is, while a positive (+) voltage is applied to anode
electrode
123 and a negative (-) voltage is applied to cathode electrode
121.
A turn-on process in which the device transits from off-state to the on-state
will
be described in the following.
When a positive (+) voltage is applied to gate electrode layer
117, an
n channel (inverted n region) which is inverted to n type and having very high
electron density is generated at p base region
107 near gate oxide film
115. Electrons, which are one of the current carriers (hereinafter referred
to as carriers) are injected from n
+ emitter region
109 through
the n channel to n
- region
105, and flow to p
+ collector
region
101 to which the positive (+) voltage is applied. When the electrons
reach p
+ collector region
101, holes, which are other current
carrier are injected from p
+ collector region
101 to n
-
region
105 and flow to n
+ emitter region
109 to which
the negative (-) voltage is applied. Thus, the flow reaches the position where
the aforementioned n channel is in contact with n
- region
105.
This process is referred to as storage process, and the time necessary for this
process is referred to as storage time (t
storage) or turn-off delay
time (td(
off)). Power loss during the storage time is so small that
it can be neglected, as compared with steady loss, which will be described layer.
Thereafter, from anode electrode
123 and cathode electrode
121,
sufficient current carriers are stored in n
- region
105 to such
an amount that is larger by two or three orders of magnitude than the concentration
of semiconductor substrate (1×10
12 to 1×10
15 cm
-3),
in accordance with the difference between potentials applied to both electrodes.
Accordingly, a low resistance state referred to as conductivity modulation is caused
by the hole-electron pairs, thus turn-on is completed. This process is referred
to as a rise process, and the time necessary for this process is referred to as
rise time (t
rise). Power loss during this time is approximately the
same or larger than the steady loss, which will be described layer later, and constitutes
roughly one fourth of the entire loss.
The steady state after the completion of turn-on is referred to as on-state,
and the power loss represented by a product of on-state voltage caused by on resistance
(effectively, potential difference between both electrodes) and the conduction
current is referred to as on-loss or steady loss.
When a positive voltage is applied to gate electrode layer
117, an n
+
accumulation region
425a having high electron density is formed along
the sidewalls of trench
113, as shown in FIG.
99.
Off-state is realized by applying a negative (-) voltage to gate electrode
layer
117, even when forward bias is being applied to anode electrode
123-cathode
electrode
121.
A turn off process in which the device transits from on state to off state will
be described in the following.
When a negative (-) voltage is applied to gate electrode layer
117, n
channel (inverted n region) formed on the side surface of gate electrode layer
117 is eliminated, and supply of electrodes from n
+ emitter region
109 to n
- region
105 is stopped. The process up to here
is referred to as storage process, and the time necessary for this process is referred
to as storage time (ts) or turn off delay time (td(
off)). The power
loss during this time is very small as compared with the turn on loss and the steady
loss, and it can be neglected.
As the electron density reduces, the density of electrons which has been introduced
to n
- region
105 gradually reduces from the vicinity of n
+
emitter region
109. In order to maintain charge neutralize condition, holes
which have been introduced to n
- region
105 also reduce, and
p base region
107 and n
- region
105 are reversely biased.
Consequently, depletion layer begins to extend at the interface between p base
region
107 and n
- region
105, and tends to have a thickness
which corresponds to the applied voltage in the off state between both electrodes.
The process up to here is referred to as a fall process, and the time necessary
for this process is referred to as fall time (tf). The power loss during this time
is approximately the same or larger than the aforementioned turn off loss and steady
loss, and it constitutes roughly one fourth of the entire loss.
Further, holes in an electrically neutral region where both carriers remain
outside the aforementioned depletion region (p
+ collector region
101)
pass through the depletion region and extracted through p
+ contact region
111 to emitter electrode
121, thus carriers are all eliminated and
turn off is completed. This process is referred to tail process, and the time necessary
for this process is referred to as tail time (t
tail). The power loss
during the tail time is referred to as tail loss, which is approximately the same
or larger than the turn on loss, loss during the fall time and steady loss, and
it constitutes roughly one fourth of the entire loss.
The steady state after the completion of turn off is referred to as off state
and power loss caused by the product of leak current in this state and the voltage
between both electrodes is referred to as off loss. However, generally it is smaller
than other power losses and it can be neglected.
The above described first and second prior art examples relate to current control
type devices in which minority carriers are extracted from gate electrodes
309
and
359 to set off-state. Therefore, at the time of turn off, it is necessary
to extract a considerable amount of the main current from the gate electrode. When
a relatively large current is to be extracted, there will be a large surge current
caused by inductance of interconnections or the like, and heat radiation caused
by current must also be taken into consideration. Therefore, it becomes necessary
to provide a protecting circuit against surge voltage and excessive current, in
the circuit for controlling the gate voltage. This makes the gate control circuit
complicated. Further, it is possible that the control circuit is thermally destroyed
or suffers from thermal runaway because of heat, and hence a cooling mechanism
must be provided. This makes the device larger.
A semiconductor device which solves these problems is disclosed in Japanese Patent
Laying-Open No. 5-243561. The semiconductor device disclosed in this application
will be described as a fourth prior art example.
FIG. 100 is a plan view schematically showing the structure of the semiconductor
device in accordance with the fourth prior art example, and FIGS. 101 and 102 are
cross sectional views taken along the lines P-P′ and Q-Q′ of FIG.
100, respectively.
Referring to FIGS. 100 to
102, the fourth prior art example shows
an electrostatic induction thyristor. On one surface of a high resistance n type
base layer
501, a p type emitter layer
503 is formed with an n type
buffer layer
502 interposed. On the other surface of n type base layer
501,
a plurality of trenches
505 are formed spaced by a small distance from each
other. In these trenches
505, gate electrodes
507 are formed embedded,
with gate oxide film
506 interposed. At every other region between the trenches
505, n type turn off channel layer
508 is formed. On the surface
of turn off channel layer
508, a p type drain layer
509 is formed.
At a surface portion sandwiched between p type drain layers
509, an n type
source layer
510 is formed.
A cathode electrode
511 is formed to be electrically connected to p type
drain layer
509 and n type source layer
510. An anode electrode
512
is formed to be electrically connected to p type emitter layer
503.
In the fourth prior art example, when the positive voltage is applied to gate
electrode
507 to raise the potential of n type base layer
501 sandwiched
between the trenches
505, electrons are introduced from n type source layer
510, so that the device turns on. Meanwhile, when a negative voltage is
applied to a gate electrode layer
507, a p type channel is formed on a side
surface of the trench of n type turn off channel layer
508, carriers of
n base layer
501 are discharged through p drain layer
509 to cathode
electrode
511, and therefore the device turns off.
In the fourth prior art example, the gate electrode
507 has an insulated
gate structure. Therefore, in the fourth prior art example, the gate electrode
507b is not of the current control type in which current is directly
drawn out from the substrate, but it is of a voltage controlled type in which control
is realized by the voltage (gate voltage) applied to the gate electrode.
Since the fourth prior art example is of the voltage controlled type, it is
not necessary to extract a large current from gate electrode layer
507 at
the time of turn off. Accordingly, it is not necessary to provide a protecting
circuit or a cooling mechanism in consideration of surge current and heat caused
when large current is extracted. Therefore, the fourth prior art example is advantageous
in that the gate control circuit can be simplified.
However, in the fourth prior art example, at the surface region sandwiched
between trenches
507 extending parallel to each other as shown in FIG. 100,
there are p type drain layer
509 and n type source layer
510 adjacent
to each other. Since p type drain layer
509 has a potential barrier with
respect to the electrons, the electron current entering the cathode electrode
511
flows only through the portion of n type source layer
510. Therefore, there
is inhibiting factor such as partial increase in current density, which results
in degraded on characteristics.
In the third prior art example shown in FIG. 98, it is not possible to improve
on-state voltage Vf, and hence power consumption of the semiconductor device is
considerably large. This will be described in greater detail.
As a method of improving ON voltage (on-state voltage Vf of a diode) which is
a basic characteristic of IGBT, there is a method of improving injection efficiency
of electrons on the side of the cathode. In order to improve injection efficiency
of electrons, it is necessary to increase impurity concentration on the side of
the cathode or to increase the effective cathode area. The effective cathode area
means the area of a portion (denoted by the solid line in the figure) where n
+
region (effective cathode region) including n
+ emitter region
109
and storage region
425a is in contact with p type base region
107
and n
- region
105.
In the third prior art example, the depth of the trench
413 is 3-5 μm,
as already described. Therefore, when a positive voltage is applied to gate electrode
layer, extension of the storage layer generated around the trench
113 is
limited. Accordingly, it is not possible to ensure the large effective cathode
area. This hinders improvement in injection efficiency of electrons on the side
of the cathode, and hence ON voltage of IGBT cannot be reduced.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a power semiconductor device
which allows simplification of gate control circuit, provides good on characteristic
and reduces steady loss.
Another object of the present invention is to provide a power semiconductor
device which allows simplification of gate control circuit, has low on-state voltage
Vf and low steady loss.
The semiconductor device in accordance with an aspect of the present invention
including a diode structure in which main current flows between both main surfaces
sandwiching an intrinsic or a first conductivity type semiconductor substrate includes
a first impurity region of a first conductivity type, a second impurity region
of a second conductivity type, a control electrode layer, a first electrode layer
and a second electrode layer. The first impurity region of the first conductivity
type is formed on a first main surface of the semiconductor substrate and has impurity
concentration higher than that of the semiconductor substrate. The second impurity
region of the second conductivity type is formed on a second main surface of the
semiconductor substrate, and sandwiches with the first impurity region, a low impurity
concentration region of the semiconductor substrate. The semiconductor substrate
has a plurality of trenches extending parallel to each other on the first main
surface, and each trench is formed to reach the low impurity concentration region
of the semiconductor substrate through the first impurity region from the first
surface. The first impurity region is formed entirely at the first main surface
of the semiconductor substrate sandwiched by the trenches extending parallel to
each other. The control electrode layer is formed to oppose to the first impurity
region and the low impurity concentration region of the semiconductor substrate
in the trench with an insulating film interposed. The first electrode layer is
formed on the first main surface of the semiconductor substrate and electrically
connected to the first impurity region. The second electrode layer is formed on
the second main surface of the semiconductor substrate and electrically connected
to the second impurity region.
In the semiconductor device in accordance with one aspect of the present invention,
the control electrode layer opposes to the first impurity region and the low impurity
concentration region of the semiconductor substrate with an insulating film interposed.
In other words, the gate control is of voltage control type. Therefore, it is not
necessary to extract a large current from the control electrode at the time of
turn off. Therefore, it is not necessary to provide a protecting circuit for a
cooling mechanism in the gate control circuit in consideration of surge voltage
and heat caused when a large current flows. Therefore, as compared with the first
and second prior art examples, gate control circuit can be simplified.
Further, the device is a bipolar device. In the bipolar device, the holes
and electrons contribute to the operation. Therefore, even when the substrate thickness
is improved to meet the demand of higher breakdown voltage and current path in
the on state becomes longer, resistance can be maintained low, since there is generated
conductivity modulation by the holes and electrons. Therefore, power loss can be
reduced and amount of heat radiation can be reduced.
Further, the control electrode layer opposes to the first impurity region
and a low impurity concentration region of the semiconductor substrate. Therefore,
by applying a voltage to the control electrode layer, the low impurity concentration
region of the semiconductor substrate near the trench which is filled with the
control electrode layer can be turned to a channel having high electron density
approximately the same as the density of first impurity region. Consequently, the
channel region near the trench can be regarded as a first impurity region, and
hence a state as if the first impurity region is enlarged can be realized. When
the first impurity region is enlarged, the contact area between the low impurity
concentration region of the semiconductor substrate and the enlarged first impurity
region, that is, the effective cathode area is increased. Thus, efficiency in injecting
electrons on the side of the cathode is improved, and on-state voltage Vf of the
diode can be reduced.
Further, only the first impurity region is formed on the first main surface
of the semiconductor substrate sandwiched between the trenches. Therefore, as compared
with an example in which impurity regions of different conductivity types exist
on the first main surface, the electron current entering from the cathode flows
uniformly through the first main surface of the semiconductor substrate between
the trenches. Accordingly, inhibiting factor such as partial increase in current
density can be eliminated, and good on characteristic is obtained.
In the above described aspect, preferably the plurality of trenches include first,
second and third trenches extending parallel to each other. The first impurity
region is formed entirely at the first main surface of the semiconductor substrate
between the first and second trenches. A third impurity region of the second conductivity
type is formed at the first main surface of the semiconductor substrate between
the second and third trenches. Therefore, the third impurity region is formed shallower
than the trench, and is electrically connected to the first electrode layer.
At the first main surface of the semiconductor substrate, the third impurity
region
is provided adjacent to the first impurity region with a trench interposed. The
third impurity region has a conductivity type different from that of the first
impurity region. Therefore, at the time of turn off of the device, holes are extracted
from the third impurity region. Thus, the speed of turn off of the device can be
improved and the turn off loss can be reduced.
The third impurity region is provided adjacent to the first impurity region at
the first main surface of the semiconductor substrate with a trench interposed.
Therefore, by adjusting the ratio of existence of the third and first impurity
regions, desired turn off speed and on-state voltage Vf can be selected.
According to another aspect of the present invention, the semiconductor
device includes a pnpn structure in which main current flows between both main
surfaces with an intrinsic or first conductivity type semiconductor substrate sandwiched
therebetween, which includes a first impurity region of a first conductivity type,
a second impurity region of a second conductivity type, a third impurity region
of the second conductivity type, a control electrode layer, a first electrode layer
and a second electrode layer. The first impurity region of the first conductivity
type is formed at the first main surface of the semiconductor substrate. The second
impurity region of the second conductivity type is formed at the second surface
of the semiconductor substrate. The third impurity region of the second conductivity
type is formed below the first impurity region to sandwich a region of the semiconductor
substrate with itself and the second impurity region. The semiconductor substrate
has a plurality of trenches extending parallel to each other at the first main
surface, and each trench is formed to reach a region of the semiconductor substrate
through first and third impurity regions from the first main surface. The first
impurity region is formed entirely at the first main surface of the semiconductor
substrate sandwiched between the trenches extending parallel to each other. The
control electrode layer is formed to oppose to the first and third impurity regions
and the semiconductor substrate region with an insulating film interposed, in the
trench. The first electrode layer is formed on the first main surface of the semiconductor
substrate and electrically connected to the first impurity region. The second electrode
layer is formed on the second main surface of the semiconductor substrate and electrically
connected to the second impurity region.
In the semiconductor device in accordance with aforementioned another aspect
of
the present invention, the control electrode layer opposes to the first and third
impurity regions and the semiconductor substrate region with an insulating film
interposed. In other words, the gate control is of voltage controlled type. Therefore,
it is not necessary to extract a large current from the control electrode layer
at the time of turn off. Accordingly, it is not necessary to provide a protecting
circuit or a cooling mechanism in the gate control circuit in consideration of
surge voltage or heat generated when a large current flows. Therefore, compared
with the first and second prior art examples, the gate control circuit can be simplified.
Further, the device is a bipolar device. In the bipolar device, both holes
and electrons contribute to the operation. Therefore, even when the substrate thickness
is increased to meet the demand of higher breakdown voltage and the current path
in the on state becomes longer, there will be a conductivity modulation generated
by the holes and electrons. Therefore, the on resistance can be maintained low.
Therefore, increase in steady loss can be suppressed and the amount of heat radiation
can be reduced.
Further, only the first impurity region is formed at the main surface of
the semiconductor substrate between the trenches. Therefore, as compared with the
examples in which impurity regions of different conductivity types exist at the
first main surface, electron current entering from the cathode side flows uniformly
through the first main surface of the semiconductor substrate between the trenches.
Therefore, inhibiting factor such as partial increase in current density can be
eliminated, and good on characteristic is obtained.
In the above described aspect, preferably, the plurality of trenches include
first,
second and third trenches extending parallel to each other. The first impurity
region is formed entirely at the first main surface of the semiconductor substrate
between the first and second trenches. A fourth impurity region of the second conductivity
type is formed at the first main surface of the semiconductor substrate between
the second and third trenches. The fourth impurity region is made shallower than
the trench, and is electrically connected to the first electrode layer.
The fourth impurity region is provided at the first main surface of the semiconductor
substrate to be adjacent to the first impurity region with the trench interposed.
Further, the fourth impurity region has a conductivity type different from that
of the first impurity region. Accordingly, holes are extracted from the fourth
impurity region at the time of turn off of the device. Therefore, turn off speed
of the device can be improved and turn off loss can be reduced.
The fourth impurity region is provided adjacent to the first impurity region
with the trench interposed, at the first main surface of the semiconductor substrate.
Therefore, by adjusting the ratio of existence of the fourth and first impurity
regions, a desired turn off speed and on-state voltage can be selected.
In accordance with still further aspect of the present invention, the semiconductor
device includes a diode structure in which main current flows between both main
surfaces with an intrinsic or first conductivity type semiconductor substrate sandwiched
therebetween, which device includes a first impurity region of a first conductivity
type, a second impurity region of a second conductivity type, a third impurity
region of the second conductivity type, a fourth impurity region of the first conductivity
type, a control electrode layer, a first electrode layer and a second electrode
layer. The first impurity region of the first conductivity type is formed as the
first main surface of the semiconductor substrate, and has an impurity concentration
higher than that of the semiconductor substrate. The second impurity region of
the second conductivity type is formed on the second main surface of the semiconductor
substrate. The semiconductor substrate has trenches extending parallel to each
other and sandwiching the first impurity region. The third impurity region of the
second conductivity type is a sidewall of the trench and formed at the first main
surface. The fourth impurity region of the first conductivity type is provided
immediately below the third impurity region to be in contact with the sidewall
of the trench and the semiconductor substrate region, and has lower concentration
than the first impurity region.
The control electrode layer is formed to oppose to the third and fourth impurity
regions and semiconductor substrate region with an insulating film interposed,
in the trench. The first electrode layer is formed on the first main surface of
the semiconductor substrate and is electrically connected to the first and third
impurity regions. The second electrode layer is formed at the second main surface
of the semiconductor substrate and electrically connected to the second impurity region.
In the semiconductor device in accordance with aforementioned still further aspect
of the present invention, the control electrode layer opposes to the third and
fourth impurity regions and the semiconductor substrate region with the insulating
film interposed. In other words, the gate control is of voltage control type. Therefore,
it is not necessary to extract a large current from the control electrode layer
at the time of turn off. Therefore, it is not necessary to provide a protecting
circuit or a cooling mechanism in the gate control circuit in consideration of
surface voltage or heat radiation generated when a large current flows. Therefore,
as compared with the first and second prior art examples, the gate control circuit
can be simplified.
Further, the device is a bipolar device. In the bipolar device, both the
holes and the electrons contribute to the operation. Therefore, even if the substrate
thickness is increased to meet the demand of higher breakdown voltage and current
path in the on state becomes longer, there will be conductivity modulation by the
holes and electrons. Therefore, the resistance can be maintained low. Accordingly,
the amount of heat radiation is small and increase in steady loss can be suppressed.
Further, the control electrode layer opposes to the third and fourth impurity
regions and the semiconductor substrate region. Therefore, by applying a positive
voltage to the control electrode layer, regions near the trenches in which control
electrode layers are filled can have such high electron density that is approximately
the same as in the first impurity region. Therefore, all the regions near the trench
can be regarded as the first impurity region, and a state as if the first impurity
region is enlarged can be realized. When the first impurity region is enlarged,
the contact area between the enlarged first impurity region and the semiconductor
substrate region, that is, the effective cathode area is increased. Thus, the efficiency
in injecting electrons on the side of the cathode is improved, and on-state voltage
Vf of the diode can be reduced.
By applying a voltage to the control electrode layer, the region of the opposite
conductivity type near the trench can have approximately the same high electron
density as that of the first impurity region. Therefore, the region of the opposite
conductivity type such as the third impurity region as well as the fourth impurity
region can be regarded as the first impurity region. Since the third impurity region
is also regarded as a first impurity region in addition to the fourth impurity
region, the effective cathode area can further be increased. Thus, the efficiency
in injecting electrons on the cathode side can further be improved, and the on-state
voltage Vf on the diode can further be reduced.
Preferably, in the above described aspect, an isolating impurity region
is further provided, formed at the first main surface of the semiconductor substrate.
On one side of the outermost of the plurality of trenches extending parallel to
each other, another trench is positioned, while on the other side, the isolating
impurity region is formed in contact with the outermost trench and deeper than
the trench.
Since isolating impurity region is provided to surround the region in which
a diode structure or a thyristor structure is formed, the effect of electrical
isolation from other elements can be enhanced, and breakdown voltage of the device
is improved and stabilized.
Preferably, in the above described aspect, the depth of the trench from
the first main surface is at least 5 μm and at most 15 μm.
As the depth of the trench is at least 5 μm, the storage region having
high
electron density can be generated widely along the sidewall of the trench at on-state.
Therefore, as compared with the third prior art example, wider effective cathode
area is ensured. Therefore, the efficiency in injecting electrons on the cathode
side can further be improved, and the on-state voltage Vf can be reduced. Further,
since it is difficult to form a trench deeper than 15 μm with a minute width
(of at most 0.6 μm), the depth of the trench is at most 15 μm.
In the semiconductor device according to a still further aspect of the present
invention, main current flows between both main surfaces of an intrinsic or a first
conductivity type semiconductor substrate, and the device includes a first impurity
region of a second conductivity type, a second impurity region of a second conductivity
type, a third impurity region of the first conductivity type, a control electrode
layer, and first and second electrode layers.
The first impurity region is formed on the side of the first main surface of
the semiconductor substrate. The second impurity region is formed at the second
main surface of the semiconductor substrate, and with the first impurity region,
sandwiches a low concentration region of the semiconductor substrate. The semiconductor
substrate has a trench reaching the semiconductor substrate region from the first
main surface through the first impurity region. The third impurity region is formed
on the first impurity region to be in contact with the sidewall of the trench of
the first main surface of the semiconductor substrate. The control electrode layer
is formed to oppose to the first and third impurity regions and the semiconductor
substrate region in the trench with an insulating film interposed, and controls
current flowing between the first and second main surfaces in accordance with an
applied control voltage. The first electrode layer is formed on the first main
surface of the semiconductor substrate and electrically connected to the first
and third impurity regions. The second electrode layer is formed on the second
main surface of the semiconductor substrate and electrically connected to the second
impurity region. When the first and second main surfaces of the semiconductor substrate
is in a conducted state, an accumulation region of the first conductivity type
is formed around the trench, to be in contact with the third impurity region. In
the conduction state, the ratio Rn=(n/n+p) of the contact area n between the effective
cathode region including the third impurity region and accumulation region with
the first impurity region and the semiconductor substrate region with respect to
the area p on the side of the first main surface of the first impurity region in
at least 0.4 and at most 1.0.
Since the ratio Rn is at least 0.4 and at most 1.0, which is higher than the
third prior art example, efficiency in injecting electrons on the side of the cathode
is improved as compared with a prior art example, and hence on-state voltage Vf
can be reduced.
Preferably, in the above described aspects, the depth of the trench from
the first main surface is at least 5 μm and at most 15 μm. Since the
depth of the trench is at least 5 μm, the storage region having high electron
density can be generated wider along the sidewall of the trench at on-state. Therefore,
wider effective cathode area than the third prior art example can be ensured. Therefore,
the efficiency in injecting electrons on the cathode side can further be enhanced,
and on-state voltage Vf can be reduced. In the present device, it is difficult
to form a trench deeper than 15 μm with a minute width (of at most 0.6 μm),
and hence the depth of the trench is at most 15 μm.
In the above described aspect, preferably, the trench includes a plurality of
trenches, having first, second and third trenches. At the semiconductor substrate
between the first and second trenches, the first and third impurity regions are
formed. At the first main surface of the semiconductor substrate between the second
and third trenches, only the semiconductor substrate region is positioned. On the
semiconductor substrate between the second and third trenches, a conductive layer
is formed with a second insulating layer interposed. The conductive layer is electrically
connected to each of the control electrode layers filling the second and third trenches.
Since the conductive layer is electrically connected to the control electrode
layer, when a positive voltage, for example, is applied to the control electrode
layer at on-state, the positive voltage is also applied to the conductive layer.
The conductive layer opposes to the semiconductor substrate region between the
second and third trenches with the second insulating layer interposed. Therefore,
when the positive voltage is applied to the conductive layer, the surface region
between the second and third trenches can have approximately the same high electron
density as that of a third impurity region. Therefore, the third impurity region
is enlarged by the surface region of the substrate sandwiched between the second
and third trenches. Accordingly, the effective cathode area is increase, efficiency
in injecting electrons on the cathode side can further be enhanced, and the on-state
voltage Vf of the diode can further be reduced.
In the above described aspect, preferably, there are a plurality of trenches,
including first, second and third trenches. At the semiconductor substrate between
the first and second trenches, first and third impurity regions are formed. At
the first main surface of the semiconductor substrate between the second and third
trenches, the fourth impurity region of the second conductivity type having lower
concentration than the second impurity region is formed. On the semiconductor substrate
between the second and third trenches, a conductive layer is formed with a second
insulating layer interposed. The conductive layer is electrically connected to
each of the control electrode layers filling the second and third trenches.
Since the conductive layer is electrically connected to the control electrode
layer, when a positive voltage, for example, is applied to the control electrode
layer at on-state, the positive voltage is also applied to the conductive layer.
The conductive layer opposes to the fourth impurity region between the second and
third trenches with the second insulating layer interposed. Since the fourth impurity
region has lower concentration than the second impurity region, when the positive
voltage is applied to the conductive layer, the surface region between the second
and third trenches comes to have approximately the same high electron density as
that of the third impurity region. Therefore, the third impurity region is enlarged
by the surface area of the substrate sandwiched between the second and third trenches.
Thus, the effective cathode area is increased, efficiency in injecting electrons
on the cathode side is further enhanced, and the on-state voltage Vf diode can
further be reduced.
Since the fourth impurity region is set to have lower concentration than the
second impurity region, thyristor operation occurs when the device operates. As
a result, the ON voltage lowers advantageously when rated current is conducted.
When the device is turned off, a negative voltage, for example, is applied to
the control electrode layer. At this time, since the negative voltage is also applied
to the conductive layer, a region having higher hole density than the fourth impurity
region is generated at the surface of the fourth impurity region below the conductive
layer. Since the region having a high hole density is formed, extraction of holes
at the time of turn off is facilitated, thus turn off speed of the device is improved
and the turn off loss can be reduced.
In the above described aspect, preferably, the fourth impurity region of the
second
conductivity type having lower concentration than the first impurity region is
further provided to be in contact with the sidewall of the trench at a lower portion
of the first impurity region and to sandwich with the second impurity region, the
semiconductor substrate region.
Since the fourth impurity region has lower concentration than the first impurity
region, when a negative voltage is applied to the control electrode layer at off-state,
there is generated a region having higher hole density than the concentration of
the first impurity region, along the sidewall of the trench, in the fourth impurity
region. Since the region having high hole density is formed, extraction of holes,
which are carriers, can be facilitated and smoothly performed at the time of turn
off of the device, so that switching characteristic can be improved.
In the semiconductor device in accordance with a still further aspect of the
present
invention, current flows between both main surfaces of an intrinsic or a first
conductivity type semiconductor substrate, and the device includes a first impurity
region of a second conductivity type, a second impurity region of a second conductivity
type, a third impurity region of the first conductivity type, a fourth impurity
region of the second conductivity type, a control electrode layer, and first and
second electrode layers. The first impurity region is formed on the side of the
first main surface of the semiconductor substrate. The second impurity region is
formed at the second main surface of the semiconductor substrate and, sandwiches,
with a first impurity region, a low concentration region of the semiconductor substrate.
The semiconductor substrate has a trench reaching the semiconductor substrate region
from the first main surface through the first impurity region. The third impurity
region is formed on the first impurity region to be in contact with a sidewall
of the trench at the first main surface of the semiconductor substrate. The fourth
impurity region is formed to be adjacent to the third impurity region at the main
surface of the semiconductor substrate on the first impurity region, and it has
higher concentration than the first impurity region.
The control electrode layer is formed to oppose to the first and third impurity
regions and the low concentration region of the semiconductor substrate with an
insulating film interposed in the trench, and controls current flowing between
the first and second main surfaces in accordance with an applied control voltage.
The first electrode layer is formed at the first main surface of the semiconductor
substrate and electrically connected to the third and fourth impurity regions.
The second electrode layer is formed on the second main surface of the semiconductor
substrate and electrically connected to the second impurity region. Here, the following
relation holds where Dt represents the depth of the trench from the first main
surface, Wt represents the width of said trench, De represents the depth of the
third impurity region from the first main surface, We represents the width of the
third impurity region from one trench to another trench, and Pt represents pitch
between adjacent trenches:
##EQU1##
The ratio Rn=(n/n+p) can be approximated as shown by the above expression, in
accordance with dimensions of various portions. Since dimensions of various portions
are set so that the ratio Rn is at least 0.4, efficiency in injecting electrons
on the side of the cathode can be improved and the on-state voltage Vf can be reduced,
as compared with the third prior art example.
The method of manufacturing the semiconductor device in accordance with a present
invention is for manufacturing a semiconductor device in which main current flows
between both main surfaces of an intrinsic or a first conductivity type semiconductor
substrate, including the following steps.
First, by selective ion implantation to the first main surface of the semiconductor
substrate, a first impurity region of a second conductivity type is formed. Then,
the second impurity region of the second conductivity type is formed at the second
main surface of the semiconductor substrate. By selective ion implantation, a third
impurity region of the first conductivity type is formed at the first main surface
in the first impurity region. By performing anisotropic etching on the first main
surface, a plurality of trenches including first, second and third trenches are
formed at the semiconductor substrate. Thus, first and third impurity regions are
formed along the sidewalls of the trench at the first main surface between the
first and second trenches, and only a low concentration region of the semiconductor
substrate is positioned at the first main surface between the second and third trenches.
A control layer is formed in the trench to oppose to the low concentration region
of the semiconductor substrate and the first and third impurity regions between
the first and
