Semiconductor device and method for manufacturing the same Number:7,189,994 from the United States Patent and Trademark Office (PTO) owispatent It is an object of the present invention to form a TFT which is required to have a high withstanding voltage characteristic as well as to lower an off-current, a TFT which is required to have a high withstanding voltage characteristic as well as to raise an on-current, and a TFT in which a short channel structure and the decline in the threshold voltage arising therefrom are attached importance to, on one and the same substrate. A TFT having gate insulating films with different thickness can be formed on one and the same substrate by providing auxiliary electrodes in addition to the gate electrodes over a semiconductor film as well as laminating the insulating films.<H manufacturing, Semiconductor, Semiconductor, d, 7189994.html, Patent, pto, 7189994

Title: Semiconductor device and method for manufacturing the same

Abstract: It is an object of the present invention to form a TFT which is required to have a high withstanding voltage characteristic as well as to lower an off-current, a TFT which is required to have a high withstanding voltage characteristic as well as to raise an on-current, and a TFT in which a short channel structure and the decline in the threshold voltage arising therefrom are attached importance to, on one and the same substrate. A TFT having gate insulating films with different thickness can be formed on one and the same substrate by providing auxiliary electrodes in addition to the gate electrodes over a semiconductor film as well as laminating the insulating films.

Patent Number: 7,189,994 Issued on 03/13/2007 to Arao

Inventors: Arao; Tatsuya (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Kanagawa-ken, JP)

Appl. No.: 10/677,316

Filed: October 3, 2003

Foreign Application Priority Data


Oct 07, 2002 [JP]			2002-293499

Current U.S. Class: 257/59 ; 257/319; 257/320; 257/347; 257/66; 257/73

Current International Class: H01L 29/04 (20060101); H01L 31/036 (20060101); H01L 31/0376 (20060101); H01L 31/20 (20060101)

Field of Search: 257/59,66,72,73,347,319,320

References Cited [Referenced By]

U.S. Patent Documents


4849798	July 1989	Wantanabe
5164805	November 1992	Lee
5475238	December 1995	Hamada
5835172	November 1998	Yeo et al.
5973378	October 1999	Ohtani
6150700	November 2000	Lee
6255166	July 2001	Ogura et al.
6278131	August 2001	Yamazaki et al.
6316787	November 2001	Ohtani
6555424	April 2003	Lin et al.
6590229	July 2003	Yamazaki
6593592	July 2003	Yamazaki et al.
6639244	October 2003	Yamazaki et al.
6639265	October 2003	Arao et al.
6657228	December 2003	Ohtani
2002/0014624	February 2002	Yamazaki et al.
2002/0175376	November 2002	Ohtani et al.

Foreign Patent Documents


03-280018	Dec., 1991	JP
04-219736	Aug., 1992	JP
05-251702	Sep., 1993	JP
8-17238	Feb., 1996	JP
11-345976	Dec., 1999	JP
2000-058849	Feb., 2000	JP
2000-284722	Oct., 2000	JP
2002-50770	Feb., 2002	JP

Other References

Tanaka et al., "A Novel Unified-Structure Field-Induction-Drain (UFID) Poly-Si TFTs in CMOS Circuits for LCD Application", SID 91 Digest, pp. 539-542, May 1991. cited by other .
Specification for abandoned U.S. Appl. No. 07/910,412, filed Jul. 8, 1992. cited by other.

Primary Examiner: Tran; Thien F.
Attorney, Agent or Firm: Nixon Peabody LLP Costellia; Jeffrey L.

Claims

What is claimed is:

1. A semiconductor device comprising: a semiconductor layer formed on an insulating surface and the semiconductor layer comprising a channel forming region; a first insulating film formed on the semiconductor layer, the first insulating film formed to cover an entire surface of the channel forming region; a first auxiliary electrode formed over the semiconductor layer with the first insulating film interposed therebetween; a second insulating film formed on and in contact with the first insulating film and the first auxiliary electrode, the second insulating film formed to cover the entire surface of the channel forming region with the first insulating film interposed therebetween; and a gate electrode formed over the channel forming region with the first insulating film and second insulating film interposed therebetween, wherein the first auxiliary electrode is formed outside of the channel forming region.

2. The semiconductor device according to claim 1, wherein the first insulating film has a thickness of 1 to 100 nm, and the second insulating film has a thickness of 5 to 100 nm.

3. The semiconductor device according to claim 1, wherein the first insulating film has a thickness of 5 to 50 nm, and the second insulating film has a thickness of 5 to 100 nm.

4. The semiconductor device according to claim 1, wherein the first auxiliary electrode is partially overlapped with the gate electrode with the second insulating film interposed therebetween.

5. The semiconductor device according to claim 1, wherein the first auxiliary electrode is formed between the channel forming region and a drain region in the semiconductor layer.

6. The semiconductor device according to claim 1, wherein a second auxiliary electrode is formed over the semiconductor layer with the first insulating film interposed therebetween, and the second auxiliary electrode is formed between a source region and the channel forming region in the semiconductor layer.

7. The semiconductor device according to claim 1, wherein an impurity element is included in a portion of the semiconductor layer opposed to the first auxiliary electrode through the first insulating film.

8. The semiconductor device according to claim 1, wherein a first distance between the gate electrode and the semiconductor layer is longer than a second distance between the first auxiliary electrode and the semiconductor layer.

9. The semiconductor device according to claim 1, wherein a third auxiliary electrode is formed on the second insulating film.

10. The semiconductor device according to claim 9, wherein the third auxiliary electrode has a curved surface or an inclined surface.

11. A semiconductor device comprising: a semiconductor layer comprising a channel forming region; a first insulating film formed on the semiconductor layer, the first insulating film formed to cover an entire surface of the channel forming region; a first auxiliary electrode for controlling the carrier density between a source region or a drain region, and the channel forming region in the semiconductor layer; a second insulating film formed on the first insulating film and the first auxiliary electrode, the second insulating film formed to cover the entire surface of the channel forming region with the first insulating film interposed therebetween; and a gate electrode formed over the channel forming region with the first insulating film and second insulating film interposed therebetween.

12. The semiconductor device according to claim 11, wherein the first insulating film has a thickness of 1 to 100 nm, and the second insulating film has a thickness of 5 to 100 nm.

13. The semiconductor device according to claim 11, wherein the first insulating film has a thickness of 5 to 50 nm, and the second insulating film has a thickness of 5 to 100 nm.

14. The semiconductor device according to claim 11, wherein the first auxiliary electrode is partially overlapped with the gate electrode with the second insulating film interposed therebetween.

15. The semiconductor device according to claim 11, wherein the first auxiliary electrode is formed between the channel forming region and the drain region in the semiconductor layer.

16. The semiconductor device according to claim 11, wherein a second auxiliary electrode is formed over the semiconductor layer with the first insulating film interposed therebetween, and the second auxiliary electrode is formed between the source region and the channel forming region in the semiconductor layer.

17. The semiconductor device according to claim 11, wherein an impurity element is included in a portion of the semiconductor layer opposed to the first auxiliary electrode through the first insulating film.

18. The semiconductor device according to claim 11, wherein a first distance between the gate electrode and the semiconductor layer is longer than a second distance between the first auxiliary electrode and the semiconductor layer.

19. The semiconductor device according to claim 11, wherein a third auxiliary electrode is formed on the second insulating film.

20. The semiconductor device according to claim 19, wherein the third auxiliary electrode has a curved surface or an inclined surface.

21. A semiconductor device comprising: a first thin film transistor over a substrate, the first thin film transistor comprising a first semiconductor layer, a first gate insulating film, and a first gate electrode; a second thin film transistor over the substrate, the second thin film transistor comprising a second semiconductor layer, a second gate insulating film having a first film and a second film, and a second gate electrode; and a first auxiliary electrode formed between the first film and the second film, wherein the first auxiliary electrode is formed outside of a channel forming region in the second semiconductor layer, and wherein the first gate insulating film is thinner than the second gate insulating film.

22. The semiconductor device according to claim 21, wherein one of the first film and the second film is a same film as the first gate insulating film.

23. The semiconductor device according to claim 21, wherein the first gate insulating film has a thickness of 1 to 100 nm thick, and the second gate insulating film has a thickness of 6 to 200 nm.

24. The semiconductor device according to claim 21, wherein the first gate insulating film has a thickness of 5 to 50 nm thick, and the second gate insulating film has a thickness of 6 to 200 nm.

25. The semiconductor device according to claim 21, wherein the first auxiliary electrode is formed between a drain region and a channel forming region in the second semiconductor layer.

26. The semiconductor device according to claim 21, wherein a third auxiliary electrode is formed between the first film and the second film in the second gate insulating film, the third auxiliary electrode is formed between a source region and a channel forming region in the second semiconductor layer.

27. The semiconductor device according to claim 21, wherein the first auxiliary electrode is partially overlapped with the second gate electrode.

28. The semiconductor device according to claim 21, wherein each of the first auxiliary electrode, the first gate electrode, and the second gate electrode is connected to a different wiring.

29. The semiconductor device according to claim 21, wherein an impurity element is included in a portion of the semiconductor layer opposed to the first auxiliary electrode through the second gate insulating film.

30. The semiconductor device according to claim 21, wherein a first distance between the second gate electrode and the second semiconductor layer is longer than a second distance between the first auxiliary electrode and the second semiconductor layer.

31. The semiconductor device according to claim 21, wherein the first thin film transistor further comprises: an insulating film covering the first gate electrode and the first gate insulating film; and a second auxiliary electrode formed on the insulating film.

32. The semiconductor device according to claim 31, wherein the second auxiliary electrode has a curved surface or an inclined surface.

33. The semiconductor device according to claim 32, wherein each of the first auxiliary electrode, the second auxiliary electrode, the first gate electrode, and the second gate electrode are connected to a different wiring.

34. A semiconductor device comprising: a first thin film transistor over a substrate, the first thin film transistor comprising a first semiconductor layer, a first gate insulating film, and a first gate electrode; a second thin film transistor over the substrate, the second thin film transistor comprising a second semiconductor layer, a second gate insulating film having a first film and a second film, and a second gate electrode; a first auxiliary electrode for controlling the carrier density between a source region or drain region and a channel forming region in the second semiconductor layer, wherein the first auxiliary electrode is formed between the first film and the second film, and wherein the first gate insulating film is thinner than the second gate insulating film.

35. The semiconductor device according to claim 34, wherein one of the first film and the second film is a same film as the first gate insulating film.

36. The semiconductor device according to claim 34, wherein the first gate insulating film has a thickness of 1 to 100 nm thick, and the second gate insulating film has a thickness of 6 to 200 nm.

37. The semiconductor device according to claim 34, wherein the first gate insulating film has a thickness of 5 to 50 nm thick, and the second gate insulating film has a thickness of 6 to 150 nm.

38. The semiconductor device according to claim 34, wherein the first auxiliary electrode is formed between a drain region and a channel forming region in the second semiconductor layer.

39. The semiconductor device according to claim 34, wherein a third auxiliary electrode is formed between the first film and the second film in the second gate insulating film, the third auxiliary electrode is formed between a source region and a channel forming region in the second semiconductor layer.

40. The semiconductor device according to claim 34, wherein the first auxiliary electrode is partially overlapped with the second gate electrode.

41. The semiconductor device according to claim 34, wherein each of the first auxiliary electrode, the first gate electrode, and the second gate electrode is connected to a different wiring.

42. The semiconductor device according to claim 34, wherein an impurity element is included in a portion of the semiconductor layer opposed to the first auxiliary electrode through the second gate insulating film.

43. The semiconductor device according to claim 34, wherein a first distance between the second gate electrode and the second semiconductor layer is longer than a second distance between the first auxiliary electrode and the second semiconductor layer.

44. The semiconductor device according to claim 34, wherein the first thin film transistor further comprises: an insulating film covering the first gate electrode and the first gate insulating film; and a second auxiliary electrode formed on the insulating film.

45. The semiconductor device according to claim 44, wherein the second auxiliary electrode has a curved surface or an inclined surface.

46. The semiconductor device according to claim 45, wherein each of the first auxiliary electrode, the second auxiliary electrode, the first gate electrode, and the second gate electrode are connected to a different wiring.

47. A semiconductor device comprising: a semiconductor layer formed on an insulating surface and the semiconductor layer comprising a first region, at least one second region, a source region, and a drain region; a first insulating film formed on the semiconductor layer, the first insulating film formed to cover an entire surface of the first region and an entire surface of the second region; a first auxiliary electrode formed over the semiconductor layer with the first insulating film interposed therebetween; a second insulating film formed on and in contact with the first insulating film and the first auxiliary electrode, the second insulating film formed to cover the entire surface of the first region with the first insulating film interposed therebetween; and a gate electrode formed over the second insulating film, wherein the first region overlaps with the gate electrode, with the first insulating film and the second insulating film interposed therebetween, and does not overlap with the first auxiliary electrode, wherein the first region is formed between the source region and the drain region, the second region is formed between the first region and at least one of the source and drain regions, and wherein the first auxiliary electrode is formed over the second region with the first insulating film interposed therebetween.

48. The semiconductor device according to claim 47, wherein the first insulating film has a thickness of 1 to 100 nm, and the second insulating film has a thickness of 5 to 100 nm.

49. The semiconductor device according to claim 47, wherein the first insulating film has a thickness of 5 to 50 nm, and the second insulating film has a thickness of 5 to 100 nm.

50. The semiconductor device according to claim 47, wherein the first auxiliary electrode is partially overlapped with the gate electrode with the second insulating film interposed therebetween.

51. The semiconductor device according to claim 47, wherein an impurity element is included in the second region.

52. The semiconductor device according to claim 47, wherein the first auxiliary electrode controls the carrier density between the source region, the drain region, and the first region.

53. The semiconductor device according to claim 47, wherein a first distance between the gate electrode and the semiconductor layer is longer than a second distance between the first auxiliary electrode and the semiconductor layer.

54. The semiconductor device according to claim 47, wherein a second auxiliary electrode is formed on the second insulating film.

55. The semiconductor device according to claim 54, wherein the second auxiliary electrode has a curved surface or an inclined surface.

56. A semiconductor device comprising: a first semiconductor layer comprising a first region, a first source region, and a first drain region; a second semiconductor layer comprising a second region, at least one third region, a second source region, and a second drain region; a first insulating film formed on the first and second semiconductor layers; a first auxiliary electrode formed over the second semiconductor layer with the first insulating film interposed therebetween; a first gate electrode formed over the first semiconductor layer with the first insulating film interposed therebetween; a second insulating film formed on the first insulating film, the first auxiliary electrode, and the first gate electrode; and a second gate electrode formed over the second region with the first and second insulating films interposed therebetween, wherein the second region is formed between the second source region and the second drain region, the third region is formed between the second region and at least one of the second source and drain regions, and wherein the first auxiliary electrode is formed over the third region with the first insulating film interposed therebetween.

57. The semiconductor device according to claim 56, wherein the first insulating film has a thickness of 1 to 100 nm, and the second insulating film has a thickness of 5 to 100 nm.

58. The semiconductor device according to claim 56, wherein the first insulating film has a thickness of 5 to 50 nm, and the second insulating film has a thickness of 5 to 100 nm.

59. The semiconductor device according to claim 56, wherein the first auxiliary electrode is partially overlapped with the second gate electrode with the second insulating film interposed therebetween.

60. The semiconductor device according to claim 56, wherein an impurity element is included in the third region.

61. The semiconductor device according to claim 56, wherein the first auxiliary electrode controls the carrier density between the second source region, the second drain region, and the third region.

62. The semiconductor device according to claim 56, wherein a first distance between the second gate electrode and the second semiconductor layer is longer than a second distance between the first auxiliary electrode and the second semiconductor layer.

63. The semiconductor device according to claim 56, wherein a second auxiliary electrode is formed on the second insulating film.

64. The semiconductor device according to claim 63, wherein the second auxiliary electrode has a curved surface or an inclined surface.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device which comprises a circuit formed from a thin film transistor (hereinafter referred to as TFT) and the manufacturing method thereof. The present invention further relates to a display module typified by an active matrix liquid crystal module and an EL module, each fabricated using a TFT, and also to an electronic device which comprises such display modules as its components.

2. Description of the Related Art

Recently, the development of a semiconductor device having a large-scale integrated circuit formed from a TFT has been advanced. The TFT comprises a thin semiconductor film (with a thickness of about several to several hundred nanometers) formed over a substrate having an insulating surface. An active matrix liquid crystal display device, an EL display device, and a close coupling image sensor are known as typical examples of the semiconductor devices. Further, a system on panel is proposed, wherein a central processing unit (hereinafter referred to as a CPU), a dynamic random-access memory (hereinafter referred to as a DRAM), an image processing circuit, a sound processing circuit and the like are provided on one and the same substrate besides a pixel portion and a driving circuit portion. Particularly, a TFT having crystalline silicon film as an active layer has high electron field-effect mobility, therefore the TFT is applicable to form a circuit with various functions.

For example, in a liquid crystal module mounted in a liquid crystal display device, a pixel circuit for displaying an image in each functional block and a driving circuit for controlling the pixel circuit, functional circuits are formed on a single substrate. The driving circuit includes a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like, using CMOS circuits as a fundamental circuit. And, functional circuits include a CPU, a DRAM, an image processing circuit, a sound processing circuit, and the like except a pixel circuit and a driving circuit.

A TFT of a pixel region (hereinafter referred to as a pixel TFT) is formed of an n-channel TFT, and it drives a liquid crystal by applying voltage thereto as a switching device. Since a liquid crystal is driven with an alternating current, a system called frame inversion drive is mostly adopted. As for this system, a pixel TFT is required to have characteristics of keeping an off-current value (a drain current which flows during an off operation of a TFT) sufficiently low in order to suppress power consumption.

A lightly doped drain (hereinafter referred to as LDD) structure is known as a TFT structure for lowering the off-current value. This structure has a region doped with dilute impurity elements between a channel forming region and a source region or between a channel forming region and a drain region; the region is called an LDD region. The LDD structure has an effect of preventing deterioration due to injection of hot carriers by alleviating an electrical field adjacent to a drain.

A driving circuit (a buffer circuit, a level shifter circuit, a sampling circuits, and the like) which drives a pixel TFT uses a CMOS circuit as fundamental circuit. A TFT used for a driving circuit preferably has a structure wherein an on-current is to be attached more importance to than an off-current. An LDD region is provided below a gate electrode in this structure. An LDD structure had a disadvantage of reducing an on-current as well as off-current, however, this structure can decrease deterioration of on-current due to an injection of hot carriers by alleviating an electric field adjacent to a drain.

As to a driving circuit, a buffer circuit, a level shifter circuit, a sampling circuit, and the like are circuits for applying voltage to a gate wiring in a pixel region, and high voltage is applied to the driving circuit as well as a pixel region. Therefore, a thick gate insulating film is required.

Further, a TFT of a functional circuit including a CPU, a DRAM, an image processing circuit, a sound processing circuit, and the like except a pixel circuit and a driving circuit needs high speed operation; accordingly, a short channel TFT is preferable. However, a short channel TFT causes threshold voltage decline and allows an off-current to flow easily. Therefore, a TFT with a short channel and a thin gate insulating film is preferable for a TFT used for a CPU, a DRAM, an image processing circuit, a sound processing circuit, and the like.

Thus, a process becomes complex when manufacturing TFTs having different structures on one and the same substrate. Specifically, in the case of manufacturing a short channel TFT, only mask design needs to be changed, however, in the case of making the thickness of gate insulating films different in each region of a substrate, a process different from the conventional one needs to be introduced. In particular, the process described below is employed: only a gate insulating film of a TFT for a driving circuit is etched; a thermally-oxide film is formed by heating it at a high temperature; a gate insulating film of a TFT for a driving circuit is made thin; and a gate insulating film for a pixel TFT is made thick (See reference 1: Japanese Patent laid-open No. 2000-284722).

SUMMARY OF THE INVENTION

A structure appropriable for all the TFTs described below has not been established: A pixel TFT which is required to have a high withstanding voltage characteristic as well as to lower an off-current, a TFT for a driving circuit which is required to have a high withstanding voltage characteristic as well as to raise an on-current, such as a buffer circuit, a shift register circuit, level shifter circuit, or a sampling circuit, or a TFT for a functional circuit, such as a CPU, a DRAM, an image processing circuit, or a sound processing circuit wherein a short channel structure and the decline in the threshold voltage arising therefrom are attached importance to.

In addition, there is a problem of increase in the manufacturing process for its complexity in forming a TFT having an LDD structure and a TFT wherein an LDD region is overlapped with a gate electrode with a gate insulating film interposed therebetween. It is obvious that the increase in the manufacturing process raises the manufacturing cost and also lowers the manufacturing yield.

The present invention provides a technique for solving such problems. Specifically, in a semiconductor device having a circuit formed from TFTs, an electro-optic device manufactured with TFTs, typified by an active matrix liquid crystal device, or a light emitting device typified by an EL display device, the present invention provides a method for severally fabricating TFTs having different structures on one and the same substrate by applying a process similar to the conventional one. Namely, a TFT in which a gate insulating film is multi layered and also an electrode different from a gate electrode (hereinafter referred to as an auxiliary electrode) is placed on a semiconductor film is proposed. It is an object of the present invention to provide TFTs having gate insulating films with different thickness on one and the same substrate, to improve the reliability and the performance characteristics of a semiconductor device, and to reduce the power consumption. Also, it is an object of the present invention to provide a TFT structure realizing reduction in manufacturing cost and yield improvement by applying the conventional process.

Moreover, fining pitch of the respective display pixels is promoted in proportion to higher definition (increase in the number of pixels) and miniaturization. When manufacturing a TFT finely, mask alignment is important. And misalignment may cause the problem of reduction in yield. The present invention further provides a TFT structure wherein yield improvement is realized in an electro-optic device manufactured with TFTs, typified by an active matrix liquid crystal device or a light emitting device typified by an EL display device.

A configuration of the invention disclosed in this specification comprises: a semiconductor layer comprising a channel forming region; a first insulating film formed on the semiconductor layer; an auxiliary electrode formed over the semiconductor layer with the first insulating film interposed therebetween; a second insulating film formed on the first insulating film and the auxiliary electrode; and a gate electrode formed over the channel forming region with the first insulating film and second insulating film interposed therebetween, wherein the auxiliary electrode is formed outside of the channel forming region.

Another configuration of the invention disclosed in the specification comprises: a semiconductor layer comprising a channel forming region; a first insulating film formed on the semiconductor layer; an auxiliary electrode for controlling the carrier density between a source region, a drain region, and the channel forming region in the semiconductor layer; a second insulating film formed on the first insulating film and the auxiliary electrode; and a gate electrode formed over the channel forming region with the first insulating film and second insulating film interposed therebetween.

In the above configurations of the invention, the thickness of the first insulating film is 1 to 100 nm, preferably 5 to 50 nm, and the thickness if the second insulating film is 5 to 100 nm.

When one auxiliary electrode is provided for a tin film transistor, the auxiliary electrode is provided between a channel forming region and a drain region in a semiconductor layer. On the other hand, when two auxiliary electrodes are provided for a TFT, one of the auxiliary electrodes is provided between a source region and a channel forming region, and the other is provided between a drain region and the channel forming region.

Each of the auxiliary electrode and the gate electrode is connected to a different wiring.

The auxiliary electrode may be partially overlapped with the gate electrode with the second insulating film interposed therebetween.

Impurity element may be doped in a region of the semiconductor layer opposed to the auxiliary electrode through the first insulating film. That is, the semiconductor layer may have a low-concentration impurity region between the channel forming region and at least one of the source and drain regions. In this case, the low-concentration impurity region is formed under the auxiliary electrode.

Another configuration of the invention disclosed in the specification comprises: a first thin film transistor over a substrate, the first thin film transistor comprising a first semiconductor layer, a first gate insulating film, and a first gate electrode; a second thin film transistor over the substrate, the second thin film transistor comprising a second semiconductor layer, a second gate insulating film having lamination films, and a second gate electrode; and a first auxiliary electrode formed between the lamination films, wherein the first auxiliary electrode is formed outside of a channel forming region in the second semiconductor layer and wherein the first gate insulating film is thinner than the second gate insulating film.

Another configuration of the invention disclosed in the specification comprises: a first thin film transistor over a substrate, the first thin film transistor comprising a first semiconductor layer, a first gate insulating film, and a first gate electrode; a second thin film transistor over the substrate, the second thin film transistor comprising a second semiconductor layer, a second gate insulating film having a lamination films, a second gate electrode; a first auxiliary electrode for controlling the carrier density between a source region or drain region and a channel forming region in the second semiconductor layer, wherein the first auxiliary electrode is formed between the lamination films, and wherein the first gate insulating film is thinner than the second gate insulating film.

In the above configurations of the invention, thickness of the first insulating film is 1 to 100 nm, preferably 5 to 50 nm, and the thickness of the second gate insulating film is 6 to 200 nm.

One of the lamination films is a same film as the first gate insulating film.

Each of the first auxiliary electrode, the first gate electrode, and the second gate electrode is connected to a different wiring.

When one auxiliary electrode is provided for a thin film transistor, the auxiliary electrode is provided between a channel forming region and a drain region in a semiconductor layer. On the other hand, when two auxiliary electrodes are provided for a TFT, one of the auxiliary electrodes is provided between a source region and a channel forming region, and the other is provided between a drain region and the channel forming region.

The first thin film transistor may further comprises an insulating film covering the first gate electrode and the first gate insulating film, and a second auxiliary electrode formed on the insulating film.

In this case, the second auxiliary electrode has a curved surface or an inclined surface.

Impurity element may be doped in a region of the semiconductor layer opposed to the first auxiliary electrode through the first insulating film. That is, the semiconductor layer may have a low-concentration impurity region between the channel forming region and at least one of the source and drain regions. In this case, the low-concentration impurity region is formed under the first auxiliary electrode.

Another configuration of the invention disclosed in the specification comprises: forming a first semiconductor layer and a second semiconductor layer on an insulating surface; forming a first insulating film on the first semiconductor layer and the second semiconductor layer; forming a first gate electrode and a first auxiliary electrode on the first insulating film; forming a second insulating film on the first gate electrode, the first auxiliary electrode, and the first insulating film; and forming a second gate electrode on the second insulating film, wherein the first gate electrode is formed over the first semiconductor layer with the first insulating film interposed therebetween, wherein the first auxiary electrode is formed over the second semiconductor layer with the first insulating film interposed therebetween, and wherein the second gate electrode is formed over the second semiconductor layer with the first and second insulating film interposed therebetween.

In the above configuration of the invention, the first auxiliary electrode, the first gate electrode, and the second gate electrode are etched so that each of these electrodes is connected to a different wiring.

A second auxiliary electrode can be formed on the second insulating film at the same time when the second gate electrode is formed. In this case, the second auxiliary electrode is connected to a different wiring from the wiring mentioned above.

The second electrode is formed over the second semiconductor layer and first auxiliary electrode.

Since the configurations of the present invention makes it possible to control the carrier density between the source region or drain region and the channel forming region without forming the LDD region, misalignment of a mask used in a process for forming the LDD region can be avoided, and thus decrease in yield can be restrained.

According to the configurations of the present invention, a number of TFTs having gate insulating films each having different thickness can be formed on a same substrate without using a special process. Moreover, even if the LDD region is not formed, an optional voltage is applied to the first auxiliary electrode and second auxiliary electrode, thereby the carrier density in the semiconductor layer under respective auxiliary electrodes can be changed.

In addition, a TFT having a thick gate insulating film is used as a TFT for a driving circuit such as a shift register circuit, level shifter circuit, buffer circuit, or sampling circuit and a pixel TFT, thereby a TFT, which has a high withstanding voltage, enables a low power consumption design, and has a high reliability, can be made. Furthermore, a TFT having a short channel length and a thin gate insulating film is used as a TFT for functional circuits including CPU, DRAM, an image processing circuit, and an audio processing circuit, thereby operating characteristics and reliability can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A 1D show Embodiment Mode 1;

FIGS. 2A 2D show Embodiment Mode 2;

FIGS. 3A 3D show Embodiment Mode 3;

FIGS. 4A 4D show Embodiment Mode 4;

FIG. 5 shows an example of a cross sectional view of a liquid crystal display device (Embodiment 1);

FIG. 6 shows an example of a cross sectional view of an EL display device (Embodiment 2);

FIGS. 7A 7D show Embodiment 3;

FIGS. 8A 8D show Embodiment 4;

FIGS. 9A 9C show Embodiment 5;

FIG. 10 shows Embodiment 6;

FIGS. 11A 11G show examples of electronic devices;

FIGS. 12A 12D show examples of electronic devices; and

FIG. 13 shows a liquid crystal module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment Mode 1

An example of the invention is shown in FIGS. 1A 1D. This embodiment shows a process where a P-TFT and N-TFT having a thin gate insulating film and first auxiliary electrodes (in FIGS. 1A 1D, TFT comprising the gate insulating film G1), and a P-TFT and N-TFT having a thick gate insulating film, first auxiliary electrodes, and second auxiliary electrodes (in FIGS. 1A 1D, TFT comprising the gate insulating film G1 and G2) are formed at the same time.

As shown in FIG. 1A, a crystalline semiconductor film is formed on a substrate 101 through an insulating film 102 as a base film, then the crystalline semiconductor film is etched in an optional pattern and thus separated crystalline semiconductor films 103 to 106 are formed. Then, a first gate insulating film (hereinafter, shown as G1 in the embodiment and FIGS. 1A 1D) 107 is deposited. Typically, the first gate insulating film (G1) 107 functions as a gate insulating film for a TFT for a driving circuit to which a fast operation is required. Thickness of the first gate insulating film is small, 1 to 100 nm, and preferably 5 to 50 nm. When the thickness is smaller than thickness within the range, a problem of formation of parasitic capacity and resultant difficulty in the fast operation occurs.

Next, a first conductive film is deposited, then masks (not shown) are formed using a photolithography technique, then an unnecessary area in the first conductive film is removed using a known etching method, and thus first gate electrodes 108, 109 and first auxiliary electrodes 110a, 110b, 111a, and 111b are formed in a desired pattern. The electrodes are formed as the gate electrodes (hereinafter, described as first gate electrodes in the embodiment) in a TFT having a thin gate insulating film, and formed as the auxiliary electrodes (hereinafter, described as first auxiliary electrodes in the embodiment) in a TFT having a thick gate insulating film. The first auxiliary electrodes in a TFT are preferably arranged with an optional interval. Typically, the electrodes are arranged with an interval approximately equal to a channel length (4 to 12 .mu.m, preferably 6 to 10 .mu.m).

Next, as shown in FIG. 1B, a second gate insulating film 120 (hereinafter, shown as G2 in the embodiment and FIG. 1) is formed. The first gate insulating film (G1) and second gate insulating film (G2) are gate insulating films for the TFT having a thick gate insulating film (in FIGS. 1A 1D, TFT comprising the gate insulating film G1 and G2), and typically function as gate insulating films for the pixel TFT or a TFT to which the withstanding voltage is required such as the TFT in the buffer circuit. Therefore, thickness of the second gate insulating film (G2) is larger than that of the first gate insulating film, and preferably 5 to 100 nm.

Next, a second conductive film 121 is formed, then masks 122, 123 are formed using a photolithography technique, then an unnecessary area in the second conductive film is removed using a known etching method, and thus second gate electrodes and second auxiliary electrodes are formed in a desired pattern. The electrodes are formed as auxiliary electrodes in a TFT having a thin gate insulating film (in FIG. 1, TFT comprising the gate insulating film G1), and formed as a gate electrode and an auxiliary electrode in a TFT having a thick gate insulating film (in FIGS. 1A 1D, TFT comprising the gate insulating film G1 and G2).

When the second conductive film is etched, first, the resist masks 122, 123 are formed in an area where the second gate electrodes are formed. After that, as shown in FIG. 1C, the second conductive film is etched, thereby the second auxiliary electrodes 131a to 134a and 131b to 134b are formed. In this case, by properly fitting conditions, the second auxiliary electrodes having a curved surface, that is, the second auxiliary electrodes 131a to 134a and 131b to 134b that incline towards the first gate insulating film 107 and second gate insulating film 120 formed on the semiconductor layers 103 to 106 are formed in an optional pattern.

In FIGS. 1A 1D, thickness of the crystalline semiconductor film is depicted almost equal to thickness of the first gate electrode for convenience, however, actually the thickness of the crystalline semiconductor film is 25 to 70 nm, and the thickness of the gate electrodes is 120 to 500 nm. Therefore, while the auxiliary electrodes can be formed on a side of the gate electrodes having a large difference in thickness, the auxiliary electrodes can not be formed on a side of the crystalline semiconductor film. Then, the second gate electrodes 135 and 136 are formed by removing the resist masks.

Next, as shown in FIG. 1D, doping is performed using the first gate electrodes 108, 109, the second auxiliary electrodes 131a to 134a and 131b to 134b, the second gate electrodes 135, 136, and the first auxiliary electrodes 110a, 110b, 111a, and 111b as masks, thereby the source region and drain region are formed by adding an impurity element. Dopant that pertains n-type or p-type is added to a source region or drain region 141, 143 in a P-channel type TFT and a source region or drain region 140, 142 in an N-channel type TFT in a density range of 1.times.10.sup.20 to 1.times.10.sup.21/cm.sup.3.

The LDD region can be provided by performing the doping to the crystalline semiconductor film under the first auxiliary electrodes 110a, 110b, 111a, and 111b.

Although a couple of first auxiliary electrodes were formed in the n-channel type TFT 152 and p-channel type TFT 153, the electrode can be formed singly. In this case, the auxiliary electrode is provided between the drain region and gate electrode.

According to the above process, the n-channel type TFT 150 or p-channel type TFT 151 having a thin gate insulating film, and the n-channel type TFT 152 or p-channel type TFT 153 having a thick gate insulating film are formed at the same time.

In the embodiment, since each of the first gate electrodes, first auxiliary electrodes, second gate electrodes, and second auxiliary electrodes is patterned individually, an optional voltage can be applied to each of the electrodes. Therefore, in consideration of functions required for respective TFTs, an optional voltage is applied to the first auxiliary electrodes and second auxiliary electrodes, thereby carrier density within the crystalline semiconductor film under respective auxiliary electrodes can be controlled. That is, hot carrier effect can be restrained with a similar function as the LDD region. Typically, in a low-on-current TFT, resistance can be preferably decreased in the crystalline semiconductor film by controlling the applied voltage to the auxiliary electrodes and increasing the carrier density. In a high-off-current TFT, the resistance can be preferably increased in the crystalline semiconductor film by controlling the applied voltage to the auxiliary electrodes and restraining the carrier density. The second gate electrodes and second auxiliary electrodes can be unseparated or connected with each other.

Electrical potential of the first auxiliary electrodes and second auxiliary electrodes need not be fixed, and can be changed with time in consideration of functions required for respective TFTs. That is, in a TFT, it is possible to increase the on-current or decrease the off-current by adjusting the voltage applied to the auxiliary electrodes. In this case, the voltage applied to the auxiliary electrodes can be properly controlled according to the required off-current or on-current.

According to the above process, TFTs with gate insulating films having different thickness each can be made on a same substrate without using a special process. Moreover, even if the LDD region is not formed, the carrier density in the crystalline semiconductor film under respective auxiliary electrodes can be changed by applying an optional voltage to the first auxiliary electrodes and second auxiliary electrodes. Thus, the hot carrier effect, which may occur at a junction interface between the channel forming region and the source region or drain region, can be restrained. Therefore, the TFT having a thick gate insulating film is used as the TFT for the driving circuit such as the shift register circuit, level shifter circuit, buffer circuit, or sampling circuit and used as the pixel TFT, thereby a TFT having the high withstanding voltage characteristics enables the low power consumption design and the high reliability. Furthermore, a TFT having a short channel length and a thin gate insulating film is used as a TFT for the functional circuits including the CPU, DRAM, image processing circuit, and audio processing circuit, thereby the operating characteristics and reliability can be improved.

Embodiment Mode 2

An example of the invention is shown in FIGS. 2A 2D. The embodiment shows a process for forming a TFT having the LDD region in the active matrix substrate described in the first embodiment.

As shown in FIG. 2A, a crystalline semiconductor film is formed on a substrate 201 through an insulating film 202 as a base film, and then the crystalline semiconductor film is etched in an optional pattern and thus separated crystalline semiconductor films 203 to 206 are formed. Then, a first gate insulating film (hereinafter, shown as G1 in the embodiment and FIGS. 2A 2D) 207 is deposited. The first gate insulating film (G1) 207 has a small thickness, and the thickness of the first gate insulating film is 1 to 100 nm, preferably 5 to 50 nm.

Next, a first conductive film is deposited, then masks (not shown) are formed using the photolithography technique, then an unnecessary area in the first conductive film is removed using a known etching method, and thus first gate electrodes 208, 209 and first auxiliary electrodes 210a, 210b, 211a, and 211b are formed in a desired pattern. The electrodes are formed as gate electrodes (hereinafter, described as first gate electrodes in the embodiment) in a TFT having a thin gate insulating film, and formed as auxiliary electrodes (hereinafter, described as first auxiliary electrodes in the embodiment) in a TFT having a thick gate insulating film. The first auxiliary electrodes in a TFT are preferably arranged with an optional interval. Typically, the electrodes are arranged with an interval approximately equal to the channel length (4 to 12 .mu.m, preferably 6 to 10 .mu.m).

Next, doping is performed into the crystalline semiconductor film except for a channel forming region. Although not shown in FIG. 2A, in a TFT having a thick gate insulating film (in FIGS. 2A 2D, TFT in which the gate insulating film comprises G1 and G2), the doping is performed after the crystalline semiconductor film between the first auxiliary electrodes (that is, areas between regions 210a and 210b, and between regions 211a and 211b in FIG. 2A) is covered by resist masks so that the doping is not performed thereto. The LDD region is formed by performing the doping. The dopant that pertains the n-type or p-type is added to LDD regions 210, 218 in a P-channel type TFT and LDD regions 215, 217 in a N-channel type TFT in a density range of 1.times.10.sup.17 to 1.times.10.sup.18/cm.sup.3.

Next, as shown in FIG. 2B, the second gate insulating film 220 (hereinafter, shown as G2 in the embodiment and FIGS. 2A 2D) is formed. The first gate insulating film (G1) and second gate insulating film (G2) are gate insulating films for the TFT having a thick gate insulating film (in FIGS. 2A 2D, TFT in which the gate insulating film comprises G1 and G2). Thickness of the second gate insulating film (G2) is larger than that of the first gate insulating film, and preferably 5 to 100 nm.

Next, as shown in FIG. 2C, a second conductive film 221 is formed, then masks 222, 223 are formed using the photolithography technique, then an unnecessary area in the second conductive film is removed using a known etching method, and thus second gate electrodes and second auxiliary electrodes are formed in a desired pattern. In a TFT having a thin gate insulating film (in FIGS. 2A 2D, TFT in which the gate insulating film comprises G1), the second auxiliary electrodes are formed. On the other hand, in a TFT having a thick gate insulating film (in FIGS. 2A 2D, TFT in which the gate insulating film comprises G1 and G2), the second auxiliary electrodes and second gate electrodes are formed.

When the second conductive film is etched, first, the resist masks 222, 223 are formed in an area where the second gate electrodes are formed. After that, the second conductive film is etched, thereby the second auxiliary electrodes 231a to 234a and 231b to 234b are formed. In this case, by properly fitting conditions, the second auxiliary electrodes having a curved surface, that is, the second auxiliary electrodes 231a to 234a and 231b to 234b that incline towards the first gate insulating film 207 and second insulating film 220 formed on the semiconductor layers 203 to 206 in an optional pattern are formed.

Then, the second gate electrodes 235, 236 are formed by removing the resist masks.

Next, as shown in FIG. 2D, doping is performed using the first gate electrodes 208, 209, second auxiliary electrodes 231a to 234a and 231b to 234b, second gate electrodes 235, 236, and first auxiliary electrodes 210a, 210b, 211a, and 211b as masks, thereby the source region and drain region are formed. The dopant that pertains the n-type or p-type is added to the source region or drain region 241, 243 in the P-channel type TFT and the source region or drain region 240, 242 in the N-channel type TFT in a density range of 1.times.10.sup.20 to 1.times.10.sup.21/cm.sup.3. The LDD region can be provided by performing the doping to the crystalline semiconductor film under the first auxiliary electrodes 210a, 210b, 211a, and 211b.

According to the above process, an n-channel type TFT 250 or a p-channel type TFT 251 having a thin gate insulating film, and an n-channel type TFT 252 or a p-channel type TFT 253 having a thick gate insulating film can be formed on a same substrate at the same time.

In the embodiment, since each of the first gate electrodes, first auxiliary electrodes, second gate electrodes, and second auxiliary electrodes is patterned individually, an optional voltage can be applied to respective electrodes. Therefore, in consideration of functions required for respective TFTs, an optional voltage is applied to the first auxiliary electrodes and second auxiliary electrodes, thereby carrier density in the crystalline semiconductor film under respective auxiliary electrodes can be controlled. That is, the hot carrier effect can be restrained with a similar function as the LDD. Typically, in a low-on-current TFT, resistance can be preferably decreased in the crystalline semiconductor film by controlling the applied voltage to the auxiliary electrodes and increasing the carrier density. In a high-off-current TFT, the resistance can be preferably increased in the crystalline semiconductor film by controlling the applied voltage to the auxiliary electrodes and restraining the carrier density.

Electrical potential of the first auxiliary electrodes and second auxiliary electrodes need not be fixed, and can be changed with time in consideration of functions required for respective TFTs. That is, in a TFT, it is possible to increase the on-current or decrease the off-current by adjusting the voltage applied to the auxiliary electrodes. In this case, the voltage applied to the auxiliary electrodes can be properly controlled according to the required off-current or on-current. The second gate electrodes and second auxiliary electrodes can be unseparated or connected with each other.

According to the above process, TFTs with the gate insulating films each having different thickness and the LDD region can be made on a same substrate by using a conventional process without using a special process. Moreover, the first auxiliary electrodes and second auxiliary electrodes are provided at a vicinity of the channel forming region and the LDD region. Therefore, the carrier density in the crystalline semiconductor film under respective auxiliary electrodes can be adjusted finely by applying an optional voltage to the first auxiliary electrodes and second auxiliary electrodes. Thus, the hot carrier effect can be further restrained. Therefore, the TFT having a thin gate insulating film is used as the TFT for the function circuit, and the TFT having a thick gate insulating film is used as the TFT for the pixel area and the TFT for the driving circuit, thereby the operating characteristics and reliability of a semiconductor device can be improved and a low consumption design is enabled.

Embodiment Mode 3

An example of the invention is shown in FIGS. 3A 3D. In this embodiment, the second auxiliary electrodes are formed only in the TFT having the thin gate insulating film (in FIGS. 3A 3D, TFT in which the gate insulating film comprises G1) in the active matrix substrate described in the first embodiment.

As shown in FIG. 3A, a crystalline semiconductor film is formed on a substrate 301 through an insulating film 302 as a base film, and then the crystalline semiconductor film is etched in an optional pattern and thus separated crystalline semiconductor films 303 to 306 are formed. Then, a first gate insulating film (hereinafter, shown as G1 in the embodiment and FIGS. 3A 3D) 307 is deposited. The first gate insulating film (G1) 307 has a small thickness, and the thickness of the first gate insulating film is 1 to 100 nm, preferably 5 to 50 nm.

Next, a first conductive film is deposited, then masks (not shown) are formed using the photolithography technique, then an unnecessary area in the first conductive film is removed using a known etching method, and thus first gate electrodes 308, 309 and first auxiliary electrodes 310a, 310b, 311a, and 311b are formed in a desired pattern. The electrodes are formed as the gate electrodes (hereinafter, described as first gate electrodes in the embodiment) in a TFT having a thin gate insulating film, and formed as the auxiliary electrodes (hereinafter, described as first auxiliary electrodes in the embodiment) in a TFT having a thick gate insulating film. The first auxiliary electrodes in a TFT are preferably arranged with an optional interval. Typically, the electrodes are arranged with an interval approximately equal to the channel length (4 to 12 .mu.m, preferably 6 to 10 .mu.m).

Next, as shown in FIG. 3B, the second gate insulating film 320 (hereinafter, shown as G2 in the embodiment and FIGS. 3A 3D) is formed. The first gate insulating film (G1) and second gate insulating film (G2) are gate insulating films for the TFT having a thick gate insulating film (in FIG. 3, TFT in which the gate insulating film comprises G1 and G2), and thickness of the second gate insulating film (G2) is larger than that of the first gate insulating film, and preferably 5 to 100 nm. Next, a second conductive film 321 is formed, and then the second conductive film 321 is partially covered by a resist mask 322.

Next, an unnecessary area in the second conductive film is removed using a known etching method, and thus second auxiliary electrodes 331a, 331b, 332a, and 332b are formed in a desired pattern. In this case, by