Semiconductor device and manufacturing method therefor Number:7,417,253 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor device and manufacturing method therefor

Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

Patent Number: 7,417,253 Issued on 08/26/2008 to Yamazaki,   et al.

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Inventors:	Yamazaki; Shunpei (Tokyo, JP), Ohtani; Hisashi (Kanagawa, JP), Hamatani; Toshiji (Kanagawa, JP)
Assignee:	Semiconductor Energy Laboratory Co., Ltd. (Kanagawa-Ken, JP)
Appl. No.:	11/086,446
Filed:	March 23, 2005

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	10337886	Jan., 2003	6977394
	09924846	Aug., 2001	6784037
	09431131	Nov., 1999	6274887

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Foreign Application Priority Data

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Nov 02, 1998 [JP]			10-311633
Nov 10, 1998 [JP]			10-336561

Current U.S. Class:	257/72 ; 257/69
Current International Class:	H01L 21/00 (20060101)
Field of Search:	257/69-72

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Primary Examiner: Schillinger; Laura M
Attorney, Agent or Firm: Nixon Peabody LLP Costellia; Jeffrey L.

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Claims

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What is claimed is:

1. A light emitting device comprising: a substrate; a thin film transistor over the substrate; an interlayer insulating film over the thin film transistor; a first electrode over the interlayer insulating film, the first electrode electrically connected to the thin film transistor through a contact hole formed in the interlayer insulating film; and a light emitting layer disposed adjacent to a side edge of a bank, over the first electrode, wherein the first electrode has a depression on a surface thereof due to the contact hole, wherein the light emitting layer has a flattened upper surface over the depression, wherein a portion of the light emitting layer resides in the contact hole, over the first electrode, and wherein the light emitting layer does not extend to an upper surface of the bank.

2. The light emitting device according to claim 1, wherein the light emitting device is incorporated into an electronic equipment selected from the group consisting of a video camera, a digital camera, a projector, a television, a head mount display, a car navigation system, an image reproduction device, a portable telephone, a computer, a goggle type display, and an electronic game equipment.

3. The light emitting device according to claim 1, wherein an LDD region is formed in a semiconductor film of the thin film transistor.

4. The light emitting device according to claim 1, wherein an LDD region is formed in a semiconductor film of the thin film transistor, and wherein the LDD region is not overlapped with a gate electrode of the thin film transistor.

5. The light emitting device according to claim 1, wherein the light emitting layer includes a high molecular material.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having circuits structured with thin film transistors (hereinafter referred to as TFT). For example, the present invention relates to electro-optical devices, typically liquid crystal display panels, and to the structure of electronic equipments loaded with such electro-optical devices as parts. Note that throughout this specification semiconductor device generally indicates devices that acquire their function through the use of semiconductor characteristics, and electro-optical devices, semiconductor circuits, as well as electronic equipments are semiconductor devices.

2. Description of the Related Art

Active matrix type liquid crystal display devices composed of TFT circuits that use polysilicon films have been in the spotlight in recent years. They are the backbone for realizing high definition image displays, in which a plurality of pixels are arranged in a matrix state, and the electric fields that occur in the liquid crystals are controlled in that matrix state.

With this active matrix type liquid crystal display device, as the resolution becomes high definition such as XGA and SXGA, the number of pixels exceeds one million. The driver circuit that drives all of the pixels is extremely complex, and furthermore is formed from a large number of TFTs.

The required specifications for actual liquid crystal display device (also called liquid crystal panels) are strict, and in order for all of the pixels to operate normally, high reliability must be secured for both the pixels and the driver circuit. If an abnormality occurs in the driver circuit, especially, this invites a fault called a line defect in which one column (or one row) of pixels turns completely off.

However, TFTs which use polysilicon films are still not equal to the MOSFETs (transistors formed on top of a single crystal semiconductor substrate), used in LSIs etc., from a reliability point of view. As long as this shortcoming is not overcome, such a view that it is difficult to use TFTs when forming an LSI circuit gets stronger.

The applicant of the present application considers that a MOSFET has three advantages from a reliability standpoint, and infers the reason thereof as follows. A schematic diagram of a MOSFET is shown in FIG. 2A. The MOSFET contains a drain region 201 formed on a single crystal silicon substrate, and an LDD (lightly doped drain) region 202. In addition, there is a field insulating film 203, and a gate insulating film 205 directly under a gate wiring 204.

In that arrangement, the applicant considered that there are three advantages from a reliability standpoint. The first advantage is an impurity concentration gradient seen when looking at the drain region 201 from the LDD region 202. As shown in FIG. 2B, the impurity concentration gradually becomes higher from the LDD region 202 toward the drain region 201 for a conventional MOSFET. This gradient is considered effective in improving reliability.

Next, the second advantage is that the LDD region 202 and the gate wiring 204 overlap. Known examples of this structure include GOLD (gate-drain overlapped LDD), LATID (large-tilt-angle implanted drain), etc. It becomes possible to reduce the impurity concentration in the LDD region 202, the relaxation effect of the electric field becomes larger, and the hot carrier tolerance increases.

Next, the third advantage is that a certain level of distance exists in between the LDD region 202 and the gate wiring 204. This is due to the field insulating film 203 being formed by a shape in which it is slipped under the gate wiring. Namely, a state in which only the overlapped portion of the thick film gate insulating film becomes thick, so an effective relaxation of the electric field can be expected.

A conventional MOSFET compared with a TFT in this way has several advantages, and as a result, is considered to possess a high reliability.

In addition, attempts have been made in which these MOSFET advantages are applied to a TFT. For example, Hatano et al (M. Hatano, H. Akimoto, and T. Sakai, IEDM97 Technical Digest, p. 523-526) realized a GOLD structure that uses sidewalls formed by silicon.

However, compared with a normal LDD structure, the structure published in the paper has a problem in that the off current (the current that flows when the TFT is in the off state) gets large, and therefore a countermeasure is necessary.

As described above, the applicant of the present invention considers that, when the TFT and the MOSFET are compared, the problems associated with a TFT structure affect its reliability (especially its hot carrier tolerance).

SUMMARY OF THE INVENTION

The present invention is technology for overcoming this type of problem, and therefore has an object of the invention to realize a TFT that boasts the same or higher reliability than a MOSFET. In addition, another object of the invention is to realize a semiconductor device with high reliability which includes semiconductor circuits formed by circuits using this type of TFTs.

An active layer of the NTFT of the present invention is firstly characterized by including three impurity regions, other than a channel forming region, which have at least three different impurity concentrations. With this, an LDD structure can be obtained, in which the impurity concentration becomes gradually higher away from the channel forming region (in proportion to the distance from the channel forming region). Namely, it is possible to increase the TFT's reliability by a relieved electric field at the drain edge (vicinity of the border between the drain and the channel forming region).

An aim of the inventor of the present invention is to intentionally form a plurality of regions with the concentration gradient of the LDD section of an exemplary, conventional MOSFET. Therefore, there is no problem with the existence of three or more impurity regions.

Further, a second characteristic of the present invention resides in that it is formed into a state in which the gate wiring (including the gate electrodes) covers (overlaps) at least a part of the LDD region, through the gate insulating film. Deterioration due to a hot carrier can also be effectively suppressed with this type of structure

In addition, a third characteristic of the present invention is that, through the multiplier effect of the first characteristic and the second characteristic described above, the reliability of a TFT can be raised.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing showing a cross section of a CMOS circuit of the present invention;

FIGS. 2A and 2B are drawings showing the structure of a cross section of a conventional MOSFET;

FIGS. 3A to 3E are drawings showing the manufacturing step of a CMOS circuit of Embodiment 1;

FIGS. 4A to 4D are drawings showing the manufacturing step of the CMOS circuit of Embodiment 1;

FIGS. 5A and 5B are drawings showing the manufacturing step of a polysilicon film of Embodiment 1;

FIGS. 6A and 6B are drawings showing the manufacturing step of the polysilicon film of Embodiment 4;

FIGS. 7A and 7B are drawings showing the manufacturing step of the polysilicon film of Embodiment 5;

FIGS. 8A to 8D are drawings showing the manufacturing step of the CMOS circuit of Embodiment 7;

FIGS. 9A to 9D are drawings showing the manufacturing step of the CMOS circuit of Embodiment 8;

FIGS. 10A and 10B are drawings showing the manufacturing step of the CMOS circuit of Embodiment 9;

FIGS. 11A and 11B are drawings showing the manufacturing step of the CMOS circuit of Embodiment 11;

FIG. 12 is a drawing showing the external appearance of an electro-optical device of Embodiment 16;

FIGS. 13A to 13D are drawings showing electronic equipments of Embodiment 18;

FIG. 14 is a drawing of a CMOS circuit viewed from a top surface of the present invention;

FIGS. 15A to 15C are drawings showing the structure of a pixel matrix circuit of Embodiment 12;

FIG. 16 is a drawing showing the structure of the pixel matrix circuit of Embodiment 13;

FIG. 17 is a drawing showing the structure of the pixel matrix circuit of Embodiment 14;

FIG. 18 is a drawing showing the structure of the pixel matrix circuit of Embodiment 15;

FIGS. 19A to 19H are drawings for comparing several types of TFT structures of the present invention;

FIGS. 20A and 20B are drawings showing the energy bands for an NTFT (off-state) of the present invention;

FIGS. 21A to 21E are drawings showing the manufacturing step of the CMOS circuit of Embodiment 19;

FIGS. 22A and 22B are drawings showing the manufacturing step of the polysilicon film of Embodiment 8;

FIGS. 23A to 23D are drawings showing electronic equipments of Embodiment 18;

FIGS. 24A to 24D are drawings showing electronic equipments of Embodiment 18;

FIG. 25 is a drawing showing the outline of an EL display panel of Embodiment 20;

FIG. 26 is a drawing showing the cross section of the pixel portion in the EL display panel of Embodiment 20;

FIGS. 27A-27B are drawings showing the top view of the pixel portion in the EL display panel and the circuit structure for the pixel region, respectively of Embodiment 20;

FIG. 28 is a drawing showing the cross section of the pixel portion in an EL display panel of Embodiment 21;

FIGS. 29A-29C are drawings showing different circuit structures for pixel portions in EL display panels of Embodiment 22;

FIGS. 30A-30B is drawings showing the outline of an EL display panel of Embodiment 24;

FIGS. 31A-31B is drawings showing the outline of an EL display panel of Embodiment 25.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment mode of the present invention is explained with reference to FIG. 1. Note that a cross sectional view is shown in FIG. 1, and that a view looking from above is shown in FIG. 14. In FIG. 1, reference numeral 101 denotes a substrate having an insulating surface. It is possible to use, for example, a glass substrate with a prepared silicon oxide film, a quartz substrate, a stainless steel substrate, a metallic substrate, a ceramic substrate, or a silicon substrate.

A characteristic of the present invention resides in the structure of an active layer in an N-channel type TFT (hereafter referred to as NTFT). An NTFT active layer is formed by including a channel forming region 102, a pair of first impurity regions 103, a pair of second impurity regions pair 104, and a pair of third impurity regions 105. Note that the impurities doped into each of the impurity regions are elements belonging to the group 15 of the periodic table (typically phosphorous and arsenic).

The channel forming region 102 at this time is either an intrinsic semiconductor layer, or a semiconductor layer which has been doped with boron to a concentration of 1.times.10.sup.16 to 5.times.10.sup.18 atoms/cm.sup.3. Boron is an impurity used to control the threshold voltage and to prevent punch-through, but other elements can be substituted if the similar effects may be provided. The doping concentration in that case is similar to the level for boron.

Note that the semiconductor layers that can be used by the present invention include not only semiconductors with silicon as their main component, such as silicon, germanium, and silicon germanium. Chemical compound semiconductor layer such as gallium arsenide can also be used. In addition, the present invention is applicable to TFTs that use amorphous semiconductors (amorphous silicon etc.) as the active layer, as well as to TFTs that use semiconductors that include crystals (including single crystal semiconductor thin films, polycrystalline semiconductor thin films, microcrystalline thin films).

Further, each of the first impurity regions 103 on the NTFT has a length of between 0.1 to 1 .mu.m (typically between 0.1 to 0.5 .mu.m, preferably between 0.1 to 0.2 .mu.m), and includes a concentration of a periodic table group 15 element (phosphorous is typical) in the range of 1.times.10.sup.15 to 1.times.10.sup.17 atoms/cm.sup.3 (typically between 5.times.10.sup.15 to 5.times.10.sup.16, preferably between 1.times.10.sup.16 to 2.times.10.sup.16 atoms/cm.sup.3). Note that this impurity concentration is denoted as "n.sup.-" (the "n.sup.-" region refers to the first impurity regions 103 in this specification).

Also note that throughout this specification, unless otherwise particularly specified, "impurity" is used to specify either a periodic table group 13 element or group 15 element.

Each of the second impurity regions 104 has a length of between 0.5 to 2 .mu.m (typically between 1 to 1.5 .mu.m), and includes a concentration of a periodic table group 15 element in the range of 1.times.10.sup.16 to 1.times.10.sup.19 atoms/cm.sup.3 (typically between 1.times.10.sup.17 to 5.times.10.sup.18 atoms/cm.sup.3, preferably between 5.times.10.sup.17 to 1.times.10.sup.18 atoms/cm.sup.3). It is desirable to regulate the impurity concentration in the second impurity region 104 to between 5 to 10 times the impurity concentration of the first impurity regions 103. Note that this impurity concentration is denoted as "n" (the "n" region refers to the second impurity regions 104 in this specification).

Further, each of the third impurity regions 105 has a length of between 2 to 20 .mu.m (typically between 3 to 10 .mu.m), and includes a concentration of a periodic table group 15 element in the range of 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3 (typically between 1.times.10.sup.20 to 5.times.10.sup.20 atoms/cm.sup.3). Each of the third impurity regions 105 becomes a source region or a drain region which provides an electrical connection between the source wiring, or the drain wiring, and the TFT. Note that this impurity concentration is denoted as "n.sup.+" (the "n.sup.+" region refers to the second impurity regions 105 in this specification).

In addition, in the present invention, each of the third impurity regions 105 plays a very important role for gettering, from the inside of the channel forming region 102, the catalytic element used in crystallization of the channel forming region. The effect thereof will now be briefly explained.

In the present invention, a catalytic element for promoting the crystallization (typically nickel) can be used during crystallization of an amorphous semiconductor film. However, nickel is a metallic element, so it may be the cause of a leak current if any remains in the channel forming region. In other words, it is desirable to provide a process in which the catalytic element is at least removed from the channel forming region after the catalytic element has been used.

The present invention is characterized in that a periodic table group 15 element (preferably phosphorous) is used in the source region and the drain region in order to remove the catalytic element. Namely, by conducting a heat treatment after forming the source region and the drain region (the third impurity regions 105), the nickel that remains inside the channel forming region 102 is gettered (captured) into the third impurity regions 105. Thus, the catalytic element used for crystallization can be removed from inside the channel forming region 102.

Therefore, the gettered catalytic element collects in the third impurity regions 105, where it exists at high concentration. The present applicant investigated this by SIMS (secondary ion mass spectroscopy), and found that the concentration of the catalytic element to be between 1.times.10.sup.17 to 1.times.10.sup.20 atoms/cm.sup.3 (typically between 1.times.10.sup.18 to 5.times.10.sup.19 atoms/cm.sup.3). However, the third impurity regions 105 may only perform the function as an electrode, so that the existence of a large amount of the catalytic element will not generate any problems.

On the other hand, the concentration of the catalytic element in the channel forming region 102 is greatly reduced (or eliminated) by gettering action. The present inventor investigated by SIMS and found that the concentration of the catalytic element had been reduced to 2.times.10.sup.17 atoms/cm.sup.3or less (typically, between 1.times.10.sup.14 to 5.times.10.sup.16 atoms/cm.sup.3) in the channel forming region. (Strictly speaking, a pad was formed to have a composition identical to that of the channel forming region 102, and then measured by SIMS). Thus, a characteristic of the present invention resides in that there is a large difference in the catalytic element concentration depending upon their positions (a difference of 100 to 1,000 times) even within the same active layer.

The active layer of the NTFT according to the present invention, as described above, is characterized in that it includes at least three impurity regions that include the same impurity with different concentrations other than the channel forming region. With employing such a structure, an arrangement can be realized in which the impurity concentration (a periodic table group 15 element) gradually increases as the distance from the channel forming region 102 to each of the first impurity regions 103, the second impurity regions 104, and the third impurity regions 105 becomes long (in proportion to the distance from the channel forming region 102).

Further, since the object of the invention is to intentionally form a concentration gradient like that seen in the LDD section of the conventional MOSFET example, by using a plurality of impurity regions, there is no problem if more than three impurity regions exist.

A gate insulating film 106 is formed on the active layer thus formed. The gate insulating film 106 is formed so that it overlaps the second impurity regions 104 for the case in FIG. 1. This is a unique process structure when forming the second impurity regions 104, which becomes a characteristic when the present invention is embodied. The gate insulating film 106 is formed so as to be brought into contact with the channel forming region 102, the first impurity regions 103, and the second impurity regions 104.

A gate wiring 107 is further formed on the gate insulating film 106. As the material for the gate wiring 107, a single metallic layer, an alloy layer, or a laminate structure of these combination may be employed such as tantalum (Ta); tantalum nitrite (TaN); titanium (Ti); chromium (Cr); tungsten (W); molybdenum (Mo); silicon (Si); aluminum (Al); or Copper (Cu).

Typical examples of the laminate structure include the structures comprising: Ta/Al; Ta/Ti; Cu/W; and Al/W. In addition, metallic silicide structures (specifically, structures given conductivity with a combination of silicon and a metallic silicide such as Si/WSix, Si/TiSix, Si/CoSix, and Si/MoSix) may be employed.

However, when forming sidewalls made of silicon, it is preferred to place a material on the top surface thereof with a high selective etching ratio compared to silicon. This is used to prevent etching all the way to the gate wiring when forming the sidewalls. Otherwise, it is necessary to use a protective film on the top surface as a stopper for protection when forming the sidewalls.

Further, though it will be described later, a PTFT structure prepared with no sidewall for the CMOS circuit of the present invention is effective. Therefore, since a later step for removing only the sidewalls is included, it is necessary to choose a material for the gate wiring that is not etched during removal of the sidewalls. In the paper described as the conventional example, it has a structure with a silicon gate directly contacting silicon sidewalls, it is not possible to realize the CMOS circuit of the present invention by using that structure as it is.

Further, when performing a heat treatment for the gettering process described above, it is necessary to pay attention to the thermal resistance etc. of the gate wiring 107 (or a gate wiring 113). A restriction on the temperature of the heat treatment arises if a low melting point metal such as aluminum is included. In addition, tantalum oxidizes very easily, and it is necessary to provide a protective film of silicon nitride etc., so that the tantalum is not exposed to the environment of the heat treatment.

A silicon nitride film 108 shown in FIG. 1 is a protective film provided for that reason. It is effective to dope a fine amount of boron into the silicon nitride film 108, because this increases the thermal conductivity and can provide a radiating effect.

Sidewalls 109 are formed in the sidewalls (side portions) of the gate wiring 107. A layer with silicon as its main component is used as the sidewalls 109 for the present invention (specifically, a silicon layer or a silicon germanium layer). Especially, the use of intrinsic silicon, is desirable. Of course, an amorphous, crystalline, or microcrystalline structure may be used.

The present invention takes a structure in which the sidewalls 109 overlap on the first impurity regions 103 (the first impurity regions 103 and the sidewalls 109 overlap through the gate insulating film 106). With this structure, advantages similar to the GOLD structure or the LATID structure of a MOSFET can be obtained.

Further, in order to realize this type of structure, it is necessary to have a structure in which a voltage is applied to the first impurity regions 103 by the sidewalls 109. If the sidewalls 109 are formed of intrinsic silicon layer, the resistance is high but a leak current is generated, so that there is a benefit in that the sidewall portion does not form a capacitor. Namely, it is possible to prevent a dielectric storage capacity from being formed in the sidewalls when the gate voltage is turned off.

In addition, the active layer film thickness becomes thin for the case of a TFT, in the range of 20 to 50 nm, and during operation the depletion layer expands completely to the lower part of the active layer, and the TFT becomes a fully depression type (FD type). By making the FD type TFT into an overlapping gate type, an electric field is formed in the direction in which a hot carrier is difficult to generate. On the contrary, by using a general offset structure with an FD type TFT, there is the fear that an electric field will be formed in a direction that promotes hot carrier injection.

The NTFT of the present invention can achieve a high reliability that is equal to, or greater than, that of a MOSFET by using a structure like the one described above. Further, by applying a gate voltage to the first impurity regions 103 by using the sidewalls 109, it is possible to achieve an effect that is similar to that of an overlap structure.

Next, by arranging each of the first impurity regions 103, each of the second impurity regions 104, and each of the third impurity regions 105 in the stated order, a structure can be realized in which the impurity concentration gradually becomes higher from the channel forming region 102 toward the source region (or drain region). With employing this structure, it is possible to effectively control the TFT off current.

In addition, the second impurity region 104 is set some distance apart from the gate voltage, so that an electric field relaxation effect, similar to that of the overlap portion of the MOSFET shown in FIG. 2A, can be obtained. Further, the hot carrier that is generated by the first impurity regions 103 is injected straight up toward the sidewalls 109, so a trap state is not formed directly above the channel forming region 102.

The NTFT of the present invention is explained above, however a p-channel type TFT (hereinafter referred to as PTFT) is basically a structure in which an LDD region and an offset region are not provided. Of course, it may employs a structure in which an LDD region and an offset region are arranged, however PTFTs have always had high reliability, so that it is desirable to gain the on current and balance the characteristics with the NTFT. As shown in FIG. 1, this balance of characteristics is especially important for applying the present invention to a CMOS circuit. However, it may apply the structure of the present invention to a PTFT.

The active layer of a PTFT in FIG. 1 possesses a channel forming region 110 and a pair of fourth impurity regions 111, which become the source region (or the drain region). Note that the impurity concentration (an element from periodic table group 13, boron is typical) is denoted as "p.sup.++" (the fourth impurity regions 111 are referred to as "p.sup.++" throughout this specification).

The fourth impurity regions 111 invert to p-type due to the periodic table group 13 element, but if a periodic table group 15 element is doped to the same concentration as in the third impurity regions 105 at a previous step, a sufficient gettering effect will be shown.

Therefore, catalytic element used for crystallization also exist in the fourth impurity regions 111 at a concentration of 1.times.10.sup.17 to 1.times.10.sup.20 atoms/cm.sup.3 (typically, 1.times.10.sup.18 to 5.times.10.sup.19 atoms/cm.sup.3) for this case. Since the fourth impurity regions 111 may only perform the function as an electrode, there is no problem if the catalytic element is present in large amounts. Of course the catalytic element concentration in the channel forming region 110 is 1/100 to 1/1000 times that in the fourth impurity regions 111, so the concentration is 2.times.10.sup.17 atoms/cm.sup.3 or less (1.times.10.sup.14 to 5.times.10.sup.16 atoms/cm.sup.3 is typical).

In addition, a gate insulating film 112 is formed in a self-aligning manner using the gate wiring 113 as a mask. As the characteristics of the process of the present invention, there are enumerated such facts that the sidewalls 109 are present in the NTFT, and the sidewalls are removed and do not remain in the PTFT.

The NTFT and PTFT formed in this manner are then covered by the first insulating films 114 (which also may be referred to as first interlayer insulating films), and source wirings 115 and 116, and a drain wiring 117 are formed. After forming these wirings in the structure of FIG. 1, a silicon nitride layer 118 is formed as a protective film to thereby increase the passivation effect. A second insulating layer 119 is formed out of a resin material on the silicon nitride layer 118. It is not necessary to place restrictions to the use of a resin material, however using a resin material is effective in maintaining flatness. Note that for a case in which another film is formed on the second insulating film 119, it is acceptable to denote the second insulating film 119 by "second inter layer insulating film."

A CMOS circuit in which an NTFT and a PTFT are combined in a complimentary manner has been explained thus far, however it is possible to apply the present invention to an NMOS circuit using an NTFT and to a pixel TFT formed from NTFTs. Of course, it can also be applied to a complex semiconductor circuit in which a CMOS circuit is taken as a basic unit.

In addition, the most characteristic point of the present invention resides in that it is formed in several stages so that the impurity concentration in the LDD region of an NTFT increases as a distance from the channel forming region increases. Furthermore, the catalytic element (an element used during crystallization) inside the channel forming region is reduced to a level in which it does not hinder the electrical characteristics of the TFT.

Thus it is not necessary to place limits on the TFT structure provided that this structure is included, and the present invention can be applied to a top gate structure (a planer structure is typical) and to a bottom gate structure (an inverted stagger structure is typical).

(Advantages of the NTFT Structure of the Present Invention)

The advantages of the NTFT structure of the present invention are now discussed. The present invention's NTFT structure is characterized by a multiply-formed LDD region, from the first impurity regions 103 (the 1st LDD regions) and the second impurity regions 104 (the 2nd LDD regions), ones of which are overlapped by a gate electrode.

The superiority of the present invention will be explained by using a comparison with a conventional structure. FIGS. 19A and 19B show an NTFT with no LDD structure and its electrical characteristics (characteristic gate voltage Vg vs. drain current Id), respectively. The same is shown in FIGS. 19C and 19D for the case of a normal LDD structure, in FIGS. 19E and 19F for the so-called GOLD structure, and in FIGS. 19G and 19H for the NTFT of the present invention.

Note that throughout the figures, "n.sup.+" denotes the source region or the drain region, channel denotes the channel forming region, and "n.sup.-" denotes the LDD region ("n" denotes the second LDD region). Further, "Id" is the drain current, and "Vg" is the gate voltage.

The off current is high if there is no LDD structure, as shown in FIGS. 19A and 19B, and the on current (the drain current when the TFT is in an on state) and off current easily degrade.

Next, for the case with an LDD structure, the off current is considerably suppressed, and the degradation of the on current and the off current can be suppressed. However, the degradation of the on current cannot be completely suppressed.

Then, the structure in which the LDD region and the gate electrode overlap (FIGS. 19C and 19D) is a structure that places great importance on suppressing the degradation of the on current found in a conventional LDD structure.

While the on current degradation can be sufficiently suppressed for this case, it has the problem of the off current being somewhat higher than in a normal LDD. This structure is employed by Hatano et al. in their paper which is the conventional example, but the high off current problem is recognized for the present invention, and a structure to solve the problem is searched out.

For the structure of the present invention, as shown in FIGS. 19G and 19H, the inner LDD region (the side closer to the channel forming region) overlaps the gate electrode, while the outer LDD region is formed so as not to overlap the gate electrode. By employing this structure, it is possible to reduce the off current while maintaining the effect that suppresses the on current degradation.

To the question of why does the off current get large in the structure shown in FIGS. 19E and 19F, the present inventor surmises the following. This explanation is made using FIGS. 20A and 20B.

When the NTFT is in an off state, a negative voltage of several dozen volts is applied to a gate electrode 41. In this state, if a positive voltage of several dozen volts is placed on a drain region 42, a very large electric field is formed at the edge portion on the drain side of a gate insulating film 43.

At this time, holes 45 which are minority carriers are induced in an LDD region 44, as shown in FIG. 20A. An energy band diagram is shown in FIG. 20B for this time. Namely, the minority carriers form a current path that connects the drain region 42, the LDD region 44, and a channel forming region 46. This current path is considered to bring about an increase in the off current.

In order to interrupt this current path along the way, the present applicant considers that it is necessary to form a separate resistive member in the location where the gate electrode is not overlapped, in other words a second LDD region. The structure of the present invention hit upon in this way.

The structure of the present invention outlined above is explained in detail by the embodiments shown below.

Embodiment 1

In embodiment 1, the manufacturing method of the CMOS circuit shown in FIG. 1 is explained using FIGS. 3A to 3E, FIGS. 4A to 4D, and FIGS. 5A-5B.

First, a 200 nm silicon oxide film 302 that becomes a base film is formed on a glass substrate 301. It may laminate a silicon nitride film onto the base film, and may use only a silicon nitride film. Plasma CVD, thermal CVD, or sputtering may be used as a film deposition method. Of course, doping boron into the silicon nitride film is effective to increase the radiation effect.

Next, a 50 nm amorphous silicon film is formed by plasma CVD, thermal CVD, or sputtering, on the silicon oxide film 302. Crystallization of the amorphous silicon film is carried out afterward by using the technique disclosed in Japanese Patent Application Laid-open No. Hei 7-130652, forming a semiconductor film containing crystals. This process is explained using FIGS. 5A and 5B.

First, a silicon oxide film 502 is formed as a base film on a glass substrate 501, and an amorphous silicon film 503 is formed thereon. Film deposition of the silicon oxide film 502 and the amorphous silicon film 503 is performed successively by sputtering in embodiment 1. Next, a 10 ppm nickel by weight of nickel acetate salt solution is applied, forming a nickel containing layer 504. (See FIG. 5A.)

Note that it is acceptable to use any of the following elements, either singly or in combination, instead of nickel (Ni): germanium