Semiconductor device with a selection gate and a peripheral gate Number:7,417,281 from the United States Patent and Trademark Office (PTO) owispatent A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.<H Semiconductor, peripheral, Semiconductor, d, 7417281.html, Patent, pto, 7417281

Title: Semiconductor device with a selection gate and a peripheral gate

Abstract: A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

Patent Number: 7,417,281 Issued on 08/26/2008 to Sugimae, et al.

Inventors: Sugimae; Kikuko (Yokohama, JP), Kutsukake; Hiroyuki (Yokohama, JP), Ichige; Masayuki (Yokohama, JP), Matsui; Michiharu (Fujisawa, JP), Takeuchi; Yuji (Yokohama, JP), Shirota; Riichiro (Fujisawa, JP)
Assignee: Kabushiki Kaisha Toshiba (Tokyo, JP)

Appl. No.: 11/733,488

Filed: April 10, 2007

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10881180	Jul., 2004
10326179	May., 2005	6894341

Foreign Application Priority Data


Dec 25, 2001 [JP]			2001-390993
Mar 15, 2002 [JP]			2002-072460

Current U.S. Class: 257/316 ; 257/E21.69; 438/211; 438/258

Current International Class: H01L 29/94 (20060101)

Field of Search: 257/316,314,E21.69 438/211,258

References Cited [Referenced By]

U.S. Patent Documents


RE35838	July 1998	Momodomi et al.
6067249	May 2000	Lee et al.
6153476	November 2000	Inaba et al.
6215144	April 2001	Saito et al.
6420754	July 2002	Takahashi et al.
6475883	November 2002	Powell et al.
6720612	April 2004	Takeuchi et al.
6849490	February 2005	Hayashi
6894341	May 2005	Sugimae et al.
2002/0036317	March 2002	Matsui et al.
2002/0182798	December 2002	Saito et al.
2003/0003661	January 2003	Lee

Foreign Patent Documents


8-148586	Jun., 1996	JP
2000-21998	Jan., 2000	JP
2000-114361	Apr., 2000	JP
2000-311992	Nov., 2000	JP
2002-280463	Sep., 2002	JP
2001-0014829	Feb., 2001	KR

Primary Examiner: Weiss; Howard
Assistant Examiner: Ingham; John C
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 10/881,180, filed Jul. 1, 2004, which is a divisional of U.S. application Ser. No. 10/326,179, filed Dec. 23, 2002, now U.S. Pat. No. 6,894,341, issued May 17, 2005. This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-390993, filed Dec. 25, 2001; and No. 2002-072460, filed Mar. 15, 2002. The entire contents of each of these documents are incorporated herein by reference.

Claims

What is claimed is:

1. A semiconductor device comprising: a semiconductor substrate; a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate; a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other; a second diffusion region formed adjacent to and apart from an end of the plurality of first diffusion regions formed substantially in line on the semiconductor substrate; a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions and the second diffusion region; a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode; a first insulation film free from nitrogen, filled between adjacent ones of the plurality of memory cell gate electrodes and between an end of the plurality of memory cell gate electrodes and the selection gate electrode, and formed on a side surface of the peripheral gate electrode; and a second insulation film including nitrogen, formed on the side surface of the peripheral gate electrode via the first insulation film and on regions other than between the adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes and the selection gate electrode, and formed on a side surface of the selection gate electrode, which is in contact with the second diffusion region, without interposing the first insulation film.

2. The semiconductor device according to claim 1, further comprising: an interlayer insulation film formed over the plurality of memory cell gate electrodes, the selection gate electrode, the peripheral gate electrode, the first insulation film, and the second insulation film, and formed of a material different from that of the second insulation film; and a contact electrode formed through the interlayer insulation film along the selection gate electrode, connected to the second diffusion layer, and disposed adjacent to the selection gate electrode via the second insulation film.

3. The semiconductor device according to claim 1, wherein hydrogen concentration in the first insulation film is smaller than that in the second insulation film.

4. The semiconductor device according to claim 1, wherein density of traps with respect to charges existing in the first insulation film is smaller than that in the second insulation film.

5. The semiconductor device according to claim 1, wherein the first insulation film is formed of silicon oxide.

6. The semiconductor device according to claim 1, wherein the second insulation film is formed of silicon nitride.

7. The semiconductor device according to claim 1, wherein the first insulation film is formed of silicon oxide and the second insulation film is formed of silicon nitride.

8. A semiconductor device, comprising: a semiconductor substrate; a first and a second memory cell array disposed on the semiconductor substrate, each of the first and the second memory cell array comprising: a plurality of memory cell transistors each having a memory cell gate and source/drain diffusion regions, the memory cell transistors being disposed adjacent to one another sharing one of the source/drain diffusion regions and being connected in series; and selection transistors formed on the semiconductor substrate at opposite ends of the plurality of memory cell transistors connected in series, sharing one of the source/drain diffusion regions with the memory cell transistors of the opposite ends, and each having a first diffusion region disposed on the semiconductor substrate as the other of the source/drain diffusion regions, one of the selection transistors of the first memory cell array being disposed adjacent to one of the selection transistors of the second memory cell array to share the first diffusion region; a peripheral circuit portion disposed apart from the first and the second memory cell array and having a peripheral transistor formed on the semiconductor substrate, the peripheral transistor including a peripheral gate electrode; a first insulation film free from nitrogen, filled between adjacent ones of the plurality of memory cell transistors, formed at a thickness on a side surface of the peripheral gate electrode so as to set a thickness between the memory cell gates to be larger than the thickness on the side surface of the peripheral electrode, and formed at a substantially zero thickness on a surface of the semiconductor substrate on opposite sides of the peripheral gate electrode; and a second insulation film including nitrogen, formed on the side surface of the peripheral gate electrode via the first insulation film, formed on regions other than between adjacent ones of the plurality of memory cell transistors and on the gate electrode of each of the plurality of memory cell transistors via the first insulation film, and formed on a side surface of the selection gate electrode, which is in contact with the second diffusion region, without interposing the first insulation film.

9. The semiconductor device according to claim 8, further comprising: an interlayer insulation film formed so as to cover the first and the second memory cell arrays and the peripheral circuit, a main component of the interlayer insulation film being different from that of the second insulation film; and a contact electrode connected to the first diffusion layer through the interlayer insulation film and disposed adjacent to the selection transistor via the second insulation film.

10. The semiconductor device according to claim 8, wherein hydrogen concentration in the first insulation film is smaller than that in the second insulation film.

11. The semiconductor device according to claim 8, wherein density of traps with respect to charges existing in the first insulation film is smaller than that in the second insulation film.

12. The semiconductor device according to claim 8, wherein the first insulation film is formed of silicon oxide.

13. The semiconductor device according to claim 8, wherein the second insulation film is formed of silicon nitride.

14. A semiconductor device comprising: a semiconductor substrate; a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate; a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other; a second diffusion region formed adjacent to and apart from an end of the plurality of first diffusion regions formed in line on the semiconductor substrate; a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions formed in line and the second diffusion region; a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode; a pair of third diffusion regions formed on the semiconductor substrate such that the peripheral gate electrode is formed between the third diffusion regions; a first insulation film free from nitrogen, filled between adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes formed in line and the selection gate electrode, formed on a side surface of the peripheral gate electrode, and a thickness of the first insulating film between the memory cell gate electrodes being larger than thickness of the first insulation film formed on an upper half side surface of the peripheral gate electrode; and a second insulation film including nitrogen, formed on the side surface of the peripheral electrode via the first insulation film, formed on regions other than between the adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes and the selection gate electrode, and formed on a side surface of the selection gate electrode, which is in contact with the second diffusion region, without interposing the first insulation film.

15. The semiconductor device according to claim 14, wherein the first insulation film includes silicon oxide, and the second insulation film includes silicon nitride.

16. The semiconductor device according to claim 14, further comprising: a third insulation film formed on top portions of the memory cell gate electrodes and the peripheral gate electrode; and a fourth insulation film formed such that the first insulation film between the plurality of memory cell gate electrodes is covered with the fourth insulation film, the first insulation film including silicon oxide, the third and fourth insulation films including silicon nitride, the plurality of memory cell gate electrodes being covered with the third and the fourth insulation films as a whole.

17. The semiconductor device according to claim 14, wherein the pair of third diffusion regions include a portion formed just under the side surface of the peripheral electrode.

18. A semiconductor device having a plurality of memory cells comprising: a semiconductor substrate; a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate; a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other; a second diffusion region formed adjacent to and apart from an end of the plurality of first diffusion regions formed substantially in line on the semiconductor substrate; a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions and the second diffusion region; a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode; a first insulation film free from nitrogen, filled between adjacent ones of the plurality of memory cell gate electrodes and between an end of the plurality of memory cell gate electrodes and the selection gate electrode, and formed on a side surface of the peripheral gate electrode, wherein the first insulation film filled between adjacent ones of the plurality of memory cell gate electrodes has a void; and a second insulation film including nitrogen and formed on the side surface of the peripheral gate electrode via the first insulation film and on regions other than between the adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes and the selection gate electrode.

19. The semiconductor device according to claim 18, wherein the plurality of memory cells comprises a NAND structure.

20. The semiconductor device according to claim 18, wherein density of traps with respect to charges existing in the first insulation film is smaller than that in the second insulation film.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device which includes a memory cell portion including a memory cell gate and selection gate and a peripheral circuit portion including a peripheral gate, and a manufacturing method of the semiconductor device.

2. Description of the Related Art

An electrically erasable programmable read-only memory (EEPROM) which electrically writes/erases data has heretofore been known as a semiconductor memory. In the EEPROM, memory cells are arranged in intersections of rows and columns intersecting with one another to constitute a memory cell array. In the memory cell, a MOS transistor including a stacked gate structure is used in which floating and control gates are stacked.

In the EEPROM, at a data write/erase operation time, an operation is performed which comprises: applying a strong electric field between the control gate and a channel; passing a tunnel current through a gate insulation film; and implanting or removing charges with respect to the floating gate. In this operation, when a tunnel current flows in the vicinity of the gate insulation film, an electric stress is applied to the gate insulation film.

Moreover, it is generally known that there are a large number of traps with respect to the charges in a silicon nitride film. Particularly when the charges are captured in the traps in the silicon nitride film covering the surface of a source/drain diffusion layer, the diffusion layer in the vicinity of the surface of a substrate is depleted. As a result, a parasitic resistance of the source/drain increases, and drop of on-current of the transistor is caused.

Moreover, when the charges are trapped in the silicon nitride film in the vicinity of the gate insulation film, deterioration of electric characteristics occurs such as fluctuation of a threshold voltage of the transistor, and drop of withstanding voltage of a silicon oxide film. That is, when a material having high dielectric constant exists between the gates of the memory cell transistors disposed at a small interval, electrons are trapped. This raises a problem that the value of even a transistor disposed adjacent to the transistor with voltage applied thereto rises.

Particularly in a NAND flash memory, a large number of, such as 16 or 32, memory cell transistors are connected in series and are arranged close to one another. Therefore, when miniaturization advances, a voltage change of a specific memory cell transistor exerts an influence onto another memory cell transistor disposed adjacent to the specific transistor, and there is possibility of an erroneous operation or a problem in reliability.

When there is a film containing a large hydrogen content in the vicinity of the gate insulation film, hydrogen is taken into the silicon oxide film and structure defects such as Si--H coupling are easily generated in an interface with a silicon substrate.

More specifically, a portion of SiO.sub.2 bonds is replaced with H, thereby making free bonds which serve as trap centers.

When the above-mentioned Si--H coupling is cut by an electric stress, and the like, a cut portion functions as a trap with respect to the charge. Particularly when this trap is generated in the silicon oxide film as the gate insulation film, or a post oxide film in the vicinity of the gate insulation film, the deterioration of the electric characteristics such as fluctuation of the threshold voltage of the transistor and drop of the silicon oxide film withstanding voltage are caused.

Moreover, the charges are captured in the traps of the post oxide film with which the surface of the source/drain diffusion layer is covered. Then, the diffusion layer in the vicinity of the substrate surface is depleted. As a result, the parasitic resistance of the source/drain increases, and drop of the on current of the transistor is sometimes caused.

This problem becomes particularly remarkable, when a gate length is smaller than about 0.2 .mu.m. That is, when the silicon oxide film, post oxide film, or silicon nitride film in which the traps are generated in the vicinity of the gate insulation film occupy a large ratio in the whole gate, this problem becomes remarkable.

The silicon nitride film is necessary for selective etching in forming a contact hole. On the other hand, since adverse influence of the silicon nitride film is seen with respect to the electric characteristics, it is difficult to enhance both yield and reliability of the semiconductor device.

To solve the problem, in Jap. Pat. Appln. KOKAI No. 2002-280463 as a prior application, when a contact hole is formed after gate processing, under a second insulation film (silicon nitride film) as an etching stopper, another first insulation film is disposed. This first insulation film is disposed to fill between gate electrodes of the memory cell transistor. Thereby, the influence of hydrogen in the second insulation film or charges captured in the second insulation film onto the electric characteristics of a device can be reduced.

Particularly in a memory cell portion, the first insulation film fills between the gate electrodes, and the second insulation film does not exist in the vicinity of the gate insulation film of the transistor. Therefore, the characteristics of the memory cell transistor can be prevented from being deteriorated, and reliability enhancement of the device results. That is, when the silicon oxide film is disposed between the gates of the memory cell transistor, the charges can be prevented from being trapped in the film having high dielectric constant between the gates.

However, in this structure, the first and second insulation films are also formed simultaneously with respect to a peripheral transistor. For the peripheral transistor, different from the memory cell, it is necessary to form an LDD structure as a hot electron countermeasure, or suppress a short channel effect by diffusion of impurities. To satisfy the above-described demand, it is a problem that the insulation film which is thick enough to fill between the memory cell transistors are also formed in the peripheral transistor. That is, when a gate sidewall insulation film is thick, the source/drain diffusion layer is offset from the gate, and the characteristics deterioration of the peripheral transistor are brought.

Therefore, there has been a demand for realization of a structure of a semiconductor device and manufacturing method of the device in which a peripheral transistor can efficiently be formed simultaneously with a high-reliability memory cell, and high reliability and high yield can be achieved.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a semiconductor device comprising:

a semiconductor substrate;

a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate;

a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other;

a second diffusion region formed adjacent to and apart from an end of the plurality of first diffusion regions formed substantially in line on the semiconductor substrate;

a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions and the second diffusion region;

a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode;

a first insulation film filled between adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes and the selection gate electrode, formed at a substantially uniform thickness on a side surface of the peripheral gate electrode, and including a main component other than nitrogen; and

a second insulation film formed on at least the side surface of the peripheral gate electrode via the first insulation film and formed of a material different from that of the first insulation film.

According to a second aspect of the present invention, there is provided a semiconductor device, comprising:

a semiconductor substrate;

a first and a second memory cell array disposed on the semiconductor substrate, each of the first and the second memory cell array comprising: a plurality of memory cell transistors each having a memory cell gate and source/drain diffusion regions, the memory cell transistors being disposed adjacent to one another sharing one of the source/drain diffusion regions and being connected in series; and selection transistors formed on the semiconductor substrate at opposite ends of the plurality of memory cell transistors connected in series, sharing one of the source/drain diffusion regions with the memory cell transistors of the opposite ends, and having a first diffusion region disposed on the semiconductor substrate as the other of the source/drain diffusion regions, one of the selection transistors of the first memory cell array being disposed adjacent to one of the selection transistors of the second memory cell array to share the first diffusion region;

a peripheral circuit portion disposed apart from the first and the second memory cell array and having a peripheral transistor formed on the semiconductor substrate, the peripheral transistor including a peripheral gate electrode;

a first insulation film filled between adjacent ones of the plurality of memory cell transistors, formed at a substantially uniform thickness on a side surface of the peripheral gate electrode so as to set a thickness between the memory cell gates to be larger than the substantially uniform thickness on the side surface of the peripheral electrode, formed at a substantially zero thickness on a surface of the semiconductor substrate on opposite sides of the peripheral gate electrode, and including a main component other than nitrogen; and

a second insulation film formed on at least the side surface of the peripheral gate electrode via the first insulation film.

According a third aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising:

forming a first gate electrode layer, a first insulation film, and a second gate electrode layer on a semiconductor substrate in this order;

by processing the second gate electrode layer, the first insulation film, and the first gate electrode layer by lithography, forming a plurality of memory cell gate electrodes in a memory cell portion, while simultaneously forming a peripheral gate electrode in a peripheral circuit portion;

by using the plurality of memory cell gate electrodes and the peripheral gate electrode as masks, forming a plurality of diffusion regions on the semiconductor substrate; and

forming a second insulation film so as to fill between adjacent ones of the plurality of memory cell gate electrodes and cover the memory cell gate electrodes of the memory cell portion entirely and continuously, while simultaneously forming the second insulation film along a side surface of the peripheral gate electrode of the peripheral circuit portion and along the semiconductor substrate adjacent to an underpart of the peripheral gate electrode, and

removing the second insulating film formed on the semiconductor substrate adjacent to the underpart of the peripheral gate electrode.

According a fourth aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising:

forming a first memory cell gate array including a plurality of memory cell gate electrodes, a first selection gate pair formed on opposite ends of the first memory cell gate array, a second memory cell gate array including a plurality of memory cell gate electrodes, and a second selection gate pair formed on opposite ends of the second memory cell gate array such that one gate of the second selection gate pair is disposed adjacent to one gate of the first selection gate pair, while forming a plurality of peripheral gates apart from the first memory cell gate array, the first selection gate pair, the second memory cell gate array, and the second selection gate pair on a semiconductor substrate;

by using the first memory cell gate array, the first selection gate pair, the second memory cell gate array, the second selection gate pair, and the plurality of peripheral gates as masks, forming a plurality of diffusion regions in the semiconductor substrate;

forming a first insulation film including a main component other than nitrogen over a whole surface of the semiconductor substrate, so as to fill between adjacent ones of the plurality of memory cell gate electrodes, between the opposite ends of the first memory cell gate array and the first selection gate pair, and between the opposite ends of the second memory cell gate array and the second selection gate pair, and to form the first insulation film on a side surface of one gate of the first selection gate pair disposed adjacent to and opposite to that of one gate of the second selection gate pair, a first region of the semiconductor substrate between the opposite selection gates, side surfaces of the plurality of peripheral gates, and a second region of the semiconductor substrate disposed adjacent to the side surfaces of the peripheral gays;

removing the first insulation film on the first and the second region;

forming a second insulation film including nitrogen as the main component over a whole exposed surface;

forming an interlayer insulation film having a large etching selectivity to the second insulation film on the second insulation film;

etching the interlayer insulation film on the first region to form a contact hole; and

filling a conductive material in the contact hole to connect the conductive material to one of the plurality of diffusion regions formed in the first region.

According to a fifth aspect of the present invention, there is provided a semiconductor device, comprising;

a semiconductor substrate;

a plurality of first diffusion regions arranged apart from one another substantially in line on the semiconductor substrate;

a plurality of memory cell gate electrodes insulatively formed on the semiconductor substrate between the first diffusion regions disposed adjacent to each other;

a second diffusion region formed adjacent to and apart an end of the plurality of first diffusion regions formed in line on the semiconductor substrate;

a selection gate electrode insulatively formed on the semiconductor substrate between the end of the first diffusion regions formed in line and the second diffusion region;

a peripheral gate electrode insulatively formed on the semiconductor substrate apart from the plurality of memory cell gate electrodes and the selection gate electrode;

a pair of third diffusion regions formed on the semiconductor substrate such that the peripheral gate electrode is formed between the third diffusion regions;

a first insulation film filled between adjacent ones of the plurality of memory cell gate electrodes and between the end of the plurality of memory cell gate electrodes formed in line and the selection gate electrode, formed on a side surface of the peripheral gate electrode, including a main component other than nitrogen, and a thickness of the first insulating film between the memory cell gate electrodes being larger than thickness of the first insulation film formed on an upper half side surface of the peripheral gate electrode; and

a second insulation film formed on at least the side surface of the peripheral electrode via the first insulation film and formed of a material different from that of the first insulation film.

According a sixth aspect of the present invention, there is provided a manufacturing method of the present invention, comprising:

forming a first gate electrode layer, a first insulation film, and a second gate electrode layer on a semiconductor substrate in this order;

by processing the second gate electrode layer, the first insulation film, and the first gate electrode layer by lithography, forming a plurality of memory cell gate electrodes in a memory cell portion, while simultaneously forming a peripheral gate electrode in a peripheral circuit portion;

by using the plurality of memory cell gate electrodes as masks, forming a plurality of first diffusion regions on the semiconductor substrate;

forming a second insulation film so as to line the exposed surfaces of the plurality of memory cell gate electrodes of the memory cell portion, the semiconductor substrate exposed between the plurality of memory cell gate electrodes, the exposed surface of the peripheral gate electrode of the peripheral circuit portion, and the semiconductor substrate adjacent to an underpart of the peripheral gate electrode;

removing a portion of the second insulation film which covers the peripheral gate electrode;

forming a third insulation film so as to fill between the plurality of memory gate electrodes via the second insulation film and to simultaneously line the peripheral gate electrode; and

by using the peripheral gate electrode as a mask, forming a pair of second diffusion regions on the semiconductor substrate.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a plan view showing a layout of a memory cell portion of a conventional NAND type EEPROM;

FIG. 2 is a sectional view of a prior-art NAND type EEPROM, corresponding to a section taken along line II-II of FIG. 1;

FIG. 3 is a sectional view taken along line III-III of FIG. 1;

FIG. 4 is a sectional view along a bit line of a semiconductor device according to a first embodiment of the present invention;

FIG. 5 is a sectional view of a modification of the semiconductor device according to the first embodiment;

FIG. 6 is a sectional view showing a void in an insulation film allowable in the first embodiment;

FIG. 7 is a sectional view showing one step of a manufacturing method of the semiconductor device according to the first embodiment;

FIG. 8A is a sectional view showing a step next to that of FIG. 7;

FIG. 8B shows a modification example of processing the first insulation film 18;

FIGS. 9 to 12 are sectional views showing a step following that of FIG. 8A in a stepwise manner;

FIG. 13 is a sectional view along a bit line of the semiconductor device according to a second embodiment;

FIGS. 14 to 17 are sectional views showing the manufacturing method of the semiconductor device according to the second embodiment in the stepwise manner;

FIG. 18 is a sectional view along the bit line of the semiconductor device according to a third embodiment;

FIGS. 19 to 21 are sectional views showing the manufacturing method of the semiconductor device according to a third embodiment in the stepwise manner;

FIG. 22 is a sectional view showing a gate offset of the prior-art NAND type EEPROM;

FIG. 23A is a sectional view along the bit line showing steps including gate electrode formation of the semiconductor device according to a fourth embodiment;

FIG. 23B is a sectional view along a word line of the semiconductor device of the fourth embodiment;

FIGS. 24 to 30 are sectional views showing the step following FIG. 23A in the stepwise manner;

FIGS. 31 to 33 are sectional views showing the manufacturing steps of the semiconductor device according to a fifth embodiment in the stepwise manner; and

FIGS. 34 to 38 are sectional views showing the manufacturing steps of the semiconductor device according to a sixth embodiment in the stepwise manner.

DETAILED DESCRIPTION OF THE INVENTION

Prior to description of embodiments of the present invention, a configuration and problem of EEPROM will generally be described.

For the EEPROM, a NAND type EEPROM shown in FIGS. 1 to 3 is known as a system suitable for a large-capacity memory. In a memory cell array of the EEPROM, a plurality of memory cell transistors are connected in series, one end is connected to a drain-side selection gate transistor 53, and the other end is connected to a source-side selection gate transistor 54. A well 51 is disposed on a portion of a semiconductor substrate 50, and a striped element region 55 is formed in the well. Each element region 55 is separated by an element isolation region 56. On the striped element region 55, a plurality of cell transistors including a stacked gate structure are arranged in columns, and cell transistors are arranged in a matrix form as the whole memory cell region. A peripheral circuit portion (not shown in FIG. 1) is disposed outside the memory cell region, and a peripheral gate 72 is disposed in the region (FIG. 2).

Each memory cell includes a gate electrode portion 52 disposed on a gate insulation film 57 on the element region 55, and the gate electrode portion 52 is formed by stacking a floating gate electrode 58 as a charge accumulation layer, inter-gate insulation film 59, control gate electrode 60, and gate mask material 70. Furthermore, the control gate electrode 60 is connected to other gate electrodes in a row line direction, and forms a word line 61.

The memory cell transistors are connected in series with each other via diffusion layer regions 62 disposed on the element region. A plurality of memory cells are connected in series to form one NAND cell (memory cell unit).

Opposite ends of the NAND cell in each bit line direction are connected to the drain-side selection gate transistor 53 and source-side selection gate transistor 54. Each of the selection gate transistors includes a gate electrode disposed on the gate insulation film 57, and is coupled to the NAND cell via the diffusion layer region 62.

Moreover, the stacked gate structure of the selection gate transistor is similar to that of the memory cell transistor, but the transistor includes an electrode structure in which a floating gate electrode and a control gate electrode are connected, and functions similarly to a conventional MOSFET.

Moreover, a bit line contact diffusion layer 62' is disposed in the element region 55 on a side of the drain-side selection gate transistor opposite to the NAND cell. This bit line contact diffusion layer 62' is connected to a bit line contact 63. This bit line contact 63 is connected to a bit line 64.

A post oxide film 65 is formed on the surfaces of the respective gates 52, 53 and 54. A silicon nitride film 67 is formed on the surface of the post oxide film 65, diffusion layer 62, drain contact diffusion layer 62, and source diffusion layer 66 on the side of the source-side selection gate transistor 54 opposite to the memory cell. An interlayer insulation film 68 is formed on the surface of the silicon nitride film 67.

Here, the bit line contact 63 is formed through the gate insulation film 57, silicon nitride film 67, and interlayer insulation film 68, and the bit line 64 is formed on the interlayer insulation film 68. The bit line is disposed so as to be separated between the NAND cells disposed adjacent to each other in a column direction.

Moreover, the source diffusion layer 66 formed on the side of the source-side selection gate transistor opposite to the NAND cell is connected to a source line. The source line is in a layer above that of the gate electrode, and connects the NAND cells disposed adjacent to each other in the column direction.

The peripheral gate 72 can supply a gate potential to the floating gate electrode 54, and similarly functions as the conventional MOSFET, and the stacked gate structure is similar to that of the memory cell gate 52. A source/drain regions 73 are disposed in the well 51 on both sides of the peripheral gate.

Moreover, as shown in FIG. 3, a plurality of element isolation regions 56 are formed so as to divide the upper surface of the element region 55 disposed in the well 51 on the semiconductor substrate 50. The bit line contact 63 is connected to the whole surface of the element region 55 held between the element isolation regions 56. The silicon nitride film 67 is formed on the element isolation region 56, and the interlayer insulation film 68 is formed on the nitride film. The bit line contact 63 is formed through these interlayer insulation film 68 and silicon nitride film 67. The bit line wiring 64 is formed on the bit line contact 63.

As described above, in the prior-art semiconductor device, the silicon nitride film 67 with which the whole surface of the gate electrode is covered is formed. A reason why the silicon nitride film 67 is necessary will be described hereinafter.

As shown in FIGS. 1 to 3, the bit line contact 63 is designed so as to have substantially no allowance with respect to the width of the element region 55. That is, the bit line contact 63 is disposed over the full width of the element region 55. It is to be noted that the width of the bit line contact 63 is sometimes larger than that of the element region 55. Thereby, the area of the cell array can be reduced as much as possible.

In this semiconductor device, even when a contact is formed in a position over the element isolation region because of misalignment of a mask, the bit line contact has to be passed through the device separation region. When the bit line contact is passed through the device separation region, the corresponding portion causes junction leak current or causes drop of device separation withstanding voltage.

To prevent this phenomenon, as described above, the silicon nitride film 67 is used in the prior-art semiconductor device. This is used to impart selectivity between the silicon oxide film and silicon nitride film in etching at a contact opening process in the miniaturized semiconductor device. Thereby, even when positioning deviation occurs, the etching can once stop on the silicon nitride film 67.

After opening the contact hole reaching the silicon nitride film 67, by a method of changing etching conditions to etch the silicon nitride film 67 and further changing the conditions to etch the silicon oxide film on the substrate, a contact hole 71 in the source/drain diffusion layer is completely opened.

When the bit line contact hole 71 is opened in this manner, the element isolation region 56 can be prevented from being largely etched, and the contact hole 71 is prevented from passing through the element isolation region 56.

However, when the silicon nitride film exists in the vicinity of the memory cell region as described above, the traps in the silicon nitride film causes problems such as characteristics deterioration of the transistor and withstanding voltage drop of the silicon oxide film.

The present invention has been developed in consideration of the problem, and the embodiments of the present invention will be described hereinafter with reference to the drawings.

FIRST EMBODIMENT

FIG. 4 is a partial sectional view along the bit line of the semiconductor device (NAND flash memory) according to a first embodiment of the present invention. A part of a memory cell portion 30 and a part of a peripheral circuit portion 31 are shown. A bit line contact 15 is formed substantially in a middle of the memory cell portion 30, and is connected to a bit line 22.

It is to be noted that the basic arrangement of the transistor in the memory cell region and the peripheral circuit are the same as those of the conventional NAND flash memory shown in FIGS. 1 and 3, and therefore these drawings will also be referred to. The basic configuration of the section along the bit line is similar to the prior-art structure of FIG. 2, but the present embodiment is characterized by the configuration of the insulation film with which the transistor is covered.

In FIG. 4, memory cell units are arranged in left and right directions of the bit line contact 15. In the left direction, a selection gate 3 and three associated memory cell gates 2 are shown. As not shown, the end of the predetermined number of memory cell gates connected in series is connected to another selection gate (3).

Similar memory cell units are formed also in the right direction of the bit line contact 15. However, FIG. 4 shows only one selection gate 3 connected to the bit line 15 and one memory cell gate 2 disposed adjacent to the selection gate 3. The structure of another selection gate (not shown) is the same as that shown in the middle of FIG. 4, and differs in that the selection gate is connected to the source line instead of the bit line.

A peripheral gate 4 of the peripheral circuit portion 31 is formed apart from the selection gate 3 on a semiconductor substrate 1.

Each memory cell gate 2 includes a stacked structure disposed on a gate insulation film 5 on the semiconductor substrate 1. In an upward direction on the gate insulation film 5, the stacked structure includes a floating gate electrode 6 as a charge accumulation layer, inter-gate insulation film 7, control gate electrode 10 including a polycrystal silicon layer 8 and WSi layer 9, and gate mask material 11 including an SiN layer.

A source/drain region 12 of each memory cell is disposed in the semiconductor substrate 1 on the both sides of the memory cell gate 2. In the same memory cell unit, the memory cell transistors disposed adjacent to each other share one source/drain region 12, and thereby a plurality of memory cell transistors are connected in series. That is, the plurality of memory cells are connected in series to form the NAND cell (memory cell unit) as one memory cell array.

Moreover, the gate insulation film 5 is the silicon oxide film or oxynitride film, and the inter-gate insulation film 7 is an oxide-nitride-oxide (ONO) film in which the silicon nitride film is held between the silicon oxide films.

Furthermore, in the end of the memory cell array, the selection gate 3 is formed on the gate insulation film 5. The selection gate 3 includes the stacked structure similar to that of the memory cell gate 2, but the width of each layer is formed to be larger than that of the memory cell gate. In the semiconductor substrate on the side of the selection gate opposite to the memory cell, a source/drain region 13 of the selection transistor is formed to be a bit line contact diffusion layer.

Additionally, the peripheral circuit portion 31 is disposed in a region on the semiconductor substrate apart from the memory cell portion 30 to form the peripheral transistors. For the peripheral transistor, the peripheral gate 4 is disposed on a gate insulation film 14 disposed on the semiconductor substrate. The peripheral gate 4 includes the stacked structure similar to that of the memory cell gate 2, but the width of each layer is formed to be larger than that of the memory cell gate 2 or selection gate 3.

Moreover, the selection gate 3 and peripheral gate 4 can supply potential to the floating gate electrode 6, and function similarly to the conventional MOSFET. In this case, as shown in FIG. 5, in the selection gate 3 and peripheral gate 4, an opening 25 is disposed in the inter-gate insulation film 7, and the floating gate electrode 6, polycrystal silicon layer 8, and WSi layer 9 may also electrically be connected in the structure.

The side surfaces of the memory cell gate 2, selection gate 3, and peripheral gate 4 are covered with a post oxide film 16. A silicon oxide film 17 is formed on the semiconductor substrate 1, and the post oxide film 16 is formed on the silicon oxide film 17.

A first insulation film 18 is disposed on the sidewall and upper surface of the memory cell transistor, one side surface of the selection gate, and side surface of the peripheral gate. The first insulation film 18 has a thickness, for example, of about 0.05 .mu.m or more, and does not contain nitrogen as a main component. The first insulation film 18 is disposed to fill among the memory cell gates 2 of the memory cell transistors. A film having little hydrogen content and few traps with respect to charges is suitable for the first insulation film 18. Usable examples of the film include a silicon oxide film, oxynitride film, and the like. An oxynitride film is obtained by nitriding a silicon oxide film, so that the oxynitride film does not include nitrogen as a main component.

In this case, to "fill" means not only completely filling but also having a cavity. Even when air gaps such as void and seam are included, the function or effect of the insulation film does not change. That is, as shown in FIG. 6, an air gap (seam) 26 may also be disposed in the first insulation film 18 between the memory cell gates 2. In this case, the upper end of the air gap 26 is closed by the first insulation film 18, and the air gap 26 should not be exposed from the first insulation film 18.

In this case, for example, an interval between the gate electrodes is about 0.2 .mu.m, gate width is about 0.2 .mu.m, and height is about 0.6 .mu.m. As for the interval between the gate electrodes, an interval between the memory cell gates 2 is small, and an interval between the selection gates 3 between which the bit line contact 15 is held is large. Since the interval of the gate electrodes between the memory cell gates 2 is strongly concerned with the whole area of the memory cell array, the interval is reduced in order to reduce the area. On the other hand, since the bit line contact is formed between the selection gates of the memory cell arrays disposed adjacent to each other, the interval is large.

A second insulation film 19 is disposed on the side surface of the memory cell transistor in which the first insulation film 18 is not formed and on the first insulation film of the side surface of the peripheral gate 4. The thickness of the second insulation film 19 is about 0.02 to 0.06 .mu.m. Since the second insulation film 19 contains nitride as a main component, and is a hydrogen supplier, the thickness is preferably as small as possible. The second insulation film 19 has more hydrogen content than that of first insulation film 18, and also has more traps with respect to the charges.

In the peripheral circuit portion 31, a first interlayer insulator 20 is disposed on the second insulation film 19. Here, the thickness of the first interlayer insulator 20 is in a range of about 0.1 .mu.m to 0.3 .mu.m. The first interlayer insulator 20 can be formed of silicon oxide or silicon nitride. Moreover, in the memory cell portion 30, a second interlayer insulator 21 is formed on the first insulation film 18, first interlayer insulator 20 of the peripheral circuit portion, and peripheral gate 4.

A bit line 22 is disposed on the bit line contact 15. For the number of transistors of the NAND cell, the arbitrary number, such as 16 to 32, of memory cell transistors are formed between two selection gates. Moreover, when a distance between the memory cell gates is about 0.2 .mu.m or less, the effect of the present embodiment is remarkable.

In the present embodiment, the second insulation film 19 is disposed as an etching stopper prior to the contact hole opening in the side surfaces of the selection gates 3 disposed adjacent to and opposite to each other. Moreover, since a distance (gap) between the adjacent memory cell gates 2 is relatively small, the gap is completely filled with the first insulation film 18. Moreover, the distance between the adjacent selection gates 3 is larger than that between the adjacent memory cell gates 2, and the first insulation film 18 is not disposed between the selection gates.

A lightly-doped source/drain diffusion layer 23 is disposed in the semiconductor substrate 1 under the sidewall of the peripheral gate 4, and a heavily-doped source/drain diffusion layer 24 is disposed in the semiconductor substrate 1 outside the lightly-doped source/drain diffusion layer.

In the peripheral gate 4, the first insulation film 18 is disposed in the lower layer of the second insulation film (nitride film) 19. Thereby, the influence of hydrogen in the second insulation film 19 or charges captured in the second insulation film 19 onto electric characteristics of a transistor can be reduced.

That is, according to the semiconductor device of the present embodiment, process margin of etching for opening the contact hole is enhanced, and the deterioration of the electric characteristics such as the fluctuation of the threshold voltage of the transistor and drop of the withstanding voltage in the gate insulation film can be prevented. Therefore, there can be provided the semiconductor device and manufacturing method which have high reliability and yield.

Particularly in the memory cell transistor portion, the first insulation film 18 fills between the gate electrodes, and the second insulation film 19 does not exist in the vicinity of the gate oxide film 5 of the memory cell gate 2. Therefore, the characteristics deterioration of the memory cell transistor due to the charge trap can be prevented, and the reliability enhancement of the semiconductor device can be achieved.

Moreover, during the etching for forming the contact electrode 15, since the second insulation film (nitride film) 19 functions as the etching stopper, high reliability and yield can be obtained.

A manufacturing method of the semiconductor device of the present embodiment will next be described. First, as shown in FIG. 7, the silicon oxide film 17 is disposed on the semiconductor substrate 1. The floating gate 6, inter-gate insulation film 7, polycrystal silicon layer 8, WSi layer 9, and gate mask material 11 are successively stacked, and processed into a predetermined shape to form the memory cell gate 2, selection gate 3, and peripheral gate 4.

Subsequently, post oxidation is performed in order to recover from damages at a gate processing, and the post oxide film 16 is formed around each gate electrode of the stacked structure. Next, predetermined impurities are ion-implanted in order to form the source/drain region 12, source/drain region 13 serving as the bit line contact diffusion layer, and lightly-doped diffusion layer 23 of the peripheral gate 4. The ion implantation may be performed after the first insulation film is formed in the subsequent step.

Next, as shown in FIG. 8A, the first insulation film 18 is formed over the whole surface of the exposed part. The first insulation film 18 completely fills between the memory cell gate electrodes 2 of the memory cell transistors, and the film 18 is formed on the surface between the selection gates 3 in thickness such that the film does not completely fill between the selection gates 3.

It is to be noted that as shown in FIG. 8B, there is another method comprising: after depositing the interlayer insulator 20, etching and removing the first insulation film 18 and post oxide film 16 by a chemical mechanical polishing (CMP) method until the memory cell gate 2, the selection gate 3, and the upper surface of the gate mask material 11 including the silicon nitride film on the peripheral gate 4 are exposed.

In this case, even when there are air gaps in the first insulation film 18 filling between the memory cell gates 2, no problem occurs.

In this manner, the sidewall spacer 18 is disposed on the peripheral gate 4 of the transistor of the peripheral portion, and the sidewall spacer 18 of the same material is also disposed on the memory cell gate 2 and selection gate 3 of the memory cell portion to fill the interval. In this manner, the reliability of the memory cell is enhanced, and a lightly doped drain (LDD) structure described later is made possible.

Subsequently, as shown in FIG. 9, the memory cell portion 30 is covered with a mask material 33, and the first insulation film 18 formed in the upper part of the peripheral gate 4 and the first insulation film 18 formed on the upper surface of the semiconductor substrate 1 are removed by reactive ion etching (RIE) in the peripheral circuit portion 31. At this time, a tapered portion 34 is formed in the first insulation film 18 in the sidewall upper part. Thereafter, the mask material 33 is removed.

Next, the first insulation film 18 around the peripheral gate 4 is used as a mask to implant ions into the semiconductor substrate 1, so that the heavily-doped diffusion layer 24 including LDD structure is formed. When the impurity concentration of the heavily-doped diffusion layer 24 is raised by a considerable degree, the high-speed operation of the peripheral transistor is possible.

Furthermore, simultaneously with the forming of the heavily-doped diffusion layer 24, the first insulation film 18 around the peripheral gate 4 is used as a mask to implant the ions obliquely into the semiconductor substrate 1, and a channel impurity region (not shown) may partially be formed in the semiconductor substrate 1 so as to be in contact with the lightly-doped diffusion layer 23 under the peripheral gate 4. When the channel impurity region is formed, the impurity concentration to be implanted is set to be lower than an ion concentration of impurities for forming the heavily-doped diffusion layer 24, and the heavily-doped diffusion layer 24 is prevented from being removed.

Subsequently, as shown in FIG. 10, the mask (not shown) is used to remove the first insulation film 18 between the selection gates 3 of the memory cell portion 30. Here, a large part of the first insulation film 18 formed on the upper surface of the selection gate 3 is removed, and only a part of the upper surface on the side adjacent to the memory cell gate 2 remains.

Subsequently, as shown in FIG. 11, the second insulation film 19 is formed over the whole exposed surface. Here, as the second insulation film 19, a film is used which has etching tolerance against the etching for opening the bit line contact hole. For example, to use the silicon oxide film as the interlayer insulator (first interlayer insulator 20 described later) in which the contact hole is formed, the silicon nitride film is used as the second insulation film 19.

Next, as shown in FIG. 12, the first interlayer insulator 20 including, for example, BPSG, BSG, and TEOS films are deposited. Thereafter, thermal treatment is applied to fluidize the first interlayer insulator 20 followed by flattening the first interlayer insulator 20 by CMP method, and the first interlayer insulator 20 fills between the selection gates 3 and around the peripheral gate 4. When CMP is used, CMP having selectivity to the second insulation film 19 is used to stop polishing on the second insulation film 19. Another method shown in FIG. 8B may be adopted as aforementioned.

In this case, the first insulation film 18 fills between the memory cell gates 2 of the memory cell portion 30, and the first insulation film 18 needs to exist in the end of each memory cell unit. Additionally, the seam (air gap) may also be generated. Moreover, the topmost portion of the first insulation film 18 may drop to a position lower than the height of the gate mask material 11 of the memory cell gate 2. Alternatively, even with the seam entering the first insulation film 18 between the memory cell gates 2, there is no problem as long as the seam does not contact the semiconductor substrate 1.

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