Semiconductor device and manufacturing method of the same Number:7,436,046 from the United States Patent and Trademark Office (PTO) owispatent Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1.times.10.sup.19 cm.sup.-3 or less.<H manufacturing, Semiconductor, Semiconductor, d, 7436046.html, Patent, pto, 7436046

Title: Semiconductor device and manufacturing method of the same

Abstract: Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1.times.10.sup.19 cm.sup.-3 or less.

Patent Number: 7,436,046 Issued on 10/14/2008 to Kondo, et al.

Inventors: Kondo; Masao (Higashimurayama, JP), Sugii; Nobuyuki (Tokyo, JP), Kimura; Yoshinobu (Tokyo, JP)
Assignee: Renesas Technology Corp. (Tokyo, JP)

Appl. No.: 11/242,961

Filed: October 5, 2005

Foreign Application Priority Data


Oct 05, 2004 [JP]			2004-292598

Current U.S. Class: 257/616 ; 257/368; 257/617; 257/E29.297

Current International Class: H01L 31/117 (20060101)

Field of Search: 257/288,368,616,617,E29.297

References Cited [Referenced By]

U.S. Patent Documents


6927414	August 2005	Ouyang et al.
7141477	November 2006	Noda
7172935	February 2007	Lochtefeld et al.

Foreign Patent Documents


9-321307	Dec., 1997	JP
10-270685	Oct., 1998	JP
2000-31491	Jan., 2000	JP
2002-217413	Aug., 2002	JP
2003-110102	Apr., 2003	JP
2004-39762	Feb., 2004	JP

Primary Examiner: Warren; Matthew E
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP.

Claims

The invention claimed is:

1. A semiconductor device having an MISFET, comprising: (a) a silicon-germanium layer formed over a semiconductor substrate; (b) a strained silicon layer formed over the silicon-germanium layer; (c) a gate insulating film formed over the strained silicon layer; (d) a gate electrode formed over the gate insulating film; and (e) a source region and a drain region; wherein the strained silicon layer is thicker than a critical film thickness at which misfit dislocations occur and the misfit dislocations exist on an interface between the strained silicon layer and silicon-germanium layer, wherein the source region and drain region are each comprised of an impurity diffusion region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion, and wherein the extension region is formed in a region shallower than the interface between the strained silicon layer and the silicon-germanium layer, and the extension region has a thickness greater than a critical film thickness at which misfit dislocations occur.

2. A semiconductor device according to claim 1, wherein the MISFET is an LDMISFET.

3. A semiconductor device according to claim 1, wherein the source region and drain region each has an impurity diffusion region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion region, and wherein on the interface between the silicon-germanium layer and the strained silicon layer, the extension region has an impurity concentration of 1.times.10.sup.19 cm.sup.-3 or less.

4. A semiconductor device according to claim 1, wherein the source region and drain region are each comprised of an impurity diffusion region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion region, and wherein the extension region is formed in a region shallower than the interface between the strained silicon layer and silicon-germanium layer.

5. A semiconductor device according to claim 4, wherein the impurity diffusion region of the source region or the impurity diffusion region of the drain region is formed in a region deeper than the interface between the strained silicon layer and the silicon-germanium layer.

6. A semiconductor device according to claim 1, wherein the source region and drain region are formed in the strained silicon layer.

7. A semiconductor device according to claim 2, wherein the source region has an impurity diffusion region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion region, and wherein on the interface between the strained silicon layer and silicon-germanium layer, the extension region has an impurity concentration of 1.times.10.sup.19 cm.sup.-3 or less.

8. A semiconductor device according to claim 7, wherein a drain offset region is formed between the drain region and the channel formation region, and wherein the drain offset region is formed in a region deeper than the interface between the strained silicon layer and the silicon-germanium layer.

9. A semiconductor device according to claim 2, wherein the source region is formed in the strained silicon layer.

10. A semiconductor device according to claim 9, wherein the thickness of the source region is thicker than the critical film thickness at which misfit dislocations occur.

11. A semiconductor device according to claim 2, wherein the source region has an impurity region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion region, and wherein the extension region is formed in a region shallower than the interface between the strained silicon layer and the silicon-germanium layer.

12. A semiconductor device according to claim 2, wherein the source region has an impurity region and an extension region which is shallower or has a lower impurity concentration than the impurity diffusion region, and wherein the extension region is formed in a region shallower than the interface between the strained silicon layer and the silicon-germanium layer and has a thickness greater than the critical film thickness at which misfit dislocations occurs.

13. A semiconductor device according to claim 11 or 12, wherein a drain offset region is formed between the drain region and the channel formation region, and wherein the impurity diffusion region of the source region, the drain region or the drain offset region is formed in a region deeper than the interface between the strained silicon layer and silicon germanium layer.

14. A semiconductor device according to claim 8, wherein 1/2 or greater of the thickness of the drain offset region exists in the strained silicon layer.

15. A semiconductor device according to claim 8, wherein at least 1/2 of the impurity contained in the drain-offset region exists in the strained silicon layer.

16. A semiconductor device according to claim 8, wherein the peak position of the impurity contained in the drain offset region exists in the strained silicon layer.

17. A semiconductor device according to claim 13, wherein 1/2 or greater of the thickness of the drain offset region exists in the strained silicon layer.

18. A semiconductor device according to claim 13, wherein at least 1/2 of the impurity contained in the drain-offset region exists in the strained silicon layer.

19. A semiconductor device according to claim 13, wherein the peak position of the impurity contained in the drain offset region exists in the strained silicon layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent application No. 2004-292598 filed on Oct. 5, 2004, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the invention pertains to a technology effective when applied to a semiconductor device having a strained silicon layer.

There is a technology of forming a strain-relaxed silicon-germanium layer (SiGe layer) over a semiconductor substrate made of silicon and then forming a strained silicon layer by the epitaxial growth of a silicon layer over this silicon-germanium layer. This strained silicon layer has a higher electron mobility than that of an ordinary silicon layer so that by forming a channel of an MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the strained silicon layer, the mobility of electrons flowing through the channel can be heightened, which leads to an improvement in the electrical properties of the MISFET (for example, as described in IEDM Technical Digest, p 23-26 (2002)).

As a technology of forming a strained silicon layer over a silicon-germanium layer, that of forming a silicon-germanium layer which has a small film thickness, is free of penetration dislocations, and has a flat surface on an atomic level is disclosed, for example, in Japanese Unexamined Patent Publication No. 2002-217413. According to this technology, misfit dislocations exist on the interface between a silicon substrate and the silicon-germanium layer.

In Japanese Unexamined Patent Publication No. 2004-39762, disclosed is a technology of increasing the moving speed of carriers at the end of a source, thereby achieving the speed-up of an MISFET. Described specifically, this technology is, in an MISFET having a strained SiGe layer formed over a buried insulator film, a gate electrode formed over this strained SiGe layer via a gate insulating film, and a source region and a drain region formed on both sides of the gate electrode, to maximize the Ge concentration of the channel region (under the center of the gate electrode), while minimizing the Ge concentration of the source region and drain region.

In Japanese Unexamined Patent Publication No. 2000-031491, disclosed is a technology of forming an SiGe strain-applied layer as thin as about 200 nm over an SOI (Silicon On Insulator) substrate, thereby preventing threading dislocations of the SiGe strain-applied layer, generation of cracks and worsening of surface property.

In Japanese Unexamined Patent Publication No. Hei 9(1997)-321307, disclosed is a technology of forming a high-quality strained silicon layer having a sufficient strain without damaging a reducing effect of a floating capacity brought by an SOI structure. Described specifically, after formation of an SiGe layer, as a strain-applied semiconductor layer, over a silicon substrate, a buried oxide layer is formed to divide this SiGe layer into upper and lower regions and the upper SiGe layer is thinned. In order to reduce the defects such as dislocations which occur during formation of the SiGe layer and buried oxide layer, heat treatment is performed, followed by the formation of a strained silicon layer over the upper SiGe layer. This technology makes it possible to form a strained silicon layer having a sufficient strain while maintaining a reducing effect of a floating capacity brought by an SOI structure, because the thin SiGe layer (upper side) and the strained silicon layer are formed over the buried oxide layer.

In Japanese Patent Laid-Open No. Hei 10(1998)-270685, disclosed is a technology of forming a strained silicon layer over a silicon-germanium layer and then forming an MISFET over the strained silicon layer. In this technology, the source region and drain region of the MISFET are formed in the strained layer so that the pn junction between the source region and drain region exists in the strained silicon layer. By this, junction leakage of the MISFET can therefore be prevented.

In Japanese Unexamined Patent Publication No. 2003-110102, disclosed is a technology of improving the power added efficiency of a power amplification MISFET to be used for mobile terminals. Described specifically, the technology disclosed in this document is to form an MISFET by forming a first SiGe layer which is a first conductivity type and has a high impurity concentration, a second SiGe layer which is a first conductivity type and has a low impurity concentration, and a strained Si layer having a low impurity concentration over a silicon substrate in the order of mention and cause a portion of the strained Si layer to serve as a channel region; and forming a source electrode so as to pass through the second SiGe layer having a low impurity concentration and electrically connect to the first SiGe layer having a high impurity concentration or the silicon substrate. A high-density crystal defect region is formed only inside the silicon substrate or the first SiGe layer and the second SiGe layer is prevented from contacting the high-density crystal defect region.

SUMMARY OF THE INVENTION

By forming a strain-relaxed silicon-germanium layer over a semiconductor substrate and then forming a silicon layer over this silicon-germanium layer to form a strained silicon layer, it is possible to improve the electron mobility compared with that of the ordinary silicon layer. Attempts to improve the performance of an MISFET by forming the channel region of the MISFET from this strained silicon layer have been made by various research institutes.

It is known that when a strained silicon layer is formed over a strain-relaxed silicon-germanium layer, there is a relationship, as illustrated in FIG. 1, between a germanium concentration in the silicon-germanium layer and a critical thickness of the strained silicon layer at which no misfit dislocation occurs. As illustrated in FIG. 1, with an increase in the concentration of geranium, the critical thickness of the strained silicon layer decreases. For example, when the concentration of germanium is 10%, the critical thickness of the strained silicon layer is about 36 nm, and when the concentration of germanium is 20%, the critical thickness of the strained silicon layer is about 20 nm. When the concentration of germanium is 30%, the critical thickness of the strained silicon layer is about 16 nm.

When the thickness of the strained silicon layer exceeds a critical thickness, misfit dislocations occur in the vicinity of the interface between the strained silicon layer and silicon-germanium layer in order to relax a stress appearing in the strained silicon layer. Misfit dislocations are, as illustrated schematically in FIG. 2, linear and most of their whole length exists in the vicinity of the interface between the strained silicon layer and the silicon-germanium layer and they thread (penetrate) the surface of the strained silicon layer at some position.

It is conventionally thought to be essential to form an MISFET or LD (Laterally Diffused) MISFET over a strained silicon layer without causing misfit dislocations by adjusting the thickness of the strained silicon layer to not greater than the critical thickness. In practice, the thickness of the strained silicon layer is designed not to exceed the critical thickness. Leak current is thought to occur owing to misfit dislocations. Accordingly, the strained silicon layer is as thin as not greater than the critical thickness.

The manufacturing steps of an MISFET include a washing step and heat treatment step. By the washing step or heat treatment step for the formation of a gate insulating film or the like, the surface of a semiconductor substrate made of silicon is usually etched approximately 10 nm to 20 nm in depth.

When the concentration of germanium is 15% or greater, the critical thickness of the strained silicon layer at which not misfit dislocations occur is about 25 nm or less. This critical thickness is not sufficient for the above-described etching amount of the semiconductor substrate.

When the strained silicon layer is etched as a result of some processing and becomes very thin, diffusion of germanium from the silicon-germanium layer formed below the strained silicon layer spreads even to the vicinity of the surface of the strained silicon layer and causes a problem such as reduction in electron mobility in the channel region of the MISFET.

In addition, small unevenness in the thickness of the strained silicon layer leads to great unevenness in the transistor electrical properties of the MISFET. In other words, the electron mobility becomes uneven in the channel region owing to small unevenness in the thickness of the strained silicon layer, leading to a difficulty in maintaining a high yield in the manufacture of the MISFET.

Moreover, the MISFET is required to have a high breakdown voltage so that a gate insulating film must be thickened. In this case, however, a reduction in the thickness of the strained silicon layer becomes so large that it is thought to be difficult to use the strained silicon layer.

In MISFET or LDMISFET, it is the common practice to form, over the surface of its source or drain region, a metal silicide film such as cobalt silicide film or titanium silicide film in self alignment in order to reduce the resistance of the source or drain region. The metal silicide film is formed by bringing a metal film into contact with a silicon layer and then heating to cause a reaction therebetween. During this reaction, a portion of the silicon layer corresponding to the thickness of the metal silicide film thus formed is consumed. If a strained silicon layer is thin, it is consumed completely during the silicide reaction. Moreover, the silicide reaction extends even to a silicon-germanium layer formed below the strained silicon layer. When the silicide reaction thus reaches the silicon-germanium layer, an abnormal reaction occurs, which leads to generation of shape anomaly on the surface of a semiconductor substrate and an increase in resistance.

To prevent such a phenomenon, the silicide reaction is performed after accumulation of an additional silicon layer over the strained silicon layer in the source and drain regions by selective epitaxial growth, thereby thickening the silicon layer in the source and drain regions. This step for causing selective epitaxial growth of the silicon layer in the source and drain regions complicates the manufacturing method and therefore increases a manufacturing cost.

When a leak current is reduced by adjusting the source and drain regions to be shallower than the interface between the strained silicon layer and silicon-germanium layer, the source and drain regions become very thin, causing problems such as an increase in parasitic resistance and deterioration in the electrical properties of the device.

Another problem also occurs when an LDMISFET is formed over a strained silicon layer. In order to heighten the efficiency of a power amplifier composed of the LDMISFET, it is usually necessary to reduce the resistance of a drain offset region and reduce the on resistance of the transistor. The film thickness of the drain offset region must therefore be adjusted to 70 nm or greater, preferably about 100 nm. When a strained silicon layer constituting the LDMISFET is adjusted to a critical film thickness or less while adjusting the drain offset region to have the above-described thickness, most of the drain offset region is inevitably formed in the silicon-germanium layer below the strained silicon layer. At this time, the electron mobility of the silicon-germanium layer is lower than that of the strained silicon layer and moreover, lower than that of the ordinary silicon layer so that the resistance of the drain offset region cannot be reduced fully. For example, the sheet resistance when the LDMISFET is formed over an ordinary silicon layer is 1.6 k.OMEGA./.quadrature., while the sheet resistance when a strained silicon layer having a thickness not greater than a critical film thickness is formed over the silicon-germanium layer and then an LDMISFET is formed over this strained silicon layer is 1.9 k.OMEGA./.quadrature.. In spite of using the strained silicon layer, the sheet resistance becomes larger compared with the use of an ordinary silicon layer. This means that because the strained silicon layer is thin, most of the drain offset region is formed in the silicon-germanium layer having low electron mobility.

An object of the present invention is to provide a technology capable of suppressing a decrease in electron mobility in a channel region formed in a strained silicon layer.

Another object of the present invention is to provide a technology capable of improving a production yield of an MISFET formed over a strained silicon layer.

A further object of the present invention is to provide a technology capable of forming an MISFET requiring a high breakdown voltage over a strained silicon layer.

A still further object of the present invention is to provide a technology capable of suppressing an abnormal reaction between a metal and a silicon-germanium layer formed below a strained silicon layer when a metal silicide film is formed over the surface of source and drain regions.

A still further object of the present invention is to provide a technology capable of reducing the on resistance of an LDMISFET formed over a strained silicon layer.

The above-described and the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.

Outline of the typical inventions, of the inventions disclosed in the present application, will next be described.

A semiconductor device according to the present invention has an MISFET equipped with (a) a silicon-germanium layer formed over a semiconductor substrate, (b) a strained silicon layer formed over the silicon-germanium layer, (c) a gate insulating film formed over the strained silicon layer, (d) a gate electrode formed over the gate insulating film, and (e) source and drain regions, wherein the strained silicon layer is thicker than a critical film thickness at which misfit dislocations occur; and the misfit dislocations exist on the interface between the strained silicon layer and the silicon-germanium layer.

A manufacturing method of a semiconductor device according to the present invention has the steps of: (a) forming a silicon-germanium layer over a first semiconductor substrate, (b) forming, over the silicon-germanium layer, a strained silicon layer having a thickness greater than a critical film thickness at which misfit dislocations occur, thereby forming misfit dislocations on the interface between the silicon-germanium layer and the strained silicon layer; (c) preparing a second semiconductor substrate having an insulating film formed thereover; (d) bonding the surface of the first semiconductor substrate over which the strained silicon layer has been formed to the surface of the second semiconductor substrate over which the insulating film has been formed; (e) removing the first semiconductor substrate and the silicon-germanium layer formed thereover, thereby forming a strained silicon layer free of misfit dislocations via the insulating film over the second semiconductor substrate; (f) forming a gate insulating film over the strained silicon layer; (g) forming a gate electrode over the gate insulating film, and (h) forming a source region and a drain region in the strained silicon layer.

Advantages of the typical inventions, of the inventions disclosed in the present application, will next be described briefly.

A decrease in electron mobility can be suppressed in a channel region formed in a strained silicon layer, because the thickness of the strained silicon layer is made thicker than a critical film thickness at which no misfit dislocation occurs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the relationship between a germanium concentration and critical thickness of a strained silicon layer;

FIG. 2 is a schematic view illustrating misfit dislocations;

FIG. 3 is a circuit block diagram of an IC chip for amplifier circuit constituting an RF power module;

FIG. 4 is a cross-sectional view illustrating one cross-section of an RF power module;

FIG. 5 illustrates one example of a digital mobile phone system using an RF power module;

FIG. 6 is a plan view illustrating the schematic constitution of an MISFET (semiconductor device) according to Embodiment 1 of the present invention;

FIG. 7 is a cross-sectional view taken along a line A-A of FIG. 6;

FIG. 8 is a partially enlarged cross-sectional view of FIG. 7;

FIG. 9 is a schematic cross-sectional view illustrating how impurity diffusion occurs via misfit dislocations;

FIG. 10 is a graph illustrating the relationship between the depth from the surface of a semiconductor substrate and impurity concentration;

FIG. 11 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to Embodiment 1;

FIG. 12 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 11;

FIG. 13 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 12;

FIG. 14 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 13;

FIG. 15 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 14;

FIG. 16 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 15;

FIG. 17 is a cross-sectional view illustrating a semiconductor device according to Embodiment 2;

FIG. 18 is a partially enlarged cross-sectional view of FIG. 17;

FIG. 19 is a cross-sectional view illustrating a semiconductor device according to Embodiment 3;

FIG. 20 is a partially enlarged cross-sectional view of FIG. 19;

FIG. 21 is a plan view illustrating the schematic constitution of a semiconductor device according to Embodiment 4;

FIG. 22 is a cross-sectional view taken along a line A-A of FIG. 21;

FIG. 23 is a partially enlarged cross-sectional view of FIG. 22;

FIG. 24 is a graph illustrating the relationship between an impurity concentration and breakdown voltage;

FIG. 25 is a graph illustrating the relationship between a depth from the surface of a semiconductor substrate and the concentration of an n type impurity or carrier mobility when an ordinary silicon layer is used;

FIG. 26 is a graph illustrating the relationship between a depth from the surface of a semiconductor substrate and the concentration of an n type impurity or carrier mobility when a strained silicon layer having not greater than the critical film thickness is used;

FIG. 27 is a graph illustrating the relationship between a depth from the surface of a semiconductor substrate and the concentration of an n type impurity or carrier mobility when a strained silicon layer having at least the critical film thickness is used;

FIG. 28 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 4;

FIG. 29 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 28;

FIG. 30 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 29;

FIG. 31 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 30;

FIG. 32 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 31;

FIG. 33 is a cross-sectional view illustrating a semiconductor device according to Embodiment 5;

FIG. 34 is a partially enlarged cross-sectional view of FIG. 33;

FIG. 35 is a cross-sectional view illustrating a semiconductor device according to Embodiment 6;

FIG. 36 is a partially enlarged cross-sectional view of FIG. 35;

FIG. 37 is a cross-sectional view illustrating a semiconductor device according to Embodiment 7;

FIG. 38 is a partially enlarged cross-sectional view of FIG. 37;

FIG. 39 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 7;

FIG. 40 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 39;

FIG. 41 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 40;

FIG. 42 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 41;

FIG. 43 is a cross-sectional view illustrating a semiconductor device according to Embodiment 8;

FIG. 44 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to Embodiment 8;

FIG. 45 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 44;

FIG. 46 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 45;

FIG. 47 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 46;

FIG. 48 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 47;

FIG. 49 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 48;

FIG. 50 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 49;

FIG. 51 is a cross-sectional view illustrating one step for forming sidewall spacers made of a silicon oxide film;

FIG. 52 is a cross-sectional view illustrating a step following that of FIG. 51;

FIG. 53 is a cross-sectional view illustrating a manufacturing step of a semiconductor device according to Embodiment 9;

FIG. 54 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 53;

FIG. 55 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 54;

FIG. 56 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 55;

FIG. 57 is a cross-sectional view illustrating a manufacturing step of the semiconductor device following that of FIG. 56; and

FIG. 58 is a graph showing a preferable thickness range of a strained silicon layer.

DETAILED DESCRIPTION OF THE INVENTION

The meaning of some terms used in embodiments will hereinafter be described prior to the detailed description of the embodiments of the present invention.

1. GSM (Global System for Mobile Communication) is one of wireless communication systems or a standard used for a digital mobile telephone. There are three frequency bands defined for GSM. Of these, a 900 MHz band is called GSM900 or simply GSM; a 1800 MHz band is called GSM1800, or DCS (Digital Cellular System) or PCN; and a 1900 MHz band is called GSM 1900, DCS1900 or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In addition, GSM850 which operates in the 850 MHz band is sometimes used in North America.

2. A GMSK modulation system is a system used for communication of audio signals in which the phase of a carrier wave is shifted according to transmit data. An EDGE modulation system is a system used in data communications and it is a system in which an amplitude shift may be further added to a phase shift of GMSK modulation.

In the below-described embodiments, a description will be made after divided in plural sections or in plural embodiments if necessary for convenience's sake. These plural sections or embodiments are not independent each other, but in a relation such that one is a modification example, details or complementary description of a part or whole of the other one unless otherwise specifically indicated.

In the below-described embodiments, when a reference is made to the number of elements (including the number, value, amount and range), the number is not limited to a specific number but can be greater than or less than the specific number unless otherwise specifically indicated or principally apparent that the number is limited to the specific number.

Moreover in the below-described embodiments, it is needless to say that the constituting elements (including element steps) are not always essential unless otherwise specifically indicated or principally apparent that they are essential.

Similarly, in the below-described embodiments, when a reference is made to the shape or positional relationship of the constituting elements, that substantially analogous or similar to it is also embraced unless otherwise specifically indicated or principally apparent that it is not. This also applies to the above-described value and range.

In all the drawings for describing the embodiments, like members of a function will be identified by like reference numerals and overlapping descriptions will be omitted.

The embodiments of the present invention will next be described in detail based on accompanying drawings.

Embodiment 1

FIG. 3 is a circuit block diagram of an IC (Integrated Circuit) chip 1C for amplifier circuit which constitutes an RF (Radio Frequency) power module. FIG. 3 is a circuit block diagram of an IC chip using two frequency bands (dual band system) of, for example, GSM900 and DCS1800, and using two communication systems of a GMSK (Gaussian filtered Minimum Shift Keying) modulation system and an EDGE (Enhanced Data GSM Environment) modulation system at each frequency band.

The IC chip 1C has a power amplifier circuit 2A for GSM900, a power amplifier circuit 2B for DCS1800, and a peripheral circuit 3 which effects control, compensation and the like on amplifying operations of the those power amplifier circuits 2A and 2B. The power amplifier circuits 2A and 2B may respectively have three amplifying stages 2A1 through 2A3 and 2B1 through 2B3 and three matching circuits 2AM1 through 2AM3 and 2BM1 through 2BM3. In other words, input terminals 4a and 4b of the IC chip 1C are electrically connected to inputs of the amplifying stages 2A1 and 2B1, each corresponding to a first stage, via the input matching circuits 2AM1 and 2BM1, while the outputs of the amplifying stages 2A1 and 2B1, each corresponding to the first stage, are electrically connected to the inputs of the amplifying stages 2A2 and 2B2, each corresponding to a second stage, via the inter-stage matching circuits 2AM2 and 2BM2. The outputs of the second-stage amplifying stages 2A2 and 2B2 are electrically connected to the inputs of the final-stage amplifying stages 2A3 and 2B3 via the inter-stage matching circuits 2AM3 and 2BM3. The outputs of the final-stage amplifying stages 2A3 and 2B3 are electrically connected to the output terminals 5a and 5b.

The peripheral circuit 3 has a control circuit 3A and a bias circuit 3B which applies a bias voltage to each of the amplifying stages 2A1 through 2A3 and 2B1 through 2B3. The control circuit 3A is a circuit which generates a desired voltage to be applied to each of the power amplifier circuits 2A and 2B and has a power supply control circuit 3A1 and a bias voltage generating circuit 3A2. The power supply control circuit 3A1 is a circuit for generating a first power supply voltage to be applied to each of drain terminals of power MISFETs (LDMISFETs) in the amplifying stages 2A1 through 2A3 and 2B1 through 2B3. Also, the bias voltage generating circuit 3A2 is a circuit for generating a first control voltage for controlling the bias circuit 3B. According to this Embodiment 1, when the power supply control circuit 3A1 generates the first power supply voltage, based on an output level designation signal supplied from a baseband circuit provided outside the IC chip 1C, the bias voltage generating circuit 3A2 generates the first control voltage, based on the first power supply voltage generated by the power supply control circuit 3A1. The baseband circuit is a circuit for generating the output level designation signal. The output level designation signal may be a signal for designating output levels of the power amplifier circuits 2A and 2B and is generated based on the distance between a cellular phone and a base station, that is, the intensity of a radio wave.

FIG. 4 is a cross-sectional view illustrating one cross-section of an RF power module PM having the IC chip 1C mounted on a module board MCB. In FIG. 4, the IC chip 1C is mounted while the back surface of the substrate 1S is directed to the main surface of the module board MCB. The IC chip 1C has, as described above, the power amplifier circuits 2A and 2B and peripheral circuit 3 formed. For example, LDMISFET Qn1 constituting the amplifying stage 2A1 of the power amplifier circuit 2A, inductor (passive element) L1 and capacitor (passive element) C1 constituting the matching circuit 2AM2, and LDMISFET Qn2 constituting the amplifying stage 2A2 of the power amplifier circuit 2A are illustrated in FIG. 4.

A backside electrode 10 of the IC chip 1C is bonded to a chip mounting electrode 11 formed over a module board MCB. This electrode 11 is electrically and thermally bonded to a backside electrode 13G of the module board MCB via a plurality of thermal vias 12. The backside electrode 13G is supplied with a reference potential (for example, ground potential GND, i.e., about 0V). In other words, the reference potential supplied to the electrode 13G of the module board MCB is supplied to the substrate 1S through the thermal vias 12 and the electrode 11. Heat generated upon the operation of the IC chip 1C is transferred via the electrode 11 and the thermal vias 12 from the back surface of the substrate 1S to the backside electrode 13G of the module board MCB, from which the heat is dissipated. Electrodes 13S formed in the vicinity of the outer periphery of the back surface of the module board MCB indicate signal electrodes. Incidentally, the module board MCB has a multi-layered wiring structure formed by stacking a plurality of insulator plates one after another and integrating them. Although the insulator plates are each made of ceramics, such as alumina (aluminum oxide: Al.sub.2O.sub.3 and dielectric constant=9 to 9.7) having a small dielectric loss up to, for example, a millimeter wave region, the present invention is not limited to it. Various changes may be made thereto and a glass epoxy resin may be used.

FIG. 5 illustrates one example of a digital cellular phone system DPS using the RF power module PM according to Embodiment 1. Sign ANT in FIG. 11 indicates a signal wave transmitting/receiving antenna; reference numeral 15 indicates a frontend module; reference numeral 16 indicates a baseband circuit. The baseband circuit 16 has a function of converting an audio signal to a baseband signal or converting a receive signal to an audio signal. The baseband circuit 16 has, in addition, a function of generating a modulation scheme switching signal or a baseband switching signal.

Reference numeral 17 indicates a modulator-demodulator having a function of down-converting a receive signal to demodulate it, thereby generating a baseband signal or a function of generating a transmit signal. Signs FLT1 and FLT2 indicate filters for eliminating noise and the like from a receive signal. The filter FLT1 is used for GSM, while the filter FLT2 is used for DCS.

The baseband circuit 16 is composed of a plurality of semiconductor integrated circuits such as DSP (Digital Signal Processor), microprocessor and semiconductor memory. The frontend module 15 has impedance matching circuits MN1 and MN2, low pass filters LPF1 and LPF2, switch circuits 18a and 18b, capacitors C5 and C6 and a duplexer 19.

The impedance matching circuits MN1 and MN2 are connected to transmission output terminals of the RF power module PM to perform impedance matching. The low pass filters LPF1 and LPF2 are circuits for attenuating higher harmonics; the switch circuits 18a and 18b are transmission/reception changeover switch circuits; the capacitors C5 and C6 are elements for cutting DC components from a receive signal, and the duplexer 19 is a circuit for branching a signal lying in the GSM900 band from a signal lying in the DCS1800 band.

These circuits and elements illustrated in FIG. 5 are mounted on one wiring board so as to be configured as a module. Incidentally, changeover signals CNT1 and CNT2 of the switch circuits 18a and 18b are supplied from the baseband circuit 16.

The MISFET according to Embodiment 1 will next be described. The MISFET of this Embodiment 1 is used for, for example, the peripheral circuit 3 illustrated in FIG. 3. FIG. 6 is a schematic plain view of an MISFET Q1 of Embodiment 1. In FIG. 6, a gate electrode 26 extends over a region encompassed by an element isolation region 23. On the side of this gate electrode 26, an n type strained silicon layer 28a or an n type strained silicon layer 29a is formed. An n.sup.+ type strained silicon layer 32a is formed outside the n type strained silicon layer 28a, while an n.sup.+ type strained silicon layer 33a is formed outside the n type strained silicon layer 29a. A p.sup.+ type strained silicon layer 30a is formed outside the n.sup.+ type strained silicon layer 32a with the element isolation region 23 sandwiched therebetween. From FIG. 6, an interconnect layer, sidewall spacers formed over the side walls of the gate electrode 26, and a cobalt silicide film formed over the n.sup.+ type strained silicon layer 32a and n.sup.+ type strained silicon layer 33a are omitted.

FIG. 7 is a cross-sectional view taken along a line A-A of FIG. 6. In FIG. 7, a p.sup.- type silicon-germanium layer 21 is formed over a p.sup.- type semiconductor substrate 20 obtained by introducing a p type impurity (such as boron) into silicon. In this p.sup.- type silicon-germanium layer 21, a p type silicon-germanium layer 24 is formed. A p type strained silicon layer 22 is formed over the p type silicon-germanium layer 24. This p type strained silicon layer 22 and the p type silicon-germanium layer 24 constitute a p well.

In the lower layer region of the p.sup.- type silicon-germanium layer 21, amounts of germanium to be added to silicon are changed stepwise from 0% to 15%. This makes it possible to positively generate crystal defects in the lower layer region of the p.sup.- type silicon-germanium layer 21, thereby relaxing a strain caused by a difference in a lattice constant between silicon and germanium. The upper layer region of the p.sup.- type silicon-germanium layer 21 and p type silicon-germanium layer 24, the amount of germanium to be added to silicon is almost fixed to 15%. The strain is almost completely relaxed and crystal defects scarcely exist.

A p type silicon layer is formed over the p type silicon-germanium layer 24. Since the lattice constant of this p type silicon layer is different from that of the p type silicon-germanium layer 24, a strain occurs in the p type silicon layer and the p type silicon layer becomes a p type strained silicon layer 22.

In an active region of the p type strained silicon layer 22, that is, a region separated by an element isolation region 23, the MISFET Q1 according to Embodiment 1 is formed. This MISFET Q1 has a gate insulating film 25 formed over the p type strained silicon layer 22 and a gate electrode 26 formed over the gate insulating film 25. The gate insulating film 25 is made of, for example, a silicon oxide film. Instead, the gate insulating film 25 may be made of a so-called High-k film having a higher dielectric constant than a silicon oxide film. The gate electrode 26 has, for example, a polysilicon film 26a and a cobalt silicide film 24 stacked one after another in order to decrease a resistance. The film to be stacked is not limited to the cobalt silicide film 34 but instead, a titanium silicide film or nickel silicide film may be used.

Sidewall spacers 31 are formed over the side walls of the gate electrode 26. The sidewall spacers 31 are made of, for example, a silicon oxide film. Below one of the side walls 31, an n type strained silicon layer 28a and n type silicon-germanium layer 28b are formed, while below the other side wall 31, an n type strained silicon layer 29a and an n type silicon-germanium layer 29b are formed. An n type impurity such as phosphorus (P) has been introduced into the n type strained silicon layer 28a and n type silicon-germanium layer 28b. By these n type strained silicon layer 28a and n type silicon-germanium layer 28b, an extension region which is a portion of the source region is formed. Similarly, an extension region which is a portion of the drain region is formed by the n type strained silicon layer 29a and n type silicon-germanium layer 29b.

An n.sup.+ type strained silicon layer 32a and an n.sup.+ type silicon-germanium layer 32b are formed outside the extension region made of the n type strained silicon layer 28a and n type silicon-germanium layer 28b. The n.sup.+ type strained silicon layer 32a is more highly doped with an n type impurity than the n type strained silicon layer 28a and at the same time, the n.sup.+ type silicon-germanium layer 32b is more highly doped with an n type impurity than the n type silicon-germanium layer 28b. An impurity diffusion region which will be a portion of the source region is formed by these n.sup.+ type strained silicon layer 32a and n.sup.+ type silicon-germanium layer 32b. In other words, the source region is made of the extension region and impurity diffusion region. The extension region of the source region is shallower than the impurity diffusion region formed outside of the extension region.

Similarly, outside the extension region made of the n type strained silicon layer 29a and n type silicon-germanium layer 29b, an impurity diffusion region made of the n.sup.+ type strained silicon layer 33a and the n.sup.+ type silicon-germanium layer 33b is formed. The drain region is also made of the extension region and impurity diffusion region having a higher impurity concentration than the extension region. The extension region of the drain region is also shallower than the impurity diffusion region formed outside of the extension region.

A cobalt silicide film 34 is formed over the n.sup.+ type strained silicon layer 32a and this cobalt silicide film 34 constitutes a portion of the source region. Similarly, the cobalt silicide film 34 is formed over the n.sup.+ type strained silicon layer 33a and this cobalt silicide film 34 also constitutes a portion of the drain region.

An insulating film 35 which will be an interlayer insulating film is formed over the MISFET Q1, and this insulating film 35 has a contact hole 36 formed therein. A conductive material such as tungsten is filled in this contact hole 36 to form a plug 37. This plug 37 is made of, for example, a barrier film made of a titanium or titanium nitride film and a tungsten film. An interconnect 38 electrically connected to the plug 37 is formed over this plug 37. This interconnect 38 is made of, for example, an aluminum film.

FIG. 8 is an enlarged view of the MISFET Q1 of FIG. 7. In FIG. 8, the p type strained silicon layer 22 is formed over the p type silicon-germanium layer 24. This p type strained silicon layer 22 has a thickness of about 50 nm. A ratio (concentration) of germanium in this p type silicon-germanium layer 24 is 15%. As can be understood from FIG. 1, when the ratio of germanium is 15%, the critical film thickness at which misfit dislocations MF occur on the interface between the p type strained silicon layer 22 and p type silicon-germanium layer 24 is about 25 nm. The thickness of the p type strained silicon layer 22 in this case is about 50 nm, greater than the critical film thickness at which misfit dislocations MF occur. The misfit dislocations MF have therefore appeared in the vicinity of the interface between the p type strained silicon layer 22 and p type silicon-germanium layer 24.

It was considered before that when misfit dislocations MF occurred, a leak current was caused via the misfit dislocations MF themselves. The thickness of the p type strained silicon layer 22 formed over the p type silicon-germanium layer 24 was therefore adjusted to not greater than the critical film thickness to prevent generation of misfit dislocations MF. According to the test by the present inventors, however, it has been confirmed that the misfit dislocations themselves are electrically inactive. This means that misfit dislocations do not cause an increase in a leak current compared with a case where no misfit dislocation occurs. Accordingly, existence of misfit dislocations MF at any junction portion of the MISFET Q1 causes no problem.

In the MISFET Q1 of Embodiment 1, the p type strained silicon layer 22 is made thicker than the critical film thickness. Following advantages are available by such an increase in the thickness of the p type strained silicon layer 22.

The strain of the p type strained silicon layer 22 formed by the epitaxial growth over the strained-relaxed p type silicon-germanium layer 24 is maintained at almost a fixed magnitude until its thickness reaches about 4 times as much as the critical film thickness at which generation of misfit dislocations starts. Even in the p type strained silicon layer thicker than the critical film thickness, the improving effect of electron mobility by strain can be kept as is. In other words, it is possible to improve electron mobility by using the p type strained silicon layer 22 thicker than the critical film thickness for the channel region of the MISFET Q1. When a ratio of germanium in the p type silicon-germanium layer 24 is 10% or greater, the electron mobility of the p type strained silicon layer 22 formed over the p type silicon-germanium layer 24 becomes at least twice as much as that of an ordinary silicon layer.

Since the p type strained silicon layer 22 is thicker than the critical film thickness, it is possible to prevent diffusion of germanium from the p type silicon-germanium layer 24 formed below the p type strained silicon layer 22 from extending to the surface (channel region) of the p type strained silicon layer 22. Accordingly, a decrease in electron mobility which will otherwise occur by the diffusion of germanium into the channel region of the MISFET Q1 can be suppressed. In other words, when the p type strained silicon layer 22 is thin, germanium diffused from the underlying p type silicon-germanium layer 24 reaches even the surface of the p type strained silicon layer 22 and mobility of electrons flowing through the channel lowers. In this Embodiment 1, however, the thickened p type strained silicon layer 22 can inhibit a reduction in electron mobility due to germanium diffusion.

In addition, since the p type strained silicon layer 22 is made thicker than the critical film thickness, minute unevenness in the thickness of the p type strained silicon layer 22 does not lead to unevenness in the transistor characteristics of the MISFET Q1. A decrease in the yield of non-defective products, which will otherwise occur by minute unevenness in the thickness of the p type strained silicon layer 22, can therefore be inhibited. In other words, owing to an increase in the thickness of the p type strained silicon layer 22, an influence of minute unevenness in the film thickness can be made relatively small compared with the case where the p type strained silicon layer 22 is thin.

Moreover, this strained silicon technology can be applied to an MISFET which must increase the thickness of the gate insulating film 25 in order to satisfy the request for high breakdown voltage. Since the p type strained silicon layer 22 has an increased thickness, the p type strained silicon layer 22 still has a sufficient film thickness even after the p type strained silicon layer is thinned by the formation of the gate insulating film 25. This strained silicon technology can thus be applied to the case where high breakdown voltage is required. In other words, the gate insulating film 25 is usually formed by thermal oxidation. At this time, the gate insulating film 25 is formed as if it eats away the p type strained silicon layer 22. The MISFET with high breakdown voltage must have a relatively thick gate insulating film 25 so that a reduction in the thickness of the p type strained silicon layer 22 relatively increases. In this Embodiment 1, however, the p type strained silicon layer 22 can be thickened sufficiently so that the p type strained silicon layer 22 has still an enough thickness in spite of a reduction in the film thickness.

In addition, since the p type strained silicon layer 22 is thick, the source and drain regions can be thickened by several times as much as the conventional ones. This leads to a reduction in the parasitic resistance of the source and drain regions. In the related art, the film thickness of the p type strained silicon layer 22 must be not greater than critical film thickness to avoid generation of misfit dislocations. The upper limit of the film thickness of the source and drain regions was about critical film thickness. In this Embodiment 1, however, the p type strained silicon layer 22 has a thickness several times as much as that of the critical film thickness so that the source and drain regions can be thickened and parasitic resistance can be reduced.

A cobalt silicide film 34 is formed over the source and drain regions for the purpose of reducing resistance. This cobalt silicide layer 34 is formed by silicidation of the surface of the n.sup.+ type strained silicon layer 32a and n.sup.+ type strained silicon layer 33a. In other words, the cobalt silicide film 34 is formed by consuming the n.sup.+ type strained silicon layer 32a and n.sup.+ type strained silicon layer 33a as if it eats them up. In the related art, since the n.sup.+ type strained silicon layers 32a and 33a are thin, the silicidation extends even to the n.sup.+ type silicon-germanium layers 32b and 33b below the n.sup.+ type strained silicon layers 32a and 33a and an abnormal reaction occurs when the silicide reaction is effected without any pre-treatment. With a view to overcoming this problem, a strained silicon layer is added by the selective epitaxial growth over the n.sup.+ type strained silicon layers 32a and 33a, which complexes the manufacturing process. In this Embodiment 1, on the other hand, the n.sup.+ type strained silicon layers 32a and 33a having enough thickness prevent the silicidation from reaching the underlying n.sup.+ type silicon-germanium layers 32b and 33b. In this Embodiment 1, the manufacturing method can be simplified because no strained silicon layer is accumulated over the n.sup.+ type strained silicon layers 32a and 33a.

By adjusting the thickness of the p type strained silicon layer 22 or n.sup.+ type strained silicon layers 32a and 33a to be thicker than the critical film thickness, the above-described effect is achieved and in addition, a leak current does not increase through the misfit dislocations MF themselves, if any. The misfit dislocations MF themselves do not increase a leak current, but it is known that they will be a path for impurity diffusion. When there exist misfit dislocations MF, consideration must be given to the path for impurity diffusion.

FIG. 9 illustrates how misfit dislocations MF exist on the interface between the p type strained silicon layer 22 and p type silicon-germanium layer 24. FIG. 9 suggests that an n type impurity is diffused into the drain region via misfit dislocations MF from the n type strained silicon layer 28a and n type silicon-germanium layer 28b constituting the extension region of the source region. Thus, the misfit dislocations MF become a path for impurity diffusion. In FIG. 9, diffusion of an impurity narrows the distance between the source region and drain region and a leak current occurs owing to this impurity diffusion. The present inventors have found by a test that generation of a leak current owing to the narrowing of the distance between the source region and drain region by impurity diffusion occurs only in the below-described case.

It occurs only when the misfit dislocations MF lie in a region in which the source region and drain region are closest to each other, that is, in a region between a portion of the source region below the end of the gate electrode 26 and a portion of the drain region below the end of the gate electrode 26. The present inventors have found that the presence or absence of a leak current depends on an impurity concentration of the source region and drain region below the end of the gate electrode 26 at which the misfit dislocations MF lie.

Most of the misfit dislocations MF exist in the vicinity of the interface between the strained silicon layer (including the p type strained silicon layer 22, n type strained silicon layers 28a and 29a, and the n.sup.+ type strained silicon layers 32a and 33a) and the silicon-germanium layer (including the p type silicon-germanium layer 24, n type silicon-germanium layers 28b and 29b, and n.sup.+ type silicon-germanium layers 32b and 33b) so that a position in the depth direction at which the impurity concentration is to be monitored can be considered as the interface between the strained silicon layer and silicon germanium layer.

FIG. 10 shows the relationship between the depth below the end of the gate electrode 26 and the impurity concentration. In FIG. 10, supposing that Ci represents an impurity concentration on the interface between the strained silicon layer and silicon-germanium layer, it has been revealed that impurity diffusion via the misfit dislocations MF can be suppressed by adjusting this impurity concentration Ci to not greater than 1.times.10.sup.19 cm.sup.-3. In other words, impurity diffusion can be suppressed by adjusting an n type impurity concentration in the source region (extension region) and drain region (extension region) below the end of the gate electrode 26 to not greater than 1.times.10.sup.19 cm.sup.-3. Impurity diffusion can be suppressed by adjusting the impurity concentration to not greater than a predetermined value, because diffusion tends to occur at a higher impurity concentration.

The impurity concentration in the source and drain regions usually lowers as an increase in the depth from the surface. The above-described conditions can be satisfied if the thickness of the n type strained silicon layers 28a and 29a is adjusted to a predetermined value or greater. In the MISFET of Embodiment 1 illustrated in FIGS. 7 and 8, the impurity concentration on the interface between the strained silicon layer and silicon-germanium layer below the end of the gate electrode 26 is, for example, 1.times.10.sup.18 cm.sup.-3, lower than the above-described value: 1.times.10.sup.19 cm.sup.-3.

It has been confirmed based on the results of the test that intrusion of the misfit dislocations MF into the strained silicon layer (refer to FIG. 2), which occurs at a certain probability, does not lead to an increase in leak current. The intrusion of the misfit dislocations MF may presumably form a path for impurity diffusion. The intrusion of the misfit dislocations MF is formed in a substantially vertical direction from the interface between the strained silicon layer and silicon-germanium layer toward the surface of the strained silicon layer. Accordingly, impurity diffusion from the source or drain region once occurs downward and after arrival at the interface between the strained silicon layer and silicon-germanium layer, it moves in a horizontal direction. Impurity diffusion so brisk as to cause a leak current therefore does not occur in consideration of the necessity of a very long distance for connecting the source region and the drain region.

A manufacturing method of the MISFET Q1 of the present invention will next be described based on accompanying drawings.

As illustrated in FIG. 11A, a p.sup.- type semiconductor substrate 20 is prepared by introducing a p type impurity (such as boron) into silicon at a low concentration. A p.sup.- type silicon-germanium layer 21 is formed over this p.sup.- type semiconductor substrate 20. This p.sup.- type silicon-germanium layer 21 can be formed, for example, by using CVD (Chemical Vapor Deposition). This p.sup.- type silicon-germanium layer 21 is obtained by causing the growth of about 1 .mu.m while increasing stepwise a ratio of germanium from 0% to 15% and then causing the growth of about 1 .mu.m while keeping the ratio of germanium at 15%.

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