Semiconductor device Number:7,436,070 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor device

Abstract: A non-insulated DC-DC converter hs a power MOS.cndot.FRT for a highside switch and a power MOS.cndot.FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS.cndot.FET for the highside switch and the power MOS.cndot.FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS.cndot.FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

Patent Number: 7,436,070 Issued on 10/14/2008 to Uno,   et al.

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Inventors:	Uno; Tomoaki (Takasaki, JP), Shiraishi; Masaki (Hitachi, JP), Matsuura; Nobuyoshi (Takasaki, JP), Nagasawa; Toshio (Takasaki, JP)
Assignee:	Renesas Technology Corp. (Tokyo, JP)
Appl. No.:	11/108,825
Filed:	April 19, 2005

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Foreign Application Priority Data

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Apr 19, 2004 [JP]			2004-123153

Current U.S. Class:	257/777 ; 257/337; 257/481
Current International Class:	H01L 23/48 (20060101)
Field of Search:	363/147 257/337,339,341,342,476,481,678,685,686,723,777

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References Cited [Referenced By]

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U.S. Patent Documents

6184585	February 2001	Martinez et al.
6775164	August 2004	Wong et al.

Foreign Patent Documents

	2001-025239		Jan., 2001		JP
	2002-217416		Aug., 2002		JP
	2004342735		Dec., 2004		JP

Primary Examiner: Riley; Shawn
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP.

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Claims

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What is claimed is:

1. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective operations of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the third semiconductor chip is disposed in such a manner that a distance between the third semiconductor chip and the first semiconductor chip is set shorter than a distance between the third semiconductor chip and the second semiconductor chip, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit which controls the operation of the first field effect transistor, and a second control circuit which controls the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; (b) a fourth chip mounting section with the fifth semiconductor chip mounted thereover, and electrically connected to the cathode of the second Schottky barrier diode; (c) a wire which electrically connects the fourth chip mounting section to the output of the first control circuit; and (d) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal.

2. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections: a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective operations of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the third semiconductor chip is disposed in such a manner that a distance between the third semiconductor chip and the first semiconductor chip is set shorter than a distance between the third semiconductor chip and the second semiconductor chip, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit which controls the operation of the first field effect transistor, and a second control circuit which controls the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the cathode of the second Schottky barrier diode to the output of the first control circuit, and wherein the fifth semiconductor chip is mounted over the third chip mounting section in a state in which the anode of the second Schottky barrier diode is electrically connected to the second power supply terminal through the third chip mounting section.

3. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective operations of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the third semiconductor chip is disposed in such a manner that a distance between the third semiconductor chip and the first semiconductor chip is set shorter than a distance between the third semiconductor chip and the second semiconductor chip, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit which controls the operation of the first field effect transistor, and a second control circuit which controls the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal, and wherein the fifth semiconductor chip is mounted over the first semiconductor chip in a state in which the cathode of the second Schottky barrier diode is electrically connected to a gate electrode of the first field effect transistor of the first semiconductor chip.

4. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the second semiconductor chip is placed in a position closer to the second power supply terminal than the output terminal, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; (b) a fourth chip mounting section with the fifth semiconductor chip mounted thereover, and electrically connected to the cathode of the second Schottky barrier diode; (c) a wire which electrically connects the fourth chip mounting section to the output of the first control circuit; and (d) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal.

5. A semiconductor device, comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the second semiconductor chip is placed in a position closer to the second power supply terminal than the output terminal, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the cathode of the second Schottky barrier diode to the output of the first control circuit, and wherein the fifth semiconductor chip is mounted over the third chip mounting section in a state in which the anode of the second Schottky barrier diode is electrically connected to the second power supply terminal through the third chip mounting section.

6. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the second semiconductor chip is placed in a position closer to the second power supply terminal than the output terminal, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal, and wherein the fifth semiconductor chip is mounted over the first semiconductor chip in a state in which the cathode of the second Schottky barrier diode is electrically connected to a gate electrode of the first field effect transistor of the first semiconductor chip.

7. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the first semiconductor chip is disposed in such a manner that one side thereof approaches one side of the first chip mounting section, which is adjacent to one side of the second chip mounting section, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; (b) a fourth chip mounting section with the fifth semiconductor chip mounted thereover, and electrically connected to the cathode of the second Schottky barrier diode; (c) a wire which electrically connects the fourth chip mounting section to the output of the first control circuit; and (d) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal.

8. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the first semiconductor chip is disposed in such a manner that one side thereof approaches one side of the first chip mounting section, which is adjacent to one side of the second chip mounting section, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the cathode of the second Schottky barrier diode to the output of the first control circuit, and wherein the fifth semiconductor chip is mounted over the third chip mounting section in a state in which the anode of the second Schottky barrier diode is electrically connected to the second power supply terminal through the third chip mounting section.

9. A semiconductor device comprising: a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at intervals; a plurality of external terminals disposed around the first, second and third chip mounting sections; a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor; a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor; a third semiconductor chip disposed over the third chip mounting section and including a control circuit which controls operations of the first and second field effect transistors; a fourth semiconductor chip disposed over the second chip mounting section and having a first Schottky barrier diode; and a sealing body which seals the first, second, third and fourth semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals, wherein the plurality of external terminals include a first power supply terminal which supplies an input power supply potential, second power supply terminals which supply a potential lower than the input power supply potential, a signal terminal which controls the control circuit of the third semiconductor chip, and an output terminal which outputs an output power supply potential to the outside, wherein the first field effect transistor has a source-drain path series-connected between the first power supply terminal and the output terminal; wherein the second field effect transistor has a source-drain path series-connected between the output terminal and the second power supply terminal, wherein the control circuit of the third semiconductor chip controls respective gates of the first and second field effect transistors in accordance with a control signal inputted to the signal terminal, wherein the first semiconductor chip is disposed in such a manner that one side thereof approaches one side of the first chip mounting section, which is adjacent to one side of the second chip mounting section, and wherein the first Schottky barrier diode of the fourth semiconductor chip has a cathode electrically connected to the output terminal and an anode electrically connected to the second power supply terminal, and is electrically connected so as to be parallel with the second field effect transistor, wherein the control circuit of the third semiconductor chip includes a first control circuit for control of the operation of the first field effect transistor, and a second control circuit for control of the operation of the second field effect transistor, wherein a cathode of a second Schottky barrier diode is electrically connected to an output of the first control circuit, an anode of the second Schottky barrier diode is electrically connected to the second power supply terminal, and the second Schottky barrier diode is electrically connected between the output of the first control circuit and the second power supply terminal, wherein the sealing body further includes: (a) a fifth semiconductor chip having the second Schottky barrier diode; and (b) a wire which electrically connects the anode of the second Schottky barrier diode to the second power supply terminal, and wherein the fifth semiconductor chip is mounted over the first semiconductor chip in a state in which the cathode of the second Schottky barrier diode is electrically connected to a gate electrode of the first field effect transistor of the first semiconductor chip.

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Description

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CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent application No. 2004-123153, filed on Apr. 19, 2004, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates in general to a semiconductor device, and, more particularly, to a technique that is effective when applied to a semiconductor device having a power supply circuit.

A DC-DC converter, which is widely used as one example of a power supply circuit, has a configuration wherein a power MOS.cndot.FET (Metal Oxide Semiconductor Field Effect Transistor) for a highside switch and a power MOS.cndot.FET for a lowside switch are connected in series. The power MOS.cndot.FET for the highside switch has a switch function for control of the DC-DC converter. The power MOS.cndot.FET for the lowside switch has a switch function for synchronization and rectification. The conversion of a power supply voltage is performed by alternately turning these two power MOS.cndot.FETs on/off while being synchronized with each other.

Meanwhile, there is a known DC-DC converter in which a Schottky barrier diode is electrically connected to its output in parallel with the power MOS.cndot.FET for the lowside switch. That is, the Schottky barrier diode, which has a lower forward voltage VF than a parasitic (body) diode of the power MOS.cndot.FET for the lowside switch, is connected in parallel with the power MOS.cndot.FET for the lowside switch. A current that flows during the dead time (corresponding to a period in which both power MOS.cndot.FETs for highside and lowside switches are turned off) of the DC-DC converter is commutated to the Schottky barrier diode, to thereby reduce the diode conduction loss, as well as a diode recovery loss due to a reverse recovery time (trr) being made fast, whereby a loss produced during the dead time of the DC-DC converter is reduced, thereby to improve its voltage conversion efficiency. In a DC-DC converter considered by the present inventors, the power MOS.cndot.FET for the highside switch, the power MOS.cndot.FET for the lowside switch, a control IC (Integrated circuit) for controlling the operations of those power MOS.cndot.FETs, and the Schottky barrier diode are respectively formed in discrete semiconductor chips, and the respective semiconductor chips are encapsulated in separate packages.

An example of such a DC-DC converter has been described in, for example, Japanese Unexamined Patent Publication No. 2002-217416, which discloses a technique for forming a highside switch by use of a horizontal power MOS.cndot.FET and forming a lowside switch by use of a vertical power MOS FET.

A technique, using resistors and capacitors, for reducing noise that presents a problem for a DC-DC converter in which a control circuit, driver circuits and power MOS.cndot.FETs are brought into one chip, has been disclosed in, for example, Japanese Unexamined Patent Publication No. 2001-25239.

SUMMARY OF THE INVENTION

Meanwhile, the present inventors have found that a DC-DC converter having a construction as described above, in which the power MOS.cndot.FET for the highside switch, the power MOS.cndot.FET for the lowside switch, the control IC and the Schottky barrier diode are respectively formed in discrete semiconductor chips and the respective semiconductor chips are respectively encapsulated in separate packages, has the following problems.

That is, with a construction in which several packages are provided, problems result in that the commutation of a load current to the Schottky barrier diode during the dead time is impaired by the inductances of a wiring for electrically connecting the cathode of the Schottky barrier diode and the output of the DC-DC converter and a wiring for electrically connecting the anode of the Schottky barrier diode and a ground wiring, so that despite the use of a Schottky barrier diode having a lower forward voltage than that of the parasitic diode, a sufficient effect cannot be obtained in terms of a reduction in diode conduction loss and a reduction in diode recovery loss due to the reverse recovery time being made fast.

A problem arises in that, when the load current that flows through the Schottky barrier diode during the dead time becomes small due to the wiring inductances and the load current flows even into the body diode of the power MOS.cndot.FET for the lowside switch, the potential on the output side of the DC-DC converter is reduced to a negative potential by the forward voltage of the body diode, and the output of the control IC electrically connected to the power MOS.cndot.FET is also brought to a negative potential, so that a parasitic npn bipolar transistor is turned on within the control IC, to thereby increase the current consumption of the control IC. Further, a problem arises in that a malfunction occurs in that, when its increased state proceeds and a potential between the source electrode (BOOT) side of a p channel MOS.cndot.FET of a CMOS (Complementary MOS) inverter of the control IC and the output of the DC-DC converter becomes lower than a prescribed potential value, a protection circuit function of the DC-DC converter works automatically to stop the operation of the power MOS.cndot.FET for the highside switch. In addition to the above, a problem also arises in that, when a plurality of DC-DC converters are electrically connected to a load circuit like a CPU or the like to construct an overall system, including a plurality of DC-DC converters, miniaturization of the overall system is impaired when Schottky barrier diodes are connected to the individual DC-DC converters in separate packages.

An object of the present invention is to provide a technique that is capable of enhancing the power supply conversion efficiency of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the following descriptions in the present specification and the accompanying drawings.

A summary of representative aspects of the invention disclosed in the present application will be explained in as follows:

The present invention provides a semiconductor device comprising a first power supply terminal for supply of a first potential, at least one second power supply terminal for supply of a second potential that is lower than the first potential, first and second field effect transistors that are series-connected between the first and second power supply terminals, a control circuit which is electrically connected to inputs of the first and second field effect transistors and which control operations of the first and second field effect transistors, and an output wiring section connected to a wiring that connects the first and second field effect transistors, wherein a Schottky barrier diode connected in parallel with the second field effect transistor is provided between the output wiring section and the second power supply terminal, wherein the first field effect transistor, the second field effect transistor, the control circuit and the Schottky barrier diode are respectively formed in discrete semiconductor chips, and wherein the separate semiconductor chips are encapsulated in one sealing body.

Advantageous effects obtained by the present invention as disclosed in the present application will be explained in brief as follows:

The first field effect transistor, the second field effect transistor, the control circuit and the Schottky barrier diode are respectively formed in discrete semiconductor chips, and the discrete semiconductor chips are encapsulated in one sealing body. Consequently, a wiring section that electrically connects the anode of the Schottky barrier diode and the output wiring section, and a wiring section that electrically connects the cathode of the Schottky barrier diode and the second power supply terminal can be shortened in length. Further, the inductances of the wiring sections can be reduced. It is therefore possible to reduce the diode conduction loss and the diode recovery loss during a dead time and enhance the voltage conversion efficiency of a semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one example of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating one example of a control circuit of the semiconductor device shown in FIG. 1;

FIG. 3 is a timing chart showing one example of the operation of the semiconductor device shown in FIG. 1;

FIG. 4 is a schematic diagram showing one example of the packaging used for a semiconductor device considered by the present inventors;

FIG. 5 is a schematic diagram of a circuit of the semiconductor device;

FIG. 6 is a diagram showing a parasitic operation of a semiconductor chip formed with a control chip;

FIG. 7 is an equivalent circuit diagram showing parasitic inductance components on the semiconductor device shown in FIG. 4;

FIG. 8 is a schematic diagram showing a circuit operation of the semiconductor device;

FIG. 9 is a diagram showing a device section at the circuit operation of FIG. 8;

FIG. 10 is a schematic diagram showing an a configuration example of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is an overall plan view showing a main surface side of the semiconductor device shown in FIG. 10;

FIG. 12 is a side view showing the semiconductor device shown in FIG. 11;

FIG. 13 is an overall plan view illustrating a back surface side of the semiconductor device shown in FIG. 11;

FIG. 14 is a perspective view showing an outward appearance of the semiconductor device shown in FIG. 11;

FIG. 15 is an overall plan view showing a main surface side of a package as seen through the inside of the package of the semiconductor device shown in FIG. 11;

FIG. 16 is a cross-sectional view taken along line Y1-Y1 of FIG. 15;

FIG. 17 is a cross-sectional view taken along line X1-X1 of FIG. 15;

FIG. 18 is an overall plan view showing a main surface side of a first semiconductor chip that constitutes the semiconductor device shown in FIG. 11;

FIG. 19 is a cross-sectional view taken along line X2-X2 of FIG. 18;

FIG. 20 is a fragmentary cross-sectional view showing the first semiconductor chip shown in FIG. 18;

FIG. 21 is a cross-sectional view taken along line Y2-Y2 of FIG. 18;

FIG. 22 is a fragmentary cross-sectional view illustrating a third semiconductor chip that constitutes the semiconductor device shown in FIG. 11;

FIG. 23 is a fragmentary cross-sectional view depicting a fourth semiconductor chip that constitutes the semiconductor device shown in FIG. 11;

FIG. 24 is a plan view showing one example of the packaging of the semiconductor device shown in FIG. 11;

FIG. 25 is a side view illustrating the semiconductor device shown in FIG. 24;

FIG. 26 is a circuit diagram showing one example of a circuit system configuration including the semiconductor device shown in FIG. 11;

FIG. 27 is a flow diagram depicting an assembly process of the semiconductor device shown in FIG. 11;

FIG. 28 is a fragmentary plan view showing one example illustrative of a main surface side of each unit area of a lead frame employed in the assembly process of the semiconductor device shown in FIG. 11;

FIG. 29 is a plan view illustrating a back surface side of each unit area of the lead frame shown in FIG. 28;

FIG. 30 is a plan view showing each unit area of the lead frame employed in the assembly process of the semiconductor device shown in FIG. 11;

FIG. 31 is a plan view depicting an example of a semiconductor device according to a second embodiment of the present invention;

FIG. 32 is a plan view showing an example, exclusive of metal wiring boards, of the semiconductor device shown in FIG. 31;

FIG. 33 is a cross-sectional view taken along line Y3-Y3 of FIG. 31;

FIG. 34 is a cross-sectional view taken along line X3-X3 of FIG. 31;

FIG. 35 is a plan view showing a top surface of a semiconductor device according to a third embodiment of the present invention;

FIG. 36 is a cross-sectional view taken along line Y4-Y4 of FIG. 35;

FIG. 37 is a cross-sectional view taken along line X4-X4 of FIG. 35;

FIG. 38 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 39 is a cross-sectional view showing a semiconductor device illustrative of a modification of FIG. 38;

FIG. 40 is a plan view illustrating an example of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 41 is a cross-sectional view taken along line X5-X5 of FIG. 40;

FIG. 42 is a plan view showing an example of a semiconductor device according to a sixth embodiment of the present invention;

FIG. 43 is a plan view illustrating an example of the semiconductor device, exclusive of a metal wiring board and bonding wires shown in FIG. 42;

FIG. 44 is a cross-sectional view taken along line Y6-Y6 of FIG. 42;

FIG. 45 is a cross-sectional view taken along line X6-X6 of FIG. 42;

FIG. 46 is a schematic diagram showing an example of a semiconductor device according to a seventh embodiment of the present invention;

FIG. 47 is a diagram illustrating an operating state of a parasitic device of a third semiconductor chip in the configuration of the semiconductor device shown in FIG. 46;

FIG. 48 is a diagram illustrating an operating state of the parasitic device of the third semiconductor chip in the configuration of the semiconductor device shown in FIG. 46;

FIG. 49 is a plan view showing an example of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 50 is a cross-sectional view taken along line Y7-Y7 of FIG. 49;

FIG. 51 is a plan view showing an example of a semiconductor device according to an eighth embodiment of the present invention;

FIG. 52 is a cross-sectional view taken along line Y8-Y8 of FIG. 51;

FIG. 53 is a plan view showing an example of a semiconductor device according to a ninth embodiment of the present invention; and

FIG. 54 is a cross-sectional view taken along line Y9-Y9 of FIG. 53.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Whenever circumstances require it for convenience, the subject matter of the present invention will be described as being divided into a plurality of sections or embodiments. However, unless otherwise specified in particular, they are not irrelevant to one another. One has to do with modifications, details and supplementary explanations of some or all of the others.

When reference is made to a number of elements or the like (including the number of pieces, numerical values, quantity, range, etc.) in the following description of the embodiments, the number is not limited to a specific number and may be greater than or less than or equal to the specific number, unless otherwise specified in particular and definitely limited to the specific number in principle. It is also needless to say that components (including element or factor steps, etc.) employed in the following embodiments are not always essential, unless otherwise specified in particular and considered to be definitely essential in principle. Similarly, when reference is made to shapes, positional relations and the like of the components or the like in the following description of the embodiments, they will include ones substantially analogous or similar to their shapes or the like, unless otherwise specified in particular and considered not to be definitely so in principle. This similarly applies even to the above-described numerical values and ranges. Those elements each having the same function in all of the drawings are respectively given the same reference numerals, and a repetitive description thereof will therefore be omitted. In the embodiments, a MOS.cndot.FET (Metal Oxide Semiconductor Field Effect Transistor) shown with a field effect transistor, as typical, is abbreviated as "MOS", a p channel type MIS.cndot.FRT is abbreviated as "pMIS" and an n channel type MIS.cndot.FET is abbreviated as "nMIS". The embodiments of the present invention will hereinafter be described in detail on the basis of the drawings.

First Preferred Embodiment

A semiconductor device according to a first embodiment of the present invention operates as a non-insulated DC-DC converter of the type used in a power supply circuit of an electronic apparatus like, for example, a desk top personal computer, a notebook-size personal computer, a server or a game machine or the like. FIG. 1 shows one example of a circuit diagram of the non-insulated DC-DC converter 1. The non-insulated DC-DC converter 1 includes a control circuit 2, driver circuits (first and second control circuits) 3a and 3b, power MOSs (first and second field effect transistors) Q1 and Q2, a Schottky barrier diode (first diode) D1, a coil L1 and a capacitor C1, etc.

The control circuit 2 is a circuit which supplies a signal for controlling the voltage switch-on widths (on time) of the power MOSs Q1 and Q2. The control circuit 2 is packaged aside from the power MOSs Q1 and Q2. The output (corresponding to a terminal for the control signal) of the control circuit 2 is electrically connected to corresponding inputs of the driver circuits 3a and 3b. The outputs of the driver circuits 3a and 3b are electrically connected to corresponding gates of the power MOSs Q1 and Q2. The driver circuits 3a and 3b consist of circuits which respectively control the potentials applied to the gates of the power MOSs Q1 and Q2 in accordance with the control signal supplied from the control circuit 2 to thereby control the operations of the power MOSs Q1 and Q2. The driver circuits 3a and 3b are respectively formed of a CMOS inverter circuit, for example. One example of a circuit diagram of the driver circuit 3a is shown in FIG. 2. The driver circuit 3a has a circuit configuration wherein a p channel power MOS Q3 and an n channel power MOS Q4 are complementary-connected in series. The driver circuit 3a is controlled based on a control input signal IN1, and it controls the level of an output signal OUT1 through the power MOS Q1. Incidentally, symbol G indicates a gate, symbol D indicates a drain and symbol S indicates a source. Since the driver circuit 3b is substantially identical in operation to the driver circuit 3a, its description is omitted.

The power MOSs Q1 and Q2 shown in FIG. 1 are series-connected between a terminal (first power supply terminal) ET1 for the supply of an input power supply potential (first power supply potential) Vin and a terminal (second power supply terminal) for the supply of a reference potential (second power supply potential) GND. That is, the power MOS Q1 is provided in such a manner that its source-drain path is connected in series between the terminal ET1 and an output node (output terminal) N1. The power MOS Q2 is provided in such a manner that its source-drain path is connected in series between the output node N1 and the terminal for the supply of the ground potential GND. The input power supply potential Vin ranges from about 5 to 12V, for example. The reference potential GND, for example, is a power supply potential lower than the input power supply potential, e.g., 0 (zero)V corresponding to ground potential. The operating frequency (corresponding to a cycle or period in which each of the power MOSs Q1 and Q2 is turned on and off) of the non-insulated DC-DC converter 1 is about 1 MHz, for example.

The power MOS Q1 is a power transistor for a highside switch (high potential side: first operating voltage), and it has a switch function for storing energy into the coil L1 that supplies power to the output (the input of a load circuit 4) of the non-insulated DC-DC converter 1. The power MOS Q1 is formed of a vertical field effect transistor whose channel is formed in the direction of thickness of a semiconductor chip. According to the discussions of the present inventors, switching losses (turn-on loss and turn-off loss) greatly appear in sight in the power MOS Q1 due to each parasitic capacitance added to the power MOS Q1 as the operating frequency of the non-insulated DC-DC converter 1 becomes higher. It is thus desirable to normally employ a horizontal field effect transistor, whose channel is formed along a main surface (surface intersecting the thickness direction of the semiconductor chip) of the semiconductor chip, as the field effect transistor for the highside switch in consideration of the switching losses. This is because, since a horizontal field effect transistor is smaller than a vertical field effect transistor in terms of the area in which a gate electrode and a drain region overlap each other, the parasitic capacitance (gate parasitic capacitance) added between the gate and drain can be reduced. However, when an attempt is made to obtain a resistance (on resistance) formed at the operation of the horizontal field effect transistor at approximately the same value as the vertical field effect transistor, the cell area of the horizontal field effect transistor must be increased to be greater than or equal to about 2.5 times the cell area of the vertical field effect transistor. Therefore, it brings about a disadvantage in achieving a device size reduction. On the other hand, the channel width per unit area can be increased in the vertical field effect transistor, as compared with the horizontal field effect transistor, and its on resistance can be reduced. That is, the formation of the power MOS Q1 by the vertical field effect transistor makes it possible to realize a device size reduction and bring the packaging to a smaller size.

On the other hand, the power MOS Q2 is a power transistor for a lowside switch (low potential side: second operating voltage). Further, the power MOS Q2 is a rectifying transistor of the non-insulated DC-DC converter 1, and it has the function of performing rectification in sync with a frequency sent from the control circuit 2 with its resistance being held low. The power MOS Q2 is formed of a vertical power MOS whose channel is formed along the direction of thickness of the semiconductor chip in a manner similar to the power MOS Q1. This results from the following reasons, for example. FIG. 3 shows one example of a timing chart of the non-insulated DC-DC converter 1. Ton indicates the pulse width at the turning on of the power MOS Q1 for the highside switch, and T indicates the pulse cycle. As shown in FIG. 3, the power MOS Q2 for the lowside switch is longer than the power MOS Q1 for the highside switch in its on time (the time during which the voltage is being applied). Therefore, since a loss caused by the on resistance of the power MOS Q2, rather than the switching losses, greatly appear in sight in the power MOS Q2, it is advantageous to employ a vertical field effect transistor whose channel width per unit area can be increased, as compared with the horizontal field effect transistor. That is, since the on resistance can be reduced by forming the power MOS Q2 for the lowside switch using a vertical field effect transistor, the voltage conversion efficiency can be enhanced even though the current that flows through the non-insulated DC-DC converter 1 increases.

The output node N1 for supplying an output power supply potential to the outside is provided between wirings for connecting the source of the power MOS Q1 of the non-insulated DC-DC converter 1 shown in FIG. 1 and the drain of the power MOS Q2 thereof. The output node N1 is electrically connected to the coil L1 through an output wiring, and it is electrically connected to the load circuit 4 through an output wiring. The Schottky barrier diode D1, which has a lower forward voltage Vf than a parasitic diode Dp of the power MOS Q2, is electrically connected between the output wiring for connecting the output node N1 and the coil L1 and the terminal for the supply is of the reference potential GND so as to be parallel with the power MOS Q2. The anode of the Schottky barrier diode D1 is electrically connected to the terminal for the supply of the reference potential GND, whereas the cathode thereof is electrically connected to the output wiring for connecting the coil L1 and the output node N1. Connecting the Schottky barrier diode D1 in this way makes it possible to reduce the voltage drop at the dead time when the power MOS Q2 is turned off and to reduce a conduction loss in its diode. The diode recovery loss can be reduced by making a reverse recovery time (trr) fast.

The capacitor C1 is electrically connected between the output wiring for connecting the coil L1 and the load circuit 4 and the terminal for the supply of the reference potential GND. As the load circuit 4, a CPU (Central Processing Unit) or DSP (Digital Signal Processor) or the like of the electronic apparatus can be illustrated by way of example. Terminals ET2 and ET3 shown in FIG. 1 are terminals for supplying power supply voltages to the drivers 3a and 3b, respectively.

In such a circuit, the conversion of the power supply voltage is performed by alternately turning the power MOSs Q1 and Q2 on/off while being synchronized with each other. That is, when the power MOS Q1 for the highside switch is on, a current (first current) I1 flows from the terminal ET1, which is electrically connected to the drain of the power MOS Q1, to the output node N1 via the power MOS Q1. When the power MOS Q1 for the highside switch is off, a current I2 flows due to a back electromotive voltage of the coil L1. Turning on the power MOS Q2 for the lowside switch, when the current I2 is flowing, enables a reduction in the voltage drop. The current I1 is a large current of about 20A, for example.

One example of the packaging configuration of a non-insulated DC-DC converter discussed by the present inventors is shown in FIG. 4. In the non-insulated DC-DC converter 50A, a power MOS Q1 for a highside switch, a power MOS Q2 for a lowside switch, driver circuits 3a and 3b and a Schottky barrier diode D1 are respectively formed in discrete or separate semiconductor chips 5a through 5d, and they are respectively encapsulated in separate packages 6a through 6d. Then, the respective packages 6a through 6d are electrically connected to one another through wirings of a wiring board over which the packages 6a through 6d are mounted. However, it has been found by the present inventors that the following problems arise in such a package configuration.

The first problem is that, since the Schottky diode D1 is provided in the discrete package, the path of the wiring for electrically connecting the cathode of the Schottky barrier diode D1 and the output wiring of the DC-DC converter, and the path of the wiring for electrically connecting the anode of the Schottky barrier diode D1 and the ground wiring become long, to thereby increase the parasitic inductances Lk and La on these wirings, with the result that the effect of an improvement in the voltage conversion efficiency is reduced due to the connection of the Schottky barrier diode D1. That is, it is a problem that the commutation of a load current into the Schottky barrier diode D1 during the dead time (a period in which both power MOSs Q1 and Q2 are turned off) of the non-insulated DC-DC converter 1 is inhibited by the wiring inductances Lk and La, so that even though the Schottky barrier diode D1, which has a lower forward voltage Vf than the parasitic diode Dp, is connected, a sufficient effect cannot be obtained upon a reduction in diode c