Semiconductor device reducing power consumption in standby mode Number:7,436,205 from the United States Patent and Trademark Office (PTO) owispatent A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the "H" and "L" levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the "H" level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the "L" and "H" levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.<H Semiconductor, consumption, Semiconductor, d, 7436205.html, Patent, pto, 7436205

Title: Semiconductor device reducing power consumption in standby mode

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the "H" and "L" levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the "H" level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the "L" and "H" levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Patent Number: 7,436,205 Issued on 10/14/2008 to Tada

Inventors: Tada; Akira (Tokyo, JP)
Assignee: Renesas Technology Corp. (Tokyo, JP)

Appl. No.: 11/708,458

Filed: February 21, 2007

Foreign Application Priority Data


Feb 24, 2006 [JP]			2006-049014

Current U.S. Class: 326/33 ; 326/81; 327/544

Current International Class: H03K 17/16 (20060101)

Field of Search: 326/33-35,81-83,86,95,98,112-113 327/544 365/226-229

References Cited [Referenced By]

U.S. Patent Documents


6049245	April 2000	Son et al.
6285213	September 2001	Makino
6556071	April 2003	Notani et al.
7164616	January 2007	Miller et al.
7345947	March 2008	Miller et al.
7355455	April 2008	Hidaka
2004/0004499	January 2004	Yonemaru

Foreign Patent Documents


9-064715	Mar., 1997	JP
9-321600	Dec., 1997	JP
2000-059200	Feb., 2000	JP

Other References

Suhwan Kim et al., "Experimental Measurement of a Novel Power Gating Structure With Intermediate Power Saving Mode", Proceedings of the 2004 International Symposium on Low Power Electronics and Design (ISLPED'04), 2004, pp. 20-25. cited by other .
Norio Hama et al., "SOI Circuit Technology For Batteryless Mobile System With Green Energy Sources", Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 2002, pp. 280-283. cited by other.

Primary Examiner: Barnie; Rexford
Assistant Examiner: Lo; Christopher
Attorney, Agent or Firm: Buchanan, Ingersoll & Rooney PC

Claims

What is claimed is:

1. A semiconductor device comprising: a first voltage interconnection supplying a first voltage; a second voltage interconnection supplying a second voltage; a third voltage interconnection supplying a third voltage; a first voltage supply interconnection arranged between said first and second voltage interconnections; an internal circuit connected between said second voltage interconnection and said first voltage supply interconnection, and forming a current path between said second voltage interconnection and said first voltage supply interconnection according to an input signal; and a first voltage supply control circuit connected between said first voltage interconnection and said first voltage supply interconnection, and being capable of controlling a conductive state between said first voltage interconnection and said first voltage supply interconnection according to an input instruction signal, wherein said first voltage supply control circuit includes: a first switch arranged between said first voltage supply interconnection and said first voltage interconnection, and a first logic circuit controlling said first switch according to said instruction signal; and said first logic circuit includes: a second switch arranged between said third voltage interconnection and a control end of said first switch, and electrically coupling said third voltage interconnection to the control end of said first switch according to an instruction signal setting said first switch to a conductive state, and a third switch arranged between said first voltage supply interconnection and the control end of said first switch, and electrically coupling said first voltage supply interconnection to the control end of said first switch when said first switch attains a non-conductive state with a lower amount of current than in a conductive state caused by said second switch attaining a non-conductive state.

2. The semiconductor device according to claim 1, wherein said first and third voltage interconnections are electrically coupled together, and said first and third voltages are at the same level, the control ends of said second and third switches of said first logic circuit are electrically coupled together, and receives the same instruction signal, said second switch of said first logic circuit is formed of a field-effect transistor of a first conductivity type, said third switch of said first logic circuit is formed of a field-effect transistor of a second conductivity type.

3. The semiconductor device according to claim 1, wherein said first switch is formed of a field-effect transistor, and said field-effect transistor has a gate electrically coupled to a body region or a substrate region of said field-effect transistor.

4. The semiconductor device according to claim 1, wherein said first switch is formed of a field-effect transistor, and a predetermined bias voltage is applied to a body region or a substrate region of said field-effect transistor.

5. The semiconductor device according to claim 1, wherein said first logic circuit controls said first switch according to a plurality of said instruction signals, said second switch electrically couples said third voltage interconnection to the control end of said first switch based on a combination of a plurality of said instruction signals provided for setting said first switch to the on state, and said third switch electrically couples the control end of said first switch to said first voltage supply interconnection based on a combination of a plurality of said instruction signals provided for setting said first switch to the off state.

6. The semiconductor device according to claim 1, wherein said first voltage supply control circuit includes a second logic circuit controlling said first switch in response to said instruction signal; and said second logic circuit includes: a fourth switch arranged between said third voltage interconnection and the control end of said first switch, and electrically coupling said third voltage interconnection to the control end of said first switch according to said instruction signal setting said first switch to the conductive state, and a fifth switch arranged between said first voltage supply interconnection and the control end of said first switch, and electrically coupling said first voltage supply interconnection to the control end of said first switch when said first switch attains a non-conductive state with a lower amount of current than in a conductive state caused by said fourth switch attaining a non-conductive state.

7. The semiconductor device according to claim 1, wherein said first voltage supply control circuit includes: a fourth switch arranged between said first voltage supply interconnection and said first voltage interconnection, and a second logic circuit controlling said fourth switch according to said instruction signal.

8. The semiconductor device according to claim 1, wherein said first voltage supply control circuit further includes a fourth switch arranged between said first voltage supply interconnection and said first voltage interconnection, and having a control end electrically coupled to the control end of said first switch.

9. The semiconductor device according to claim 1, wherein said first voltage supply control circuit further includes a fourth switch controlling connection between the control end of said first switch and said first voltage supply interconnection via said third switch in response to a first control signal.

10. The semiconductor device according to claim 9, wherein the voltage signal level of said first control signal of said fourth switch is adjustable.

11. The semiconductor device according to claim 10, wherein said first voltage supply interconnection is set to an intermediate potential between said first and second voltages according to the voltage signal level of said first control signal.

12. The semiconductor device according to claim 9, wherein said first voltage supply control circuit further includes a fifth switch connecting a connection node between said third and fourth switches to said first voltage interconnection in response to a second control signal.

13. The semiconductor device according to claim 1, wherein said first voltage supply control circuit further includes a resistance arranged between the control end of said first switch and said first voltage supply interconnection via said third switch.

14. The semiconductor device according to claim 1, further comprising: a second voltage supply interconnection arranged between said first and second voltage interconnections; and a second voltage supply control circuit connected between said second voltage interconnection and said second voltage supply interconnection, and being capable of controlling a state of electrical conduction between said second voltage interconnection and said second voltage supply interconnection according to said instruction signal, wherein said second voltage supply control circuit includes: a fourth switch arranged between said second voltage supply interconnection and said second voltage interconnection, and a second logic circuit controlling said fourth switch according to said instruction signal; and said second logic circuit includes: a fifth switch arranged between said first voltage interconnection and a control end of said fourth switch, and electrically coupling said first voltage interconnection to the control end of said fourth switch according to said instruction signal setting said fourth switch to an on state, and a sixth switch arranged between said second voltage supply interconnection and the control end of said fourth switch, and electrically coupling said second voltage supply interconnection to the control end of said fourth switch when said fourth switch attains a non-conductive state with a lower amount of current than in a conductive state caused by said fifth switch attaining a non-conductive state.

15. The semiconductor device according to claim 1, wherein said first switch is arranged in a first circuit block region, and said second and third switches are arranged in a second circuit block region different from said first circuit block region.

16. The semiconductor device according to claim 1, wherein said instruction signal includes a plurality of input instruction signals, and at least one of said first to third switches operates in response to reception of a plurality of said input instruction signals.

17. The semiconductor device according to claim 1, wherein said internal circuit corresponds to a memory array having a plurality of memory cells.

18. The semiconductor device according to claim 17, wherein each of said memory cells includes a flip-flop circuit for setting first and second storage nodes to different potential levels according to data to be stored, respectively; said flip-flop circuit includes: a first transistor arranged between said second voltage and said first storage node, and having a gate electrically coupled to said second storage node, a second transistor arranged between said voltage supply interconnection and said first storage node, and having a gate electrically coupled to said second storage node, a third transistor arranged between said second voltage and said second storage node, and having a gate electrically coupled to said first storage node, and a fourth transistor arranged between said voltage supply interconnection and said second storage node, and having a gate electrically coupled to said first storage node; said first switch is turned off in response to said instruction signal in a data write operation; and said first voltage supply interconnection is set to an intermediate potential between said first and second voltages.

19. The semiconductor device according to claim 17, wherein said internal circuit includes a plurality of said memory arrays; and said semiconductor device further comprises: a plurality of said first voltage supply interconnections corresponding to said plurality of memory arrays, respectively, and a plurality of said voltage supply control circuits corresponding to said plurality of first voltage supply interconnections, respectively, each connected between said first voltage interconnection and the corresponding first voltage supply interconnection, and each being capable of controlling a conductive state between said first voltage interconnection and the corresponding first voltage supply interconnection according to an instruction signal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. Particularly, the invention relates to a semiconductor device having a structure that interrupts electric connections of power and ground lines to logic circuits or the like in a standby mode, and is pertinent to a semiconductor device that can reduce power consumption in the standby mode.

2. Description of the Background Art

In recent years, degrees of integration as well as performance of semiconductor devices have been developing, and application ranges thereof have been increasing. With these situations, it has been technically required to reduce power consumption of semiconductor devices and semiconductor chip bodies. More specifically, it is required to increase a battery operation time of an internal battery in a data information device that includes a telephone, an electronic notebook and a small personal computer in an integrated fashion. In information processing devices of high performance, it is required to reduce sizes of a cooling device and a power supply device. Since effective use of energy resources has been socially demanded for protecting the global environment, the reduction in power consumption of the semiconductor devices as well as the improvement of the performance have been important constituent techniques for high value addition to the semiconductor devices.

As an example of such techniques, there has been a semiconductor device using multiple kinds of thresholds, i.e., a multi-threshold CMOS which will be referred to as an "MTCMOS" hereinafter. The MTCMOS circuit is formed of a logic circuit group and transistors of high threshold voltages, and can prevent increase in power consumption of the logic circuit group formed of CMOSs when the logic circuit group is on standby. In connection with this, Japanese Patent Laying-Open Nos. 09-064715, 09-321600 and 2000-059200 have disclosed various manners that can reduce the power consumption in the standby mode.

More specifically, a logic circuit group includes one or a plurality of logic gate(s), each of which is formed of a P-channel MOS transistor having a threshold voltage of a small absolute value and an N-channel MOS transistor having a low threshold voltage of the small absolute value.

FIG. 38 shows a conventional MTCMOS circuit.

Referring to FIG. 38, a logic circuit group L1 includes a P-channel MOS transistor P2 of a low threshold voltage and an N-channel MOS transistor Q1 of a low threshold voltage, which are connected between a pseudo power supply line VA on a high potential side and a pseudo ground line VB on a low potential side.

Pseudo power supply line VA is connected via a P-channel MOS transistor P1 having a high threshold to a power supply voltage Vcc provided from a power supply line VL. Pseudo ground line VB is connected via an N-channel MOS transistor Q2 having a high threshold to a ground voltage GND provided from a ground line GL. Transistor P1 receives on its gate a control signal /Sleep, and transistor Q2 receives on its gate an inverted signal of control signal /Sleep provided via an inverter IV.

Inverter IV is formed of P- and N-channel MOS transistors PT1 and NT1 connected between power supply voltage Vcc and ground voltage GND. A connection node N1 between transistors PT1 and NT1 is electrically coupled to a gate of transistor Q2. This MTCMOS circuit operates as follows. In an active mode, control signal /Sleep is set to an "L" level, and transistors P1 and Q2 are turned on so that pseudo power supply line VA and pseudo ground line VB are electrically coupled to power supply voltage Vcc and ground voltage GND, respectively.

Thereby, pseudo power supply line VA and pseudo ground line VB are supplied with the required voltages via low-resistance paths, respectively, and thereby can perform predetermined circuit operations.

In the standby mode, control signal /Sleep is set to an "H" level so that transistors P1 and Q2 are turned off.

Therefore, power supply voltage Vcc and pseudo power supply line VA are electrically isolated. Likewise, ground voltage GND and pseudo ground line VB are electrically isolated.

Thereby, transistors P1 and Q2 significantly reduce a leak current in the whole circuit.

In general, a lower threshold voltage of a transistor lowers a leak current preventing capability. Thus, the power consumption increases in transistors P2 and Q1. Therefore, this circuit structure reducing the leak currents in transistors P1 and Q2 can reduce the power consumption in the standby mode. More specifically, even when logic circuit group L1 uses, e.g., transistors of a low threshold voltage, the leak current in the transistors of the logic circuit group can be suppressed so that the power consumption of the whole circuit can be reduced.

During the standby period of the above circuit structure, pseudo power supply line VA and pseudo ground line VB are electrically isolated from power supply Vcc and ground voltage GND provided from power supply line and ground line, respectively, and are set to a high-impedance state. Therefore, small amounts of currents continuously leak to pseudo power supply line VA and pseudo ground line VB via the transistors forming logic circuit group L1 with the passage of time. The leak current occurs because logic circuit group L1 is formed of the transistors of low threshold voltages as described above, and the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other.

When logic circuit group L1 is formed of a sequential circuit or the like such as a register circuit, a latch circuit or a flip-flop circuit that can store a logical state, and a standby period is long, a potential difference that can hold the logic state may not ensured between pseudo power supply line VA and pseudo ground line VB. Thus, stored information may be lost. Consequently, the semiconductor device cannot be restored to the original state even when it enters an active mode after the standby period. In logic circuits or the like other than the circuit that is required to store the logic state, such a state may be allowed that the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other.

Referring to FIG. 39, another MTCMOS circuit in the prior art will now be described.

The MTCMOS circuit in FIG. 39 differs from the structure in FIG. 38 in that a transistor P3 is additionally arranged in parallel with transistor Q2 and between a node N0 and ground voltage GND. Other structures are substantially the same, and description thereof is not repeated.

Referring to FIG. 40, description will now be given on the case where the potential level of pseudo ground line VB in FIGS. 38 and 39 rises with time.

Referring to FIG. 40, the leak current on the side of power supply voltage Vcc supplied via logic circuit group L1 raises the potential level of pseudo ground line VB in the structure of FIG. 38 with time as illustrated by dotted line in FIG. 40. A balanced state is attained when the leak current on the side of power supply voltage Vcc is balanced with the leak current passing through the transistor. In this case, the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other as already described.

In the structure of FIG. 39, transistor P3 is supplied on its gate with a control signal SV (at the "L" level) in the standby mode. Thereby, the potential of pseudo ground line VB rises to a potential level near the threshold voltage of transistor P3 so that transistor P3 starts to be turned on, and the current starts to flow from pseudo ground line VB via transistor P3. Thus, when the potential of node N0 rises to the threshold voltage of transistor P3, transistor P3 is fully turned on. If the potential is lower than it, the degree of the turn-on of transistor P3 is small.

Therefore, as illustrated in solid line in FIG. 40, the potential of node N0 attains the balanced state when it attains a level keeping the balance between the quantity of the current passing to pseudo ground line VB through logic circuit group L1 and the quantity of the current passing to ground voltage GND through transistor P3. This balanced potential depends on the threshold voltage of transistor P3, a transistor width and others. Thus, the potential level of pseudo ground line VB can be adjusted owing to provision of transistor P3. This structure is disclosed by Suhwan Kim, Stephen V. Kosonocky, Daniel R, Knebel, and Kevin Stawiasz, "Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode," Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 20-25, 2004.

However, even in either of the case where transistor P3 in FIG. 39 is employed to adjust the potential level, and the case where transistor P3 is not employed, the charging current that flows immediately after the start of the standby mode until a balanced state and thus a certain predetermined balanced potential are attained is pulling from power supply voltage Vcc by the leak current flowing through logic circuit group L1.

Therefore, when the power consumption can be reduced during the above period, the power consumption can be further reduced.

SUMMARY OF THE INVENTION

The invention has been made for overcoming the above problems, and it is an object of the invention to provide a semiconductor device that can reduce power consumption.

A semiconductor device according to the invention includes a first voltage interconnection supplying a first voltage; a second voltage interconnection supplying a second voltage; a third voltage interconnection supplying a third voltage; a first voltage supply interconnection arranged between the first and second voltage interconnections; an internal circuit connected between the second voltage interconnection and the first voltage supply interconnection, and forming a current path between the second voltage interconnection and the first voltage supply interconnection according to an input signal; and a first voltage supply control circuit connected between the first voltage interconnection and the first voltage supply interconnection, and being capable of controlling a state of electrical conduction between the first voltage interconnection and the first voltage supply interconnection according to an input instruction signal. The first voltage supply control circuit includes a first switch arranged between the first voltage supply interconnection and the first voltage interconnection, and a first logic circuit controlling the first switch according to the instruction signal. The first logic circuit includes a second switch arranged between the third voltage interconnection and a control end of the first switch, and electrically coupling the third voltage interconnection to the control end of the first switch according to an instruction signal setting the first switch to an on state; and a third switch arranged between the first voltage supply interconnection and the control end of the first switch, and electrically coupling the first voltage supply interconnection to the control end of the first switch according to an instruction signal attaining an off state of passing a smaller quantity of current through the first switch than the on state.

The semiconductor device according to the invention includes the internal circuit forming the current path between the second voltage interconnection and the first voltage supply interconnection; and the first voltage supply control circuit capable of controlling the state of electrical conduction between the first voltage supply interconnection and the first voltage interconnection. The first voltage supply control circuit includes the first switch arranged between the first voltage supply interconnection and the first voltage interconnection, the second switch arranged between the third voltage interconnection and the control end of the first switch, and electrically coupling the third voltage interconnection to the control end of the first switch according to the instruction signal turning on the first switch, and the third switch electrically coupling the first voltage supply interconnection to the control end of the first switch according to the instruction signal attaining the off state of passing a smaller quantity of current through the first switch than the on state. When the first switch is turned on according to the instruction signal, the control end of the first switch is charged by a third voltage. When the first switch is turned off according to the instruction signal, the third switch electrically couples the first voltage supply interconnection to the control end of the first switch to discharge the charges. Thereby, the current path of the internal circuit arranged between the first and second voltage interconnections can reduce the quantity of charges pulled out from the second voltage interconnection, and thereby can reduce the power consumption. Since the third switch is connected to the first voltage interconnection through the first switch, a current interrupting effect of the first switch can reduce the leak current leaking to the first voltage interconnection via the third switch. Therefore, the leak current of the first voltage supply control circuit can be reduced, and the current consumption of the whole circuit can be reduced.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic structure of a semiconductor device according to a first embodiment of the invention.

FIGS. 2A-2C illustrate an MTCMOS circuit according to the first embodiment of the invention.

FIG. 3 shows an example of an arithmetic and logic unit forming a logic circuit group L1.

FIG. 4 illustrates a voltage level of a pseudo ground line of the MTCMOS circuit according to the first embodiment of the invention.

FIG. 5 illustrates an MTCMOS circuit according to a first modification of the first embodiment of the invention.

FIG. 6 illustrates another voltage supply control circuit according to the first modification of the first embodiment of the invention.

FIG. 7 illustrates a transistor according to the first modification of the first embodiment of the invention.

FIGS. 8A and 8B illustrate a transistor having a T-shaped gate.

FIGS. 9A and 9B illustrate a transistor having a partially trench-isolated structure.

FIGS. 10-14 illustrate MTCMOS circuits according to second to sixth modifications of the first embodiment of the invention, respectively.

FIG. 15 illustrates a voltage level of a pseudo ground line of the MTCMOS circuit according to the sixth modification of the first embodiment of the invention.

FIGS. 16 and 17 illustrate MTCMOS circuits according to seventh and eighth modifications of the first embodiment of the invention, respectively.

FIG. 18 illustrates a voltage level of a pseudo ground line of the MTCMOS circuit according to the eighth modification of the first embodiment of the invention.

FIGS. 19 and 20 illustrate MTCMOS circuits according to ninth and tenth modifications of the first embodiment of the invention, respectively.

FIGS. 21A, 21B and 21C illustrate a voltage supply control circuit according to an eleventh modification of the first embodiment of the invention.

FIG. 22 shows a schematic structure for partially illustrating a storage according to a second embodiment of the invention.

FIG. 23 illustrates a circuit structure of a memory cell according to the second embodiment of the invention.

FIG. 24 specifically illustrates a layout structure of a lower layer region of the memory cell according to the second embodiment of the invention.

FIGS. 25, 26 and 27 specifically illustrate layout structures in which first, second and third metal interconnection layers are formed at upper layer regions of the memory cell according to the second embodiment of the invention, respectively.

FIG. 28 illustrates a structure in which a voltage supply control circuit is arranged for a pseudo ground line of the memory cell according to the second embodiment of the invention.

FIG. 29 illustrates a voltage level of the pseudo ground line in standby and active modes.

FIG. 30 illustrates the voltage level of the pseudo ground line in data write, data read and Nop states.

FIG. 31 illustrates a relationship between potentials of various nodes in an operation of writing inverted data of data stored in the memory cell.

FIG. 32 illustrates a structure having a voltage supply control circuit corresponding to each of memory arrays according to a second modification of the second embodiment of the invention.

FIGS. 33A and 33B illustrate an MTCMOS circuit according to a third embodiment of the invention.

FIGS. 34A and 34B illustrate other structures of switches.

FIG. 35 illustrates an MTCMOS circuit according to a fourth embodiment of the invention.

FIG. 36 illustrates an MTCMOS circuit according to a first modification of the fourth embodiment of the invention.

FIG. 37 illustrates an MTCMOS circuit according to a second modification of the fourth embodiment of the invention.

FIG. 38 illustrates a conventional MTCMOS circuit.

FIG. 39 illustrates another conventional MTCMOS circuit.

FIG. 40 illustrates a potential level of a pseudo ground line in FIGS. 38 and 39 rising with time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will now be described with reference to the drawings. In the following description, the same or corresponding portions bear the same reference numbers, and description thereof is not repeated.

First Embodiment

Referring to FIG. 1, a semiconductor device 10 according to a first embodiment of the invention includes a CPU 50 controlling a whole circuit, a storage 15 having a memory for storing information, a controller 20 that is a peripheral circuit for producing a clock signal or a control signal, and a logic unit 100 for executing various arithmetic and logic operations.

In general, the semiconductor device is provided at its peripheral region with pads, and is supplied via the pads with, e.g., a power supply voltage, a ground voltage, external instruction signals and the like. In this example, FIG. 1 shows a power supply voltage pad PDV supplied with a power supply voltage Vcc, a ground voltage pad PDG supplied with a ground voltage GND and pads PD supplied with other voltages, external instruction signals and the like.

FIG. 1 shows, by way of example, a ground line GL for supplying the ground voltage for the circuits via ground voltage pad PDG. There is also arranged a power supply line VL for supplying power supply voltage Vcc for the circuits via power supply voltage pad PDV. Power supply voltage Vcc and ground voltage GND in the following description are supplied from power supply line VL and ground line GL, i.e., voltage interconnections supplying the voltages, respectively. Although one interconnection is described by way of example as each of the voltage interconnections supplying power supply voltage Vcc and ground voltage GND, respectively, the voltage interconnections are employed corresponding to the types of the voltage levels to be supplied.

Referring to FIGS. 2A-2C, an MTCMOS circuit according to the first embodiment of the invention will now be described. A logic circuit group L1 included in logic unit 100 will be described as a typical example of an internal circuit included in semiconductor device 10.

Referring to FIG. 2A, the MTCMOS circuit according to the first embodiment of the invention includes logic circuit group L1, a transistor P1 having a threshold voltage larger in absolute value than those of transistors forming logic circuit group L1, and a voltage supply control circuit VBC arranged between ground voltage GND supplied from ground line GL and a pseudo ground line VB. Pseudo ground line VB supplies ground voltage GND to logic unit 100, and forms a voltage supply interconnection.

Voltage supply control circuit VBC includes a transistor Q2 as well as P- and N-channel MOS transistors 1 and 2. The P- and N-channel MOS transistors may be merely referred to as the "transistors" hereinafter. Transistors 1 and 2 are arranged between a power supply voltage Vcc2 and a node N0 with a node N1 arranged therebetween. Transistors 1 and 2 form a logic circuit LC0. Each of transistors 1 and 2 receives on its gate a control signal /Sleep. Transistor Q2 is arranged between node N0 and ground voltage GND, and has a gate electrically coupled to node N1. Control signal /Sleep is input according to an active mode and a standby mode of the circuit and, in this embodiment, is provided, e.g., from CPU 50.

The active mode indicates a state in which logic circuit group L1 can operate to output signals according to a signal (e.g., a control signal provided from CPU 50, a clock signal or the like) provided to logic circuit group L1, and provides a signal. In other words, it indicates a state in which an operation current is passed by a switching operation of turning on and of the transistors forming logic circuit group L1. In the description of the embodiment, "on" of the transistor indicates a conductive state, and "off" indicates a non-conductive state.

The standby mode indicates a state in which the circuits forming logic circuit group L1 are not operating and, in other words, indicates an off state in which operation currents do not flow through the transistors forming logic circuit group L1. Usually, an off current of the like of the transistor i.e., a current that is smaller in quantity than the operation current of the transistor in the active mode flows through the transistor forming logic circuit group L1.

When the semiconductor device (chip) is a semiconductor storage device such as an SRAM, such operations are performed in the active mode that a signal activating the semiconductor device (e.g., an activating signal for a chip select signal) is externally provided to the semiconductor device, and data reading or data writing is effected on memory cells. In the standby mode, such operations are performed that a signal deactivating the semiconductor device (e.g., a deactivating signal for the chip select signal) is externally provided to the semiconductor device, and memory cells hold data thereof.

Although this example shows a structure in which the voltage interconnections, i.e., power supply lines different from each other supply two power supply voltages Vcc1 and Vcc2, respectively, and the voltages are set, e.g., to 1.8V. However, the voltage values may be different from each other. For example, a threshold voltage Vth of a smaller absolute value of the transistor is from 0.3 V to 0.35 V. Threshold voltage Vth of a larger absolute value of the transistor is from 0.4 V to 0.45 V.

The following description will be primarily given on the MTCMOS circuit that includes logic circuit group L1 formed of the transistors of a low threshold voltage and voltage supply control circuit VBC formed of the transistors of a high threshold voltage. However, voltage supply control circuit VBC according to the invention can be applied to structures other than the above MTCMOS circuit. Thus, it can be applied to the case in which the transistors forming logic circuit group L1, transistor P1 and the transistors (transistors Q2, 1) forming voltage supply control circuit VBC have the same threshold voltage. This is true also with respect to the following modification and embodiments.

An operation of the MTCMOS circuit according to the first embodiment of the invention will now be described.

In the active mode, control signal /Sleep is at the "L" level. Thereby, transistor P1 is on and electrically couples power supply voltage Vcc1 to a pseudo power supply line VA. Pseudo power supply line VA supplies power supply voltage Vcc1 to logic unit 100, and forms a voltage supply interconnection.

Since control signal /Sleep provided to voltage supply control circuit VBC is at the "L" level, transistor 1 is turned on to couple electrically power supply voltage Vcc2 to node N1, and transistor Q2 is turned on. Thereby, pseudo ground line VB is electrically coupled to ground voltage GND.

Therefore, logic circuit group L1 is supplied with a voltage required for operations, and executes a predetermined operation.

In the standby mode, control signal /Sleep attains the "H" level. Thereby, transistor P1 is turned off to isolate electrically power supply voltage Vcc1 from pseudo power supply line VA.

Control signal /Sleep provided to voltage supply control circuit VBC is at the "H" level so that transistor 2 is turned on, and transistor 1 is turned off.

In this operation, nodes N1 and N0 are electrically coupled together.

In the active mode, since transistor 1 is turned on to couple electrically power supply voltage Vcc2 to node N1, a gate region of transistor Q2 including node N1 has accumulated the charged electric charges.

Therefore, the charged charges in node N1, i.e., the charges charged and stored in the region connected to the gate of transistor Q2 are discharged to node N0 in response to the turn-on of transistor 2. Thereby, the charges accumulated in node N1 are discharged to node N0 immediately after the start of the standby mode, in contrast to the case where the potential level of pseudo ground line VB is gradually charged by the leak current of power supply voltage Vcc1 in the standby mode. Therefore, the quantity of current pulled out from power supply voltage Vcc1 can be small.

In this structure, nodes N0 and N1 are electrically coupled together in the standby mode as described above. Thus, the diode connection is made in transistor Q2. Therefore, when the potential of pseudo ground line VB rises to the voltage level of the threshold voltage of transistor Q2, transistor Q2 starts to be turned on, and the current starts to flow from pseudo ground line VB via transistor Q2. Thus, when the potential of node N1 rises to the threshold voltage of transistor Q2, transistor Q2 is completely turned on. Otherwise, the degree of turn-on is lower than the above.

When the voltage on pseudo ground line VB excessively rises, the above structure operates to lower the voltage on pseudo ground line VB, and has the effect of adjusting the voltage level. Therefore, an additional element P3, which is used in the conventional structure FIG. 39, is not required for adjusting the voltage level, and an area of the circuits can be reduced.

In the above structure, transistor 2 is connected to ground voltage GND via transistor Q2. In the standby mode, the quantity of current flowing through transistor Q2 is smaller than that in the on state. Therefore, the current reducing effect of transistor Q2 can reduce the leak current flowing via transistor 2 to ground voltage GND.

From a result of a simulation of the embodiment, it has been determined that the current can be reduced by 10% as compared with the conventional structure.

Therefore, the leak current of logic circuit LC0 can be reduced, and the power consumption of the whole circuit can be reduced.

Further, the level of the potential of node N0 attains a balanced state when a sum of the quantities of the current flowing to pseudo ground line VB via logic circuit group L1 and the current flowing to pseudo ground line VB via logic circuit LC0 is balanced with a quantity of the current flowing to ground voltage GND via transistor Q2. This balanced potential depends on the threshold voltage, the transistor width and the like of transistor Q2.

Although the description has been given on the structure of FIG. 2A that has transistor P1 arranged between power supply voltage Vcc1 and pseudo power supply line VA, the invention can be likewise applied to a structure of FIG. 2B in which transistor P1 and pseudo power supply line VA are eliminated, and power supply voltage Vcc1 is directly supplied to logic circuit group L1.

The invention can be applied to still another structure of FIG. 2C in which transistor P1 is used as a driver transistor of a voltage down converter VDC.

FIG. 2C shows an example of a structure in which a power supply voltage Vdd of 3.3 V is stepped down to supply a voltage of 1.8 V (=Vcc2) to pseudo power supply line VA. Voltage down converter VDC includes a driver transistor P1, a comparator CP and resistances R1 and R2. Driver transistor P1 is arranged between power supply voltage Vdd and pseudo power supply line VA, and receives an output signal of comparator CP on its gate. Comparator CP makes a comparison between the voltage on an internal node Nd and a reference voltage Vref, and provides a result of the comparison. More specifically, when the voltage on internal node Nd is higher than reference voltage Vref (1.8 V), it provides the output at the "H" level so that driver transistor P1 is turned off. When the voltage on internal node Nd is lower than reference voltage Vref (1.8 V), it provides the output at the "L" level so that drive transistor P1 is turned on. Resistances R1 and R2 are connected in series between power supply voltage Vdd and ground voltage GND with internal node Nd therebetween. The resistance division based on resistances R1 and R2 is adjusted to place the voltage of about 1.8 V on internal node Nd when power supply voltage Vdd is 3.3 V.

According to the above structure, transistor P1 illustrated in FIG. 2A can be used as driver transistor P1 in the final stage of voltage down converter VDC.

Although the following description will be given primarily in connection with the structure in FIG. 2A, the invention can similarly applied to other structures. The description has been given by way of example on the structure in which two power supply voltages Vcc1 and Vcc2 are supplied. However, power supply voltage Vcc is used in the following description for the sake of simplicity.

Referring to FIG. 3, an arithmetic and logic circuit forming logic circuit group L1 will now be described.

FIG. 3 shows a full adder as an example of the arithmetic and logic circuit. More specifically, AND circuits AD1-AD9 and a flip-flop circuit FF are arranged.

AND circuit AD1 provides a result of logical AND between input data IA and IB to one of input nodes of AND circuit AD8. AND circuit AD2 provides a result of logical AND between input data IB and IC0 to one of input nodes of AND circuit AD8. AND circuit AD3 provides a result of logical AND between input data IA and IC0 to one of input nodes of AND circuit AD8. AND circuit AD8 receives results provided from AND circuits AD1-AD3, and provides a result of logical AND of them to flip-flop circuit FF as an output data ICN. Flip-flop circuit FF receives and holds output data ICN provided from AND circuit AD8. When next input data IA and IB are input, flip-flop circuit FF provides output data ICN as input data IC0.

AND circuit AD4 provides a result of logical AND of input data IA, IB and IC0 to one of the input nodes of AND circuit AD9. AND circuit AD5 provides a result of logical AND of the inverted data of input data IC0, the inverted data of input data IB and input data IA to one of input nodes of AND circuit AD9. AND circuit AD6 provides a result of logical AND of the inverted data of input data IC0, input data IB and the inverted data of input data IA to one of input nodes of AND circuit AD9. AND circuit AD7 provides a results of logical AND of input data IC, the inverted data of input data IA and the inverted data of input data IB to one of input nodes of AND circuit AD9. AND circuit AD9 provides a results of the logical AND of the output data of AND circuits AD4-AD7 as output data IS. Output data IS is a sum data of input data IA and IB, and output data ICN is carry data.

Although the full adder has been described as an example of logic circuit group L1, logic circuit group L1 is not restricted to the above structure, and may be formed of various circuits such as inverters, NAND circuits, NOR circuits and the like as well as a combination thereof. Also, it may be formed of arithmetic and logic units (ALUs) such as subtractors, multipliers and the like.

Referring to FIG. 4, description will now be given on the voltage level of the pseudo ground line of the MTCMOS circuit according to the first embodiment of the invention. Waveforms illustrated therein are obtained by a simulation performed with transistor Q2 having a length l of 0.18 .mu.m and a width w of 0.94 .mu.m, transistor 2 having a length l of 0.18 .mu.m and a width of 0.94 .mu.m, transistor 1 having a length l of 0.18 .mu.m and a width of 1.14 .mu.m, and logic circuit group L1 having a current path that is formed of transistors each having a length l of 0.18 .mu.m. Among these transistors, N-channel MOS transistors have a total width (w) of 19.5 .mu.m, and P-channel MOS transistors have a total width (w) of 20.84 .mu.m.

As already described, when the structure merely employs only transistor Q2, the potential level of pseudo ground line VB gradually rises with time, approaches the potential level of pseudo power supply line VA and will attain the balanced state at a predetermined potential level.

Referring to FIG. 4, the conventional structure illustrated in FIG. 39 employs transistor P3 in parallel with transistor Q2 for the purpose of adjusting the potential level of pseudo ground line, and performs the adjustment to lower the balanced potential. According to this configuration, charges are pulled out from the side of power supply voltage Vcc until the balanced potential is attained.

According to the structure of the first embodiment of the invention, however, the charged charges accumulated in node N1 connected to the gate of transistor Q2 can be used for raising the potential of pseudo ground line VB so that the low power consumption can be achieved by efficiently using the charged charges. During the standby, nodes N0 and N1 are electrically coupled to provide diode connection in transistor Q2 so that the potential of pseudo ground line VB can be adjusted to a low level. Therefore, the structure can also achieve the effect of suppressing the potential rising without employing transistor P3.

Therefore, the voltage supply control circuit according to the first embodiment of the invention can reduce the power consumption as compared with the conventional structure. Although transistor P3 for adjusting the balanced potential can be additionally employed, components of the circuits can be reduced in number by eliminating transistor P3, which results in the circuit structure that is advantageous in layout and cost.

First Modification of the First Embodiment

FIG. 5 illustrates an MTCMOS circuit according to a first modification of the first embodiment of the invention.

Referring to FIG. 5, the MTCMOS circuit according to the first modification of the first embodiment of the invention differs from the foregoing structure in that voltage supply control circuit VBC is replaced with a voltage supply control circuit VBCa. Other structures are substantially the same, and therefore description thereof is not repeated.

Voltage supply control circuit VBCa includes a transistor Q2a in place of transistor Q2, and transistor Q2a has a gate electrically coupled to a back gate thereof. When a back gate bias is applied to transistor Q2a, a forward bias is applied to lower a threshold of transistor Q2a.

Therefore, such a situation is attained that even a low voltage level of node N1 can readily turn on transistor Q2a, and this lowers the balanced potential of pseudo ground line VB. Thereby, the balanced potential of pseudo ground line VB can be adjusted. Since the capacity of node N1 increases, the charged charges can raise the potential to a larger extent.

According to the above structure, the balanced potential, e.g., of pseudo ground line VB is adjusted to a low level, and this adjustment can likewise ensure a sufficiently large potential difference between pseudo power supply line VA and pseudo ground line VB. In the active mode, the threshold of transistor Q2a is likewise low, and the circuit operation speed can be high.

Referring to FIG. 6, description will now be given on a voltage supply control circuit VBC# according to a first modification of the first embodiment of the invention.

Referring to FIG. 6, this structure differs from the structure in FIGS. 2A-2C in that voltage supply control circuit VBC is replaced with a voltage supply control circuit VBC#.

Voltage supply control circuit VBC# includes a transistor Q2# in place of transistor Q2, and a bias is directly applied to its back gate in contrast to the structure of electrically coupling the gate and the back gate together as illustrated in FIG. 5. This structure can achieve the substantially same as that illustrated in FIG. 5.

Referring to FIG. 7, description will now be given on transistor Q2# according to the first modification of the first embodiment of the invention.

Referring to FIG. 7, a P-well region 111 is formed in an N-well region 101 formed on a P-type silicon (Si) substrate 105, and N.sup.+-well impurity regions 107 and 108 are formed in P-well region 111 to provide source and drain regions, respectively. An isolating oxide film 102 is formed at a region other than the impurity regions at the well surface. A gate 109 is arranged between the source and drain regions, and is electrically coupled to node N1. The source and drain regions are electrically coupled to ground voltage GND and node N0, respectively. A P-type impurity region 106 is arranged as a back gate voltage in P-well 111, and is supplied with a voltage VG as a back gate bias. The structure of transistor Q2# in which voltage VG is applied to impurity region 106 as a back gate voltage has been described. Transistor Q2a has a similar structure (not shown) except for that impurity region 106 is electrically coupled to node N1, and therefore description thereof is not repeated. Although the back gate bias has been described, such a structure may be employed that the gate of transistor Q2a is electrically coupled to the substrate to apply a substrate bias, and thereby a similar effect can be achieved.

Description will now be given on a transistor structure in which a back gate voltage can be applied in another manner.

Referring to FIGS. 8A and 8B, a transistor QB1 having a T-shaped gate will now be described. FIG. 8A is a plan of transistor QB1 having a back gate potential fixed structure achieved by a T-shaped gate. FIG. 8B illustrates a sectional structure of a transistor QB1 taken along line C#-C# in FIG. 8A.

As shown therein, transistor QB1 having the back gate potential fixed structure is formed on an SOI substrate that is formed of a silicon substrate 31, a buried insulating film 32 and an SOI layer 33. SOI layer 33 is provided with a complete isolation film 34 that extends from the surface of SOI layer 33 to buried insulating film 32. Complete isolation film 34 formed around SOI layer 33 insulates and isolates SOI layer 33 from neighboring elements (transistors) so that transistor QB1 of the back gate potential fixed structure can be formed in SOI layer 33.

In SOI layer 33, a P.sup.--body region 35 and a body contact region 36 neighbors to each other. A T-shaped gate electrode 37 is formed on P.sup.--body region 35 (channel region) between a drain region 39 and source region 30 with a gate insulating film (not shown) therebetween. A lateral portion of the T-shape of gate electrode 37 is formed on a boundary region between P.sup.--body region 35 and body contact region 36.

Body contact region 36 in transistor QB1 having the back gate potential fixed structure described above can be electrically connected to T-shaped gate electrode 37 or source region 30 via an external interconnection such as an aluminum interconnection.

Referring to FIGS. 9A and 9B, description will now be given on a transistor QB2 of a partial trench isolating structure.

FIG. 9A is a plan showing transistor QB2 of the back gate potential fixed structure. FIG. 9B shows a sectional structure of transistor QB2 taken along line D#-D# in FIG. 9A.

Transistor QB2 of the back gate potential fixing structure shown in these figures is formed in SOI layer 33 that is isolated from other surrounding elements by complete isolation film 34, similarly to transistor QB1 of the back gate potential fixed structure.

In SOI layer 33, P--body region 35 and body contact region 36 are formed with a partial isolation film 38 therebetween. Since a portion (35) of P.sup.--body region 35 is formed under partial isolation film 38, the portion (35) of P.sup.--body region 35 under partial isolation film 38 electrically connects P.sup.---body region 35 to body contact region 36.

Gate electrode 37 is formed on P.sup.--body region 35 (channel region) located between source and drain regions 30 and 39 with a gate insulating film (not shown) therebetween. Body contact region 36 in transistor QB2 of the back gate potential fixed structure described above can be electrically connected to gate electrode 37 or source region 30 via an external interconnection such as an aluminum interconnection.

Second Modification of the First Embodiment

Voltage supply control circuit VBC has been described on the structure in which the turn-on/off of transistor Q2 is controlled in response to a single input signal, i.e., control signal /Sleep. A second modification will now be described on a structure in which the turn-on/off of transistor Q2 is controlled based on a combination of two input signals, i.e., control signals SleepA and SleepB.

Referring to FIG. 10, description will now be given on an MTCMOS circuit according to the second modification of the first embodiment of the invention.

Referring to FIG. 10, the MTCMOS circuit according to the second modification of the first embodiment of the invention differs from the foregoing structure in that voltage supply control circuit VBC is replaced with a voltage supply control circuit VBCp. Other structures are substantially the same, and therefore description thereof is not repeated. Voltage supply control circuit VBCp includes transistors 6-9 and transistor Q2.

Transistors 6 and 7 are P-channel MOS transistors, and are connected in parallel between power supply voltage Vcc and node N1. Transistors 6 and 7 receive control signals SleepA and SleepB on their gates, respectively.

Transistors 8 and 9 are N-channel MOS transistors, and are connected in series between nodes N1 and N0. Transistors 8 and 9 receive control signals SleepA and SleepB on their gates, respectively. Transistors 6-9 form a logic circuit LC1.

Transistors 6-9 have threshold voltages higher in absolute value than the threshold voltages of the transistors forming logic circuit group L1, but may have threshold voltages equal in absolute value to those of the transistor forming logic circuit group L1 as described before. When transistors 6-9 have threshold voltages higher in absolute value than the threshold voltages of the transistors forming logic circuit group L1, such a situation can be suppressed that a current leaks to node N0 via node N1 and transistors 8 and 9 in the active mode.

More specifically, description will now be given on the manner of controlling the turn-on/off of transistor Q2 based on a result of logical NAND of two input control signals SleepA and SleepB.

In this example, at least one of control signals SleepA and SleepB attains the "L" level in the active mode. For example, when control signals SleepA and SleepB are at the "H" and "L" levels, respectively, transistor 6 or 7 is turned on to couple electrically node N1 to power supply voltage Vcc, and node N1 attains the "H" level.

Thereby, transistor Q2 is turned on to couple electrically node N0 to ground voltage GND, and pseudo ground line VB is supplied with ground voltage GND.

In the standby mode, control signals SleepA and SleepB are both set to the "H" level. Thereby, both transistors 6 and 7 are turned off, and both transistors 8 and 9 are turned on to couple electrically nodes N1 and N0 together. Therefore, the charged charges in node N1 are discharged to node N0 to raise the potential, and nodes N0 and N1 are electrically coupled to achieve diode connection in transistor Q2.

Similarly to the first embodiment, therefore, the charged charges in node N1, i.e., the charged charges stored in the region connected to the gate of transistor Q2 are discharged to node N0, and this can reduce the quantity of the current pulled out from power supply voltage Vcc to reduce the power consumption.

When the potential of node N0 is at the level that achieves a balance between the quantity of the current passing to pseudo ground line VB via logic circuit group L1 and a quantity of the current passing to ground voltage GND via transistor Q2, the potential at this level attains the balanced state.

In the above case, transistors 6 and 7 are electrically coupled to node N1. Therefore, as compared with the structure of the inverter formed of transistors 1 and 2 illustrated in FIGS. 2A-2C, a larger capacity load is applied to node N1 so that a larger amount of charges are charged when nodes N1 and N0 are electrically coupled. Therefore, the quantity of the current pulled out from power supply voltage Vcc is further reduced, and the power consumption is further reduced.

Description has been given by way of example on the manner in which the on/off of transistor Q2 is controlled based on a result of the logical NAND of two control signals SleepA and SleepB. However, the modification can be applied not only to the NAND circuit executing the logical NAND but also to another circuit or the like that controls on/off of transistor Q2 according to the control signal. For example, a logic circuit such as an NOR or XOR circuit can naturally be employed.

Third Modification of the First Embodiment

FIG. 11 illustrates an MTCMOS circuit according to a third modification of the first embodiment of the invention.

Referring to FIG. 11, the MTCMOS circuit according to the third modification of the first embodiment of the invention differs from the foregoing structure in that voltage supply control circuit VBC is replaced with a voltage supply control circuit VBCq. Voltage supply control circuit VBCq according to the third modification of the first embodiment of the invention differs from voltage supply control circuit VBC illustrated in FIGS. 2A-2C in that transistors 1a and 2a are additionally employed.

Similarly to transistors 1 and 2, transistors 1a