Semiconductor device having mechanism capable of high-speed operation Number:7,436,717 from the United States Patent and Trademark Office (PTO) owispatent A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.<H Semiconductor, operation, Semiconductor, d, 7436717.html, Patent, pto, 7436717

Title: Semiconductor device having mechanism capable of high-speed operation

Abstract: A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.

Patent Number: 7,436,717 Issued on 10/14/2008 to Hidaka

Inventors: Hidaka; Hideto (Hyogo, JP)
Assignee: Renesas Technology Corp. (Tokyo, JP)

Appl. No.: 10/898,969

Filed: July 27, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10424104	Apr., 2003	6831867
09775790	Feb., 2001	6563478

Foreign Application Priority Data


Feb 14, 2000 [JP]			2000-035330
Jun 15, 2000 [JP]			2000-179714

Current U.S. Class: 365/198 ; 326/30

Current International Class: G11C 7/00 (20060101)

Field of Search: 365/198 326/30,84

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Foreign Patent Documents


60-121593	Jun., 1985	JP

Other References

"Ultra LSI Memory," by Kiyoo Ito, Baifukan, 1994, pp. 161-163 (with partial English translation). cited by other .
"Semicondutor Memories", Betty Prince, 1983, Wiley, 2.sup.nd edition pp. 162-163. cited by other.

Primary Examiner: Tran; Michael T
Attorney, Agent or Firm: McDermott Will & Emery LLP

Parent Case Text

RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/424,104, filed Apr. 28, 2003, now U.S. Pat. No. 6,831,867 which is a divisional of application Ser. No. 09/775,790 filed Feb. 5, 2001, now U.S. Pat. No. 6,563,478, claiming priority of Japanese Application No. 2000-035330, filed Feb. 14, 2000 and Japanese Application No. 2000-179714, filed Jun. 14, 2000, the entire contents of each of which are hereby incorporated by reference.

Claims

What is claimed is:

1. A semiconductor device comprising: a signal generating circuit generating first and second signals; a transmission wire transmitting at least said first signal; a plurality of drivers each having an output node connected to said transmission wire and driving a potential on said transmission wire; and a signal line arranged along said transmission wire, and configured to connect said plurality of drivers and said signal generating circuit and transmit said second signal so as to control said plurality of drivers.

2. The semiconductor device according to claim 1, wherein said signal line has a smaller propagation time constant than said transmission wire.

3. The semiconductor device according to claim 2, wherein said transmission wire and said signal line are formed by different wiring layers, respectively.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, it relates to a structure for increasing the speed of operations and implementing low power consumption.

2. Description of the Prior Art

As shown in FIG. 68, a conventional dynamic random access memory having a shared sense amplifier system comprises memory cell blocks M1, M2, . . . , Mn and sense amplifier zones YS1, YS2, . . . , YSn+1 arranged to hold the respective memory cell blocks therebetween. Each memory cell block includes a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns.

As shown in FIG. 69, each sense amplifier zone includes sense amplifiers SA arranged in correspondence to bit lines and selection gates for selectively coupling the sense amplifiers SA with memory cell blocks. Each selection gate is formed by NMOS transistors NA and NB. Symbols BL11, /BL11, BL12, /BL12, BL13 and /BL13 denote the bit lines of the memory cell block M1, symbols BL21, /BL21, BL22, /BL22, BL23 and /BL23 denote the bit lines of the memory cell block M2, symbols BL31, /BL31, BL32, /BL32, BL33 and /BL33 denote the bit lines of the memory cell block M3, and symbol G(i,j) denotes the selection gates respectively.

The respective selection gates are switched in response to gate control signals BLI(1,1), BLI(2,0), BLI(2,1), BLI(3,1), . . . . Switching of the selection gates is controlled for selectively coupling one of two memory cell blocks with the sense amplifier zone held between the two memory cell blocks.

"Ultra LSI Memory" (Kiyoo Ito, Baifukan, 1994, pp. 161 163) describes methods of driving shared sense amplifiers in detail. The following two methods are employed for driving shared sense amplifiers: Referring to FIGS. 70 and 71, symbol BLI(i,j) (j=0 or 1) denotes a gate control signal corresponding to a selected memory cell block Mi, and symbols BLI(i+1,0) and BL(i-1,1) denote gate control signals controlling coupling between sense amplifier zones coupled with the memory cell block Mi and memory cell blocks Mi+1 and Mi-1 respectively.

In the first method, the gate control signals are set to a step-up power supply voltage level (Vpp), an internal power supply voltage level (Vcc) or a ground voltage level (GND) (three-valued control system), where Vpp>Vcc>GND.

As shown in FIG. 70, all gate control signals are set to the internal level Vcc in a standby period, for example. In an active period for coupling the memory cell block Mi with the sense amplifier zones, the gate control signal BLI(i,j) corresponding to the selected memory cell block Mi is set to the level Vpp while the gate control signals BLI(i+1,0) and BLI(i-1,1) corresponding to the non-selected memory cell blocks are set to the level GND.

In the second method, the gate control signals are set to the level Vpp or the level GND (two-valued control system). As shown in FIG. 71, all gate control signals are set to the level Vpp in a standby period, for example. In an active period, the gate control signals BLI(i+1,0) and BLI(i-1,1) are set to the level GND while keeping the gate control signal BLI(i,j) at the level Vpp.

The gate control signals are controlled in the aforementioned manner, for coupling pairs of bit lines of the selected memory cell block with the sense amplifiers SA included in the sense amplifier zones. The other memory cell blocks sharing the sense amplifier zones are disconnected from the sense amplifier zones.

Thus, it follows that data of the selected memory cell block is output to a data input/output line or data of the data input/output line is written in the selected memory cell block. The number of sense amplifier zones can be halved by employing the shared sense amplifier system, thereby reducing the chip area.

Coupling/non-coupling between a memory cell block and a sense amplifier zone is decided by rise/fall of a gate control signal. In order to speed-up the access time, therefore, the gate control signal must be transmitted at a high speed.

However, the gate control signal must drive a large number of (1000 to 4000) selection gates, leading to a large load capacitance of a wire (hereinafter referred to as a BLI wire) transmitting the gate control signal. Further, such a plurality of selection gates are dispersively arranged on the BLI wire over a long distance. According to the conventional structure, therefore, transmission delay of the gate control signal is so remarkable that the access time is retarded.

In addition, power consumption in a circuit (BLI generation circuit) generating the gate control signal is increased by charging/discharging the large load capacitance. This circuit consumes current as to an internally generated step-up power supply voltage Vpp. Thus, it follows that load current is generated in a Vpp generation circuit for generating the step-up power supply voltage Vpp. Therefore, current consumption in the Vpp generation circuit or the area of the Vpp generation circuit is increased.

Further, equalization circuits precharge/equalize bit line potentials in a standby state of a dynamic random access memory. However, an equalization signal for driving the equalization circuits must also drive a large number of equalization circuits and hence has a large load capacitance. In addition, a wire transmitting the equalization signal is lengthened. According to the conventional structure, therefore, the operating speed is limited due to remarkable transmission delay of the equalization signal. Further, power consumption in a circuit generating the equalization signal is increased similarly to the case of the aforementioned BLI generation circuit.

In addition, the structures and operations of circuits for driving a memory cell array, including those for driving sense amplifiers and word lines, are not suitable for high-speed operations and low power consumption. Thus, such structures and operations must be improved.

Further, the circuits for driving the memory cell array include a number of circuits operated at a voltage (boost voltage) higher than a power supply voltage in general, leading to characteristic fluctuation of transistors in these circuits, i.e., a problem of reliability.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a semiconductor device having low power consumption and high reliability, and capable of high-speed operations.

A semiconductor device according to an aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a selection gate for selectively coupling the memory cell array with the sense amplifier circuit, a transmission wire transmitting a control signal for on-off controlling the selection gate and a control signal driver arranged on an intermediate position of the transmission wire for driving the potential of the control signal.

Preferably, the semiconductor device further comprises a driver arranged on an end of the transmission wire for driving the potential of the control signal. Preferably, a plurality of such control signal drivers are provided, and the plurality of control signal drivers are dispersively arranged on the transmission wire.

In particular, the control signal driver pulls up or pulls down the potential of the control signal.

Preferably, the control signal driver drives the potential of the control signal in a direction changing the potential of the control signal in transition from a standby period to an active period for coupling the memory cell array with the sense amplifier circuit.

Preferably, the semiconductor device further comprises a driving signal transmission wire transmitting a driving signal for operating the control signal driver, and the transmission wire and the driving signal transmission wire are arranged on different layers.

In particular, the control signal transitions between three voltage levels including a first voltage level, an intermediate voltage level and a second voltage level. The control signal driver operates when making the control signal transition from the intermediate voltage level to the first voltage level or from the intermediate voltage level to the second voltage level.

Preferably, the semiconductor device further comprises the sense amplifier circuit for reading data from or writing data in the memory cells and a precharge circuit for precharging the plurality of bit lines to a prescribed potential, and the precharge circuit is arranged between the memory cell array and the selection gate.

According to the aforementioned semiconductor device, the drivers for driving the potential of the gate control signal are arranged on the intermediate position and the end of the transmission wire transmitting the gate control signal deciding switching of the selection gate. Thus, the selection gate can be switched at a high speed, for implementing high-speed access.

In particular, high-speed driving of the gate control signal is implemented by dispersively arranging local drivers on the transmission wire.

Further, the potential of the gate control signal can be driven at a high-speed by the local drivers when starting the active period for coupling the selected memory cell array with a sense amplifier zone. Therefore, high-speed memory access is enabled.

In addition, a transmission wire ZBLI transmitting a signal driving the local drivers and a transmission wire BLI transmitting the gate control signal are formed on different layers, thereby reducing a floating capacitance on the transmission wire ZBLI and improving an effect related to signal transmission.

With respect to the gate control signal transitioning between three voltage levels, the local drivers can be operated when the potential transitions from a level GND to a level Vcc and from the level Vcc to a level Vpp, for example.

Further, the precharge circuit (equalization circuit EQ) is arranged between the memory cell array and the selection gate, so that no channel resistance of a transistor forming the selection gate is present between the precharge circuit and the bit lines and hence equalization/precharging can be performed at a high speed.

A semiconductor device according to another aspect of the present invention comprises a transmission wire transmitting a signal, a first driver arranged on an intermediate position of the transmission wire for driving the potential of the signal and a second driver arranged on an end of the transmission wire for driving the potential of the signal.

The first driver operates to pull up the potential of the signal. Alternatively, the first driver operates to pull down the potential of the signal. In particular, the semiconductor device further comprises a driving signal transmission wire transmitting a driving signal for operating the first driver, and the transmission wire and the driving signal transmission wire are arranged on different layers.

According to the aforementioned semiconductor device, the potential of the signal can be driven at a high speed when transmitting the signal over a long distance.

Further, the signal can be pulled up or pulled down at a high speed.

The transmission wire transmitting the signal and the transmission wire transmitting the signal for driving the driver are formed on different layers, so that a floating capacitance on the transmission wire transmitting the signal for driving the driver is reduced and an effect related to signal transmission is improved.

A semiconductor device according to still another aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a selection gate for selectively coupling the memory cell array with the sense amplifier circuit and a control signal generation circuit generating a control signal for on-off controlling the selection gate, and the control signal generation circuit includes a node outputting the control signal, an amplitude circuit oscillating the potential of the node between a ground voltage level and a step-up power supply voltage level higher than a power supply voltage level and an NMOS transistor connected between the node and the power supply voltage for receiving an ON signal in its gate and pulling up the potential of the node in transition for making the potential of the node transition from the ground voltage level to the step-up power supply voltage level.

Preferably, the ON signal is set to the power supply voltage level in the transition. In particular, the amplitude circuit includes a pull-up PMOS transistor having a drain connected to the node and a source supplied with the step-up power supply voltage and receiving a signal of the ground voltage level in its gate in the transition and a pull-down NMOS transistor having a drain connected to the node and a source supplied with the ground voltage and receiving a signal of the ground voltage level in its gate in the transition.

Preferably, the drain of the pull-up NMOS transistor is supplied with an externally supplied external power supply voltage as the power supply voltage.

According to the aforementioned semiconductor device, an NMOS transistor can be used as one of driving elements deciding the potential of the gate control signal. This NMOS transistor may not be supplied with a one-shot pulse signal, whereby the circuit structure is simplified. Further, channel hot carrier reliability is improved and operations are stabilized. The external power supply voltage is directly supplied to the drain of the aforementioned NMOS transistor. Thus, a load of a circuit generating an internal power supply voltage Vcc can be reduced.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading or writing signals stored in the memory cells, a selection gate for selectively coupling the memory cell array with the sense amplifier circuit and a control signal generation circuit generating a control signal for on-off controlling the selection gate, and the potential of the control signal transitions between three voltage levels, while the control signal generation circuit uses an externally supplied external power supply voltage as one of the three voltage levels.

Preferably, the three voltage levels are a ground voltage level, the external power supply voltage level and a step-up power supply voltage level higher than the external power supply voltage level, and the control signal generation circuit includes a node outputting the control signal, an amplitude circuit oscillating the potential of the node between the ground voltage level and the step-up power supply voltage level and a voltage set circuit setting the potential of the node to the external power supply voltage level.

In particular, the voltage set circuit includes a transistor connected between the node and the external power supply voltage and turned on when making the potential of the node transition from the ground voltage level or the step-up power supply voltage level to the external power supply voltage level.

According to the aforementioned semiconductor device, the external power supply voltage is used as one of the voltage levels of the gate control signal. Thus, a load on a circuit generating an internal power supply voltage Vcc can be reduced.

An intermediate potential is increased and a pull-up or pull-down operation is speeded up by using the external power supply voltage.

A semiconductor device according to a further aspect of the present invention comprises a plurality of memory cell arrays each including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a plurality of selection gates provided in correspondence to the plurality of memory cell arrays for coupling corresponding memory cell arrays with the sense amplifier circuit, a plurality of transmission wires arranged in correspondence to the plurality of selection gates for transmitting control signals for turning on/off corresponding selection gates and a short circuit, and the potential of each of the plurality of transmission wires transitions between three voltage levels including a first voltage level, a second voltage level and an intermediate voltage level between the first voltage level and the second voltage level, while the short circuit selectively couples a transmission wire transitioning from the first voltage level to the intermediate voltage level with a transmission wire transitioning from the second voltage level to the intermediate voltage level.

Preferably, the semiconductor device further comprises a control signal generation circuit operating to set the potentials of the plurality of transmission wires to the intermediate voltage level in a standby period and set the potential of the transmission wire corresponding to a selected memory cell array to the first voltage level while setting the potential of the transmission wire corresponding to a non-selected memory cell array to the second voltage level in an active period for coupling the selected memory cell array with the sense amplifier circuit, and the short circuit couples the transmission wire corresponding to the selected memory cell array with the transmission wire corresponding to the non-selected memory cell array in transition from the active period to the standby period.

In particular, a plurality of sense amplifier circuits are arranged, each of the plurality of sense amplifier circuits is shared by two memory cell arrays included in the plurality of memory cell arrays, a plurality of short circuits are arranged, and each of the plurality of short circuits is arranged between two transmission wires arranged for the corresponding two memory cell arrays respectively.

According to the aforementioned semiconductor device, the short circuit selectively coupling the transmission wire transitioning from the first voltage level to the intermediate level with the transmission wire transitioning from the second voltage level to the intermediate voltage level is arranged. Thus, power consumption can be reduced.

Further, the short circuit couples the transmission wire corresponding to the selected memory cell array with the transmission wire corresponding to the non-selected memory cell in transition from the active period to the standby period. Thus, a high-speed reset operation is implemented.

In addition, the short circuit can be arranged between BLI wires for two memory cell arrays sharing a coupled sense amplifier zone. Thus, the short circuit can be readily arranged.

A semiconductor device according to a further aspect of the present invention comprises a plurality of memory cell arrays each including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to rows and a plurality of bit lines arranged in correspondence to columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a plurality of selection gates provided in correspondence to the plurality of memory cell arrays for selectively coupling corresponding memory cell arrays with the sense amplifier circuit, a plurality of first transmission wires arranged in correspondence to the plurality of selection gates for transmitting control signals for turning on/off corresponding selection gates, a plurality of equalization circuits arranged in correspondence to the plurality of memory cell arrays for equalizing a plurality of pairs of bit lines, a plurality of second transmission wires arranged in correspondence to the plurality of equalization circuits for transmitting equalization signals for operating corresponding equalization circuits and a short circuit, while the potential of each of the plurality of first transmission wires transitions between three voltage levels including a first voltage level, a second voltage level and an intermediate voltage level between the first voltage level and the second voltage level, the potential of each of the plurality of second transmission wires transitions between two voltage levels including the first voltage level and the second voltage level, and the short circuit selectively couples a first transmission wire having a changing potential with a second transmission wire having a potential changing in a direction different from the direction of potential change of the first transmission wire.

Preferably, the semiconductor device further comprises a first signal generation circuit operating to set the potentials of the plurality of first transmission wires to the intermediate voltage level in a standby period and set the potential of the first transmission wire corresponding to a selected memory cell array to the first voltage level while setting the potential of the first transmission wire corresponding to a non-selected memory cell array to the second voltage level in an active period for coupling the selected memory cell array with the sense amplifier circuit and a second signal generation circuit operating to set the potentials of the plurality of second transmission wires to the first voltage level in the standby period and set the potential of the second transmission wire corresponding to the selected memory cell array to the second voltage level in the active period. In particular, the short circuit couples the first transmission wire corresponding to the selected memory cell array with the second transmission wire corresponding to the selected memory cell array in transition from the active period to the standby period or in transition from the standby period to the active period. In particular, a plurality of such short circuits are arranged and each of the plurality of short circuits is arranged between the first transmission wire for the corresponding memory cell array and the second transmission wire for the corresponding memory cell array.

According to the aforementioned semiconductor device, the first transmission wire having a changing potential and the second transmission wire having a potential changing in a direction different from that of the potential change are selectively coupled with respect to the gate control signal (the first transmission wire) and the equalization signal (the second transmission wire). Thus, power consumption can be reduced.

Further, the short circuit couples the first transmission wire corresponding to the selected memory cell array with the second transmission wire corresponding to the selected memory cell array in transition from the active period to the standby period. Alternatively, the short circuit couples the first transmission wire corresponding to the selected memory cell array with the second transmission wire corresponding to the selected memory cell array in transition from the standby period to the active period. Thus, high-speed selection is enabled.

In addition, the short circuit can be arranged between a BLI wire and an equalization wire arranged on the same side of the same memory cell array. Thus, the short circuit can be readily arranged.

A semiconductor device according to a further aspect of the present invention comprises a transmission wire transmitting a first control signal and a second control signal of inverse logic to the first control signal, an inversion driver arranged on an intermediate position of the transmission wire for inverting an input signal and outputting the inverted signal, a plurality of first loads dispersively arranged on the transmission wire and driven by the first control signal and a plurality of second loads, different from the plurality of first loads, dispersively arranged on the transmission wire and driven by the second control signal.

Preferably, the transmission wire includes first and second transmission wires transmitting the first control signal and third and fourth transmission wires transmitting the second control signal, the inversion driver includes a first inversion driver having an input connected with the first transmission wire and an output connected with the fourth transmission wire and a second inversion driver having an input connected with the third transmission wire and an output connected with the second transmission wire, the plurality of first loads are arranged on the first and second transmission wires, and the plurality of second loads are arranged on the third and fourth transmission wires.

In particular, the semiconductor device further comprises a driver arranged on an intermediate position of the transmission wire, and the driver is driven by either the first or second control signal and drives the potential of the other control signal.

According to the aforementioned semiconductor device, an inversion repeater is arranged between the transmission wires transmitting first and second signals of inverse logic. Thus, when the loads to be driven by the first signal are large and cause transmission delay, the first and second signals can be transmitted at a high speed over a long distance by generating the first signal on the basis of the high-speed second signal and generating the second signal on the basis of the first signal.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix and a plurality of bit lines arranged in correspondence to a plurality of columns, a precharge circuit for precharging the plurality of bit lines to a prescribed potential, a transmission wire transmitting a control signal for operating the precharge circuit and a control signal driver arranged on an intermediate position of the transmission wire for driving the potential of the control signal.

Preferably, the semiconductor device further comprises a driver arranged on an end of the transmission wire for driving the potential of the control signal, a plurality of such control signal drivers are provided and the plurality of control signal drivers are dispersively arranged on the transmission wire.

Preferably, the semiconductor device further comprises a driving signal transmission wire transmitting a driving signal for operating the control signal driver, and the transmission wire and the driving signal transmission wire are arranged on different layers.

In particular, the semiconductor device further comprises a sense amplifier circuit for reading data from or writing data in the memory cells and a selection gate for selectively coupling the plurality of bit lines with the sense amplifier circuit, and the precharge circuit is arranged between the memory cell array and the selection gate.

Preferably, the semiconductor device further comprises an activation signal transmission wire transmitting an activation signal for operating the sense amplifier circuit and an activation signal driver arranged on an intermediate position of the activation signal transmission wire for driving the potential of the activation signal. The semiconductor device further comprises a driver arranged on an end of the activation signal transmission wire for driving the potential of the activation signal, and a plurality of activation signal drivers are provided while the plurality of activation signal drivers are dispersively arranged on the activation signal transmission wire.

In particular, the memory cell array is divided into a plurality of memory blocks and further includes a plurality of main word lines arranged in common to the plurality of memory blocks, while each of the plurality of memory blocks includes a plurality of sub word lines arranged in correspondence to a plurality of rows so that one of the sub word lines is selected by a corresponding main word line and a sub word line driver driving the plurality of sub word lines.

According to the aforementioned semiconductor device, the precharge circuit (equalization circuit EQ) precharging pairs of bit lines is dispersively driven thereby implementing high-speed access.

Further, the transmission wire transmitting the signal for driving local drivers and the transmission wire transmitting the signal for driving the precharge circuit are formed on different layers. Thus, the signal transmission speed for the signal for driving the drivers is increased.

In addition, the precharge circuit (equalization circuit EQ) is arranged between the memory cell array and the selection gate. Thus, no channel resistance of a transistor forming the selection gate is present between the precharge circuit and the bit lines, whereby equalization/precharging can be performed at a high speed.

The transmission wire transmitting the activation signal for activating the sense amplifier circuit is dispersively driven for driving the activation signal at a high speed and implementing high-speed access.

Further, access can be implemented at a higher speed due to a divided word line structure.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to a plurality of rows and a plurality of bit lines arranged in correspondence to a plurality of columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a precharge circuit for precharging the plurality of bit lines to a prescribed potential, a selection gate for selectively coupling the plurality of bit lines with the sense amplifier circuit, a transmission wire transmitting an activation signal for operating the sense amplifier circuit and an activation signal driver arranged on an intermediate position of the transmission wire for driving the potential of the activation signal, and the precharge circuit is arranged between the memory cell array and the selection gate.

Preferably, the semiconductor device further comprises a driver arranged on an end of the transmission wire for driving the potential of the activation signal, a plurality of activation signal drivers are provided, and the plurality of activation signal drivers are dispersively arranged on the transmission wire.

According to the aforementioned semiconductor device, no source-to-drain channel resistance of a transistor forming the selection gate is interposed between an equalization circuit and the bit lines. Therefore, equalization can be speeded up when starting equalizing the bit lines in a reset operation. Resetting of a sense amplifier driving transistor is also speeded up by the dispersively arranged drivers. Thus, the reset operation can be speeded up by combination thereof.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to a plurality of rows and a plurality of bit lines arranged in correspondence to a plurality of columns, a precharge circuit for precharging the plurality of bit lines to a prescribed potential in response to a control signal and a control signal generation circuit supplying the control signal, and the potential of the control signal transitions between three voltage levels.

Preferably, the control signal transitions between three voltage levels including a first voltage level, a second voltage level and an intermediate voltage level, and the control signal generation circuit makes the control signal transition to the second voltage level after making the control signal transition from the first voltage level to the intermediate voltage level when making the control signal transition from the first voltage level to the second voltage level.

Preferably, the semiconductor device further comprises a sense amplifier circuit for reading data from or writing data in the memory cells and a selection gate for selectively coupling the plurality of bit lines with the sense amplifier circuit. The precharge circuit is arranged between the memory cell array and the selection gate.

According to the aforementioned semiconductor device, the precharge circuit (precharge/equalization circuit) precharging pairs of bit lines is subjected to three-valued control. Thus, current consumption as well as the area of a step-up power supply voltage generation circuit can be suppressed.

Further, the precharge circuit (precharge/equalization circuit) is arranged between the memory cell array and the selection gate. Thus, no channel resistance of a transistor forming the selection gate is present between the precharge circuit and the bit lines, whereby equalization/precharging can be performed at a high speed.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to a plurality of rows and a plurality of bit lines arranged in correspondence to a plurality of columns, a sense amplifier circuit for reading data from or writing data in the memory cells, a selection gate for selectively coupling the memory cell array with the sense amplifier circuit in response to a control signal and a control signal generation circuit generating the control signal, the potential of the control signal transitions between three voltage levels including a first voltage level, a second voltage level and an intermediate voltage level, and the control signal generation circuit makes the control signal transition to the second voltage level after making the control signal transition from the first voltage level to the intermediate voltage level when making the control signal transition from the first voltage level to the second voltage level.

Preferably, the control signal generation circuit includes a node outputting the control signal, an amplitude circuit oscillating the potential of the node between the first voltage level and the second voltage level and a transistor connected between the node and a node receiving a power supply voltage of the intermediate voltage level for pulling up the potential of the node in transition for making the potential of the node transition from the first voltage level to the second voltage level. The power supply voltage of the intermediate voltage level is an externally supplied external power supply voltage.

In the aforementioned semiconductor device, the selection gate is subjected to three-valued driving while a precharge circuit (precharge/equalization circuit) precharging the bit lines is arranged between the selection gate and the memory cell array. Thus, current consumption and a circuit load of a step-up power supply voltage circuit are reduced, while no channel resistance of a transistor forming the selection gate is present between the precharge circuit and the bit lines and hence equalization/precharging can be performed at a high speed. When employing the external power supply voltage as the intermediate voltage, a load on a circuit generating an internal power supply voltage Vcc can be reduced.

A semiconductor device according to a further aspect of the present invention comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to a plurality of rows and a plurality of bit lines arranged in correspondence to a plurality of columns, a word line driver for activating a selected word line among the plurality of word lines and a signal generation circuit generating a driving signal for driving the word line driver, and the driving signal transitions between three voltage levels.

Preferably, the driving signal transitions between three voltage levels including a first voltage level, a second voltage level and an intermediate voltage level, a plurality of such driving signals are included in correspondence to the plurality of word lines respectively, and the signal generation circuit sets the plurality of driving signals to the intermediate voltage level in a standby period and sets the driving signal corresponding to the selected word line to the second voltage level while setting the driving signal corresponding to a non-selected word line to the first voltage level in an active period.

According to the aforementioned semiconductor device, the driving signal for driving the word line driver for selecting the word line is subjected to three-valued control. Thus, current consumption as well as the area of a step-up power supply voltage generation circuit can be suppressed. Further, reliability of a gate oxide film of a transistor forming the word line driver receiving the driving signal in its gate is improved. In addition, hot carrier reliability is remarkably improved as to a PMOS transistor forming the word line driver.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the structure of a principal part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 illustrates connection between a BLI driver and local drivers Dpd on a BLI wire;

FIGS. 3 and 4 are diagrams for illustrating exemplary arrangement of BLI drivers D0 and local drivers Dpd;

FIGS. 5A and 5B are circuit diagrams for illustrating a BLI generation circuit 100 according to the first embodiment of the present invention;

FIG. 6 is a timing chart showing changes of gate control signals according to the first embodiment of the present invention;

FIG. 7 illustrates repeaters inserted into intermediate positions of a BLI wire;

FIG. 8 is a block diagram showing an example of the overall structure of a semiconductor memory device 10000 according to the first embodiment of the present invention;

FIG. 9 illustrates the structure of a principal part of a semiconductor device according to a second embodiment of the present invention;

FIG. 10 illustrates connection between a BLI driver and local drivers BDpd on a BLI wire;

FIGS. 11A and 11B are circuit diagrams for illustrating a BLI generation circuit 200 according to the second embodiment of the present invention;

FIG. 12 is a timing chart showing changes of gate control signals according to the second embodiment of the present invention;

FIGS. 13A and 13B are circuit diagrams showing another exemplary structure of the second embodiment of the present invention;

FIG. 14 is a timing chart showing changes of gate control signals in the structure shown in FIGS. 13A and 13B;

FIGS. 15A and 15B are circuit diagrams showing still another exemplary structure of the second embodiment of the present invention;

FIG. 16 is a timing chart showing changes of various signals in the structure shown in FIGS. 15A and 15B;

FIG. 17 is a timing chart showing changes of gate control signals in the structure shown in FIGS. 15A and 15B;

FIGS. 18A and 18B are circuit diagrams showing a further exemplary structure of the second embodiment of the present invention;

FIG. 19 is a timing chart showing changes of various signals in the structure shown in FIGS. 18A and 18B;

FIG. 20 is a timing chart showing changes of gate control signals in the structure shown in FIGS. 18A and 18B;

FIGS. 21A and 21B are circuit diagrams for illustrating a BLI generation circuit 300;

FIG. 22 is a timing chart showing changes of gate control signals by the BLI generation circuit 300;

FIGS. 23A and 23B are circuit diagrams for illustrating a BLI generation circuit 305 according to a third embodiment of the present invention;

FIG. 24 is a timing chart showing changes of gate control signals by the BLI generation circuit 305;

FIGS. 25A and 25B are circuit diagrams for illustrating a BLI generation circuit 310 according to a fourth embodiment of the present invention;

FIG. 26 is a timing chart showing changes of gate control signals by the BLI generation circuit 310;

FIGS. 27A and 27B are circuit diagrams for illustrating another BLI generation circuit 315 according to the fourth embodiment of the present invention;

FIG. 28 is a timing chart showing changes of gate control signals by the BLI generation circuit 315;

FIGS. 29A and 29B are circuit diagrams for illustrating still another BLI generation circuit 320 according to the fourth embodiment of the present invention;

FIG. 30 is a timing chart showing changes of gate control signals by the BLI generation circuit 320;

FIG. 31 illustrates the structure of a principal part of a semiconductor device according to a fifth embodiment of the present invention;

FIGS. 32 and 33 are diagrams for illustrating a short transistor P15 according to the fifth embodiment of the present invention;

FIG. 34 is a circuit diagram showing the structure of a signal generation circuit 40;

FIG. 35 is a timing chart showing changes of gate control signals according to the fifth embodiment of the present invention;

FIG. 36 illustrates exemplary dispersive arrangement of short transistors P15 according to the fifth embodiment of the present invention;

FIG. 37 illustrates the structure of a principal part of a semiconductor device according to a sixth embodiment of the present invention;

FIG. 38 illustrates the structure of an equalization circuit EQ;

FIG. 39 is a diagram for illustrating a signal generation circuit 50A and a short transistor P20 according to the sixth embodiment of the present invention;

FIG. 40 is a timing chart showing changes of gate control signals and equalization signals according to the sixth embodiment of the present invention;

FIG. 41 is a diagram for illustrating another signal generation circuit 50B and the short transistor P20 according to the sixth embodiment of the present invention;

FIG. 42 illustrates exemplary dispersive arrangement of short transistors P20 according to the sixth embodiment of the present invention;

FIG. 43 illustrates the relation between a BLI wire and a ZBLI wire;

FIG. 44 is a diagram for illustrating a basic structure according to a seventh embodiment of the present invention;

FIG. 45 is a diagram for illustrating the outline of the structure according to the seventh embodiment of the present invention;

FIG. 46 illustrates the structure of a principal part of a semiconductor device according to an eighth embodiment of the present invention;

FIGS. 47A and 47B are circuit diagrams for illustrating a BLEQ generation circuit according to the eighth embodiment of the present invention;

FIG. 48 is a timing chart showing changes of equalization signals according to the eighth embodiment of the present invention;

FIG. 49 illustrates the structure of a principal part of a semiconductor device according to a ninth embodiment of the present invention;

FIG. 50 illustrates the relation between a BLEQ generation circuit and a local driver EDpd;

FIG. 51 is a timing chart showing changes of equalization signals according to the ninth embodiment of the present invention;

FIG. 52 illustrates the structure of a principal part of a semiconductor device according to a tenth embodiment of the present invention;

FIG. 53 is a circuit diagram showing the structure of a sense amplifier SA;

FIG. 54 is a diagram for illustrating the structures of a sense signal generation circuit 800 and a signal generation circuit 810;

FIG. 55 illustrates the structure of an SD signal generation circuit 820;

FIG. 56 illustrates the relation between a sub word driver SWD and sub word signals;

FIG. 57 is a timing chart showing changes of equalization signals according to the tenth embodiment of the present invention;

FIG. 58 illustrates the structure of a principal part of a semiconductor device according to an eleventh embodiment of the present invention;

FIG. 59 is a circuit diagram for illustrating a BLEQ generation circuit 900 according to the eleventh embodiment of the present invention;

FIG. 60 is a timing chart showing changes of equalization signals according to the eleventh embodiment of the present invention;

FIG. 61 illustrates the structure of a principal part of a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 62 is a timing chart showing operations according to the twelfth embodiment of the present invention;

FIG. 63 illustrates the structure of a principal part of a semiconductor device according to a thirteenth embodiment of the present invention;

FIG. 64 is a timing chart showing operations of the semiconductor device according to the thirteenth embodiment of the present invention;

FIG. 65 is a timing chart showing operations corresponding to a two-valued control system for sub word lines;

FIG. 66 illustrates the structure of an SD signal generation circuit 1100 according to a fourteenth aspect of the present invention;

FIG. 67 is a timing chart showing operations according to the fourteenth embodiment of the present invention;

FIGS. 68 and 69 are diagrams for illustrating a conventional dynamic random access memory having a shared sense amplifier system; and

FIGS. 70 and 71 illustrate exemplary methods of driving a conventional shared sense amplifier.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are now described in detail with reference to the drawings. Referring to the drawings, identical or corresponding parts are denoted by the same reference numerals or symbols, and redundant description is not repeated. Signals and wires transmitting the signals are denoted by the same symbols.

First Embodiment

A semiconductor device according to a first embodiment of the present invention is now described. As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention comprises a plurality of memory cell blocks and sense amplifier zones arranged to hold the memory cell blocks therebetween.

FIG. 1 representatively shows memory cell blocks M1, M2 and M3, a sense amplifier zone SB2 shared by the memory cell blocks M1 and M2 and a sense amplifier zone SB3 shared by the memory cell blocks M2 and M3.

Each memory cell block includes a plurality of memory cells arranged in the form of a matrix, a plurality of word lines arranged in correspondence to a plurality of rows and a plurality of bit lines arranged in correspondence to a plurality of columns. Referring to FIG. 1, symbol M denotes a memory cell, symbol WL denotes a word line, and symbols BLij and /BLij (i=1, 2, . . . , j=1, 2, . . . : i corresponds to the number of the memory cell block) denote bit lines respectively.

Each sense amplifier zone includes sense amplifiers SA arranged in correspondence to pairs of bit lines and a selection gate for selecting one of two memory cell blocks arranged on both sides thereof. For example, a pair of bit lines BL11 and /BL11 and a pair of bit lines BL21 and /BL21 are connected with the sense amplifier SA through selection gates G(1,1) and G(2,0) respectively. Further, a pair of bit lines BL22 and /BL22 and a pair of bit lines BL32 and /BL32 are connected with the sense amplifier SA through selection gates G(2,1) and G(3,0) respectively.

According to the first embodiment of the present invention, drivers D0 (hereinafter referred to as BLI drivers D0) and local drivers Dpd are arranged for wires transmitting gate control signals BLI for switching the selection gate controlling coupling between the sense amplifier zone and the memory cell blocks. The wires transmitting the gate control signals BLI are referred to as BLI wires and wires transmitting gate control signals ZBLI out of phase with the gate control signals BLI are referred to as ZBLI wires.

Each selection gate is formed by NMOS transistors NA and NB. In the following description, "i" in symbols BLI(i,j), G(i,j) and ZBLI(i,j) expresses correspondence to a memory cell block Mi, and j expresses "0" (the side of a sense amplifier zone shared by the memory cell block Mi and a memory cell block Mi-1) or "1" (the side of a sense amplifier zone shared by the memory cell block Mi and a memory cell block Mi+1).

Each BLI driver D0 is supplied with a step-up power supply voltage Vpp as an operating power source and outputs a signal (gate control signal BLI) out of phase with the gate control signal ZBLI. Each local driver Dpd is formed by an NMOS transistor connected b