Semiconductor device Number:7,436,722 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor device

Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

Patent Number: 7,436,722 Issued on 10/14/2008 to Mizuno,   et al.

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Inventors:	Mizuno; Hiroyuki (Musashino, JP), Sakata; Takeshi (Hino, JP), Oodaira; Nobuhiro (Akishima, JP), Watanabe; Takao (Fuchu, JP), Kanno; Yusuke (Kodaira, JP)
Assignee:	Renesas Technology Corp. (Tokyo, JP) Hitachi ULSI Systems Co., Ltd. (Tokyo, JP)
Appl. No.:	11/761,642
Filed:	June 12, 2007

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	11363085	Feb., 2006	7242627
	11118338	Oct., 2006	7126868
	10751402	Jan., 2006	6990002
	10149221	Feb., 2004	6687175
	PCT/JP00/00616	Feb., 2000

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Current U.S. Class:	365/203 ; 365/205; 365/207
Current International Class:	G11C 7/00 (20060101)
Field of Search:	365/203,205,206,63,207

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References Cited [Referenced By]

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U.S. Patent Documents

4777625	October 1988	Sakui et al.
4973864	November 1990	Nogami
5262999	November 1993	Etoh et al.
5274598	December 1993	Fujii et al.
5315555	May 1994	Choi
5386394	January 1995	Kawahara et al.
5408438	April 1995	Tanaka et al.
5436864	July 1995	Koh et al.
5457657	October 1995	Suh
5495440	February 1996	Asakura
5525918	June 1996	Reddy
5526313	June 1996	Etoh et al.
5854562	December 1998	Toyoshima et al.
5886943	March 1999	Sekiguchi et al.
5917745	June 1999	Fujii
5978255	November 1999	Naritake
5995403	November 1999	Naritake
6104653	August 2000	Proebsting
6147514	November 2000	Shiratake
6201728	March 2001	Narui et al.
6292015	September 2001	Ooishi et al.
6333884	December 2001	Kato et al.
6452851	September 2002	Endo et al.

Foreign Patent Documents

	03-029180		Feb., 1991		JP
	03-095794		Apr., 1991		JP
	04-370596		Dec., 1992		JP
	07-153270		Jun., 1995		JP
	08-249889		Sep., 1996		JP
	11-176163		Jul., 1999		JP

Other References

Lee, K-C., et al., "Low Voltage High Speed Circuit Designs for Giga-bit DRAMs", 1996 Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp. 104-105. cited by other . Itoh, Kiyoo, VLSI Memory Design, Baifukan, 1994, pp. 162-163. cited by other.

Primary Examiner: Dinh; Son
Attorney, Agent or Firm: Miles & Stockbridge P.C.

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Parent Case Text

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CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of Application No. 11/363,085 filed Feb. 28, 2006 now U.S. Pat. No. 7,242,627, which is a continuation of application Ser. No. 11/118,338 filed May 2, 2005 (now U.S. Pat. No. 7,126,868 issued Oct. 24, 2006), which is a continuation of application Ser. No. 10/751,402 filed Jan. 6, 2004 (now U.S. Pat. No. 6,990,002 issued Jan. 24, 2006), which is a continuation of application Ser. No. 10/149,221 filed Jun. 10, 2002 (now U.S. Pat. No. 6,687,175 issued Feb. 3, 2004), which is a 371 of International Application No. PCT/JP00/00616 filed Feb. 4, 2000.

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Claims

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The invention claimed is:

1. A semiconductor device, comprising: first and second bit lines; a plurality of memory cells coupled to the first and second bit lines; third and fourth bit lines; a first transistor coupled between the first bit line and the third bit line; a second transistor coupled between the second bit line and the fourth bit line; a sense amplifier including a first circuit coupled between the first bit line and the third bit line and between the second bit line and the fourth bit line, and a second circuit coupled between the third bit line and the fourth bit line; a first precharge circuit which precharges the first and second bit lines to a first precharge potential; and a second precharge circuit which precharges the third and fourth bit lines to a second precharge potential, wherein said second circuit amplifies a signal on one of the third and fourth bit lines to a first potential and a signal on the other of the third and fourth bit line to a second potential according to a storage signal from a selected one of the plurality of memory cells, the storage signal being transferred to the sense amplifier via the first circuit, wherein the first precharge potential is between the first and second potentials, wherein the second precharge potential is higher than the first precharge potential, and wherein a gate oxide film of the first transistor and a gate oxide film of the second transistor are thicker than a gate oxide film of a transistor included in the second circuit.

2. A semiconductor device according to claim 1, wherein the first transistor transfers the signal amplified by the second circuit from the third bit line to the first bit line, and the second transistor transfers the signal amplified by the second circuit from the fourth bit line to the second bit line.

3. A semiconductor device according to claim 2, wherein the first circuit includes a third transistor having a gate connected to the first bit line and a fourth transistor having a gate connected to the second bit line and a source connected to a source of the third MOSFET, and wherein the second circuit includes a latch circuit.

4. A semiconductor device according to claim 1, wherein the first precharge circuit is coupled between the first and second bit lines.

5. A semiconductor device comprising: first and second bit lines coupled to a plurality of memory cells; a third bit line coupled to the first bit line; a fourth bit line coupled to the second bit line; a pre-sense-amplifier which generates a difference of potential between the third and fourth bit lines according to a difference of potential between the first and second bit lines; a sense amplifier coupled between the third and fourth bit lines and including PMOS transistors which are supplied with a first potential and NMOS transistors which are connected a first control line which transfers a first control signal; a first pre-charge circuit which precharges the first and second bit lines to a first pre-charge potential; a second pre-charge circuit which pre-charges the third and fourth bit lines to a second pre-charge potential higher than the first pre-charge potential; and a second control line which transfers a second control signal by which an operation state of the pre-sense amplifier is controlled, wherein the pre-sense amplifier starts to generate the difference of potential between the third and fourth bit lines by discharging the third and fourth bit lines when the second control signal is activated, wherein the PMOS transistors of the sense amplifier start to amplify the difference of potential between the third and fourth bit lines when the second control signal is activated, wherein the NMOS transistors of the sense amplifier start to amplify the difference of potential between the third and fourth bit lines when the first control signal is activated, the first control signal being activated after the second control signal, wherein the sense amplifier amplifies one of the third and fourth bit lines to a first potential and the other of the third and fourth bit lines to a second potential according to the difference of potential between the third and fourth bit lines, and wherein the first precharge potential is between the first potential and the second potential.

6. A semiconductor device according to claim 5, wherein the pre-sense amplifier includes a first transistor and a second transistor, wherein the first transistor has source and drain regions coupled between the second control line and the third bit line and a gate electrode coupled to the first bit line, and wherein the second transistor has source and drain regions coupled between the second control line and the fourth bit line and a gate electrode coupled to the second bit line.

7. A semiconductor device according to claim 5, further comprising: a plurality of word lines crossing the first and second bit lines; and a switch circuit coupled between the first and third bit lines and between the second and fourth bit lines; wherein when one of the plurality of word lines is selected, data read out from one of the plurality of memory cells is amplified by the sense amplifier and then the amplified data by the sense amplifier is written back to the one of the plurality of memory cells via the switch circuit.

8. A semiconductor device according to claim 5, wherein the second pre-charge potential is the same as the first potential.

9. A semiconductor device according to claim 5, wherein the pre-sense amplifier is directly coupled to the sense amplifier.

10. A semiconductor device according to claim 5, wherein all of the plurality of memory cells are dynamic memory cells.

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Description

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TECHNICAL FIELD

The present invention relates to a semiconductor device and particularly to a semiconductor integrated circuit device having excellent low voltage operation characteristics.

BACKGROUND ART

In this specification, reference is made to the following cited references identified with the reference numbers.

[Reference 1] "VLSI Memory Design" Kiyoo Itoh, p 162;

[Reference 2] Japanese Patent Laid-open No. Hei 2-24898 (corresponding U.S. Pat. No. 4,973,864);

[Reference 3] "Japanese Patent Laid-open No. Hei 10-3971 (corresponding U.S. Pat. No. 5,854,562);

[Reference 4] "1996 Symposium on VLSI Circuits Digests of Technical Papers, pp. 104-105;

FIG. 26.1 of the [Reference 1] is a sensing system circuit diagram of the standard DRAM (Dynamic Random Access Memory). This diagram is a so-called shared sense-amplifier structure (having the structure where one sense amplifier line is used in common by the right and left memory mats). FIG. 18 shows a circuit diagram where this structure is omitted. A C100 and a M100 form a memory cell wherein the M100 indicates a charge transfer NMOS transistor, while VPL indicates a plate voltage. BL[n], /BL[n] are bit lines, WL[m] is word line, and a memory cell is disposed at an adequate intersection to form a memory array MA100. M101, M102, M103 are NMOS transistors and VBM is a power source voltage equal to a half of the data line voltage VDL. These elements are precharge circuit 101 of the so-called half VDD precharge system for precharging the bit line to the VBM potential by turning ON the M103 from the M101. M200, M201 are PMOS transistors, while M202, M203 are NMOS transistors, forming a CMOS latch type sense amplifier 201. Moreover, M109 and M110 are NMOS transistors to form a Y switch 103a to selectively connect the bit lines BL[n], /BL[n] to the global bit lines GBL[p], /GBL[p] by turning ON the M109 and M110

FIG. 19 shows waveforms for the read operation of this memory. Here, an array voltage VDL is set to a voltage which is equal to the power source voltage VDD assumed as 1.0V. Moreover, the power source voltage VBM is assumed as 0.5V which is equal to a half of such power source voltage and a setup voltage of the word line is assumed as 2.5V.

A precharge signal EQ is negated at the time T0 and a word line WL[m] is asserted at the time T1. Thereby, the MOS transistor M100 in the memory cell selected by such word line turns ON to share the charges accumulated in the capacitor C100 within the memory cell and a parasitic capacitance added to the bit lines BL[n], /BL[n] in order to generate a potential difference Vs for reflecting information within the memory cell on the bit lines BL[n], /BL[n].

Since the sense amplifier activate signals CSP and CSN are respectively driven to 1.0V and 0V, the bit line potentials BL[n], /BL[n] are amplified up to 1.0V and 0V. In this figure, since a YS[k] is asserted, a Y switch is turned ON and the global bit lines GBL[p], /GBL[p] are also amplified simultaneously when the bit lines BL[n], /BL[n] are amplified.

The signal /BL[n] which is given the slash sign "/" before BL[n] among the signals explained above depends on the generally used expression method and this signal /BL[n] means a complementary signal of BL[n]. Moreover, a bracket [ ] is also the generally used expression method and the signal BL[n], for example, means the typical expression of signals of bus structure consisting of one or more signal lines such as BL[0], BL[1], BL[2]. This expression method is used in this specification.

FIG. 20(A) shows a result of simulation of sensing rate (tSENSE) of the sensing system circuit of DRAM of FIG. 8 conducted by the inventors of the present invention. The sensing rate (tSENSE) is defined, as shown in FIG. 20(B), as the time required until a potential difference of the bit lines BL, /BL is amplified up to the 60% of the power source voltage VDD from activation of the sensing amplifier. Temperature is assumed as two kinds of temperatures of -40.degree. C. and 125.degree. C. in terms of the junction temperature Tj. This analysis by the inventors of the present invention has proved as follows.

(A1) The sense time (tSENSE) is remarkably delayed as the power source voltage is lowered.

(A2) When the power source voltage is equal to about 1.2V or less, the sense time in the higher temperature is further than that in the lower temperature. It is because a drive current of the sensing amplifier is mainly governed with a diffusion current, in place of a drift current, among the drain current of the MOS transistor. In general, the diffusion current very sensitively changes for temperature and a threshold value of MOS transistor. Therefore, when a sense amplifier is used in the area where the diffusion current governs the operation in place of the drift current, a sensing time changes to a large extent for fluctuation of manufacturing process of LSI and fluctuation of operation environment. This event may grow up to a problem that an yield rate of an LSI circuit is lowered. As a result, cost of LSI using DRAM of the circuit of such structure rises.

Moreover, FIG. 20(C) shows dependence of a delay time of a CMOS inverter on a power source voltage as an example of a delay time characteristic (tDLAY) of an ordinary CMOS logic circuit. Temperature is assumed as two kinds of temperatures of -40.degree. C. and 125.degree. C. in terms of junction temperature Tj as in the case of FIG. 20(A). This analysis by the inventors of the present invention has proved as follows.

(B1) Deterioration in the operation rate when the power source voltage is lowered is remarkably smaller than that of the sensing system of the existing DRAM shown in FIG. 18.

(B2) The temperature characteristic in the lower voltage condition is different in the CMOS inverter and the sensing system of the existing DRAM shown in FIG. 18.

From this fact, it can be understood that the DRAM circuit including the existing sensing system shown in FIG. 18 and the logic circuit having the delay characteristic shown in FIG. 20(C) are not matched with each other through the low voltage characteristics thereof. Here, matching of a plurality of circuits means that dependence of delay characteristic on the power source voltage and temperature is similar. For example, when the power source voltage is set to a lower value, the operation rate of all circuits is delayed in the similar degree and when the temperature is lowered, the operation rate of all circuits is also delayed in the similar degree.

When the DRAM including the existing sensing system as shown in FIG. 18 and a logic circuit which are not matched are disposed simultaneously on the same LSI, the operation rate during a low voltage operation of the logic LSI including such DRAM is governed with the characteristic that operation rate of the DRAM is rather low under the lower temperature. For example, the operation rate of the LSI as a whole is governed with the racing. Moreover, when the logic LSI including such DRAM is used in a plurality of operation modes where the power source voltage and the operating frequency vary, the operating frequency in the low voltage operation mode is extremely delayed because the DRAM is included.

Therefore, it is an object of the present invention to provide a sense amplifier which stably operates even under the low voltage condition.

DISCLOSURE OF INVENTION

A typical structure of the present invention is as follows. Namely, a semiconductor device comprises a word line (WL), a first bit line pair (BL, /BL), a memory cell (MC) provided at an intersection of the word line and the first bit line pair, a second bit line pair (LBL, /LBL), switch circuits (ISO_SW_T, ISO_SW_B) for coupling the first bit line pair and second bit line pair, a sense amplifier including a first circuit (PSA) connected to the first bit line pair and a second circuit (MSA) connected to the second bit line pair, a first precharge circuit (PC1) for precharging the first bit line pair to a first precharge potential and a second precharge circuit (PC2) for precharging the second bit line pair to a second precharge potential, wherein the second circuit is a circuit for amplifying one of the first bit line pair and one of second bit line pair to a first potential (VSS) receiving a storage signal of the memory cell and the other pair to a second potential (VDL), the first precharge potential is a voltage (VBM) between the first potential and the second potential and the second precharge potential is equal to the second potential.

Moreover, according to the other aspect of the present invention, a semiconductor device comprises a word line (WL), a first bit line pair (BL, /BL), a memory cell (MC) provided at an intersection of the word line and first bit line pair, a capacitor pair including a first capacitor (C250) having a first electrode connected to one of the first bit line pair and a second electrode connected to one of the second bit line pair and a second capacitor (C251) having a third electrode connected to the other of the first bit line pair and a fourth electrode connected to the other of the second bit line pair, a switch circuit including a first switch (M206) for connecting one of the first bit line pair and one of the second bit line pair and a second switch (M207) for connecting the other of the first bit line pair and the other of the second bit line pair, a sense amplifier (SA) connected to the second bit line pair, a first precharge circuit (PC1) for precharging the first bit line pair to a first precharge potential and a second precharge circuit (PC2) for precharging the second bit line pair to a second precharge potential.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an embodiment of a sensing system circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of the read operation of FIG. 1.

FIG. 3 is a diagram showing a DRAM macro including logics using the sensing system circuit of the present invention.

FIG. 4 is a diagram showing an embodiment of a system LSI using the DRAM including logics of the present invention.

FIG. 5 is a diagram showing the other embodiment of the sensing system circuit of the present invention.

FIG. 6 is a diagram showing the read operation of FIG. 5.

FIG. 7 is a diagram showing the other embodiment of the sensing system circuit of the present invention using capacitors.

FIG. 8 is a diagram showing an embodiment of the read operation of FIG. 7.

FIG. 9 is a diagram showing the other embodiment of a sense amplifier of the present invention.

FIG. 10 is a diagram showing the other embodiment of the sensing system circuit of the present invention.

FIG. 11 is a diagram showing an embodiment of the read operation of FIG. 10.

FIG. 12 is a diagram showing an embodiment of the DRAM macro using a shared sense amplifier system.

FIG. 13 is a diagram showing an embodiment when the sensing system circuit of FIG. 1 is changed to a shared sense amplifier system.

FIG. 14 is a diagram showing an embodiment when the sensing system circuit of FIG. 5 is changed to the shared sense amplifier system.

FIG. 15 is a diagram showing an embodiment when the sensing system circuit of FIG. 7 is changed to the shared sense amplifier system.

FIG. 16 is a diagram showing an embodiment when the sensing system circuit of FIG. 10 is changed to the shared sense amplifier system.

FIG. 17 is a diagram showing a control system of the DRAM of the present invention where a circuit for detecting the end of operation of the sense amplifier is loaded.

FIG. 18 is a diagram showing the existing sensing system circuit.

FIG. 19 is a diagram showing an example of discussion of the read operation of FIG. 18 discussed by the inventors of the present invention.

FIG. 20 is a diagram showing the results of simulations by the inventors of the present invention of the low voltage characteristics of the sensing system circuit of FIG. 18 and the low voltage characteristics of the CMOS inverter.

FIG. 21 is a diagram showing the results of simulations by the inventors of the present invention of the low voltage characteristics when the sensing system circuit of FIG. 18 is operated in the VDD precharge system.

FIG. 22 is a diagram showing an embodiment when a memory array is formed using the sensing system circuit of the present invention shown in FIG. 1, FIG. 5, FIG. 7, FIG. 10, FIG. 13, FIG. 14, FIG. 15 and FIG. 16.

FIG. 23 is a diagram showing an embodiment of a re-write method of the present invention.

FIG. 24 is a diagram showing a circuit for realizing a re-write method of the present invention different from FIG. 22.

FIG. 25 is a diagram showing a re-write operation using the embodiment of FIG. 24.

FIG. 26 is a diagram showing a re-write operation of the present invention using the embodiment of FIG. 24 different from the embodiment of FIG. 25.

FIG. 27 is a diagram showing the read operation of the present invention using the embodiment of FIG. 24.

FIG. 28 is a diagram showing the write operation of the present invention using the embodiment of FIG. 24.

BEST MODE FOR CARRYING OUT THE INVENTION

The preferred embodiments of the present invention will be explained in detail with reference to the accompanying drawings. Circuit elements forming each function block of the preferred embodiments are formed, although not particularly limited, on only one semiconductor substrate made of single crystal silicon or the like with the well known technology to form CMOSs (complementary MOS transistors). The P-type MOS transistor (MOSFET) can be discriminated by giving a sign .largecircle. to the gate thereof from an N-type MOS transistor (MOSFET).

Embodiment 1

FIG. 1 shows an embodiment of a typical sensing system circuit of the present invention. C100 and M100 form a memory cell (MC). The C100 is a capacitor for storing information within the memory cell, M100 is a charge transfer NMOS transistor and VPL is a plate voltage. BL[n] and /BL[n] are bit lines, WL[m] is a word line and a memory cell is disposed at the adequate intersection to form a memory array 100. Here, the embodiment based on the folded bit line structure is shown but a open bit line structure may also be introduced. In this figure, M107 and M108 are NMOS transistors to form a Y switch Y-SW, while the local bit lines LBL[n], /LBL[n] can be selectively connected to the global bit lines GBL[P], /GBL[p] by turning ON the M107 and M108.

A sense amplifier SA1 employed in this invention has the following characteristics. Namely, the sense amplifier SA1 includes a pre-sense amplifier PSA connected to the bit line pair BL[n], /BL[n] (these can also be abbreviated as "BL") and local bit line pair LBL[n], /LBL[n] (these can also be abbreviated as "LBL"). Moreover, switch circuits (ISO_SW_T, ISO_SW_B) for controlling connection and isolation of the BL and LBL are also provided. The PSA includes a N-type MOSFET pair (M204 and M205) with the gate thereof connected to the BL and the source thereof connected in common and this N-type MOSFET pair operates as the differential MOSFET pair for receiving a signal at the gate. Moreover, a main sense amplifier MSA is a circuit including the CMOS latch type sense amplifier as the basic structure. In the MSA, the P-type MOSFET pair M200 and M201 assures that the gate and drain thereof are cross-connected and the sources are connected in common. Moreover, the N-type MOSFET pair M202 and M203 assures that the gate and drain thereof are cross-connected and the sources are connected to the drains of the N-type MOSFET pair of the PSA.

FIG. 9 of the [Reference 2] shows a sense amplifier including the PSA and MSA explained above when attention is paid to the format of circuit. Moreover, FIG. 16 of the [Reference 2] shows a circuit operation. However, the sense amplifier of the [Reference 2] relates to the SRAM. Namely, this reference does not suggest application to the DRAM of the present invention and therefore any consideration is never taken for the switch circuits (ISO_SW_T. ISO_SW.B) explained below.

The second characteristic of the present invention is that the switch circuits (ISO_SW_T. ISO_SW_B) for controlling connection and isolation of the BL and LBL are provided corresponding to difference of precharge potentials of the BL and LBL. M206 and M207 are NMOS transistors. Re-write operation can be realized by electrically connecting the BL and LBL with this switch circuit and then transferring the data amplified with the MSA to the BL from the LBL.

The third characteristic of the present invention is that the BL is precharged to VDL/2, while the LBL to VDL. The M101, M102, M103 are NMOS transistors and VBM is a power source voltage equal to a half voltage of the data line voltage VDL. These elements form a so-called precharge circuit 101 of the half VDD precharge system for precharging the bit lines BL[n], /BL[n] (first bit line pair) to the VBM potential (first precharge voltage) by turning ON the M103 from the M101. On the other hand, M104, M105 and M106 are transistors and these elements form a so-called precharge circuit 102 of the VDD precharge system for precharging the LBL (second bit line pair) to the VDL potential (second precharge voltage) by turning ON these MOS transistors.

FIG. 2 shows an example of the read operation waveforms of the memory of FIG. 1. Here, an array voltage VDL is set to a voltage which is equal to the power source voltage VDD of chip and is assumed as 1.0V for simplified explanation. Moreover, the VBM is assumed as a voltage of 0.5V which is equal to a half of the VDL, while the setup voltage of the word line is assumed as 2.5V.

The precharge signals EQ_BL and EQ_LBL are negated at the time T0 and the word line WL[m] is asserted at the time T1. Therefore, the transfer MOS transistor M100 in the memory cell selected with such word line turns ON, sharing the charges accumulated within the capacitor C100 in the memory cell and the parasitic capacitance added to the bit lines BL[n], /BL[n] and thereby a potential difference Vs reflecting information within the memory cell is generated between the bit lines BL[n] and /BL[n].

A sense amplifier is activated at the time T2 by driving a sense amplifier activate signal CSN to 0V, potential differences of the bit lines BL[n] and /BL[n] are amplified up to 1.0V and 0V and these potential differences are outputted to the local bit lines LBL[n] and /LBL[n]. Since YS[k] is asserted in this figure, the Y switch is turned ON and the global bit lines GBL[p], /GBL[p] are also amplified simultaneously with amplification of the bit lines BL[n], /BL[n].

Moreover, a wrote back signal RBK is asserted at the time T2' to execute the re-write to the memory cell by transferring the amplified signals of the local bit lines LBL[n], /LBL[n] to the bit lines BL[n], /BL[n].

The write back signal RBK and word line WL[m] are negated at the time T3, the precharge signals EQ_BL and EQ_LBL are asserted at the time T4, thereby the bit lines BL[n] and /BL[n] are precharged to 0.5V, while the local bit lines LBL[n], /LBL[n] are precharged to 1.0V.

FIG. 3 shows an embodiment of the DRAM macro using the sensing system circuit of FIG. 1. Numeral 500 designates a DRAM macro. Numeral 501 designates an indirect peripheral circuit consisting of a command decoder 502, a read/write amplifier 503 and a power source circuit 504. Moreover, BA0 to BA7 are memory banks. Each bank is composed of a timing control circuit TG, a column selection circuit Y-DEC, a row decoder X-DEC and a plurality of sense amplifiers 506a, 506b. The sensing system circuit shown in FIG. 1 corresponds to 506a or 506b of FIG. 3 and is disposed in each bank in the manner that the two units are provided opposed with each other. A control signal of the word line WL[m] or the like of FIG. 1 is controlled with the row decoder, timing control circuit and column selection circuit or the like. The GBL0, /GBL0 form a pair of the global bit lines and are laid in parallel to the bit lines BL0, /BL0 and the eight sense amplifiers of the sensing system circuit indicated with 506a, 506b of each bank are connected to a pair of global bit lines GBL (it means that a degeneration degree is 8). The GBL is provided crossing the memory bank and is connected to a block 503 including a read/write amplifier RW-AMP provided corresponding to the memory bank. The read/write amplifier RW-AMP is connected, via a selected as required or in direct, to the external input/output data signal line DQ. The control signal CNT and address signal ADD of the DRAM macro are inputted to a command decoder C-DEC and this C-DEC sends a control signal to TG or the like to execute the predetermined read or write operation.

In the embodiment of FIG. 3, it is a characteristic that since an independent sensing system circuit is formed for each bank and moreover a timing control circuit 507 is provided within each bank, each bank can be operated independently with the control from the command decoder 502. The throughput of the DRAM macro can be enhanced with the so-called interleave system by the independent operation of each bank.

FIG. 4 shows the entire part of a logic LSI (400) including the DRAM comprising the DRAM macro 500 shown in FIG. 3. VDD and VSS indicate the core power source and its ground, while VDDQ and VSSQ indicate the I/O power source and its ground. For example, the core power source voltage is 1.0V and the I/O power source voltage is 3.3V. OUT0 to OUTx indicate the output signals, while IN0 to INy are input signals and I/00 to I/0z are input/output signals, respectively. Moreover, 401 designates an I/O circuit for interface of an internal signal of the chip and an external signal of the chip. Numeral 402 designates a logic circuit formed of an inverter, NAND gate or the like and 403 designates the DRAM macro shown in FIG. 3. As an example of 402, a microprocessor (CPU) or DSP or SRAM or the like may be listed although not particularly restricted

FIG. 21 shows a result of simulation conducted for evaluating the characteristics of the sensing system circuit of the present invention shown in FIG. 1. This simulation result means a result of calculation when the bit lines BL[n], /BL[n] are precharged to the VDD in the sensing circuit of the DRAM shown in FIG. 18. A circuit configuration is same as that of FIG. 20(A) except for the precharge system. The simulation result is also the same as that of FIG. 19, except for the drive method of the sense amplifier activate signal that the CSP is fixed to the VDD potential and the CSN is driven to the VSS potential from the VDD potential. The inventors of the present invention has proved as follows from the analysis explained above.

(C1) The sense time (tSENSE) is delayed as the power source voltage is lowered but a degree of such delay is rather gradual in comparison with FIG. 20(A) and is well matched with the characteristics of the CMOS inverter (FIG. 20(C)).

(C2) In the range where at least the power source voltage is equal to or higher than 0.8V, the sense time is rather fast than that when the temperature is lower. It is because a drive current of the sense amplifier is mainly governed with a drift current, in place of a diffusion current, among the drain current of the MOS transistor and it is well matched with the characteristics of the CMOS inverter (FIG. 20(C)).

As explained above, the low voltage operation characteristic of the sensing system circuit of the VDD precharge system is more excellent than that of the half VDD precharge system to a remarkable extent and it can be understood that the DRAM sense circuit of the VDD precharge system is well matched with the CMOS inverter. Only a result of the VDD precharge system is indicated here to simplify the explanation, but the VDD precharge is executed before the drive of the sense amplifier in regard to the amplification of the local bit lines even in the sensing system circuit of the present invention shown in FIG. 1. Namely, these precharge systems are essentially identical and the characteristics shown in FIG. 21 and explained above can also be obtained.

Moreover, the VDD precharge system has a problem that a particular cell such as a dummy cell or the like is required for generation of the reference voltage. However, in the present invention, such dummy cell for the reference voltage has been eliminated by isolating the bit lines BL[n], /BL[n] connected to the memory cell and the local bit lines LBL[n], /LBL[n] for the DC element, using the half VDD precharge system for the bit lines BL[n], /BL[n] and using the VDD precharge system for the local bit lines LBL[n], /LBL[n].

As explained above, the sensing system circuit of the present invention shown in FIG. 1 is characterized as follows.

(D1) A sense time in the lower temperature condition is faster than that in the higher temperature condition even when a voltage is low.

(D2) Deterioration in a sense rate under the low voltage condition is controlled to the same degree as the deterioration of delay time of the CMOS inverter shown in FIG. 20(B).

The characteristic of the item (D1) is attained because a drive current of the sense amplifier in the present invention is mainly governed with a drift current, in place of a diffusion current, among the drain current of MOS transistor. In general, change of a diffusion current is very sensible to temperature and threshold value of MOS transistor. Therefore, when a sense amplifier is used in the area where is mainly governed with a diffusion current in place of a drift current like the sensing system circuit shown in FIG. 18, a sense time changes largely for fluctuation in manufacturing processes of LSI and fluctuation in operation environment of LSI. This change is developed up to a problem that an yield rate of the LSI circuit is lowered. As a result, a manufacturing cost of LSI using the DRAM of the circuit configuration explained above rises. Accordingly, it can be said that the sensing system circuit of the present invention is resistive to fluctuation in manufacturing processes of LSI and fluctuation in operation environment of LSI. Moreover, the sensing system circuit has a circuit configuration having a higher yield rate.

Moreover, with the characteristics of the items (D1), (D2), the DRAM macro 403 has the characteristic which is well matched with the low voltage characteristic of the logic circuit 402 of FIG. 2. Therefore, it can no longer be said that any one of above elements will mainly control the low voltage characteristic and the DRAM macro 402 can be included into the logic LSI without deterioration of the final LSI characteristic to a large extent.

In addition, the sensing system circuit of the present invention of FIG. 1 has a characteristic that this circuit does not require a particular cell such as a dummy cell which has been required for the existing VDD precharge system, while having the characteristic of the existing VDD precharge system explained in the items (D1), (D2). Thereby, the manufacturing process and circuit can be simplified remarkably and the yield rate can also be improved to realize the effect for low manufacturing cost of LSI.

The symbol MOS in FIG. 1 of which gate electrode is indicated with a white box such as M206 indicates a high dielectric voltage MOS transistor formed of a thick gate oxide film, while that of which gate electrode is indicated with a line like M202 indicates a MOS transistor formed of a thin gate oxide film. A method for using the MOS of two kinds of the gate oxide film thickness has a merit, although not particularly restricted, that an adequate voltage can be impressed to the gate electrode through the structure explained in regard to this embodiment. Since it is enough when the dielectric strength of oxide film in the thin oxide film MOS explained previously is basically capable of covering the power source voltage VDD, a high speed MOS transistor may be used. The thick oxide film MOS explained later is capable of using the MOS which is the same as that used in the output stage of the I/O circuit of LSI and it is also enough when the dielectric strength of the oxide film can basically cover the voltage up to the I/O voltage VDDQ. An example of the basic selective use of the MOS transistor as in the case of FIG. 1 will be shown in the subsequent drawings. Moreover, there is no particular restriction in the threshold voltage of MOS transistors. A structure of the DRAM macro using the sensing circuit of the present invention and the logic LSI including DRAM using the same macro is not particularly restricted to the structure shown in FIG. 3 and FIG. 4.

Moreover, in above embodiment, it is explained that the potential amplitude of the bit line appears as VSS (0V) and VDL (1V). But this merit is particularly distinctive when VDL is equal to or less than 1.8V and moreover is ranged from 1.8V to 0.5V. This merit is common in the following embodiments.

Embodiment 2

FIG. 5 shows another embodiment of the sensing system circuit of DRAM of the present invention. In FIG. 1, the MOS transistors M204, M205 in the sense amplifier connected with the bit lines BL[n], LBL[n] are respectively connected in series to M202 and M203. Meanwhile, in the sense amplifier SA2 of FIG. 5, M208 and M209 corresponding to M204 and M205 are connected in parallel to M202 and M203 to form a presense amplifier PSA in combination with M208 and M209. Moreover, the main sense amplifier MSA part is formed as a latch type circuit in which the M200 to M203 are included, sources of the M202 and M203 are coupled in common and the CMOS inverter is cross-connected. MSA and PSA are respectively isolated with the drive lines CSN and PRECSN for independent control.

A sense amplifier which is similar only in the circuit format is shown in FIG. 1 of the [Reference 3]. However, in the circuit of the [Reference 3], it is not considered, unlike the present invention, that the precharge level is different in the bit line BL and local bit line LBL and the switch circuits (M206, M207) are used for isolation and coupling of the BL and LBL.

FIG. 6 shows an example of the read operation waveforms of the sensing system of the embodiment shown in FIG. 5. The same explanation is eliminated by explaining only the part which is different from the read operation shown in FIG. 2. At the time T1, the word line WL[m] is asserted and simultaneously the drive signal PRECSN (source voltage of M208 and M209) of the pre-sense amplifier 202b shown in FIG. 5 is driven to -0.5V. Thereby, since the bit lines BL[n] and /BL[n] are connected to the gate electrodes of M208 and M209, the local bit lines LBL[n], /LBL[n] precharged to 1.0V are discharged as shown in the figure depending on the potentials of the bit lines BL[n], /BL[n]. At the time T2, the main sense amplifier 202a is activated by driving the CSN to 0V to amplify the potential difference of the local bit lines LBL[n], /LBL[n] generated through the discharge operation.

In the system of the embodiment shown in FIG. 1, the M204 and M205 are a part of the drive MOS transistor of the local bit lines LBL[n], /LBL[n] but since only a voltage around 0.5V is impressed to M204 and M205 even after the activation of the sense amplifier, a drive force of the local bit lines LBL[n], /LBL[n] is controlled with a weak drive force of the M204 and M205. Therefore, the MOS transistor having a low threshold value must be used for the M204 and M205 for the operation under a lower voltage condition in view of obtaining a large drive force even if only a voltage equal to a half of the power source voltage is impressed to the gate electrode. On the other hand, in the embodiment of FIG. 5, only the MOS transistors M202 and M203 drive the local bit lines LBL[n], /LBL[n] when the sense amplifier is activated and the MOS transistors M208 and M209 are used in the pre-sense period (the period from the time T1 to the time T2 in FIG. 6). Therefore, even when the low threshold voltage MOS transistors are not used for M208 and M209, high speed operation of the main amplifier 202a can be realized.

In the embodiment of FIG. 6, a drive signal PRECSN of the pre-sense amplifier 202b is driven up to -0.5V to drive the pre-sense amplifier consisting of M208 and M209 but the drive voltage of PRECSN is not particularly restricted. However, since only a voltage of about 0.5V is applied at the time T1 to the gate electrodes of M208 and M209, the M208 and M209 can drive the local bit lines LBL[n], /LBL[n] at a high speed when the PRECSN is driven up to a negative voltage. Moreover, when the PRECSN is driven up to a negative voltage, a voltage difference between the source and gate of the M208 and M209 becomes larger. Accordingly, the local bit lines LBL[n], /LBL[n] can be driven with a drain current resulting from the drift current to match the pre-sense time characteristic up to the time T2 from the time T1 and the delay characteristic of the logic circuit.

When the PRECSN is driven up to a negative voltage, a drive force of the M208 and M209 becomes too large and when a voltage difference of about 100 mV which is enough to drive the main sense amplifier 202a is generated on the local bit lines LBL[n], /LBL[n], and therefore it is probable that both local bit lines LBL[n], /LBL[n] may be driven to the potential near to about 0.5V. Under this condition, the effect attained by precharging the local bit lines LBL[n], /LBL[n] connected to the main sense amplifier to the VDD is lost. In order to prevent such event while the PRECSN is driven to a negative voltage, the gate length Lg of the M208 and M209 is increased or the gate width W is narrowed to adjust a current of M208 and M209 to drive the local bit lines LBL[n], /LBL[n].

Embodiment 3

FIG. 7 shows another embodiment of the sense amplifier of the present invention. In this embodiment, unlike FIG. 1 and FIG. 5, capacitors C250 and C251 formed of MOS transistors are connected between the bit lines BL[n], /BL[n] and the local bit lines LBL[n], /LBL[n]. In the embodiments of FIG. 1 and FIG. 5, a voltage difference of the bit lines BL[n], /BL[n] connected to the memory cell is detected as a drain current difference flowing corresponding to the gate voltage thereof by connecting the bit lines BL[n], /BL[n] to the gate electrode of the MOS transistor of pre-sense amplifier PSA in the sense amplifier. Meanwhile, in this embodiment, a voltage difference of the bit lines BL[n], /BL[n] connected to the memory cell is transferred to the local bit lines LBL[n], /LBL[n] through the capacitance couple (so-called AC coupling) of the capacitors C250 and C251.

FIG. 8 shows an example of the read operation waveforms of the sensing system in the embodiment of FIG. 7. Here, only a part different from the read operation explained with reference to FIG. 2 and FIG. 6 will be explained to eliminate duplicated explanation. When the word line WL[m] is asserted at the time T1, a voltage difference Vs1 corresponding to the information within the memory cell is generated to the bit lines BL[n], /BL[n] connected to the memory cell. This potential difference is transferred to the local bit lines LBL[n], /LBL[n] through the capacitance coupling of the capacitors C250, C251 of FIG. 7 and thereby a potential difference Vs2 is generated in the local bit lines LBL[n], /LBL[n]. Thereafter, the sense amplifier activate signal CSN is asserted at the time T2 to activate the sense amplifier and the potential difference Vs2.

Here, although it is not particularly restricted, it is preferable that a structure of the capacitors C250 and C251 is formed with MOS capacitor based on the NMOS transistor. The capacitor utilizing a gate capacitance of the MOS transistor has a property that capacitance changes depending on the potential difference between the gate and source/drain. Namely, when the potential difference between the gate and source/drain is large, a channel is formed to the MOS transistor and a capacitance is large and when the potential difference between the gate and source/drain is small, a channel disappears the a capacitance becomes small. Hereinafter, such effect is called the capacitance modulation effect.

In FIG. 8, a potential difference Vs2 of the local bit lines LBL[n], /LBL[n] is amplified by activating the sense amplifier at the time T2, but the capacitance of the bit lines BL[n], /BL[n] becomes large via the capacitance coupling through the C250 and C251 from the local bit lines LBL[n], /LBL[n]. Therefore, the following points must be taken into consideration to drive, at a high speed, the local bit lines LBL[n], /LBL[n] with the sense amplifier.

(E1) Any one of local bit lines LBL[n], /LBN[n] driven for the low voltage side (LBL[n] in FIG. 8) must be driven at a high speed to the row side, when it is driven, by virtually lowering a parasitic capacitance added to the bit line /BL[n]. For this purpose, it is preferable to provide a capacitor C251 having a smaller capacitance between the local bit line /LBL[n] and the corresponding bit line /BL[n]. (E2) Any one of local bit lines LBL[n], /LBL[n] driven for the high voltage side (LBL[n] in FIG. 8) must preferably be held in the high voltage side, when it is driven, without driving the local bit line /LBL[n] to the low voltage side with the parasitic capacitance when the sense amplifier is driven by virtually increasing the parasitic capacitance added to the bit line BL[n]. For this purpose, it is preferable that a capacitance C250 provided between the local bit line LBL[n] and the corresponding bit line BL[n] has a large capacitance.

The contents of items (E1) and (E2) can be realized automatically with the capacitance modulation effect explained above by using a capacitor utilizing the NMOS transistor as the capacitors C250 and C251.

A connection method when the MOS transistor is used for the capacitors C250 and C251 (the gate electrode is connected to the local bit line in FIG. 7) and the method of setting the substrate potential are not particularly restricted. However, the relationship between Vs1 and Vs2 of FIG. 8 is determined based on the charge sharing between the capacitance Ca of the capacitors C250, C251 and the parasitic capacitance Cp added to the local bit lines LBL[n], /LBL[n]. Namely, Vs2=Vs1*Ca/(CP+Ca). Therefore, it is recommended to make small Cp as much as possible when Ca is assumed to be constant. A value of Cp can be reduced as much as a junction capacitance of a diffusion layer of the MOS transistor forming the C250 and C251 by connecting the gate electrode to the local bit line such as C250 and C251.

Embodiment 4

An embodiment of the sensing system circuit of the present invention is shown in FIG. 1, FIG. 5 and FIG. 7 but it is enough, in short, when the bit lines BL[n], /BL[n] connected to the memory cell and the local bit lines LBL[n], /LBL[n] connected to the sense amplifier are electrically isolated, the bit lines BL[n], /BL[n] are precharged to the half VDD, the local bit lines LBL[n], /LBL[n] are precharged to the VDD and a voltage difference is generated in the local bit lines LBL[n], /LBL[n] corresponding to the voltage difference of the bit lines BL[n], /BL[n] generated when the word line WL[m] is asserted at the time of read operation. A structure of the sense amplifier connected between the bit lines BL[n], /BL[n] and the local bit lines LBL[n], /LBL[n] is not restricted to that shown in FIG. 1, FIG. 5 and FIG. 7. For example, the structure shown in FIG. 9 may be used.

FIG. 9 shows a structure in which the CMOS latch type sub-sense amplifier SSA consisting of the MOS transistors of M290 to M293 is added to the embodiment shown in FIG. 5. The main sense amplifier MSA includes M200 to M203 and is same as the MSA of FIG. 5. But, in the pre-sense amplifier PSA (M208, M209), the sources which are connected in common are connected to the input/output node of the sub-sense amplifier SSA. The activate signals CSP2 and CSN2 of the sub-sense amplifier are precharged, before the activation, to the VBM potential as shown by the waveforms of FIG. 9 and are driven to 1.0V and 0V at the time T2 in the same timing as the sense amplifier activate signal CSN.

When the sub-sense amplifier 290 is activated, the bit lines BL[n], /BL[n] which are precharged to the half VDD are amplified and simultaneously a current flowing into the M208 and M209 accelerates the amplifying operation of the main sense amplifier 202a consisting of M200 to M203. As a result, the local bit lines LBL[n], /LBL[n] precharged to the VDD are amplified at a high speed up to 1.0V and 0V. Moreover, since the sub-sense amplifier simultaneously amplifies the bit lines BL[n], /BL[n], the charging time of the bit lines BL[n], /BL[n] can be shortened when the write back signal RBK is activated at the time T2'.

When it is not so much required to consider the rate of re-write operation, the re-write operation may be conducted only with the sub-sense amplifier 290 by eliminating the M206 and M207.

The effect of shortening the time required for the re-write operation can also be obtained by adding a sub-sense amplifier 290 consisting of M290 and M293 to the bit lines BL[n], /BL[n] of the sensing system circuit of the present invention of FIG. 1, FIG. 5 and FIG. 7. Moreover, it is of course possible to delete the NMOS transistors M206 and M207 for re-write operation.

Various structures of sense amplifier can be considered when there is no particular restriction on the number of transistors and on the area as explained above and these structures are also not placed under the particular restriction.

Embodiment 5

As the other embodiment, it is also possible that the bit lines BL[n], /BL[n] connected to the memory cell and is precharged to the half VDD and the local bit lines LBL[n], /LBL[n] connected to the sense amplifier are electrically isolated immediately before the sense amplifier is activated, the local bit lines LBL[n], /LBL[n] are simultaneously driven through the capacitance coupling and the local bit lines LBL[n], /LBL[n] are precharged to the VDD when the sense amplifier is activated. FIG. 1 shows an embodiment to realize this purpose.

The sensing system circuit of the present invention of FIG. 10 inserts, in comparison with the sensing system circuit of FIG. 18, the PMOS transistors M260 and M261 to the bit lines BL[n], /BL[n] of FIG. 18 to control these transistors with a bit line isolation signal /SH.

FIG. 11 shows an example of read operation waveforms of the sensing system in the embodiment of FIG. 10. In this figure, only a part different from the read operation of FIG. 19 is explained to eliminate duplicated explanation. After the word line WL[m] is asserted at the time T1, the bit line isolation signal /SH is driven up to 2.5V from -0.8V at the time T1'. Thereby, the bit lines BL[n], /BL[n] are electrically isolated from the local bit lines LBL[n], /LBL[n] and moreover the local bit lines LBL[n], /LBL[n] are simultaneously driven to the high level through the capacitance coupling between the gate and drain of the M260 and M261 or between the capacitances of gate and source. Thereafter, the sense amplifier 201 is driven at the time T2 to amplify the memory cell information to the local bit lines LBL[n], /LBL[n]. At the time T2', the bit line isolation signal /SH is driven up to -0.8V from 2.5V, the bit lines BL[n], /BL[n] and the local bit lines LBL[n], /LBL[n] are electrically connected and the bit lines BL[n], /BL[n] are driven to 1V and 0V to conduct re-write operation to the memory cell.

When the sense amplifier is driven at the time T2, the local bit lines LBL[n], /LBL[n] connected to the sense amplifier are driven up to a voltage near the power source voltage from the voltage near to 0.5V. Therefore, the low voltage characteristic which is similar to that when the sensing system circuit of FIG. 18 is precharged to the VDD can be attained.

In FIG. 10, the PMOS transistor has been used for the M260 and M261, but the NMOS transistor may also be used. In this case, the signal /SH is driven to a negative voltage from a positive voltage at the time T1' and the local bit lines LBL[n], /LBL[n] are simultaneously driven to the low voltage side through the capacitance coupling. As a result, the characteristic similar to that when the sensing system circuit of FIG. 18 is precharged to the voltage VSS can be obtained. In general, since the VDD precharge system is mainly used for driving of the bit lines by the NMOS transistors at the time of driving the bit lines with the sense amplifier, this VDD precharge system has the more excellent low voltage characteristic than the VSS precharge system. However, the low voltage characteristic which is remarkably preferable to that of the half VDD precharge system can be attained with the VSS precharge system.

The sensing system circuit disclosed in the [Reference 4] may be considered as a technique similar to the embodiment of the present invention shown in FIG. 10. The [Reference 4] discloses that the bit lines connected to the memory cell are isolated electrically from the sense amplifier before activation of the sense amplifier (sense operation 1), thereafter the bit lines are driven to the high level through the capacitance coupling with the capacitor adding the bit lines in the side where the sense amplifier is connected after a constant period (sense operation 2) and thereafter the bit lines activate the sense amplifier (sense operation 3).

This embodiment of the present invention is different from the [Reference 4] mainly in the following two points.

(F1) In the method of the [Reference 4], it is necessary to add the capacitance for driving the bit lines in the side connected to the sense amplifier through the capacitance coupling. In the method of the present invention, the signal/SH is set to a sufficiently large value and moreover the local bit lines are driven with the