Semiconductor device and method for driving the same Number:7,436,731 from the United States Patent and Trademark Office (PTO) owispatent As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption is provided. The present invention provides a semiconductor device with reduced drive voltage in a period of storing a value, compared with a period of writing a value or a period of reading a value. Such a semiconductor device includes a power supply control circuit including an OR circuit electrically connected to a word line, an inverter circuit electrically connected to the OR circuit, and a transistor electrically connected to the OR circuit and the inverter circuit.<H Semiconductor, driving, Semiconductor, d, 7436731.html, Patent, pto, 7436731

Title: Semiconductor device and method for driving the same

Abstract: As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption is provided. The present invention provides a semiconductor device with reduced drive voltage in a period of storing a value, compared with a period of writing a value or a period of reading a value. Such a semiconductor device includes a power supply control circuit including an OR circuit electrically connected to a word line, an inverter circuit electrically connected to the OR circuit, and a transistor electrically connected to the OR circuit and the inverter circuit.

Patent Number: 7,436,731 Issued on 10/14/2008 to Iwata

Inventors: Iwata; Syusuke (Hyogo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Atsugi-shi, Kanagawa-ken, JP)

Appl. No.: 11/459,779

Filed: July 25, 2006

Foreign Application Priority Data


Jul 29, 2005 [JP]			2005-220530

Current U.S. Class: 365/226 ; 365/189.05; 365/189.09

Current International Class: G11C 5/14 (20060101)

Field of Search: 365/226,189.05,189.09,156,230.05

References Cited [Referenced By]

U.S. Patent Documents


4964084	October 1990	Jung et al.
5602792	February 1997	Kanaishi
5663905	September 1997	Matsuo et al.
5777926	July 1998	Trinh et al.
5870331	February 1999	Hwang et al.
5949706	September 1999	Chang et al.
6011711	January 2000	Hodges et al.
6046942	April 2000	Hwang et al.
6262932	July 2001	Nguyen
6385081	May 2002	Shiomi
6608780	August 2003	Shau
6972987	December 2005	Wong et al.
2004/0105299	June 2004	Joshi
2004/0246805	December 2004	Nii
2005/0002215	January 2005	Morishima
2005/0063232	March 2005	Chan et al.
2006/0215465	September 2006	Bhavnagarwala et al.

Foreign Patent Documents


10-106267	Apr., 1998	JP
2005-044142	Feb., 2005	JP
WO01-20612	Mar., 2001	WO

Other References

European Search Report (Application No. 06015504.1), dated Apr. 19, 2007 in English (7 pages). cited by other.

Primary Examiner: Elms; Richard T.
Assistant Examiner: Le; Toan
Attorney, Agent or Firm: Fish & Richardson P.C.

Claims

What is claimed is:

1. A semiconductor device comprising a power supply control circuit, and a memory cell, wherein the power supply control circuit comprises: a first word line; a second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit, wherein the memory cell comprises a second inverter circuit, and is electrically connected to the first word line and the second word line.

2. A semiconductor device according to claim 1, wherein the means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell comprises two transistors.

3. A semiconductor device according to claim 1, wherein the circuit which comprises two input terminals and one output terminal in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, comprises either of an OR circuit, a circuit comprising a NOR circuit and an inverter circuit, or a circuit comprising two inverter circuits and a NAND circuit.

4. A semiconductor device comprising a power supply control circuit, and a memory cell, wherein the power supply control circuit comprises: a first word line; a second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit, wherein the memory cell comprises a second inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to the first word line and the second word line.

5. A semiconductor device according to claim 4, wherein the means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell comprises two transistors.

6. A semiconductor device according to claim 4, wherein the circuit which comprises two input terminals and one output terminal in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, comprises either of an OR circuit, a circuit comprising a NOR circuit and an inverter circuit, or a circuit comprising two inverter circuits and a NAND circuit.

7. A semiconductor device comprising a power supply control circuit, and a memory cell, wherein the power supply control circuit comprises: a first word line; a second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit, wherein the memory cell is electrically connected to the first word line and the second word line, and comprises a second inverter circuit electrically connected to a ground line and a power supply line, and a transistor electrically connected to the second inverter circuit; and wherein a gate electrode of the transistor is electrically connected to the first word line.

8. A semiconductor device according to claim 7, wherein the means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell comprises two transistors.

9. A semiconductor device according to claim 7, wherein the circuit which comprises two input terminals and one output terminal in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, comprises either of an OR circuit, a circuit comprising a NOR circuit and an inverter circuit, or a circuit comprising two inverter circuits and a NAND circuit.

10. A semiconductor device according to claim 7, wherein the transistor is a thin film transistor formed over an insulating substrate.

11. A semiconductor device according to claim 7, wherein the first word line and the power supply line are formed of the same material as the gate electrode of the transistor.

12. A semiconductor device comprising a power supply control circuit, and a memory cell, wherein the power supply control circuit comprises: a first word line; a second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit, wherein the memory cell is electrically connected to the first word line and the second word line, and comprises a second inverter circuit electrically connected to a ground line and a power supply line, and first to third transistors each electrically connected to the second inverter circuit, and wherein a gate electrode of the first transistor is electrically connected to the first word line, one of either a source electrode or a drain electrode of each of the second transistor and the third transistor is electrically connected to a data line, and gate electrodes of the second transistor and the third transistor are electrically connected to the second word line.

13. A semiconductor device according to claim 12, wherein the data line is provided in the same layer as the source electrode and the drain electrode of the transistor.

14. A semiconductor device according to claim 12, wherein the means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell comprises two transistors.

15. A semiconductor device according to claim 12, wherein the circuit which comprises two input terminals and one output terminal in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, comprises either of an OR circuit, a circuit comprising a NOR circuit and an inverter circuit, or a circuit comprising two inverter circuits and a NAND circuit.

16. A semiconductor device according to claim 12, wherein the transistor is a thin film transistor formed over an insulating substrate.

17. A semiconductor device according to claim 12, wherein the first word line and the power supply line are formed of the same material as the gate electrode of the transistor.

18. A method for driving a semiconductor device, wherein the semiconductor device comprises: a memory cell electrically connected to a first word line and a second word line and comprising a first inverter circuit; and a power supply control circuit comprising: the first word line; the second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a second inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; a first transistor comprising a gate electrode electrically connected to an output terminal of the second inverter circuit; a second transistor electrically connected to the output terminal of the circuit; and a power supply line electrically connected to the first transistor and the second transistor, wherein the first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and a first voltage is supplied to the power supply line in a period of writing a value into the memory cell, and wherein the first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and a second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell.

19. A method for driving a semiconductor device, wherein the semiconductor device comprises: a memory cell which comprises a first inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to a first word line and a second word line; and a power supply control circuit comprising: the first word line; the second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a second inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the second inverter circuit, wherein the first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line in a period of writing a value into the memory cell, and wherein the first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and the second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell.

20. A method for driving a semiconductor device, wherein the semiconductor device comprises: a memory cell electrically connected to a first word line and a second word line and comprising a first inverter circuit; and a power supply control circuit comprising: the first word line; the second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a second inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; a first transistor comprising a gate electrode electrically connected to an output terminal of the second inverter circuit; a second transistor electrically connected to the output terminal of the circuit; and a power supply line electrically connected to the first transistor and the second transistor, wherein the first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and a first voltage is supplied to the power supply line electrically connected to the first transistor in a period of writing a value into the memory cell, wherein the first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and a second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell, and wherein the first word line is at a LOW level and the second word line is at a HIGH level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of reading the value written into the memory cell.

21. A method for driving a semiconductor device, wherein the semiconductor device comprises: a memory cell which comprises a first inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to a first word line and a second word line; and a power supply control circuit comprising: the first word line; the second word line; a circuit comprising one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a second inverter circuit comprising an input terminal electrically connected to the output terminal of the circuit; and means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the second inverter circuit, wherein the first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of writing a value into the memory cell, wherein the first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and the second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell, and wherein the first word line is at a LOW level and the second word line is at a HIGH level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of reading the value written into the memory cell.

22. A semiconductor device comprising a power supply control circuit, and a memory cell, wherein the power supply control circuit comprises: at least a first word line and a second word line; two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line; and a output terminal which is selectively connectable to one of a first voltage source and a second voltage source in accordance with input levels of the first word line and the second word line, wherein the memory cell are electrically connected to the first word line, the second word line and the output terminal.

23. A semiconductor device according to claim 22, wherein a second voltage supplied from the second voltage source is lower than a first voltage supplied from the first voltage source.

24. A semiconductor device according to claim 22, wherein the power supply control circuit comprises at least one of an OR circuit, a NOR circuit, an inverter circuit, and a NAND circuit.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including a memory element and a driving method of the semiconductor device.

2. Description of the Related Art

With miniaturization of a wiring by development of LSI (Large Scale Integration) manufacturing techniques, a problem of a leak current has become significant. The leak current causes problems such as heat of the LSIs or increase of power consumption. In particular, a problem of power consumption directly affects a continuous operating time of portable devices such as mobile phones and notebook personal computers, which becomes a serious problem. Therefore, various kinds of techniques are suggested for lowering power consumption of the LSIs.

For example, as the operation of LSIs, there are cases where the maximum performance is required or not. When the operating speed of the LSIs is not required to be very high, there is a technique in which a frequency of a clock is reduced to operate the LSIs. Similarly, when the maximum operating speed is not required, there is a technique in which a substrate bias is shifted and the threshold is controlled, so that a leak current is reduced.

In addition, a very high-capacity memory such as a cache is provided inside recent LSIs, and the LSIs are often composed of an SRAM (Static Random Access Memory). The SRAM stores a value by connecting inverter circuits to each other. An electric state is not changed once a value is stored; however, a leak current flows out of a power supply line which is electrically connected to the inverter circuit into a ground line.

As a configuration of an SRAM of which power consumption is reduced, a switching MOS transistor is provided between a power supply line of a memory cell group which is selected by each word line of a row decoder of the SRAM and a power supply line of a voltage supply source side, and the switching MOS transistor is opened or closed by a selection signal from the word line (Reference 1: Japanese Patent Laid-Open No. Hei 10-106267).

SUMMARY OF THE INVENTION

An operation of an SRAM includes writing and reading. Only a portion of the whole memory operates during performing this operation, and another portion thereof stores a value. A predetermined voltage is required for the operation of writing or reading; however, the predetermined voltage is not required for the operation of storing a value, and an off-current can be reduced by lowering a power supply voltage.

The SRAM disclosed in Patent Document 1 describes a structure where power of an address is changed to cut the power. However, when the power is cut, electricity flows into the ground line by the off-current of a transistor applied to the SRAM, and storing a value is considered difficult.

Thus, in the present invention, a power supply method is controlled in a memory by a method that is different from that in Patent Document 1 at the time of operating the LSI, and power consumption of the LSI is suppressed by reducing the leak current of the transistor.

In view of the aforementioned problem, it is an object of the present invention to reduce a drive voltage in a period of storing a value compared with a period of writing a value or a period of reading a value. That is, a first voltage is supplied to a power supply line of a memory cell in a period of writing the value in the memory cell in accordance with the present invention, while a second voltage lower than the first voltage is supplied to the power supply line of the memory cell in a period of storing the written value.

Specific structures of the present invention are shown below.

One mode of the present invention is a semiconductor device including a memory cell including an inverter circuit electrically connected to a power supply line, in which a first voltage is supplied to the power supply line in a period of writing a value to the memory cell. A second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell. The first voltage is supplied to the power supply line in a period of reading the value written into the memory cell.

Another mode of the present invention is a semiconductor device including a power supply control circuit and a memory cell. The power supply control circuit includes a first word line; a second word line; a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit having an input terminal electrically connected to the output terminal of the circuit; and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit. The memory cell includes a second inverter circuit, and is electrically connected to the first word line and the second word line.

Another mode of the present invention is a semiconductor device including a power supply control circuit and a memory cell. The power supply control circuit includes a first word line; a second word line; and a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit having an input terminal electrically connected to the output terminal of the circuit; and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit. The memory cell includes a second inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to the first word line and the second word line.

Another mode of the present invention is a semiconductor device including a power supply control circuit and a memory cell. The power supply control circuit includes a first word line; a second word line; a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit having an input terminal electrically connected to the output terminal of the circuit; and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit. The memory cell includes a second inverter circuit electrically connected to a ground line and a power supply line, and a transistor electrically connected to the second inverter circuit, which is electrically connected to the second word line and the first word line which is electrically connected to a gate electrode of the transistor.

Another mode of the present invention is a semiconductor device including a power supply control circuit and a memory cell. The power supply control circuit includes a first word line; a second word line; a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals; a first inverter circuit having an input terminal electrically connected to the output terminal of the circuit; and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit. The memory cell includes a second inverter circuit electrically connected to a ground line and a power supply line; first to third transistors each electrically connected to the second inverter circuit; the first word line electrically connected to a gate electrode of the first transistor; and a data line electrically connected to one of either a source electrode or a drain electrode of each of the second transistor and the third transistor. The semiconductor device is electrically connected to the first word line and the second word line which is electrically connected to gate electrodes of the second transistor and the third transistor.

In the present invention, the means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell includes two transistors.

In the present invention, the circuit including two input terminals and one output terminal, in which a HIGH level is outputted when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted when a LOW level is inputted to both of the input terminals, which includes an OR circuit, a circuit including a NOR circuit and an inverter circuit, or two inverter circuits and a NAND circuit.

In the present invention, the word line and the power supply line can be provided in the same layer as the gate electrode of a thin film transistor.

In the present invention, the data line can be formed of the same material as a source electrode and a drain electrode of the thin film transistor.

Another mode of the present invention is a driving method of a semiconductor device including a memory cell electrically connected to a first word line and a second word line, and including a first inverter circuit, and a power supply control circuit. The power supply control circuit includes the first word line, the second word line, a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, a second inverter circuit having an input terminal electrically connected to the output terminal of the circuit, a first transistor having a gate electrode electrically connected to an output terminal of the second inverter circuit, a second transistor electrically connected to the output terminal of the circuit, and a power supply line electrically connected to the first transistor and the second transistor. The first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and a first voltage is supplied to the power supply line in a period of writing a value into the memory cell. The first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and a second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell.

Another mode of the present invention is a driving method of a semiconductor device including a memory cell including a first inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to a first word line and a second word line; and a power supply control circuit including the first word line, the second word line, a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, a second inverter circuit having an input terminal electrically connected to the output terminal of the circuit, and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the second inverter circuit The first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line in a period of writing a value into the memory cell. The first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and the second voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell.

Another mode of the present invention is a driving method of a semiconductor device including a memory cell electrically connected to a first word line and a second word line, and including a first inverter circuit, and a power supply control circuit. The power supply control circuit includes the first word line, the second word line, a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, a second inverter circuit having an input terminal electrically connected to the output terminal of the circuit, a first transistor having a gate electrode electrically connected to an output terminal of the second inverter circuit, a second transistor electrically connected to the output terminal of the circuit, and a power supply line electrically connected to the first transistor and the second transistor. The first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and a first voltage is supplied to the power supply line electrically connected to the first transistor in a period of writing a value into the memory cell. The first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and a voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell. The first word line is at a LOW level and the second word line is at a HIGH level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of reading the value written into the memory cell.

Another mode of the present invention is a driving method of a semiconductor device including a memory cell including a first inverter circuit electrically connected to a ground line and a power supply line, and is electrically connected to a first word line and a second word line; and a power supply control circuit. The power supply control circuit includes the first word line, the second word line, a circuit including one output terminal, and two input terminals, one of which is electrically connected to the first word line and the other of which is electrically connected to the second word line, in which a HIGH level is outputted to the output terminal when a HIGH level is inputted to either one of the input terminals, and a LOW level is outputted to the output terminal when a LOW level is inputted to both of the input terminals, a second inverter circuit having an input terminal electrically connected to the output terminal of the circuit, and a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the means being electrically connected to the circuit and the first inverter circuit. The first word line is at a HIGH level and the second word line is at a LOW level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of writing a value into the memory cell. The first word line and the second word line are at a LOW level, so that the second transistor is turned ON, and a voltage lower than the first voltage is supplied to the power supply line in a period of storing the value written into the memory cell. The first word line is at a LOW level and the second word line is at a HIGH level, so that the first transistor is turned ON, and the first voltage is supplied to the power supply line electrically connected to the first transistor in a period of reading the value written into the memory cell.

By the present invention, low power consumption of a semiconductor device provided with a memory can be achieved. In particular, as a function of the LSI becomes complex, the capacity of a memory required for the LSI also increases, and a ratio of an area of the memory to a chip also increases. As the capacity of the memory increases, the ratio of an area of a memory cell, which requires a predetermined voltage, to the whole SRAM decreases, so that the advantageous effect of the invention is increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of an SRAM memory of the present invention;

FIG. 2 is a circuit diagram showing a configuration of a memory cell of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a power supply control circuit of the present invention;

FIG. 4 is a timing chart of an SRAM memory of the present invention;

FIG. 5 is a diagram showing a configuration of an SRAM memory of the present invention;

FIG. 6 is a circuit diagram showing a configuration of a power supply control circuit of the present invention;

FIG. 7 is a timing chart of a power supply control circuit of the present invention;

FIG. 8 is a top plan view corresponding to a memory cell of the present invention;

FIGS. 9A to 9D are cross-sectional views corresponding to a memory cell of the present invention;

FIG. 10 is a block diagram showing a CPU on which an SRAM memory of the present invention can be mounted; and

FIGS. 11A to 11E are views each showing an electronic apparatus of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment Mode

A semiconductor device in accordance with the present invention includes a memory cell array in which a plurality of memory cells is arranged, a read circuit for controlling a bit line which performs writing and reading, and an address decoder for controlling a word line. Further, a power supply control circuit is provided between the address decoder and the memory cell array. When a signal is outputted from the address decoder to the word line, the power supply control circuit controls a power supply line which is extended to the memory cell array and electrically connected to the memory cell in synchronization with the signal. At this time, a predetermined power supply voltage is applied to the power supply line.

The memory cell is formed to have a structure in which inverter circuits are electrically connected in series. Specifically, two inverter circuits are provided such that an output terminal of one inverter circuit is electrically connected to an input terminal of the other inverter circuit, and an input terminal of one inverter circuit is electrically connected to an output terminal of the other inverter. That is, a static RAM is formed.

A power supply control circuit includes at least two word lines; a circuit including one output terminal, and two input terminals which are electrically connected to the respective word lines, which outputs a HIGH level when a HIGH level is inputted to either one of the input terminals, and outputs a LOW level when a LOW level is inputted to both of the input terminals; an inverter circuit electrically connected to the circuit; and a means which is electrically connected to the circuit and the inverter circuit, which applies a first voltage or a second voltage lower than the first voltage to a memory cell. Two transistors electrically connected in series can be used as the means which applies the first voltage or the second voltage lower than the first voltage to the memory cell. The first voltage is supplied when writing/reading a value to/from the memory cell, while the second voltage is supplied when storing the value. Accordingly, compared with a period of writing the value or a period of reading the value, a drive voltage in a period of storing the value can be lowered and low power consumption of the memory cell can be achieved.

Such a memory array can be employed as a CPU (Central Processing Unit) or a cache memory of an MPU (Microprocessor). By applying the memory array to a CPU or an MPU, low power consumption of the CPU or the MPU can be achieved.

Embodiments of the present invention are described with reference to the drawings below. It is to be understood that various changes and modifications will be apparent to those skilled in the art. Therefore, unless such changes and modifications depart from the scope of the present invention, they should be construed as being included therein. Note that the same reference numeral is used to denote the same portion or a portion having a similar function among diagrams for illustrating the embodiments, and repetitive description is omitted.

A voltage value in embodiments shown below is one example, and the present invention is not limited to this value.

Embodiment 1

In this embodiment, a configuration of an SRAM memory of the present invention is described. In addition, a device including a semiconductor element such as an SRAM memory of the present invention can be called a semiconductor device.

FIG. 1 shows an example of a configuration of an SRAM memory of the present invention. A memory 103 is a byte address memory and includes addresses of from 0 to 63. The memory 103 has a structure in which 8-bit memory cells are provided in a horizontal direction and 64 lines of from an address 0 to an address 63 are provided in a vertical direction.

A memory cell 104 can store a value of 1 bit, and a memory cell array 102 includes the memory cells 104 of 8 bits.times.64 lines.

A write/read circuit 101 writes data from the outside of the memory to the memory cell array 102, reads data from the memory cell array 102, and transmits the data to the outside of the memory.

An address decoder 105 decodes a 6-bit address from the outside of the memory to be inputted into 64 word lines.

The address decoder 105 outputs a signal to word lines WR0 to WR63 or WW0 to WW63, and the signal is inputted to a power supply control circuit 106 to control power supply lines V0 to V63 of the memory cell array 102. A predetermined power supply voltage is applied to the power supply lines.

The word lines WR0 to WR63 can function as word lines for reading and WW0 to WW63 can function as word lines for writing with an output signal from the address decoder 105. That is, one of WW0 to WW63 is in a state of a high-potential side (hereinafter referred to as "a HIGH level") at the time of writing, while one of WR0 to WR63 is at a HIGH level at the time of reading. For example, only WR0 is at a HIGH level in the case where of reading a value from the address 00, while only WW63 is at a HIGH level in the case of writing a value into the address 63.

BR0 to BR7 are bit lines for reading and BW0 to BW7 are bit lines for writing. At the time of reading, values of memory cells of 8 bits selected by an address are inputted to BR0 to BR7. At the time of writing, data from the outside is inputted to BW0 to BW7.

By such an SRAM memory, data of 8 bits.times.64=512 bits can be stored.

Next, a configuration example of the memory cell 104 is shown. Note that in this embodiment, description is made of the case where 5 V is supplied as a power supply voltage in a reading period and a writing period, and 3 V is supplied as a power supply voltage in a storing period. However, the present invention is not limited to these values.

The memory cell 104 shown in FIG. 2 includes data lines 201 and 202 for writing, a data line 203, a word line 204 for writing, a power supply line 205, a ground line 206, a word line 207 for reading, N-channel transistors 208, 209, 210, and 212, a node 211, and an inverter circuit 213.

The inverter circuit 213 includes two inverter circuits 213a and 213b. An input terminal of the inverter circuit 213a is electrically connected to an output terminal of the inverter circuit 213b, while an output terminal of the inverter circuit 213a is electrically connected to an input terminal of the inverter circuit 213b. One electrode of the inverter circuit 213a and one electrode of the inverter circuit 213b included in the inverter circuit 213 are electrically connected to the power supply line 205. The other electrode of the inverter circuit 213a and the other electrode of the inverter circuit 213b are electrically connected to the ground line 206. A gate electrode of the transistor 208 and a gate electrode of the transistor 209 are electrically connected to the word line 204. One of either a source electrode or a drain electrode of the transistor 208 is electrically connected to the data line 201, while the other of either the source electrode or the drain electrode thereof is electrically connected to an output terminal of the inverter circuit 213a in the inverter circuit 213. The gate electrode of the transistor 209 is electrically connected to the word line 204, one of either a source electrode or a drain electrode thereof is electrically connected to the data line 202, and the other of either the source electrode or the drain electrode thereof is electrically connected to an output terminal of the inverter circuit 213b in the inverter circuit 213. A gate electrode of the transistor 212 is electrically connected to the node 211, one of either a source electrode or a drain electrode thereof is electrically connected to the ground line 206, and the other of either the source electrode or the drain electrode thereof is electrically connected to one of either a source electrode or a drain electrode of the transistor 210. A gate electrode of the transistor 210 is electrically connected to the word line 207, and the other of either the source electrode or the drain electrode thereof is electrically connected to the data line 203.

A normal value which is a writing value is inputted to the data line 201 for writing, while an inverted value is inputted to the data line 202 for writing. In the period other than the reading time, a normal value is written into the data line 203 for reading when the memory cell stores 1, while an inverted value is written into the data line 203 for reading when the memory cell stores 0, so that 5 V is precharged in the data line 203 by the read circuit 101.

At the time of writing, the word line 204 has 5 V and the transistors 208 and 209 are turned ON, so that a value can be written into the memory cell.

At the time of reading, the word line 207 is at a HIGH level and the transistor 210 is turned ON. In the case where the value of the memory cell is 0, a voltage of the node 211 has 5 V and the transistor 212 is turned ON, so that a voltage of the data line 203 which has been precharged is set as 0 V by the transistors 210 and 212. In the case where the value of the memory cell is 1, the transistor 212 is not turned ON so that the data line 203 is kept unchanged as 5 V since it has been precharged.

In this manner, the memory cell requires the same voltage as the overall power supply voltage of a device at the time of reading or writing. However, a value is stored in a state that only an inverter circuit is electrically separated from an LSI system in the period of storing a written value other than writing or reading. That is, in the period of storing a value, there is no exchange of a signal with the outside of the memory cell, and two inverter circuits in the inverter circuit 213 are only required to be operated. When a value is written into the memory cell once, two transistors among the four transistors in the inverter circuit 213 are turned ON and the other two transistors are turned OFF. The magnitude of a leak current of the memory cell, which flows from the power supply line 205 to the ground line 206, is determined with the two transistors in the OFF state. Although a voltage of 5 V is supplied to a conventional memory cell in the period of storing a value, a voltage of 3 V is supplied in the present invention in the period of storing a value. The leak current of the transistor in the OFF state is smaller by decreasing the power supply voltage. Accordingly, low power consumption of a memory element can be achieved. The power supply control circuit 106 is provided in order to perform such an operation.

Next, a configuration example of the power supply control circuit 106 and an operation thereof are shown. The power supply control circuit 106 includes an OR circuit 320, an inverter circuit 321, P-channel transistors 301 and 302, the word lines WR0 to WR63, and WW0 to WW63 as shown in FIG. 3. A NOR circuit and an inverter circuit, or two inverter circuits and a NAND circuit can be used as a substitute for the OR circuit 320. That is, a circuit, including two input terminals and one output terminal and having a function in which a HIGH level is outputted when a signal on a high-potential side is inputted to either of the input terminals, while a signal on a low-potential side (hereinafter referred to as "a LOW level") is outputted when a LOW level is inputted to both of the input terminals, may be used. Note that here, one input terminal is electrically connected to the word line WR0, the other input terminal is electrically connected to the word line WW0, and the output terminal is electrically connected to the input terminal of the inverter circuit.

The input terminals of the OR circuit 320 are electrically connected to the word lines WR0 to WR63 and WW0 to WW63, while the output terminal thereof is electrically connected to a gate electrode of the transistor 301 and an input terminal of the inverter circuit 321. An output terminal of the inverter circuit 321 is electrically connected to a gate electrode of the transistor 302. One of either a source electrode or a drain electrode of the transistor 301 and one of either a source electrode or a drain electrode of the transistor 302 are electrically connected to each other, which are also electrically connected to a power supply line V0.

In such a power supply control circuit 106, an output from the word line of the address decoder 105 is used as an input, and the word lines WR and WW are used as the input terminals of the OR circuit. A power supply voltage of 5 V is supplied to the power supply lines at the time when a corresponding address is at the time of reading or writing, and 3 V is supplied at the time other than that by an output of the OR circuit. For example, since WR0 is 1, a node 311 is at a LOW level, and a node 310 is at a HIGH level at the time of reading a value from the address 00, the transistor 302 is turned ON, and 5 V is supplied to the power supply line V0. As for a power supply voltage of other addresses, the transistor 301 electrically connected to 3 V is turned ON, and 3 V is supplied to V1 to V63. That is, for example, in a period of writing a value to the memory cell, the word line WR0 is at a HIGH level, the word line WW0 is at a LOW level, the transistor 302 is turned ON, and a first voltage is supplied to a power supply line electrically connected to the transistor 302. Then, in a period of storing a value written into the memory cell, the word line WR0 and the word line WW0 are at a LOW level, the transistor 301 is turned ON, and a voltage lower than the first voltage is supplied to the power supply line. Then, in a period of reading the value written into the memory cell, the word line WR0 is at a LOW level, the word line WW0 is at a HIGH level, the transistor 302 is turned ON, and the first voltage is supplied to the power supply line electrically connected to the transistor 302. Here, the transistors 301 and 302 correspond to a means for supplying the first voltage or the second voltage lower than the first voltage to the memory cell.

In this manner, by using the present invention, a voltage of 3 V is supplied in the period of storing a value, so that low power consumption of a memory element can be achieved compared with a conventional memory cell to which a voltage of 5 V is supplied in the period of storing a value. That is, by the present invention, the voltage supplied to the power supply line in the period of storing the value can be lowered compared with the voltage supplied to the power supply line in the period of writing or reading a value, so that low power consumption of the memory cell can be achieved.

Embodiment 2

In this embodiment, an operation of the SRAM memory of the present invention in the case of Embodiment 1 is described with reference to a timing chart.

FIG. 4 shows a timing chart of the SRAM memory of the present invention. A signal of the SRAM of the present invention includes a signal for showing a writing period: WE (write enable), a signal for showing a reading period: RE (read enable), a signal of a data bus written into the SRAM in the writing period: WDATA (write data), a signal of a data bus for reading the data of the SRAM in the reading period: RDATA (read data), a signal of an address bus for performing writing or reading: ADDR (read or write address), and signals to be inputted to the power supply lines V0 to V63. At the time when WE is 1, it is determined that the memory is in a writing period, and an operation of writing the data written from the outside into an address line is performed. At the time when WE is 0, writing is not performed.

WE is at a HIGH level when a value is written into the SRAM, and WE is at a LOW level in the period other than that. RE is at a HIGH level when a value is read from the SRAM, and RE is at a LOW level in the period other than that. In addition, RE can be used for the timing of precharging the data line 203 of FIG. 2, and the data line 203 is precharged by the write/read circuit 101 at timing other than that of reading.

WDATA is an 8-bit bus, and inputted with a value written into the SRAM at the time of writing. RDATA is an 8-bit bus, and inputted with a value read from the SRAM at the time of reading. ADDR is a 6-bit bus, and inputted with an address to be written or read. The inputted address is decoded into a signal to be inputted a 64-bit reading word line or a 64-bit writing word line by the decoder 105. Pulse signals shown as the power supply lines V0 to V63 are the power supply voltages supplied to the addresses 0 to 63 respectively.

A period 401 is a period when WE is at a HIGH level and writing to the SRAM is performed, and a period 402 is a period when RE is at a HIGH level and reading is performed.

In a period 403, data 00 inputted to the WDATA bus is written into the address 00 inputted to the ADDR bus. At this time, a voltage of the power supply line V0 supplied to the address 00 is 5 V, and voltages of the power supply lines V1 to V63 of the addresses other than that are 3 V. Similarly, a period 404 is a period of writing data to the address 01, 5 V is supplied only to the power supply line V1 supplied to the memory cell of the address 01, and 3 V is supplied to the other power supply lines V0, and V2 to V63. Similarly, in a period 405 and a period 406, 5 V is supplied only to the power supply lines V62 and V63 of the address 62 and the address 63 respectively, and 3 V is supplied to the other addresses.

In a period 407, data is read from the address 00 which is inputted to the ADDR bus, and its value 00 is inputted to the RDATA bus. At this time, 5 V is supplied to the power supply line V0 of the memory cell of the address 00, and 3 V is supplied to the power supply lines V1 to V63 of the addresses other than that.

A period 408 is a period in which the data bus RDATA for reading a value of the SRAM is precharged to a HIGH level. In the case of the configuration of the SRAM shown in Embodiment 1, since the memory cell of the SRAM cannot set a data bus to be at a HIGH level, it is necessary to set RE at a LOW level, and precharge by the write/read circuit 101. Accordingly, a value is read from a certain address in the reading period 402, and a period in which RE is at a LOW level is required in the case where data of a different address is read next. In this manner, in a period in which WE is at a LOW level and RE is also at a LOW level, 3 V is supplied to all the power supply lines V0 to V63 supplied to the memory cell of the SRAM. This period is a period of storing the written value.

By the present invention where a voltage of 3 V is supplied in the period of storing a value, and low power consumption of a memory element can be achieved, compared with a conventional memory cell, where a voltage of 5 V is supplied also in the period of storing a value in the memory cell.

Embodiment 3

In the case of the configuration of the power supply control circuit 106 shown in Embodiment 1, power required for an operation of writing or reading is supplied to the SRAM memory at the same timing as performing writing or reading. Howeve