Title: Semiconductor display device and manufacturing method thereof
Abstract: A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled. Therefore, the GOLD structure TFT having both the hot carrier resistance and the off-current suppressing effect can be formed and the simplification of a manufacturing process of the semiconductor display device and the improvement of performance thereof are compatible with each other.
Patent Number: 6,909,117 Issued on 06/21/2005 to Ohnuma
| Inventors:
|
Ohnuma; Hideto (Kanagawa, JP)
|
| Assignee:
|
Semiconductor Energy Laboratory Co., Ltd. (JP)
|
| Appl. No.:
|
386257 |
| Filed:
|
March 11, 2003 |
Foreign Application Priority Data
| Sep 22, 2000[JP] | 2000-289457 |
| Current U.S. Class: |
257/72; 257/69; 257/204; 257/257; 257/291; 257/359 |
| Intern'l Class: |
H01L 029/04; H01L031/03.6 |
| Field of Search: |
257/291,359,72,69,204,257
|
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|
Primary Examiner: Zarabian; Amir
Assistant Examiner: Soward; Ida M.
Attorney, Agent or Firm: Cook, Alex, McFarron, Manzo, Cummings & Mehler, Ltd.
Parent Case Text
This application is a divisional of U.S. application Ser. No. 09/957,915, filed
on Sep. 21, 2001 now U.S. Pat. No. 6,562,671.
Claims
1. A semiconductor device comprising a plurality of thin film transistors formed
over a transparent insulating substrate, each of said thin film transistors comprising:
a semiconductor layer, a gate insulating film, and a gate electrode being laminated
in order from a side near the transparent insulating substrate, and a source region
and a drain region being formed in the semiconductor layer outside the gate electrode,
wherein the gate electrode comprises a first layer gate electrode and a second
layer gate electrode located over the first layer gate electrode wherein the first
layer gate electrode extends beyond a side edge of the second layer gate electrode,
wherein a first impurity region is formed in the semiconductor layer below the
extending portion of the first layer gate electrode,
wherein a second impurity region and the source region or the drain region are
formed adjacent to each other from a side near the gate electrode in the semiconductor
layer being the outside of a side edge of the first gate electrode, and
wherein an impurity concentration of the first impurity region is higher than
that of the second impurity region and lower than that of the source region or
the drain region.
2. A device according to claim 1, wherein the first impurity region, the second
impurity region, and the source region or the drain region are the same conductivity
type impurity regions and have one of an n-type and a p-type as a conductivity type.
3. A device according to claim 1, wherein the first layer gate electrode and
the second layer gate electrode comprise different high melting metals.
4. A device according to claim 1, wherein the first layer gate electrode comprises
a TaN film as a compound containing high melting metal and the second layer gate
electrode comprises a W film as the high melting metal.
5. A device according to claim 1, wherein the semiconductor layer comprises one
of a polycrystalline silicon film and a crystalline silicon film formed using a
catalyst element.
6. An electronic equipment having a device according to claim 1, wherein the
electronic equipment is selected from the group consisting of a video camera, a
digital camera, a rear type projector, a front type projector, a head mounted display,
a goggle type display, a game machine, a car navigation system, a personal computer,
a mobile computer, a mobile telephone, an electronic book, a personal computer,
and a recording medium.
7. A semiconductor device comprising a plurality of n-channel thin film transistors
formed over a transparent insulating substrate, each of the n-channel thin film
transistors comprising:
a semiconductor layer, a gate insulating film, and a gate electrode being laminated
in order from a side near the transparent insulating substrate, and a source region
and a drain region being formed in the semiconductor layer outside the gate electrode,
wherein the gate electrode comprises a first layer gate electrode and a second
layer gate electrode located over the first layer gate electrode wherein the first
layer gate electrode extends beyond a side edge of the second layer gate electrode,
wherein a first impurity region is formed in the semiconductor layer below the
extending portion of the first layer gate electrode,
wherein a second impurity region and the source region or the drain region are
formed adjacent to each other from a side near the gate electrode in the semiconductor
layer being the outside of a side edge of the first gate electrode, and
wherein an impurity concentration of the first impurity region is higher than
that of the second impurity region and lower than that of the source region or
the drain region.
8. A device according to claim 7, wherein the first impurity region, the second
impurity region, and the source region or the drain region are n-type impurity regions.
9. A device according to claim 7, wherein an n-type impurity concentration of
the first impurity region is 2×10
16 to 2.7×10
19 atoms/cm
3,
preferably, about 1×10
17 to 5.3×10
18 atoms/cm
3.
10. A device according to claim 7, wherein an n-type impurity concentration of
the second impurity region is 4.7×10
15 to 2.7×10
18 atoms/cm
3,
preferably, about 4.7×10
17 to 5.3×10
17 atoms/cm
3.
11. A device according to claim 7, wherein an n-type impurity concentration of
the source region or the drain region is about 3×10
18 to 5×10
21
atoms/cm
3, preferably, about 1.7×10
19 to 2.7×10
20 atoms/cm
3.
12. A device according to claim 7, wherein the first layer gate electrode and
the second layer gate electrode comprise different high melting metals.
13. A device according to claim 7, wherein the first layer gate electrode comprises
a TaN film as a compound containing high melting metal and the second layer gate
electrode comprises a W film as the high melting metal.
14. A device according to claim 7, wherein the semiconductor layer comprises
one of a polycrystalline silicon film and a crystalline silicon film formed using
a catalyst element.
15. An electronic equipment having a device according to claim 7, wherein the
electronic equipment is selected from the group consisting of a video camera, a
digital camera, a rear type projector, a front type projector, a head mounted display,
a goggle type display, a game machine, a car navigation system, a personal computer,
a mobile computer, a mobile telephone, an electronic book, a personal computer,
and a recording medium.
16. A semiconductor device comprising:
a substrate;
a semiconductor layer formed over the substrate;
a gate insulating film formed over the semiconductor layer;
a gate electrode formed over the semiconductor layer with the gate insulating
film interposed therebetween, said gate electrode including a first conductive
layer and a second conductive layer formed on the first conductive layer wherein
the first conductive layer extends beyond side edges of the second conductive layer;
a pair of first impurity regions formed in the semiconductor layer below the
extending portions of the first conductive layer;
a channel region formed in the semiconductor layer between the pair of first
impurity regions;
source and drain regions formed in the semiconductor layer;
a pair of second impurity regions formed in the semiconductor layer between the
pair of first impurity regions and the source and drain regions,
wherein an impurity concentration of the first impurity region is higher than
that of the second impurity region and lower than that of the source and drain
regions.
17. A device according to claim 16, wherein the substrate is transparent.
18. A device according to claim 16, wherein the first impurity region, the second
impurity region, and the source and drain regions are the same conductivity type
impurity regions and have one of an n-type and a p-type as a conductivity type.
19. A device according to claim 16, wherein the first layer gate electrode and
the second layer gate electrode comprise different high melting metals.
20. A device according to claim 16, wherein the first conductive layer comprises
a TaN film as a compound containing high melting metal and the second layer gate
electrode comprises a W film as the high melting metal.
21. A device according to claim 16, wherein the semiconductor layer comprises
one of a polycrystalline silicon film and a crystalline silicon film formed using
a catalyst element.
22. An electronic equipment having a device according to claim 16, wherein the
electronic equipment is selected from the group consisting of a video camera, a
digital camera, a rear type projector, a front type projector, a head mounted display,
a goggle type display, a game machine, a car navigation system, a personal computer,
a mobile computer, a mobile telephone, an electronic book, a personal computer,
and a recording medium.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor display device having a circuit
comprising thin film transistors (hereinafter referred to as TFTs) and a manufacturing
method thereof. As the semiconductor display device, there is an electro-optical
device such as a liquid crystal display and an EL (electroluminescence) display,
which comprises, for example, the TFTs.
2. Description of the Related Art
Recently, an active matrix liquid crystal display technique using the TFT
is noted. An active matrix display is superior to a passive matrix display in a
response speed, a view angle, and a contrast. Thus, this currently becomes the
mainstream of a note type personal computer, a liquid crystal television, or the like.
The TFT is generally constructed using amorphous silicon or polycrystalline silicon
for a channel layer. In particular, a polycrystalline silicon TFT manufactured
in a low temperature process (generally, 600° C. or lower) has the following
characteristics. That is, a low cost and a large area can be achieved. Simultaneously,
since an electron or a hole has a high electric field mobility, when such a TFT
is used for the liquid crystal display, not only the integration of pixel transistors
but also the integration of drivers as a peripheral circuit can be achieved. Thus,
the development is progressed in each liquid crystal display maker.
However, when the polycrystalline silicon TFT is continuously driven, there
is the case where a deterioration phenomenon such as a reduction in a mobility
or an on-current (current flowing in the case where the TFT is in an on-state)
and an increase in an off-current (current flowing in the case where the TFT is
in an off-state) is observed. This is a large problem in reliability. This phenomenon
is called a hot carrier phenomenon and it is known that this is due to a hot carrier
produced by a high electric filed near a drain.
This hot carrier phenomenon is a phenomenon discovered in a MOS transistor firstly.
Thus, as hot carrier measures, various basic studies have been made until now.
In the case of the MOS transistor with a design rule of 1.5 μm or less, as
measures to the hot carrier phenomenon by a high electric field near the drain,
an LDD (Lightly to Doped Drain) structure is employed. According to the LDD structure,
low concentration impurity regions (n
-; regions) are provided in drain
end portions by using side walls in the sides of a gate and an impurity concentration
of the drain junction is made gradient to relax an electric field concentration
near the drain.
In the case of the LDD structure, a drain withstanding voltage is greatly improved
relatively to a single drain structure. However, since the resistance of the low
concentration impurity regions (n
-; regions) is large, there is such
a defect that a drain current is decreased. Also, high electric field regions are
present immediately under the side walls, impact ionization is maximized in those
regions, and hot electrons are injected into the side walls. Thus, a deterioration
mode inherent to the LDD, such as the low concentration impurity regions (n
-;
regions) are depleted and the resistance is increased becomes a problem. As a channel
length is shortened, the above problems are come to be apparent. Therefore, in
the MOS transistor with 1.5 μm or less, as a structure for overcoming the
problems, a GOLD (Gate-Overlapped LDD) structure in which the low concentration
impurity regions (n
-; regions) are formed by overlapping the end portions
of a gate electrode with each other is designed and employed.
Under such a background, even in the case of the polycrystalline silicon TFT
as a constitution element of the liquid crystal display, as in the case of the
MOS transistor, an application of the LDD structure and the GOLD structure is studied
for the purpose of relaxing a high electric field near the drain. In the case of
the LDD structure, the low concentration impurity regions (n
-; regions)
and high concentration impurity regions (n+ regions) as a source region or a drain
region outside the low concentration impurity regions are formed in a polycrystalline
silicon layer corresponding to the outer regions of the gate electrode. Thus, although
an effect for suppressing the off-current is large, there is such a defect that
an effect for suppressing a hot carrier by relaxing the electric field near the
drain is small. On the other hand, in the case of the GOLD structure, the low concentration
impurity regions (n
-; regions) of the LDD structure is formed to overlap
with the end portions of the gate electrode and a hot carrier suppressing effect
is larger than in the LDD structure. However, there is such a defect that the off-current
becomes large.
Also, as an example for studying the GOLD structure in an n-channel polycrystalline
silicon TFT, for example, there is "Mutuko Hatano, Hajime Akimoto and Takesi Sakai,
IEDM97, TECHNICAL DIGEST. pp.523-526, 1997", in which a basic characteristic of
the GOLD structural TFT is disclosed. In the basic structure of the GOLD structural
TFT, the gate electrode and LDD side walls comprise polycrystalline silicon. Also,
the low concentration impurity regions (n
-; regions) as electric field
relaxation regions and the high concentration impurity regions (n+ regions) as
the source region or the drain region outside the low concentration impurity regions
are formed in an active layer (comprising polycrystalline silicon) located immediately
under the LDD side walls. With respect to the basic characteristic, compared with
a general LDD structural TFT, a drain electric field is relaxed and a large drain
current is obtained. Also, such a characteristic that an effect for suppressing
a drain avalanche hot carrier is large is obtained.
A semiconductor display device such as the liquid crystal display device, which
comprises the polycrystalline silicon TFTs is constructed by a pixel region and
a peripheral circuit as a driver circuit and TFT characteristics required for each
circuit are different. For example, an LDD structure polycrystalline silicon TFT
having a large off-current suppressing effect is suitable for the pixel region.
In addition, a GOLD structure polycrystalline silicon TFT having a large hot carrier
resistance is suitable for the peripheral circuit as the driver circuit. When the
performance of the semiconductor display device is improved, it is suitable that
the pixel region comprises the LDD structure polycrystalline silicon TFTs and the
peripheral circuit as the driver circuit comprises the GOLD structure polycrystalline
silicon TFTs. However, since a manufacturing process is complicated, an increase
in a manufacturing cost and a reduction in a yield become a large problem.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor display device
capable of solving the above problems and a manufacturing method thereof.
According to the present invention, there is provided a semiconductor device
comprising a plurality of thin film transistors formed on a transparent insulating
substrate, each of said thin film transistors comprising: a semiconductor layer,
a gate insulating film, and a gate electrode being laminated in order from a side
near the transparent insulating substrate, and a source region and a drain region
being formed in the semiconductor layer outside the gate electrode, wherein the
gate electrode comprises a first layer gate electrode and a second layer gate electrode
located on the first layer gate electrode and the first layer gate electrode is
formed to have a longer size in a channel direction than the second layer gate
electrode, wherein a first impurity region is formed in the semiconductor layer
corresponding to an exposed region of the first layer gate electrode of the gate
electrode, wherein a second impurity region and a third impurity region are formed
adjacent to each other from a side near the gate electrode in the semiconductor
layer corresponding to the outside of the gate electrode, and wherein an impurity
concentration of the first impurity region is higher than that of the second impurity
region and lower than that of the third impurity region.
In the semiconductor device, the first impurity region, the second impurity region,
and the third impurity region are the same conductivity type impurity regions and
have one of an n-type and a p-type as a conductivity type.
In the semiconductor device, the first layer gate electrode and the second layer
gate electrode comprise different high melting metals.
In the semiconductor device, the first layer gate electrode comprises a TaN film
as a compound containing high melting metal and the second layer gate electrode
comprises a W film as the high melting metal.
In the semiconductor device, the semiconductor layer comprises one of a polycrystalline
silicon film and a crystalline silicon film formed using a catalyst element.
An electronic equipment having the semiconductor device according to the present
invention, wherein the electronic equipment is selected from the group consisting
of a video camera, a digital camera, a rear type projector, a front type projector,
a head mounted display, a goggle type display, a game machine, a car navigation
system, a personal computer, a mobile computer, a mobile telephone, an electronic
book, a personal computer, and a recording medium.
According to the present invention there is provided a semiconductor display
device comprising a plurality of n-channel thin film transistors formed on a transparent
insulating substrate, each of the n-channel thin film transistors comprising: a
semiconductor layer, a gate insulating film, and a gate electrode being laminated
in order from a side near the transparent insulating substrate, and a source region
and a drain region being formed in the semiconductor layer outside the gate electrode,
wherein the gate electrode comprises a first layer gate electrode and a second
layer gate electrode located on the first layer gate electrode and the first layer
gate electrode is formed to have a longer size in a channel direction than the
second layer gate electrode, wherein a first impurity region is formed in the semiconductor
layer corresponding to an exposed region of the first layer gate electrode of the
gate electrode, wherein a second impurity region and a third impurity region are
formed adjacent to each other from a side near the gate electrode in the semiconductor
layer corresponding to the outside of the gate electrode, and wherein an impurity
concentration of the first impurity region is higher than that of the second impurity
region and lower than that of the third impurity region.
In the semiconductor device, the first impurity region, the second impurity region,
and the third impurity region are n-type impurity regions.
In the semiconductor device, wherein an n-type impurity concentration of the
first
impurity region is 2×10
16 to 2.7×10
19 atoms/cm
3,
preferably, about 1×10
17 to 5.3×10
18 atoms/cm
3.
In the semiconductor device, wherein an n-type impurity concentration of the
second
impurity region is 4.7×10
15 to 2.7×10
18 atoms/cm
3,
preferably, about 4.7×10
17 to 5.3×10
17 atoms/cm
3.
In the semiconductor device, wherein an n-type impurity concentration of the
third
impurity region is about 3×10
18 to 5×10
21 atoms/cm
3,
preferably, about 1.7×10
19 to 2.7×10
20 atoms/cm
3.
In the semiconductor device, wherein the first layer gate electrode and the second
layer gate electrode comprise different high melting metals.
In the semiconductor device, wherein the first layer gate electrode comprises
a TaN film as a compound containing high melting metal and the second layer gate
electrode comprises a W film as the high melting metal.
In the semiconductor device, wherein the semiconductor layer comprises one of
a polycrystalline silicon film and a crystalline silicon film formed using a catalyst element.
An electronic equipment having a semiconductor device according to the present
invention, wherein the electronic equipment is selected from the group consisting
of a video camera, a digital camera, a rear type projector, a front type projector,
a head mounted display, a goggle type display, a game machine, a car navigation
system, a personal computer, a mobile computer, a mobile telephone, an electronic
book, a personal computer, and a recording medium.
According to the present invention, there is provided a method of manufacturing
a semiconductor device comprising: laminating a semiconductor layer, a gate insulating
film, a first layer gate electrode film, and a second layer gate electrode film
over a transparent insulating substrate in order from a side near the transparent
insulating substrate; forming a resist pattern for gate electrode formation over
the substrate with the laminated structure; performing dry etching using the resist
pattern as a mask to form a first shaped gate electrode comprising a first layer
gate electrode and a second layer gate electrode; ion-implanting an impurity of
one conductivity type to form a first impurity region in the semiconductor layer
corresponding to an outside of the first shaped gate electrode; performing additional
etching using the resist pattern present on the first shaped gate electrode as
a mask to form a second shaped gate electrode in which the first layer gate electrode
has a longer size in a channel direction than the second layer gate electrode;
performing rear surface exposure using the first layer gate electrode of the second
shaped gate electrode as a mask to form a negative resist pattern in a self alignment;
ion-implanting an impurity of a conductivity type identical to the one conductivity
type to form a second impurity region in the semiconductor layer corresponding
to an exposed region of the first layer gate electrode of the second shaped gate
electrode; removing the negative resist pattern; and ion-implanting an impurity
of a conductivity type identical to the one conductivity type to form a third impurity
region in the semiconductor layer corresponding to an outside of the second shaped
gate electrode.
According to the present invention, a dose of the second impurity region
is set to be lower than that of the first impurity region and higher than that
of the third impurity region.
According to the present invention, the impurity is ion-implanted by an
ion dope apparatus.
According to the present invention, respective impurity concentrations
of the second impurity region and the third impurity region are independently controlled.
According to the present invention, different kinds of high melting metals
or different compounds containing the high melting metals are applied to the first
layer gate electrode film and the second layer gate electrode film.
According to the present invention, a TaN film as a compound containing
high melting metal is applied to the first layer gate electrode film and a W film
as the high melting metal is applied to the second layer gate electrode film.
According to the present invention, the semiconductor layer is formed with
one of a polycrystalline silicon film and a crystalline silicon film formed using
a catalyst element.
According to the present invention, the semiconductor device is included
in an electronic equipment is selected from the group consisting of a video camera,
a digital camera, a rear type projector, a front type projector, a head mounted
display, a goggle type display, a game machine, a car navigation system, a personal
computer, a mobile computer, a mobile telephone, an electronic book, a personal
computer, and a recording medium.
According to the present invention, there is provided a method of manufacturing
a semiconductor device comprising: forming a semiconductor layer, a gate insulating
film, a first layer gate electrode film, and a second layer gate electrode film
on a transparent insulating substrate in order from a side near the transparent
insulating substrate; forming a resist pattern for gate electrode formation on
the substrate with a resultant structure; performing dry etching using the resist
pattern as a mask to form a first shaped gate electrode comprising a first layer
gate electrode and a second layer gate electrode; ion-implanting an impurity of
one conductivity type to form a first impurity region in the semiconductor layer
corresponding to an outside of the first shaped gate electrode; performing additional
etching using the resist pattern present on the first shaped gate electrode as
a mask to form a second shaped gate electrode in which the first layer gate electrode
has a longer size in a channel direction than the second layer gate electrode;
ion-implanting an impurity of a conductivity type identical to the one conductivity
type to form a second impurity region in the semiconductor layer corresponding
to an outside of the second shaped gate electrode; performing rear surface exposure
using the first layer gate electrode of the second shaped gate electrode as a mask
to form a negative resist pattern in a self alignment; and ion-implanting an impurity
of a conductivity type identical to the one conductivity type to form a third impurity
region in the semiconductor layer corresponding to an exposed region of the first
layer gate electrode of the second shaped gate electrode.
According to the present invention, a dose of the third impurity region
is set to be lower than that of the first impurity region and higher than that
of the second impurity region.
According to the present invention, the impurity is ion-implanted by an
ion dope apparatus.
According to the present invention, respective impurity concentrations
of the second impurity region and the third impurity region are independently controlled.
According to the present invention, different kinds of high melting metals
or different compounds containing the high melting metals are app
