Semiconductor integrated circuit device Number:6,762,951 from the United States Patent and Trademark Office (PTO) owispatent A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.<H Semiconductor, integrated, Semiconductor, i, 6762951.html, Patent, pto, 6762951

Title: Semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

Patent Number: 6,762,951 Issued on 07/13/2004 to Itoh, et al.

Inventors: Itoh; Kiyoo (Higashikurume, JP), Nakazato; Kazuo (Cambridge, GB)
Assignee: Hitachi, Ltd. (Tokyo, JP)

Appl. No.: 10/330,077

Filed: December 30, 2002

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
959906		6515892

Current U.S. Class: 365/149 ; 365/189.01; 365/207; 365/230.06

Current International Class: G11C 11/404 (20060101); G11C 11/405 (20060101); G11C 11/403 (20060101); G11C 11/4076 (20060101); G11C 11/407 (20060101); G11C 16/04 (20060101)

Field of Search: 365/149,189.01,189.09,189.11,187,203,207,230.06

References Cited [Referenced By]

U.S. Patent Documents


4771323	September 1988	Sasaki
4920391	April 1990	Uchida
5675160	October 1997	Oikawa
6314017	November 2001	Emori et al.
6388934	May 2002	Tobita
6452858	September 2002	Hanzawa et al.
6515892	February 2003	Itoh et al.
6519195	February 2003	Kanno et al.

Foreign Patent Documents


58-220464	Dec., 1983	JP
1-255269	Oct., 1989	JP
2-54572	Feb., 1990	JP
8-250673	Sep., 1996	JP
63-19847	Nov., 2001	JP

Other References

Ultra LSI Memories, Baifukan, Nov. 5, 1994, Kiyoo Itoh, pp. 12-15. .
ISSCC '72, VLSI Memory Chip Design, Kiyoo Itoh, pp. 12-13..

Primary Examiner: Auduong; Gene
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP

Parent Case Text

This is a continuation of application Ser. No. 09/959,906, filed Nov. 13. 2001, now U.S. Pat. No. 6,515,892, which is the U.S. national stage of PCT/JP99/02519, filed May 14, 1999, the entire disclosure of which is hereby incorporated by reference.

Claims

What is claimed is:

1. A semiconductor Integrated circuit device comprising: a memory array, wherein the memory array further includes: a plurality of memory cells, each having a storage MOSFET holding an information voltage in a gate of the storage MOSFET and set to an ON or OFF state according to the information voltage, and a write transistor supplying a write information voltage corresponding to the information voltage to the gate of the storage MOSFET; a plurality of write data lines, each being applied with the write information voltages given as the information voltage of corresponding ones of the memory cells; a plurality of read data lines, each being applied with the information corresponding to the ON or OFF state of the storage MOSFET of the memory cell; a word line structure connected to the control terminals of the write transistors of the memory cells; a data line select circuit selecting one of the plurality of read data lines; and first and second common data lines being connected to one of the read data lines selected by the data line select circuit, wherein, during a non-select state, the word line structure is set to a first voltage to keep the write transistors to an OFF state, wherein, in a first select period, the write transistors are set to an OFF state, the word line structure is set to a second voltage which makes the selected read data line discharge when the information voltage is high level or which does not make the selected read data line discharge when the information voltage is low level, wherein, in a second select period, in which either the Information voltage to be written into the write data lines or a read information voltage corresponding to the read information are applied, the word line structure is set to a third voltage which makes the write transistors to an ON state, wherein the first and second common data lines are precharged to a precharge voltage that is an intermediate voltage between a high level voltage and a low level voltage at a time of amplifying voltages on the first and the second common data lines in the non-select state, and wherein the read information which appears on one of the first and second common data lines corresponding to a charge share with the read data line selected by the data line select circuit is amplified using the precharge voltage of the other of the first and second common data lines as a reference voltage.

2. A semiconductor integrated circuit device according to claim 1, wherein the same number of read data lines are respectively coupled with each of the first and second common data lines via the data line select circuit, and wherein the semiconductor integrated circuit device includes a differential amplifier circuit that amplifies the read information produced on one of the first and second common data lines by the charge share, using the precharge voltage of the other of the first and second common data lines as the reference voltage.

3. A semiconductor integrated circuit device, according to claim 2, wherein the differential amplifier circuit Includes a CMOS latch circuit having a pair of CMOS inverter circuits, the pair of CMOS inverter circuits having cross-coupled inputs and outputs, and an operating voltage of the CMOS latch circuit is supplied during amplification.

4. A semiconductor integrated circuit device according to claim 3, further comprising: a write control circuit connected between the read data lines and the write data lines, wherein the write control circuit applies the read information on the read data lines to the write data lines.

5. A semiconductor integrated circuit device according to claim 4, wherein the write control circuit is comprised of a transfer gate MOSFET connecting the read lines with the write data lines.

6. A semiconductor integrated circuit device according to claim 4, wherein the write control circuit is an inverting amplifier circuit to invert and amplify the read information voltage from the read data lines and to apply the inverted amplified information voltage to the write data lines.

7. A semiconductor Integrated circuit device according to claim 1, wherein the write transistor Included in the memory cells Is a MOSFET produced In a three-dimensional shape so as to have an electrical current path in a vertical direction relative to the main surface of the semiconductor substrate on which the semiconductor integrated circuit device is produced.

8. A semiconductor Integrated circuit device according to claim 7, wherein each of the plurality of memory cells further includes a capacitor between the word line structure and the gate of the MOSFET.

9. A semiconductor Integrated circuit device according to claim 1, wherein the write transistor included in the memory cells comprises a MOSFET, and wherein each of the plurality of memory cells further includes a capacitor between the word line structure and the gate of the storage MOSFET that holds the information voltage In the gate.

10. A semiconductor integrated circuit device according to claim 1, wherein the word line structure comprises a write word line structure and a read word line structure, and the read word line structure Is set to select state in the first select period, and the write word line structure is set to select state in the second select period, wherein the write transistor of the memory cells comprises a MOSFET, and a gate of the MOSFET is connected to the write word line structure, wherein a gate of the storage MOSFET holds the information voltage, and the storage MOSFET is connected to a select MOSFET serially, and wherein a gate of the select MOSFET is connected to the read word line structure.

11. A semiconductor integrated circuit device comprising: a memory array, wherein the memory array further includes: a plurality of memory cell, each having a storage MOSFET holding an information voltage in a gate of the storage MOSFET and set to an ON or OFF state according to the information voltage, a write transistor supplying a write information voltage corresponding to the information voltage to the gate of the storage MOSFET, and a select MOSFET coupled to the storage MOSFET to supply read signals corresponding to the ON or OFF state of the storage MOSFET; a plurality of write data lines, each being applied with the write information voltage given as the information voltage of corresponding ones of the memory cells; a plurality of read data lines, each being applied with read information; a write word line connected to control terminals of the write transistors of the memory cells; a read word line connected to control terminals of the select MOSFETs of the memory cells; a data line select circuit selecting one of the plurality of read data lines; and first and second common data lines being connected to one of the read data lines selected by the data line select circuit, wherein, during a non-select state, the write and read word lines are set to a first voltage to set the write and reed transistors to an OFF state, wherein, in a first select period, the write transistors are set to an OFF state, the read word line structure is set to a second voltage which makes the select MOSFET to an ON state to discharge the selected read data line when the information voltage is high level or to an. OFF state when the Information voltage is low level so that the selected read data line is not discharged, wherein, in a second select period, in which either the Information voltage to be written into the write data lines or a read information voltage corresponding to the read signal information is applied, the write word line is set to a third voltage which makes the write transistor, to an ON state, wherein the first and second common data lines are precharged to a precharge voltage that is an intermediate voltage between a high level voltage and a low level voltage at a time of amplifying voltages on the first and second common date lines in the non-select state, and wherein the read information which appears on one of the first and second common data lines corresponding to a charge share with the read data line selected by the data line select circuit is amplified using the precharge voltage of the other of the first and second common data lines as a reference voltage.

12. A semiconductor integrated circuit device according to claim 11, wherein the same number of read data lines are respectively coupled with each of the first and second common data lines via the data line select circuit, and wherein the semiconductor integrated circuit device includes a differential amplifier circuit that amplifies the read information produced on one of the first and second common data lines by the charge share, using the precharge voltage of the other of the first and second common data lines as the reference voltage.

13. A semiconductor integrated circuit device according to claim 12, wherein the differential amplifier circuit includes a CMOS latch circuit having a pair of CMOS inverter circuits, the pair of CMOS inverter circuits having cross-couple inputs and outputs, and an operating voltage of the CMOS latch circuit is supplied during amplification.

14. A semiconductor integrated circuit device according to claim 11, further comprising: a write control circuit connected between the read data lines and the write data lines; wherein the write control circuit applies the read information on the read data lines to the write data lines.

15. A semiconductor integrated circuit device according to claim 14, wherein the write control circuit device is comprised of a transistor gate MOSFET connecting the read data lines with the write data lines.

16. A semiconductor integrated circuit device according to claim 14: wherein the write control circuit is an inverting amplifier circuit to invert and amplify the information voltage from the read data lines and to apply the inverted amplified information voltage to the write data lines.

Description

FIELD OF THE INVENTION

This invention relates to a semiconductor integrated circuit device and relates in particular to a high reliability, large capacity semiconductor memory circuit.

BACKGROUND OF THE INVENTION

Semiconductor memories are broadly classified into RAM (random access memories) and ROM (read only memory) devices. Among these devices, the dynamic RAM (DRAM) is used in the largest numbers as the main memory for computers. The memory cells that store the information are composed of one capacitor and a transistor to read out the charge stored on that capacitor. This memory cell can form the smallest structural element on the RAM and is therefore ideal for use on a large scale. Accordingly, this large scale use results in making these memory cell devices ideal for mass production at a low price.

However, the DRAM has a problem in that operation tends to be unstable. The largest cause of this instability is that the memory cell itself has no amplifying effect and therefore the read out signal voltage from the memory cell is small and the memory cell operation is susceptible to all kinds of random noise. Another drawback is that the information charge stored in the capacitor is lost due to the leakage current in the pn junction within the memory cell. Before this charge is lost, a refresh (rewrite) operation is performed periodically on the memory cell to retain the memory information stored in the memory cell. The period is referred to as the refresh period and currently requires approximately 100 milliseconds, however this refresh period becomes longer as the memory capacity increases. In other words, the leakage current must be limited but restricting the leakage current becomes more and more difficult as the elements become smaller.

A memory to solve these problems was the ROM and the flash memory in particular. As is well known, the flash memory is at least as small as a DRAM cell and the memory cell has internal gain so that the signal voltage is essentially large, and operation is therefore stable. A storage charge is also accumulated in the storage node enclosed by an insulator film so that like the DRAM, there is no current leakage from the pn junction and a refresh operation is not required. However, a weak tunnel current flows to accumulate the charge in the storage mode so that the write time is extremely long. Also, repeating the write operation causes electrical current to flow in the insulator film and the insulator film gradually deteriorate and finally the insulator film becomes a conductive film that is unable to retain information.

The ROM device is therefore generally limited to about 100,000 write operations. In other words, the flash memory cannot be utilized as a RAM. The DRAM and flash memory therefore both have a large capacity memory and respective advantages and disadvantages. The particular advantages of each device have to be considered when using the device.

A method of the known art for a three transistor cell comprised of a storage MOSFET to store an information voltage in a gate, and a write MOSFET to write an information voltage in a gate was disclosed for instance in "Ultra LSI Memories" Baifukan, Nov. 5, 1994 Kiyoo Itoh, PP. 12-15. The three-transistor cell of this type had an amplification function in the cell itself so that the signal voltage appearing in the data line was large, and read out was totally non-destructive however this device also had problems since the peripheral circuits for read and write operations were complicated and difficult to use so that the three transistor cell was not practical to use.

In view of the above problems with the prior art, it is an object of the present invention to provide a semiconductor integrated circuit device having a memory circuit with simple circuit structure that is also easy to use.

Yet another object of the present invention is to provide a semiconductor integrated circuit device having a memory circuit that is both high speed and nonvolatile. The above mentioned and other new features and objects of this invention will be apparent to one skilled in the art from the description of this invention and the accompanying reference drawings.

SUMMARY OF THE INVENTION

A simple description of the concept of the invention as disclosed in this application is as follows. A semiconductor device has a memory cell array comprised of memory cells containing a write transistor and a storage MOSFET for holding an information voltage in the gate, a word line intersecting with a write data line for conveying write information voltages and an intersecting read line for conveying read information signals corresponding to the on or off state of the storage MOSFET memory cell, the control terminals of the write transistors of the memory cell are connected by the word lines and the read signal is output on the corresponding read data line in response to the select signal from the write transistor control terminals, and one read data line is selected from among a plurality of read data lines by the data line select circuit and is connected to either a first or second common data line, the selected read data line is precharged to a first voltage potential in the non-select period, in a first select period that word line is selected for read out and discharged to a second voltage potential by the on status of the storage MOSFET of the memory cell, the first and second common data lines are precharged to a third voltage potential between the first and second voltage potentials in the non-select period, the read signal appearing in the first select period on the read data line selected by the data line select circuit and in one common data line corresponding to the dispersed charge are amplified using the precharge voltage of another common data line as the reference voltage, after the write signal is conveyed on the write data line, when necessary, in the second select period the word lines are set to a high voltage and the write transistor is set to on status to perform write or rewrite in the memory cell.

A simple description of another representative concept of the invention as disclosed in this application is as follows. Namely, a semiconductor device has a memory cell array comprised of memory cells containing a write transistor and a storage MOSFET for holding an information voltage in the gate, a word line intersecting with a write data line conveying write information signals and an intersecting read data line conveying read information signals corresponding to the on or off state of the storage MOSFET of the memory cell, the control terminals of the write transistors of the memory cell are connected by the word lines, and the read signal is output on the corresponding read data line in response to the select signal from the control terminals, a sense amplifier comprised of a CMOS latch structure is formed between the write data line and the read data line, that read data line is precharged to a first voltage potential in a first period, that write data line is precharged to a second voltage smaller than the first voltage in the first period, the word line is selected in a second period and the read data line is discharged to a third voltage potential by the on status of the storage MOSFET of the memory cell, the sense amplifier is set to operating status after the read data line has been set to the first voltage or the third voltage corresponding to the memory cell information voltage and the high level or low level state is amplified according to the operating voltage of the sense amplifier, and a data line select circuit selects one pair of data lines from among a plurality of pairs comprised of read data lines and their corresponding write data lines and connect that data line pairs to a first and second common data line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an essential portion of a circuit schematic showing an embodiment of the memory circuit comprising the semiconductor integrated circuit of this invention.

FIG. 2 is an essential portion of a circuit schematic showing another embodiment of the memory circuit comprising the semiconductor integrated circuit of this invention.

FIG. 3 is a concept view of the cross sectional structure for an embodiment of the BMOS transistor utilized in the circuit of FIG. 2.

FIG. 4 is a graph of the voltage/current characteristics of the BMOS transistor shown in FIG. 3.

FIG. 5 is a concept plan view of an embodiment of the memory cell for the circuit of FIG. 2.

FIG. 6 is a cross sectional view of the memory cell of FIG. 5 taken along lines A-A'.

FIG. 7 is a cross sectional view of the memory cell of FIG. 5 taken along lines B-B'.

FIG. 8 is a waveform chart for describing one example of the memory circuit operation of FIG. 1 and FIG. 2.

FIG. 9 is an essential portion of a circuit schematic showing another embodiment of the memory cell comprising the semiconductor integrated circuit of this invention.

FIG. 10 is an essential portion of a circuit schematic showing an embodiment of the memory cell comprising the semiconductor integrated circuit of this invention.

FIG. 11 is a waveform chart for describing one example of the memory circuit operation of FIG. 10.

FIG. 12 is an essential portion of a circuit schematic showing an embodiment of the memory cell comprising the semiconductor integrated circuit of this invention.

FIG. 13 is a waveform chart for describing one example of the memory circuit operation shown in FIG. 12.

FIG. 14 is an essential portion of a circuit schematic showing an embodiment of the memory cell comprising the semiconductor integrated circuit of this invention.

FIG. 15 is an essential portion of a circuit schematic showing yet another embodiment of the memory cell comprising the semiconductor integrated circuit of this invention.

FIG. 16 is a waveform chart for describing one example of the memory circuit operation shown in FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, a detailed description of this invention will be given while referring to the related drawings.

FIG. 1 is a circuit schematic showing an example of the memory circuit comprising the semiconductor integrated circuit of this invention. Each of the element and circuit blocks are formed by semiconductor integrated circuit manufacturing technology of the known art on a semiconductor (LSI) substrate made of single crystalline silicon.

In this embodiment, the data lines are separated into a read data lines RD and write data lines WD with no particular restrictions, however these lines extend in parallel in a perpendicular direction. In FIG. 1, the read data lines RD and write data lines WD are provided in pairs from 1 to n number of pairs and of these data line pairs, two pairs consisting of data line pair RD1, WD1-RDm and WDm are used as examples.

In one memory array MA1, one or n pairs of word lines WL11-WL1n extend in the horizontal direction so as to cross the plurality of data line pairs RD1, WD1-RDm and WDm. Of these plurality of word lines 1 through n, two pairs of word lines WL11 and WL1n are used as examples. These word lines are not subject to any particular restrictions but a plurality of memory arrays MA1-MAk from 1 through k are formed in the direction of the data lines and in each memory array MA, a plurality of word lines 1 through n, are formed the same as each memory array MA1.

The structure of the memory array is next explained using the memory array MA1 as an example. A memory cell MC11 formed at the cross point of the word line WL11 and the data lines RD1, WD1, is comprised of a storage MOSFET QR to retain an information voltage at its gate and set to on or off status when the word line WL11 is selected according to this information voltage, a write MOSFET QW at the gate of the MOSFET QR for conveying the write signal of the write data line WD, and a capacitor C formed between the gate of the MOSFET, QR and the word line WL11 to set the MOSFET QR to off status regardless of the memory voltage when the word line is not selected.

The gate of the write MOSFET QW is connected to the word line WL11. The source/drain path of the storage MOSFET QR is connected to the read data line RD1 and the ground voltage VSS (0 volts) of the circuit.

A precharge MOSFET QPR and QPW with switching being controlled by the precharge signal PR, are formed on the read data line RD1 and the write data line WD1, and the data lines RD1 and WD1 are precharged to voltage VDD in the precharge period.

A write control circuit WC1 is formed between the read data line RD1 and the write data line WD1 to convey the read data line RD1 signal to the write data line WD1. There are no particular restrictions in this embodiment and the write control circuit WC1 is comprised of a MOSFET QT1 whose switching is controlled by a control line WCL1 extending in parallel with the word line WL.

The data lines RD2, WD2 formed the same as the adjoining pair of data lines RD1 and WD1, also have an identical memory cell, precharge circuit and write control circuit.

The read data lines RD1 through RDm are connected to either of a pair of complementary common data lines /IO(1) and IO(1) by way of switch MOSFET QY11 through QY1m comprising the data line select circuits. There are no particular restrictions but the read data lines RD1 through RDm formed in the memory array MA1 are configured of even-numbered lines, and for instance the odd-numbered read data lines RD1, RD3, . . . are connected to the common data lines IO (1) and the even-numbered read data lines RD2, RD4, . . . RRDm are connected to the common data lines /IO(1).

The number of read data lines connected to the pair of the complementary common data lines IO(1) and /I/O(1) are therefore equal and the number of switch MOSFETS comprising the data line select circuit corresponding to the common data lines IO(1) and /IO(1) are also equal. The common data lines IO(1) and /IO(1) have an equivalent length and are also connected to the same number of switch MOSFETs and so have largely the same parasitic capacitance.

Here, the complementary common data lines are comprised of an inverted common data line /IO in which a low level corresponds to a logic 1, and a non-inverted complementary common data line IO (1) in which a high level corresponds to a logic level 1, the slash/indicates the overbar of the logic symbol.

A MOSFET Q1 and MOSFET Q2 are formed in the complementary common data lines IO(1) and /IO(1) to precharge to a half-precharge voltage VDD/2 corresponding to one-half of the discharge voltage (0 volts) and precharge voltage (VDD) of the read data line. The gates of the MOSFET Q1 and Q2 are supplied by the precharge signal PR. Identical common data lines and precharge circuits are also formed in the other memory arrays MA2 through MAk.

The plurality of word lines WL1 through WL1N, and WLKk1 through WLKn formed in the memory arrays MA1-MAk are selected one line apiece by the X decoder & drivers X-DEC/DRV for the memory arrays MA1-MAk.

The select signals YS1 through YSm formed by means of the Y decoder & driver Y-DEC/DRV simultaneously select the read data lines RD1-RDk that correspond to the memory arrays MA1-MAk, and connect the read data lines RD1-RDk to any or any one of the corresponding common data lines I/O(1), /IO(1) through I/O(k), /IO(k). Consequently, memory access is performed in k bit units consisting of 1 through k in this embodiment of the memory circuit. A simplified circuit can therefore be achieved by utilizing the Y decoder & driver Y-DEC/DRV such as mentioned above, in common with the data line selection operation for the memory arrays MA1 through MAk.

There are no particular restrictions on the common data lines IO (1) and /IO(1) and a CMOS latch circuit formed as the sense amplifier SA1 consists of an N-channel MOSFET QN1 and QN2 as well as P-channel MOSFET QP1 and QP2 that form CMOS inverter circuits with intersecting input and output connections. The sense amplifier SA1 consisting of these CMOS latch circuits is configured so that the respective common sources SN and SP for the N-channel MOSFET QN1, QN2 and the P-channel MOSFET QP1 and QP2 are enabled by application of operating voltages such as supply voltage VDD and ground voltages of the circuit.

An identical sense amplifiers SAk are also formed for the other common data lines IO (k) and /IO(k) shown as examples. The sources SN and SP for the amplifying MOSFETs of these sense amplifiers SA1-SAk are supplied in common with the above mentioned operating voltages. The k number of sense amplifiers SA1-SAk from 1 though k start amplifying operation all together, and amplify the read signals read out from the common data lines IO and /IO corresponding to each of the sense amplifiers.

These amplified signals are output from external terminals of the semiconductor integrated circuit device by way of output circuits not shown in the drawing. Write signals may also be supplied from the external terminals and supplied by way of the input circuits with no particular restrictions. The write signals are amplified by the above mentioned sense amplifiers SA1-SAk, conveyed to the respective write data lines by way of selected read data line and the write control circuits WC and written into the memory cell.

FIG. 2 is a circuit schematic showing another embodiment of the memory circuit comprising the semiconductor integrated circuit of this invention. The memory charge in this embodiment is intended to be nonvolatile with respect to the memory charge. The transistor for writing nonvolatile memory charges utilizes a MOSFET with a barrier insulator structure (hereafter simply BMOS) instead of the MOSFET used in the previous embodiment.

In this embodiment, the N-channel MOSFET (NMOS) for the write transistor QW is instead substituted with a MOSFET (BMOS) however in all other respects the structure of the embodiment is the same as the first embodiment, accordingly a description of those portions is omitted here.

FIG. 3 is a concept view of the cross sectional structure of the BMOS transistor of the embodiment. An important feature is that gate electrodes G are formed in a vertical structure by means of gate oxide layers (heat oxidized film thickness of tox) on both sides of the four layers of laminated polysilicon (poly 1 to poly 4). The gate electrodes formed on both sides of the polysilicon layers are in fact integrated into one piece with a constant, equivalent electrical potential as subsequently related. The polysilicon 1 and polysilicon 4 are doped with 10.sup.20 cm.sup.-3 of phosphorus, and form the drain D (or the source S) and source (or drain) of the transistor. The polysilicon 2 and polysilicon 3 are doped with an extremely weak concentration of phosphorus (approximately 10.sup.-15 to 10.sup.-17) forming a transistor substrate of intrinsic polysilicon.

A tunnel layers SN1, SN2, SN3 consisting of for instance thin (2 to 3 nm) silicon nitride layers are formed between the polysilicon 1 and polysilicon 2, the polysilicon 2 and polysilicon 3, as well as the polysilicon 3 and polysilicon 4. The tunnel layers SN1 and SN3 function as stoppers so that the high concentration phosphorus from the drain or source regions does not diffuse into the internal weak concentration layers (polysilicon 2 and polysilicon 3) when forming the transistor.

A tunnel layer that does not have a thick film is required in order to make current flow between the source and drain. The intermediate tunnel layer SN2 restricts the off current of the transistor to a small amount. In other words, the intermediate tunnel layer SN2 functions as a stopper to prevent the positive holes or electrons emitted in the polysilicon 2 and polysilicon 3 regions in the transistor from flowing as electrical current between the source and drain.

When a sufficiently high positive voltage is applied to the gate, the potential barrier of this tunnel film lowers so that a sufficiently large on current can flow between the source and drain. Of course, this intermediate layer can be reduced according to the target value of off current that is needed. The intermediate layer was assumed to be one layer here, however the tunnel layer can be composed of multiple layer if required. Typical dimensions for the BMOS of FIG. 3 are, 1=0.4 .mu.m, d=0.2 .mu.m, and tox=10 nm. When an appropriate thickness is chosen for the tunnel layer in this type of transistor, device voltage and current characteristics approaching those of a horizontal, conventional type MOS transistor with an extremely low substrate concentration can be obtained. A graph of those characteristics is shown in FIG. 4.

The maximum allowable value (I) for electrical current (IDS) flowing between the source and drain is found as follows, in order to assure nonvolatility for a 10 year period. When the allowable memory node (N) capacity (C) is 5 fF, and the allowable memory node voltage drop (delta V) for the 10 year period (delta t) is set to 0.1 volt, then I=C delta V/delta t=1.6.times.10.sup.-24 A is obtained. In normal circuit design, the transistor threshold voltage VWT is defined as a gate/source voltage (VGS) for allowing an electrical current of approximately IDS=10.sup.-8 A to flow. Since the relation of IDS and VGS is linear in the current region shown by the semi-logarithm in FIG. 4 from 10.sup.-24 A to 10.sup.-8 A, increasing the IDS by one decimal place, to set a VGS value of 100 millivolts, results in a VTW of 0.1 (volts/digit).times.16 (digit)=1.6 volts. This threshold voltage value VTW is the minimum value for maintaining the transistor (QW) in the off state for approximately 10 years. In the actual device design, the threshold value VTW is set to 2 volts, to take variations in the threshold value VTW and its temperature characteristics into account.

Since the maximum value of allowable current for retaining one piece of data of a memory cell for one day is approximately 10.sup.-20 A, then a VTW of 0.1 (volts/digit).times.12 (digit)=1.2 volts is sufficient. The standard threshold value VTW may be set to 1.6 volts in order to take manufacturing variations into account. Therefore, compared to nonvolatile operation, the required maximum word voltage (VDD+VTW or more) decreases by the amount the VTW lowers so that there is less need for a high transistor breakdown voltage for transistors inside the peripheral circuits driving the write transistors (QW) and word lines inside the memory cell.

In such cases the memory cell data is retained if a peripheral refresh (rewrite) operation for the DRAM is performed. In other words, an operation to drive the word lines and periodically perform the aforementioned read out-rewrite in sequence on each word line will prove sufficient.

FIG. 5 is a concept plan view of the memory cell for the circuit of FIG. 2. The BMOS shown in FIG. 3 is utilized as the write transistor QW. The line A-A' of a cross section of FIG. 6 and the line B-B' of a cross section of FIG. 7 are respectively shown in FIG. 5. In these FIGS. 5 through 7, word line (WL11) formed of a boron-doped P-channel polysilicon layer is placed to intersect with the data line (RD1) formed of a phosphorus-doped N-channel polysilicon layer by way of a thick insulator film. The BMOS with a cubical barrier insulator film structure shown in FIG. 3 is laminated on top of the gate electrode (N11) of a conventional MOSFET (QR of FIG. 1) so that an extremely high density memory cell can be obtained.

In contrast to the flat current flow in the storage MOSFET QR, the flow in the write transistor QW is clearly in a perpendicular direction relative to the QR flow. Therefore, in contrast to the fold-over data wiring layout of the DRAM memory cell of the known art having a theoretical surface area of 8F2 (F: smallest dimension), the device of this invention has a surface area of 4F2 so that a cell with half the surface area can be obtained. The coupling capacity (C) of FIG. 2, can be formed by a heat oxidized film between the word line WL and the polysilicon 4 as shown in FIG. 6. The size of C can be changed by adjusting the thickness of the layer of the polysilicon 4.

Compared to the DRAM cell of the known art comprised of one MOSFET and one capacitor, the memory cell of this embodiment can be manufactured with a smaller number of masks since the surface area of the memory cell is reduced by half and there are few irregularities on the surface. Therefore the memory chip of this invention is inexpensive and easier to be manufactured.

The data retaining (hold) time will also be sufficiently long if the memory cell of this embodiment is set to the write transistor QW threshold voltage (VTW) as previously described. Also, irradiation with alpha rays will make the device strongly resistant to even to soft-type errors. In other words, there is no pn junction in the memory cell node (N11) so that no junction leak current occurs as happens when using MOSFETs as write transistors such as for the memory cell of FIG. 1. Also, even if electrons or positive holes are emitted internally in the cell irradiated with alpha rays, the tunnel layer will function as a stopper for current flow from the positive holes or electrons so that no change in potential occurs inside the cell. The memory cell can therefore be operated as a nonvolatile memory.

FIG. 8 is a waveform chart for describing an example of the memory circuit operation of FIG. 1 and FIG. 2.

The precharge signal PR is set to a high level such as VDD+VT (Here, VT is the threshold voltage of the precharge MOSFET). Also, the read data lines RD1-RDm and the write data lines WD1-WDm are precharged to a high level such as the power supply voltage VDD. The common data line IO, and the common sources SP and SN for the sense amplifiers SA1-SAk are precharged in the same way to the half-precharge voltage VDD/2.

When the precharge signal PR changes to a low level, the precharge MOSFET sets to off, and each section such as the data lines are held at the precharge voltage.

Hereafter, an example of writing data from the common data line pair IO in the memory cell MC11 is described. To write a high level voltage VDD or a low level voltage of 0 volts corresponding to binary information of 1 or 0 in the memory node (gate) N11 of the memory cell MC11, after application of a voltage VW equal or greater than VDD+VTW (VTW is the threshold voltage of the write transistor QW) to the word line WL11, a VDD or 0 volts can be supplied to the write data line WD1, by way of switch MOSFET QY11 from the common data line IO, and read data line RD1 and write control circuit WC1.

Here, it is important to note that when a selected voltage VDD+VTW is applied such as to the word line WL11, the memory information of the non-selected memory cells connected to the same word line WL11 is destroyed. In other words, the write transistor QW for the non-selected memory cells MC12-MC1m connected to the word line WL11, is set to on status, and a precharge voltage VDD of the write data line WDm is applied to the respective memory cell nodes N1m, etc.

In order to prevent this kind of destruction of information, the memory cell on select word line WL11 is first read out, and except for the selected memory cell MC11, the respective information that was read out is rewritten into the other non-select memory cells MC12-MC1m. Restated, data is input from the common data line IO instead of the read out data, in the rewrite operation, for the selected memory cell MC11 and the data used as the substitute can be used for writing.

Accordingly, in the memory circuit of this embodiment, the read operation must be performed prior to the write operation. In the embodiments in FIG. 1 and FIG. 2, the surface area of the memory cell is small so that the word line is jointly used for reading and writing and therefore the word line select level has two select levels consisting of read select level VR and a write select level VW.

In non-select status, the voltages for the respective memory nodes N11, N1m of the memory cells including the binary memory information 1 and 0 being read out are both lower than the MOSFET QR threshold voltage VTR. In FIG. 8, the higher voltage corresponds to 1 of the binary information and that voltage is VN (H), so that VN (H) is assumed to be less than VTR. Such voltage condition is realized by the capacitor C in the memory cells. In other words, when the word line WL11 has set to a non-select level such as zero (0) V, a lower voltage potential for the memory node VN(H) is obtained by means of the coupling per the capacitor C.

The storage MOSFET QR for the plurality of memory cells MC11-MCn1 connected to the one read data line RD1 is set to off status regardless of the memory voltage VN(H) and VN (L) corresponding to the binary information.

In the word line first select period, below the write transistor QW threshold voltage, there is given a low voltage VR in which the storage MOSFET QR holding the information voltage VN (H) in the gate is at on status and the storage MOSFET QR holding the information voltage VN (L) in the gate is at off status, and the word line WL11 is driven by the low voltage VR. In other words, when the word line WL11 is set to a read voltage such as voltage VR, the voltage potential of memory node N11 holding the information voltage VN (H) rises according to the select voltage VR by way of the capacitor C, becoming higher than the threshold voltage VTR and the storage MOSFET QR is set to on status, and the precharged read data line DR1 is made to discharge.

The voltage potential of memory node N11 holding the information voltage VN (L) does not reach the threshold voltage VTR even with a rise in voltage potential such as on the word line WL11 so that the storage MOSFET QR stays off and the read data line DR is maintained at the precharge voltage.

After performing memory information read out of the memory cell to the read data line such as DR, the Y select line YS1 is set to high level (VDD+VT), and the select MOSFET QY11 is set to on status. A connection is thus made to any or either of the read data line DR and the common data line IO or /IO and a minute read signal VS appears by the coupling with the respective accumulated parasitic capacitance charges.

If a read data line such as DR1 is discharged to a low level, then a small voltage drop occurs on the common data line IO due to coupling with the common data line IO discharged to VDD/2, and the read data line DR1 rises by a minute voltage due to the charge supplied from the common data line IO. Conversely, if the read data line DR1 remains precharged, then the common data line IO voltage rises by a minute amount according to the coupling with the common data line IO that was precharged to VDD/2, and the voltage on the read data line DR1 drops by a minute amount, according to the charge supplied to the common data IO line.

In this way, with a binary memory information value of 1 or 0 on the common data line IO (or /IO) of a memory cell, the precharge voltage on the other common data line is then set as the reference, and a minute read out signal such as -VS or +VS appears. This read signal .+-.VS is set to approximately 200 to 500 millivolts when the power supply voltage VDD is about 1 to 3 volts.

This kind of differential voltage VS on the common data lines IO and /IO is amplified by the sense amplifier SA1 set to operating status in response to a change in the sense amplifier enabling signal SN low level (0 volts) or SP high level (VDD), and then set to a VDD high level corresponding to the memory information and a low level in response to a ground potential of 0 volts in the circuit.

The control line WCL1 for performing line select, is set to a high level after verification of the voltage potential on the read data line DR1, the MOSFET QT1 comprising the write control circuit WC1 is set to on status and connected to the read data line DR1 and the write data line DW1. In other words, if the voltage potential on the read data line DR1 is a low level then a redistribution of the electrical charge occurs with the write data line DW1 and the voltage potential of the read data line DR1 drops to the potential of q in the drawing. However if both data lines RD1 and WD1 have an equal parasitic capacitance, then the redistribution of electrical charge occurs all at once and the potential on both data lines reaches VDD/2. Afterwards, both the data lines RD1 and WD1 are set to zero (0) level by means of a discharge path formed by the sense amplifier SA1 and the memory cell MC11. If the read data line DR1 is at a high level, then the write data line DW1 is maintained at the VDD corresponding to the precharge level.

In the discharge process for the data lines RD1 and WD1, when a high level write voltage (VDD) is added to common data line IO, both data lines RD1 and WD1 change to a high level (VDD) voltage potential in response to the write voltage. When a low level (0 volts) is added, both data lines RD1 and WD1 change to a high level (VDD) in response to the write voltage.

The Y select line YS1 and control line WCL1 are set to low level after these type of write voltages are conveyed to the write data line WD1, and the MOSFET QY11 and QT1 set to off status.

Then, in the second selection period, the word line W11 changes to a high voltage VW to set the write transistor QW to on status. Turning the write transistor QW on, conveys the voltages of the write data lines WD1 through WDm to the respective memory nodes N11 through N1m, writes the information voltages corresponding to external write signals in the selected memory cell MC11, and writes inverted voltages of the original memory voltages, in the other memory cells MC12 through MC1m.

When the write operations for the selected memory cells as described above and the so-called refresh (rewrite) operations for the non-selected memory cell have finished, the word line WL11 is set to a low level such as zero (0) volts. The voltage such as at the memory node N11 of the memory cell are at a sufficiently small voltage due to the capacitor C as previously described. Here, even when a high level such as VDD is written in the memory node N11, after the read data line RD1 has discharged to zero (0) volts, electrical current flow cannot continue in the storage MOSFET QR. Therefore, there is no need for providing a circuit to set the source terminal of the storage MOSFET QR to a floating state, and as shown in the figure, a steady connection to circuit ground potential can be achieved.

The timing for setting the MOSFET QT1 of the write control circuit WC1 to an off state, or in other words, the timing for setting the control line WCL1 to a low level non-select state is determined by the rewrite operation of the non-select cell rather than the write operation of the selected cell.

The reason why rewrite operation is determined by the non-select cell is that after the data lines RD1 and WD1 and RDm and WDm have reached the respective voltage potentials p, q or p', q' in the waveform of FIG. 8, the write data line WD1 of the select cell is driven by both the sense amplifier SA1 and the memory cell MC11, but the write data lines WD2-WDm of the non-select cells MC12-MC1m are driven only by the respective corresponding memory cells.

The read operation is as follows. After the read signals of the selected memory cells in the above write operation have been amplified and output by the sense amplifiers SA1-Ak, there is no input of external write signals or restated, the selected read data line RD1 and the write data line WD1 can be kept with their voltage potential unchanged and the select level of the word line set the high voltage VW for writing. The corresponding respective read voltages of selected cells and non-selected cells for read out connected to the selected word lines are rewritten at this time.

The refresh operation is as follows. This refresh operation is mainly applicable when using a MOSFET as the write transistor QW such as in the memory cell shown in FIG. 1. Here, when a BMOS having a barrier insulator structure as in the embodiment shown in FIG. 2 is used, the leakage charge from the memory node can be limited to a value small enough to be ignored and the memory information is nonvolatile so the individual refresh operations are unnecessary however refresh operation may be required in some cases according to the BMOS design.

In the refresh operation, the Y select line YS in the waveform shown in FIG. 8 is not performed, and the word lines are set to voltage VR in the first select period in sequence from WL11 to WL1n as well as WLK1 to WLkn and the read out from the memory cell is performed, signals are conveyed to the write data line by way of the write control circuit, and then a high voltage VW can be set in the second select period and write can be performed in the memory nodes of the memory cell.

The memory cell has an internal gain function, and if a memory cell having separate read and write data lines, then the circuit method of this embodiment can be applied unchanged in such kind of memory cell.

FIG. 9 is a circuit schematic showing another embodiment of the memory cell utilized in the memory circuit of this invention. In (A) of FIG. 9 of this embodiment, a select MOSFET QR2 is formed between the read data line RD and the drain of the storage MOSFET QR1. The gate of this select MOSFET QR2 is connected to the word line WL. This structure may be considered in the memory cell of the embodiment of FIG. 1, as added with the select MOSFET QR2 and having the capacitor C removed.

In this case, the select operation of the word line is split between the read first select period and the write and rewrite second select period and the select voltages are changed. The select MOSFET QR2 and the write MOSFET QW threshold voltages are set according to these select voltages. In other words, the MOSFET QR2 is at on status at read voltage VR in the first select period, and the write MOSFET QW is at off status. In the second select period, at the write voltage VW, the write MOSFET QW is set to on status. The threshold voltage of the MOSFET QR2 is set low and the MOSFET QW threshold voltage is set high for the first select voltage VR corresponding to select/non-select operation for a word line of this kind with a three value level; and the MOSFET QW threshold voltage is set low for the second select voltage VW.

The MOSFET QR2 has been added in this embodiment so that the number of elements have increased however the capacitor C is not needed so that operation can be stabilized. In other words, the voltage margin can be increased when accessing the memory cell.

In FIG. 9, B is a changed version of the memory cell in A of the same figure. The word lines are separated into a write word line WWL and a read word line RWL. The gate of the write MOSFET QW is connected to the write word line WWL, and the gate of the select MOSFET QR2 is connected to the read word line RWL.

In this embodiment, a select/non-select operation utilizing a 3-value level for the word lines is unnecessary on account of separation of word lines into two lines, one for read and one for write. More specifically, the read word line RWL is set to select status in the word line first select period, and the select MOSFET QR2 set to on status by the select operation of read word line RWL causes current from the memory of the storage MOSFET QR1 (set to on or off status according to the memory cell information voltage) to flow in the read data line RD. If the storage MOSFET QR1 was set to on status by a high level information voltage, then the read data line RD is discharged, and if the storage MOSFET QR1 was set to off status by a low level information voltage then the read data line RD is maintained at the precharged voltage.

In the word line second select period with the write word line WWL set to select status, and the write MOSFET QW set to on status, the write voltage conveyed to the write data line WD is written into the gate of the storage MOSFET QR1. Though this embodiment increases the number of word lines by two lines, a benefit is that the write and the read word lines can respectively be set to select/non-select with binary information so that all threshold voltages of each MOSFET comprising a memory cell can be equivalent, thereby the design and manufacture is simplified.

In the write control circuit WC, when conveying the read signal appearing on the read data line RD unchanged to the write data line WD and performing rewrite (refresh), the memory node information voltage is inverted at that time. A data control register is then provided as described next, and the control of the data input/output buffer is implemented.

The concept for this control method utilizing as an example, a DRAM consisting of three transistors was previously related in the known art, in ISSCC72 (International Solid-State Circuits Conference in 1972) on pp. 12-13 of the digest. In other words, a data control cell having the same structure as a memory cell is connected to each word line. When a word line is selected, a read signal from the selected data control cell is output on the common output signal line.

The signal from the selected data control cell and the signal read out from the memory cell array via the sense amplifier are sent to an exclusive OR logic circuit and the output is sent as data output DO. However, the read signal to the data control register and the data input signal DI are summed in the same exclusive OR logic circuit and become write data in the memory cell array. In order to perform data input/output control at high speed, the channel width of the output transistor (equivalent to the read MOSFET QR) within the data control cell is made larger than the channel width of the memory cell.

FIG. 10 is an essential portion of a circuit schematic showing another embodiment of the memory cell comprising the semiconductor integrated circuit of this invention. In FIG. 10, one read data line RD1, write data line WD1 and common data line IO (1) corresponding to the read data line RD1, and one word line WL11 as well as one memory cell MC11 and write control circuit WC1 are used as typical elements to describe operation.

This embodiment comprises a memory cell MC11 the same as the embodiment of FIG. 1. In this embodiment, an inverting amplifier circuit comprised of a MOSFET QT11 and MOSFET QT12 are utilized at the write control circuit WC1 instead of the transfer gate MOSFET used previously. The MOSFET QT11 is an amplifying MOSFET whose gate is connected to the read data line RD 1. The MOSFET QT12 is an output select MOSFET for conveying the output from the drain of MOSFET QT11 to the write data line WD1. The gate of the MOSFET QT12 is connected to the control line WCL1 as the line select line.

In this structure, the memory information of the memory cell MC11 is read out to the read data line RD1, the output select MOSFET QT12 is set to on status by means of the high level on the control signal WCL1, and the inverted amplified signal obtained from the drain of the amplifier MOSFET QT11 is conveyed to the write data line WD1.

For example, if the memory node of the memory cell is stored with information at a high level, then as described before, the storage MOSFET QR is set to on status in the first select period of the word line WL11, and the read data line RD1 is discharged to a low level. Since the amplifier MOSFET QT11 sets to off status upon receiving the low level from the read data line RD1, even if the output select MOSFET QT12 is set to on status by selecting the control line WCL1, the write data line WD1 is kept unchanged at a precharge voltage potential such as VDD. Accordingly, when the write MOSFET QW is set to on status by the second select period of the word line WL11, then a high level voltage, the same as the memory voltage, is written into the memory node.

Conversely, when a low level (voltage) is stored in the memory node of the memory cell, the storage MOSFET QR sets to off status in the first select period of the word line WL11 as described before, and the read data line RD1 is maintained unchanged at a high level precharge state. Since the amplifier MOSFET QT11 sets to on status upon receiving this high level from the read data line RD1, when the output select MOSFET QT12 is set to on status by selecting the control line WCL1, the write data line WD1 is discharged to zero (0) volts. Accordingly, when the write MOSFET QW is set to on status by the second select period of the word line WL11, then a low level voltage, the same as the memory voltage, is written into the memory node.

When using an inverting amplifier function in the write control circuit WC1 in this way, the previously described data control register becomes unnecessary and design of the data input/output circuits becomes simple so that along with achieving high speed rewriting to a non-select cell, the memory cell is easier to use.

FIG. 11 is a waveform chart for describing one working example of the memory circuit operation of FIG. 10.

The word line WL11 is set to a low read voltage VR in the first select period. In the non-select period, the read data line RD1 precharged to a VDD level is changed for the memory voltage of the memory node. In other words, in a state where an information voltage higher than the threshold voltage VTR of the MOSFET QR has been applied at the gate of the storage MOSFET QR, the MOSFET QR sets to on status and is discharged from VDD to zero (0) volts as shown by the solid line in the figure. In a state where an information voltage lower than the threshold voltage VTR of the MOSFET QR has been applied at the gate of the storage MOSFET QR, the MOSFET QR is set to off status and is maintained at the VDD precharge level as shown by the dotted line in the drawing.

When the Y select line YS1 is set to a high level such as VDD+VT, the read data line RD1 and the common data line IO (or /IO) are connected, and the redistribution of the electrical charge causes the read data line RD1 and the common data line IO to set to a high level or low level just by the minute voltage VS based on VDD/2. Afterwards, the amplifying operation of the sense amplifier starts and the read data line RD1 and the common data line IO change to a high level or a low level VDD. When the control line WCL1 is set to a high level, the