Semiconductor integrated circuit Number:6,801,060 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor integrated circuit

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

Patent Number: 6,801,060 Issued on 10/05/2004 to Ikehashi,   et al.

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Inventors:	Ikehashi; Tamio (Kamakura, JP), Sugiura; Yoshihisa (Kamakura, JP), Imamiya; Kenichi (Kawasaki, JP), Takeuchi; Ken (Tokyo, JP), Iwata; Yoshihisa (Yokohama, JP)
Assignee:	Kabushiki Kaisha Toshiba (Kawasaki, JP)
Appl. No.:	10/443,820
Filed:	May 23, 2003

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	200152	Jul., 2001	6590444
	023946	Dec., 2001
	375370	Aug., 1999	6351179	Feb., 2002

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Foreign Application Priority Data

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Aug 17, 1998 [JP]			10-230478

Current U.S. Class:	327/80 ; 327/205; 327/78
Field of Search:	327/77,78,80,81,205

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References Cited [Referenced By]

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U.S. Patent Documents

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	4560889		December 1985		Hayashi
	4683382		July 1987		Sakurai et al.
	4888497		December 1989		Dallabora et al.
	5249155		September 1993		Arimoto et al.
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	5337284		August 1994		Cordoba et al.
	5394104		February 1995		Lee
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	5493234		February 1996		Oh
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	5744996		April 1998		Kotzle et al.
	5804996		September 1998		Verhaeghe et al.
	5969420		October 1999		Kuge et al.
	6064557		May 2000		Yamasaki et al.
	6078201		June 2000		Crotty
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	6259286		July 2001		Papaliolios
	6492848		December 2002		Lee

Other References

Kiyoo Ito, "Super LSI Memory," Baifukan, pp. 267-269, 307-310 (1994) (w/English translation of relevant parts)..

Primary Examiner: Cunningham; Terry D.
Attorney, Agent or Firm: Banner & Witcoff, Ltd.

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Parent Case Text

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CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 10/200,152, filed Jul. 23, 2002, which now U.S. Pat. No. 6,590,444 is a divisional of U.S. patent application Ser. No. 10/023,946, filed Dec. 21, 2001 (now abandoned), which is a divisional of U.S. patent application Ser. No. 09/375,370, filed Aug. 17, 1999, now U.S. Pat. No. 6,351,179, issued Feb. 26, 2002, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 10-230478, filed Aug. 17, 1998, the entire contents of which are incorporated herein by reference.

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Claims

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What is claimed is:

1. A semiconductor integrated circuit comprising: a power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a detection signal output circuit which receives the output voltage of said power supply voltage detecting circuit, and outputs a first detection signal when said power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to a second voltage lower than the first voltage, the detection signal output circuit comprising a Schmitt trigger circuit, wherein the Schmitt trigger circuit comprises: an input CMOS inverter comprised of an N channel MOS transistor and a P channel MOS transistor; an output CMOS inverter comprised of an N channel MOS transistor and a P channel MOS transistor; and a feed-back circuit, which is comprised of N channel MOS transistors connected in parallel between an input terminal of the output CMOS inverter and a reference potential, in which an output terminal of the output CMOS inverter is connected to gates of the N channel MOS transistors connected in parallel so that an input signal of the output CMOS inverter is fed back to the input terminal of the output CMOS inverter.

2. A semiconductor integrated circuit comprising: a power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage wherein the power supply voltage detecting circuit comprises: first and second resistors serially connected at first terminals thereof, a second terminal of the first resistor being connected to a power supply node; an N channel MOS transistor whose drain is connected to a second terminal of the second resistor and whose source is connected to ground; a P channel MOS transistor whose source is connected to the power supply node and whose drain is connected to an output terminal; a third resistor which is connected between the drain of the P channel MOS transistor and ground; and a stabilization capacitor which is connected between the drain of the P channel MOS transistor and ground in parallel to the third resistor; and a detection signal output circuit which receives the output voltage of said power supply voltage detecting circuit, and outputs a first detection signal when said power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to a second voltage lower than the first voltage.

3. The semiconductor integrated circuit according to claim 2, wherein the N channel MOS transistor is a diode-connected transistor.

4. The semiconductor integrated circuit according to claim 2, wherein a capacitor reinforces the stabilization capacitor.

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Description

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BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit and particularly, to a configuration and layout of a power supply circuit of the semiconductor integrated circuit which prevents a malfunction in a semiconductor integrated circuit caused by a transient change in power supply voltage when a power supply is turned on from occurring and suppresses a decrease in internal power supply voltage immediately after a transition from a stand-by mode to an active mode.

Conventionally, a power-on circuit has been known as a power supply voltage detecting circuit which generates a signal by detecting an increase and a decrease in power supply. When a power supply is turned on, a power supply voltage is increased and exceeds a preset value, a detection signal is generated and a prescribed latch in a semiconductor integrated circuit is reset to a required initial state using the signal. On the other hand, when a power supply voltage is decreased and reaches a preset value, a detection signal is generated, a prescribed latch is reset as in when a power supply is turned on. Then, description will be given of a necessity of resetting of a prescribed latch when a power supply voltage is decreased, taking a non-volatile memory having a floating gate as example.

A sectional view of a structure of a non-volatile memory cell is shown in FIG. 26. Cells 1 and 2 are formed on a silicon substrate, wherein a control gate 40 and a floating gate 41 are provided to each of the cells 1 and 2, channels are formed on the surface of a P well 42 and N-type diffusion layers 43 formed on the P well 42 are respectively used as a source and a drain.

A write operation of the non-volatile memory cell is effected by applying a high voltage of the order of 20V between the control gate 40 and the P well 42 with the control gate 40 being set positive. At this point, electrons are injected into the floating gate 41 from the P well 42 and the memory cell is in a written state.

Then, an erase operation is effected by applying a high voltage of the order of 20V between the control gate 40 and the P well 42 with a potential of the control gate 40 being set 0 or negative, contrary to the write operation, to draw back the electrons in the floating gate 41 injected in the write operation to the P well 42. A situation in which the cell 1 is erased is shown in FIG. 26.

That is, for example, when the cell 1 is selected on the assumption that the cells 1 and 2 of FIG. 26 each are in a written state and if the control gate 40 and the P well are respectively applied with 0V and 20V, electrons (e.sup.-) injected in the floating gate 41 are drawn back to the P well 42 by a tunnel effect to have the cell 1 to be an erased state.

At this point, the control gate 40 is applied with 20V in a non-selected cell 2 and no potential difference between the floating gate 41 and the P well 42 arises. Therefore, electrons injected in the floating gate 41 of the cell 2 are retained.

However, in a case where a power supply voltage is decreased in the erase operation for some reason, a logic circuit malfunctions due to the voltage decrease and in turn, a voltage of the control gate 40 of the cell 2 is decreased to 0V although the voltage should normally be applied with 20V. With the decrease in the voltage, electrons in the floating gate 41 of the cell 2 which should normally be retained are drawn back to the P well 42, thereby effecting an erroneous erase operation.

In order to prevent such a malfunction, it is indispensable that a decrease in power supply voltage is detected immediately when it arises and a potential of the P well 42 be decreased from 20V to 0V. A power-on signal to be generated when the power supply voltage is decreased is necessary for such a recovery operation.

Conventionally, as a circuit which generates a power-on signal, a power supply voltage detecting circuit as shown in FIG. 27 has been employed. The power supply voltage detecting circuit of FIG. 27 is constructed of: a power supply; resistors R1, R2 and R3; an N channel MOS transistor (hereinafter referred to as NMOS) M1 with a threshold voltage Vtn; a P channel MOS transistor (hereinafter referred to as PMOS) M2 with a threshold voltage Vtp; a node N1 connecting a connection point between the resistors R1 and R2 and the gate of PMOS (M2) with each other; a node N2 connecting the drain of PMOS (M2) and the resistor R3; and two inverters 15 and 16 connected to the output side. A power supply voltage and a voltage of the node N1 when a power supply is turned on are respectively denoted by V and VN1, then VN1 is given as follows:

In a case where, when a power supply is turned on, a difference between V and VN1 exceeds the absolute value .vertline.Vtp.vertline. of a threshold voltage of PMOS (M2), that is, when the power supply voltage is higher than Vdetect, which is expressed as follows:

a potential of the node N2 goes to high level (hereinafter expressed as "H") and an output of the power-supply detecting circuit changes to "H" from a low level (hereinafter referred to as "L"). With this operation adopted, a prescribed latch in a semiconductor integrated circuit can be reset. When a power supply voltage is decreased and reaches the level of the equation (2), the output changes from "H" to "L" and the prescribed latch can be reset.

Incidentally, in FIG. 27, the gate and drain of NMOS (M1) are connected with each other and used as an NMOS connected as a diode. Further, the resistor R2 may be removed in the circuit shown in FIG. 27 since no problem occurs even if the resistance R2=0 in the equations (1) and (2).

The power supply voltage detecting circuit is employed in a circuit system in which no down converter is provided. In a circuit system in which an external power supply voltage Vext is decreased to an internal power supply voltage Vint using a down converter, a configuration and function of the power supply voltage detecting circuit is more or less altered.

The down converter system used herein (see "Super LSI memory," authored by Shizuo ITO published by BAIFU KAN, p 267) is a circuit system in which Vext (for example, 3V) which is supplied from the outside of a semiconductor chip is decreased to Vint (for example, 2.5V) using a down converter and the Vint is used as a power supply for an internal circuit in the semiconductor integrated circuit.

A down converter system is especially widely used in semiconductor integrated circuits such as a memory and is useful as a very effective measure to cope with reduction in breakdown voltage of a transistor used in an internal circuit, which accompanies progress in microfabrication technique, and further, becomes an important measure to support a trend toward a multiple power supply for a semiconductor integrated circuit.

In a down converter system, two kinds of power supply detecting circuits for Vext and Vint are required. A Vext detecting circuit detects an increase in Vext and activates a down converter and a reference voltage (hereinafter referred to as Vref) generating circuit, while, when Vext is decreased, the circuit provides a function similar to a conventional manner.

A Vint detecting circuit further functions to reset a latch to a required initial condition in an increase in Vint as in a conventional manner when a power supply is turned on. However, when Vint is decreased, the Vint detecting circuit is not required to output a signal. The reason why is that the Vext detecting circuit detects a decrease in external power supply voltage prior to a decrease in internal power supply voltage Vint.

If functions of the Vext and Vint detecting circuits are considered, it is understood that a detecting circuit which outputs signals when a power supply voltage reaches the same voltage level in both cases of an increase and a decrease in power supply voltage may be adopted as a Vext detecting circuit as in a conventional manner. On the other hand, if such a circuit is adopted as a Vint detecting circuit, a problem which will be described below arises.

While Vint in a down converter system is generated by decreasing Vext using a down converter, characteristics of the down converter are, in the case, required to be determined so that a voltage level of Vint is constant regardless of a magnitude of Vext and an amount of a current consumption of an internal circuit.

However, when a lot of current is consumed in a short time in the internal circuit, an instantaneous decrease in voltage level Vint cannot be prevented from occurring. Such a situation occurs, for example, in cases where an extremely large capacitance is charged from 0V to Vint in voltage level and data are inverted in a number of latches at almost the same point of time, whereby a lot of current flows through circuits in an instant, and the like case. The term "current flowing through circuits" is that while a power supply current is normally interrupted in the course of inversion of a CMOS gate, the current flows through in an unexpected instant.

Once the Vint detecting circuit detects such a temporary decrease in Vint, there arises a problem that a latch in which important information such as an address, written data in a memory cell is stored is reset to an initial state.

Incidentally, as described above, while a down converter decreases Vext and generates Vint and consumes a current constantly in order to keep Vint at a constant level, an amount of the current consumption is different according to an ability of the down converter (an ability to keep Vint at a constant level) and as the ability is higher, the current consumption is increased.

In order to suppress power consumption in the down converter as low as possible, there have been proposed various kinds of systems in which an internal circuit is respectively operated according to two cases: one case in an active mode where a large current is consumed and thereby, a high ability is required for the circuit and the other in a stand-by mode where almost no current flows through an internal circuit (see "Super LSI memory," authored by Shizuo ITO published by BAIFU KAN, pp. 307 to 310).

FIG. 28 conceptually shows a configuration in which an internal circuit is differently operated according to cases. While a stand-by mode down converter 9 whose power consumption is low is constantly operated, an active mode down converter 10 whose power consumption is high is operated only in an active mode. In a conventional example shown in FIG. 28, Vint of the stand-by mode down converter 9 and Vint of the active mode down converter 10 are both set to the same voltage level.

A conventional active mode down converter 10 is a circuit with a high speed response in order to suppress a fluctuation in Vint. However, a time period is required from when an enable signal generating section 7 of an active mode down converter outputs an enable signal till the active mode down converter 10 reaches an operating state. When, during such a time period, an internal circuit 11 consumes a large current, there arises a problem that the stand-by mode down converter 9 cannot singly suppress fluctuations in Vint and thereby Vint is decreased. The decrease in Vint is about 0.2V.

Then, the reason why a power supply for a chip is required to adopt a multiple power supply system such as in the case of a combination of Vext and Vint and down converters which have conventionally been studied will be described in a more detailed manner of the case of a semiconductor integrated circuit such as a memory as central issues.

According to a scaling rule of a transistor, when a size of a transistor is reduced to 1/K of the original size, a magnitude of a power supply voltage is also required to be 1/K of the original voltage, in order to operate a transistor under the same electric field strength. Actually, however, the power supply voltage cannot freely be changed since the voltage is dependent on systems which are incorporated in a chip.

Hence, it has often been conducted that only sizes of transistors are reduced while a magnitude of a power supply voltage of the preceding generation is maintained. In this case, a power supply voltage is decreased on a chip and such a decreased voltage is applied to miniaturized transistors in use for an internal circuit in order that an immunity to the hot-electron effect of the transistors is not problematic in practical aspects.

In a concrete manner of description, while it is desirable from the viewpoint of high integration and realization of a high speed that a gate oxide film of an MOS transistor is thinned in a semiconductor integrated circuit of a memory such as DRAM or a non-volatile memory, there arise problems of reliability such as dielectric breakdown of the gate oxide film, reduction in hot electron resistance if the gate oxide film is only thinned without any decrease in the power supply voltage.

When a gate length of an MOS transistor is shortened and thereby, an electric field strength in the drain region is increased, electrons/holes which are accelerated in the drain region become a high energy state and are injected into a gate oxide film or the like, which results in deterioration of characteristics of the MOS transistor. The hot electron resistance herein is an ability whereby the transistor endures such a phenomenon.

Accordingly, when a thin oxide film is used, it is indispensable that a power supply voltage is decreased and the hot electron resistance is improved, but there is existent an MOS transistor with a thick gate oxide film which does not require reduction in power supply voltage in a CPU and the like, which are in a mixed manner formed on the same chip together with the DRAM, a non-volatile memory or the like, and which share the same power-supply. A power supply voltage for an MOS transistor in such a CPU and the like are not desired to be reduced together with a collective reduction in power supply voltage of the entire system since the reduction results in a decreased operating speed of the system.

For this reason, a down converter system is effective in which Vext supplied from the outside of a semiconductor integrated circuit is decreased and thus decreased voltage is used as Vint for an internal circuit. The voltage-decreasing system has heretofore been employed mainly for DRAM. As a down converter for Vext in this case, the following two kinds have been known mainly.

One is a circuit which decreases a voltage through PMOS and a circuit configuration is shown in FIG. 29. The down converter is, hereinafter, referred to as PMOS type. As shown in FIG. 29, the PMOS down converter constitutes a feed-back system and a gate voltage of PMOS (M18) is to be determined according to a value of Vint.

That is, if Vint (a power supply voltage VDD of an internal circuit) is decreased, thus decreased Vint is detected from comparison of a voltage obtained by resistance division of Vint between resistors R15 and R16, with Vref and a gate voltage of the PMOS (M18) is decreased. With the decrease in the gate voltage, Vint is increased. To the contrary, as Vint is increased, a gate voltage of the PMOS is increased and since a supply current is suppressed, an increase in Vint is restricted. Incidentally, C4 is a capacitor for stabilization and C6 is a capacitor for phase compensation in FIG. 29.

The other is a circuit which decreases a voltage through NMOS and a configuration thereof is shown in FIG. 30. The down converter is, hereinafter, referred to as NMOS type. An NMOS down converter does not constitute a feed-back system and a gate voltage of the NMOS (M10) is kept at the sum of Vint (VDD) and a threshold voltage Vt of the NMOS by voltage generating circuit constructed of a voltage limiter 13 and a charge pump circuit 14. If Vint is decreased, a potential difference between the gate and source of the NMOS (M10) is increased and thereby, a supply current is increased, so that Vint is increased. Incidentally, VDDH is an output voltage of voltage generating circuit, CDDH is a capacitor for stabilization of the output voltage and CDD is a capacitor for stabilization of Vint (VDD).

As shown in FIG. 31, in an NMOS down converter, a voltage-decreasing MOS (M10 of FIG. 30) is operated in a sub-threshold region. This is because a fluctuation in internal voltage can be suppressed small even if current consumption of the internal circuit is fluctuated over several orders of magnitude. The sub-threshold region herein means a operating region of a MOS transistor in which a smaller drain current flows compared with in a normal operation in a case where a gate is equal to or lower than a threshold voltage.

Voltages applied to electrodes and a current of a voltage-decreasing NMOS (M10) used in the NMOS down converter of FIG. 30 are shown in FIG. 31A. Vext is applied to the drain of NMOS, Vint to the source thereof and an output voltage VDDH of a voltage generating circuit to the gate thereof. That is, a drain voltage VD=Vext-Vint is applied between the source and drain and a drain current ID flows therethrough. A dependency of the drain current ID on the drain voltage VD is shown in FIG. 31B. The relation can be explained using a mathematical expression as follows.

When a gate voltage of NMOS is denoted by VDDH, a threshold voltage by Vt, an electron charge by q, Boltsmann constant by k, an absolute temperature by T, a drain current ID in the sub-threshold region of NMOS when a drain voltage is VD is expressed with a constant 10 and n in the following way:

As can be understood from the above equation, a change in VD (corresponding to a change in internal power supply voltage Vint) is proportional to a value of log (ID/IO) and is limited to be small even when a supply current ID is changed over several orders of magnitude (see FIG. 31B).

Further, while, as the voltage-decreasing NMOS, a transistor of the same kind as NMOS in use for an ordinary circuit is used, a gate width W of NMOS is required to be very large, for example, 100 mm, since, in the case of the voltage-decreasing NMOS, not only is the operation effected in a sub-threshold region and a large supply current is required to be secured. In the equation (3), increase in a gate width W corresponds with increase in factor IO.

When the NMOS down converter shown in FIG. 30 is used, capacitors for voltage stabilization are required to be connected to terminals of the internal power supply voltage Vint and the gate voltage VDDH of NMOS. A capacitor CDD connected to Vint (VDD) functions to compensate an instantaneous decrease in Vint due to power consumption of a circuit. If CDD is large, a decrease in Vint is small. On the other hand, a capacitor CDDH connected to the gate voltage VDHH of NMOS works for prevention of a fluctuation of the gate voltage from occurring in cooperation with capacitive coupling in a channel section and a capacitance between interconnections.

A magnitude of CDDH is determined in consideration of a response time of a system including a voltage limiter 13 and a charge pump circuit 14. That is, if a time period from when the voltage limiter 13 detects a decrease in VDDH till the charge pump circuit 14 restores a decreased voltage to the original voltage is short, a capacitance of the capacitor CDDH connected to the terminal of VDDH may be small, but if it is long, a large capacitance of CDDH has to be connected in order to compensate a decrease in VDDH during the time period.

While the two kinds of configurations of conventional down converters have been available, some devices are required according to characteristics of both in actual phases. What is especially required to be careful is operations of a down converter in operating modes, stand-by and active, of a semiconductor integrated circuit.

In a stand-by mode, not only current consumption of an internal circuit but also current consumption of the down converter itself are required to be small in order to suppress total current consumption of the entire chip. To the contrary, response of the down converter may be slow.

On the other hand, in an active mode, as the current consumption of the internal circuit is increased, an instantaneous increase/decrease in current consumption is unavoidable in accordance to an operating mode. The down converter is required to function to constantly keep the internal power supply voltage Vint at a prescribed level in a quick response to such an increase/decrease in current consumption.

When the PMOS down converter of FIG. 29 is used, there have been proposed various kinds of systems in which down converters are differently operated according to an active mode or a stand-by mode in order to meet the requirements as described above.

FIG. 32 conceptually shows a configuration in which such different operating modes of down converters are selected. A PMOS down converter which is of low power consumption but slow in response and a PMOS down converter which is of high power consumption, but fast in response constitute a voltage-decreasing system, wherein in a stand-by mode, the PMOS stand-by mode down converter 9a which is of low power consumption is only operated according to an enable signal, while in an active mode, the PMOS active mode down converter 9b which is fast in response is additionally operated according to an enable signal. In the mean time, in the conventional example shown in FIG. 32, an internal power supply voltage of the stand-by mode down converter and an internal power supply voltage of the active mode down converter are set to the same level.

On the other hand, when the NMOS down converter of FIG. 30 is used, two kinds of circuits are not operated selectively according to the stand-by mode or the active mode. That is, one NMOS down converter is continued to be always operated regardless of the stand-by mode or the active mode. In this case, in order to suppress a stand-by current, it is required to suppress current consumption of voltage generating circuit including the voltage limiter 13 and the charge pump circuit 14.

As a result, while a response speed of a feed-back system including the voltage limiter 13 and the charge pump circuit 14 is lowered, such a lowered response speed is not problematic since a fluctuation in voltage VDDH is small if a value of the capacitance of CDDH for stabilization is set large.

Outlines of the conventional NMOS down converters and the PMOS down converter have been described above. If down converters are selectively operated differently according to the stand-by mode or the active mode in a down converter system, no problems arise in both voltage circuits, as far as a capability and power consumption of each of the down converters are concerned. However, the down converters respectively have problems in circuit design and layout as described below. Then the problems will be described individually.

Since current consumption of a PMOS down converter can be small by using resistors R15 and R16 of high resistance of FIG. 29, the circuit is suitable for a stand-by mode. However, since the circuit constitutes a feed-back system, an internal power supply voltage Vint falls in an oscillating state or a decrease in the voltage occurs if design parameters such as phase compensation of a comparator constituted of a differential amplifier and the like are not correctly estimated. Especially, it is very difficult to design a down converter which is operated in a stand-by mode so that the circuit does not oscillate even when the circuit is operated in an operating mode in which a current is increased by 4 to 5 orders of magnitude.

That is, the PMOS down converter is easier to cause abnormality in an active mode in which increase or decrease in current consumption is more large than in a stand-by mode in which current consumption of an internal circuit is small. In this case, in order to design a feed-back system in a secured manner, it is required that current consumption of an internal circuit in each operating mode is correctly estimated and furthermore, simulations in various conditions are executed deliberately. Accordingly, a PMOS down converter has a high degree of difficulty in design and consumes a long design time compared with an NMOS down converter.

On the other hand, an NMOS down converter is easier to be used than a PMOS down converter in an operating state in which a large current is consumed. However, while the NMOS down converter has an advantage of easy design, it is hard to suppress current consumption of the down converter itself since control is effected by a charge pump circuit.

Further, the NMOS down converter has a disadvantage that the circuit requires a large layout area. That is, the NMOS down converter comprises the following elements: (1) a capacitor CDD connected to an internal power supply; (2) a capacitor CDDH connected to VDDH; (3) a voltage-decreasing NMOS transistor; and (4) VDDH voltage generating circuit (a charge pump circuit and a limiter)

and a layout area for each element is increased in the order from (1) to (4).

Why (1) and (2) occupies larger areas is that the elements each require a capacitance of the order of nanofarads (nF) in order to stabilize a voltage. In the case of DRAM, the capacitors can be constituted of those in the same shape as a memory cell. The capacitors in the same shape as a memory cell are very much small in layout area per a unit capacitance compared with an ordinary MOS capacitor.

Hence, in DRAM, restriction on a layout area caused by the (1) and (2) is comparatively small. However, when an NMOS capacitor is applied to a semiconductor integrated circuit, for example a non-volatile memory, which does not include proper capacitive devices like DRAM, a very large layout area is required compared with the case of DRAM since the capacitors of (1) and (2) are formed by ordinary MOS capacitors.

Further, when the capacitors are formed by MOS capacitors, a capacitor CDD of (1) is not problematic in reliability of an oxide film since a potential difference applied to both ends of an oxide film is of the order of an internal power supply voltage Vint (VDD), but a capacitor CDDH of (2) cannot use a MOS capacitor for CDD as it is from the viewpoint of reliability since a potential difference between both ends of an oxide film is large: VDDH=VDD+Vt (Vt is a threshold voltage of a voltage-decreasing NMOS).

Hence, as a capacitor CDDH of (2), a MOS capacitor, whose oxide film is thick, and whose breakdown voltage is large, has to be adopted and therefore, a layout area for a capacitor is further increased.

Besides, in the NMOS down converter shown in FIG. 30, Vint (VDD) which is generated in the source of a voltage-decreasing NMOS transistor (M10) is supplied to peripheral circuits blocks. At this point, if a distance between the voltage-decreasing NMOS (M10) and the peripheral circuit blocks are too much, interconnection therebetween is a cause to provide unintentional parasitic resistance. In a down converter, control is effected so that the source of a voltage-decreasing NMOS (M10) is at a constant voltage and therefore, VDD is decreased due to the parasitic resistance in the peripheral circuit block.

Further, in an NMOS down converter, though it is preferable that a uniform operation is effected over the whole of a large gate width of the voltage-decreasing NMOS (M10), if a layout area of the voltage-decreasing NMOS is too large, a part of the gate width W has a chance to get early operated compared with the other parts due to a parasitic resistance of interconnection which is connected with the voltage-decreasing NMOS (M10). Therefore, it is required that a layout area of the NMOS down converter is contracted and thereby the length of interconnection is suppressed, as a result decreasing parasitic resistance of interconnection.

However, in a memory such as a NAND flash memory (a batch-erasable memory), there is an operation in which a very large capacitance including those of word lines, a power supply node in a sense amplifier is charged in one time and at this operation, a large current flows locally. For example, in data write, a current which charges word line capacitance of the order of 60 nF flows in a wordline driver circuit in a concentrated manner. In order to suppress a fluctuation in operation of a voltage-decreasing NMOS (M10) due to such a transient large current, it is required to connect a stabilization capacitor CDD with a large capacitance to an internal power supply voltage Vint (VDD) as described above and therefore, it is not easy to contract a layout area for the NMOS down converter.

Besides, in a non-volatile memory, since a high voltage for write and erase is used in the chip, there is a possibility to use not only an internal power supply voltage Vint, which is decreased in an internal circuit, but also part of an external power supply voltage Vext in peripheral circuits. For this reason, a further restriction on layout arises in the NMOS down converter.

For example, since a high breakdown voltage transistor with a thick gate oxide film is used for a charge pump circuit 14 shown in FIG. 30, a power supply voltage of the charge pump circuit 14 is not necessarily a decreased power supply voltage Vint. In addition, the charge pump circuit 14 has large current consumption since the circuit charges a comparatively large capacitance including a word line, a well and the like. When a decreased voltage Vint is used for a power supply voltage of the charge pump circuit 14, a power supply voltage Vint (VDD) of an internal circuit has a possibility to be unstable by receiving an influence of a large charge current since the current is supplied through the voltage-decreasing NMOS (M10).

On the other hand, when an external power supply voltage Vext is used in the charge pump circuit 14, a circuit is required which switches Vext and Vint as a peripheral circuit to control the charge pump circuit 14 and both of Vext and Vint are required to be supplied to a peripheral circuit block. In such a manner, when a plurality of power supply circuits coexists in the peripheral circuit block, there is a necessity that an internal power supply voltage Vint which is supplied from a down converter and an external power supply voltage Vext which is applied to the down converter are both interconnected to the peripheral circuit block, which makes overlap of power supply lines large.

In FIG. 33, there is shown an example of a layout of a conventional semiconductor integrated circuit: that is a memory, provided with a cell array 37; a down converter 38; a peripheral circuit block 39 on a semiconductor chip 36. Since it is a precondition that a power supply interconnection to the peripheral circuit block 39 is usually limited for Vint (VDD), if an external power supply voltage Vext is used in the peripheral circuit block 39, an interconnection for Vext has required to be laid down in excess, thus producing an overhead of a layout area.

Further, in the conventional layout shown in FIG. 33, there arises a necessity for irregular power supply interconnection to lead out Vint (VDD) to the peripheral circuit block 39 from a voltage-decreasing NMOS included in the down converter 38. When the interconnection is long, an unintentional parasitic resistance is added to the source of the voltage-decreasing NMOS.

Since the down converter shown in FIG. 30 performs control so that the source voltage of the voltage-decreasing NMOS (M10) is constant, an exact control cannot be performed if a resistance is added to the source. As described above, in a layout method for a conventional NMOS down converter on a chip of a semiconductor integrated circuit, there has been a problem of increase in area due to extended inter-connection and a problem of control of a power supply voltage accompanying with the increase in area.

As described above, there has been a problem that in an internal power supply of a conventional semiconductor integrated circuit, when the power supply voltage is temporarily decreased due to a power consumption of internal circuit, the power supply voltage detecting circuit detects the decrease and resets latches erroneously.

Further, there has been another problem that in power supply circuit of a down converter system provided with down converters, in a stand-by mode and an active mode, when transition is effected from the stand-by mode with low power consumption to the active mode with high power consumption, a temporary decrease in internal power supply voltage is hard to suppress.

BRIEF SUMMARY OF THE INVENTION

There has been many problems associated with designing and a layout area of NMOS and PMOS down converters employed in a conventional semiconductor integrated circuit of a multiple power supply type and it has been difficult not only to meet requirements in miniaturization and realization of higher integration for both down converters but to obtain a semiconductor integrated circuit of a multiple power supply type which operates according to the design using both down converters.

The present invention has been made in order to solve the above described problems and accordingly, it is an object of the present invention to provide a power supply voltage detecting circuit which will not make a latch malfunction even if an internal power supply voltage changes temporarily and provide down converters respectively in stand-by and active modes which suppress decrease in internal supply voltage in transition from the stand-by mode to the active mode, whose layout require small areas, and which can be designed with ease.

A semiconductor integrated circuit of the present invention is characterized by that there is provided a power supply voltage detecting circuit which avoids malfunction when a temporary change in power supply voltage occurs, by changing a detecting level according to increase or decrease in power supply voltage.

A semiconductor integrated circuit of the present invention which uses a PMOS down converter in a stand-by mode and an NMOS down converter in an active mode is characterized in that the decrease in internal power supply voltage immediately after a transition from the stand-by mode to the active mode occurs is suppressed by setting the internal power supply voltage in the stand-by mode higher than in the active mode.

A semiconductor integrated circuit of the present invention is characterized in that a down converter is formed in a lower layer of an external power supply interconnection. Peripheral circuit blocks to which a decreased internal power supply voltage is supplied are formed in a lower layer of internal interconnection adjacent to both sides of the external power supply interconnection. Thereby, a distance between the down converter and the peripheral circuit blocks to which the internal supply voltage is supplied is minimized and further a decrease in voltage due to an interconnection resistance is avoided.

In a concrete manner of description, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a detection signal output circuit which receives the output voltages of the power supply voltage detecting circuit, and outputs a first detection signal when the power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to a second voltage lower than the first voltage.

In the semiconductor integrated circuit according to the first aspect of the present invention, the detection signal output circuit may comprise a Schmitt trigger circuit.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a second power supply voltage detecting circuit which, when the power supply voltage is higher than a second voltage, outputs a high level voltage, and when the power supply voltage is lower than the second voltage, outputs a low level voltage; and a detection signal output circuit which receives voltages of the output levels of the first and second power supply voltage detecting circuits, and outputs a first detection signal when the power supply voltage is increased to be equal to or higher than the first voltage, and a second detection signal when the power supply voltage is decreased to be equal to or lower than the second voltage which is higher than the first voltage.

In the semiconductor integrated circuit according to the second aspect of the present invention, the detection signal output circuit may comprise a flip-flop circuit to which the voltages of the output levels of the first and second power supply voltage detecting circuits are input.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit in which an external power supply voltage supplied externally is decreased and an internal power supply voltage for driving an internal circuit is generated, comprising an external power supply voltage detecting circuit which detects the external power supply voltage; and an internal power supply voltage detecting circuit which detects the internal power supply voltage, wherein the internal power supply voltage detecting circuit is comprised of a power supply voltage detecting circuit which, when the internal power supply voltage is increased to be equal to or higher than a first voltage, outputs a first detection signal, and when the power supply voltage is decreased to be equal to or lower than a second voltage which is lower than the first voltage, outputs a second detection signal.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit in which an external power supply voltage supplied externally is decreased and an internal power supply voltage for driving an internal circuit is generated, comprising an external power supply voltage detecting circuit which detects the external power supply voltage; and an internal power supply voltage detecting circuit which detects the internal power supply voltage, wherein the external power supply voltage detecting circuit and the internal power supply voltage detecting circuit have respective power supply voltage detection levels different from each other.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit in which an external power supply voltage supplied externally is decreased and an internal power supply voltage for driving an internal circuit is generated, wherein the internal power supply voltage is set to a first voltage in a stand-by mode of the semiconductor integrated circuit and a second voltage in an active mode of the semiconductor integrated circuit, and wherein the first voltage in the stand-by mode is set higher than the second voltage in the active mode.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit in which an external power supply voltage supplied externally is generated and an internal power supply voltage for driving an internal circuit is generated, comprising a stand-by mode down converter; a voltage switching circuit for the stand-by mode down converter; an active mode down converter; an enable signal generating section which makes the active mode down converter to be an enable state; and a stabilization capacitor which stabilizes the internal power supply voltage, wherein an output terminal of the enable signal generating section is connected to the active mode down converter and the voltage switching circuit in parallel, and wherein an internal power supply voltage in an stand-by mode is set higher than an internal power supply voltage in an active mode.

In the semiconductor integrated circuit according to the sixth aspect of the present invention, when a time period from when an enable signal is output from the enable signal generating section till the active mode down converter reaches an operating state is denoted by Tact, an average current of the internal circuit during the time period Tact by lint, a capacitance of a stabilization capacitor by C, an internal power supply voltage in a stand-by mode by Vstby and an internal power supply voltage in an active mode by Vint, a relation of C.times.(Vstby-Vint)/Tact>lint may be established.

According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit in which an external power supply voltage supplied externally is decreased and an internal power supply voltage for driving an internal circuit is generated, comprising a stand-by mode down converter; and an active mode down converter which constitutes together with the stand-by mode down converter a down converter for the external power supply voltage, wherein the stand-by mode down converter includes a comparator of a differential amplification type to one of whose input terminals a reference voltage is input; a P channel transistor, whose source is connected to an external power supply line which supplies the external power supply voltage, whose gate is connected to an output terminal of the comparator, and whose drain is connected to an internal power supply line which supplies the internal power supply voltage; and a resistance voltage divider which divides a voltage of the drain over resistance values of resistors and inputs a divided voltage to the other of the input terminals of the comparator, and wherein the active mode down converter includes a voltage generating circuit; and an N channel transistor, whose drain is connected to the external power supply line which supplies the external power supply voltage, whose gate is connected to an output terminal of the voltage generating circuit, and whose source is connected to the internal power supply line which supplies the internal power supply voltage.

In the semiconductor integrated circuit according to the seventh aspect of the present invention, the voltage generating circuit may include a charge pump circuit and a voltage limiter. In the semiconductor integrated circuit, the voltage generating circuit may include a resistor which is connected between an output terminal of the charge pump circuit and an input terminal of the voltage limiter.

In the semiconductor integrated circuit according to the seventh aspect of the present invention, the voltage generating circuit may include a comparator of a differential amplification type to one of whose input terminals a reference voltage is input; a P channel transistor, whose source is connected to the external power supply line which supplies the external power supply voltage, whose gate is connected to an output terminal of the comparator, and whose drain is an output terminal; and a resistance voltage divider which divides a voltage of the drain over resistance values of resistors and inputs a divided voltage to the other of the input terminals of the comparator.

In the semiconductor integrated circuit according to the seventh aspect of the present invention, the semiconductor integrated circuit may further comprise a rectifying element inserted between the output terminal of the voltage generating circuit and the external power supply line which supplies the external power supply voltage, the rectifying element for allowing a current to flow in a direction from a terminal of the external power supply voltage to the output terminal of the voltage generating circuit.

In the semiconductor integrated circuit according to the seventh aspect of the present invention, the semiconductor integrated circuit may further comprise a stabilization capacitor for an output voltage connected to the output terminal of the voltage generating circuit, a capacitance of the stabilization capacitor being smaller than a gate capacitance of the N channel transistor.

In the semiconductor integrated circuit according to the seventh aspect of the present invention, the semiconductor integrated circuit may further comprise a P channel transistor, a source of the P channel transistor being connected to the external power supply line which supplies the external power supply voltage and a drain thereof being connected to the internal power supply line which supplies the internal power supply voltage, and a charging accelerating circuit for accelerating charging of the internal power supply line by holding the P channel transistor in an ON state during a time period from when an external power supply voltage is applied till an internal power supply voltage reaches a prescribed voltage lower than a target value.

According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a down converter which generates an internal power supply voltage on a semiconductor chip from an external power supply voltage which is supplied from the outside of the semiconductor chip; and a charge pump circuit which generates a boosted voltage on the semiconductor chip from the external power supply voltage.

According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a down converter which generates an internal power supply voltage on a semiconductor chip from an external power supply voltage which is supplied from the outside of the semiconductor chip; and an external power supply line which supplies the external power supply voltage and an internal power supply line which supplies the internal power supply voltage, wherein the external power supply line and the internal power supply line are arranged in parallel to each other on the semiconductor chip, and wherein the down converter is arranged in a lower layer of the external power supply line, whereby the internal power supply voltage which is generated in the down converter is supplied to a peripheral circuit block adjacent to the down converter.

According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a down converter which generates an internal power supply voltage on a semiconductor chip from an external power supply voltage supplied from the outside of the semiconductor chip; and an external power supply line which supplies the external power supply voltage and an internal power supply line which supplies the internal power supply voltage, the external power supply line and the internal power supply line being arranged on the semiconductor chip, wherein the down converter is arranged in a lower layer of the external power supply line, and wherein a connection lead section of the external power supply line and the internal power supply line are arranged in a superposing manner, whereby the external power supply voltage and the internal power supply voltage are supplied to a peripheral circuit block adjacent to the down converter.

According to an eleventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising a down converter on a semiconductor chip, which generates an internal power supply voltage from an external power supply voltage supplied from the outside of the semiconductor chip; an external power supply line which supplies the external power supply voltage, the external power supply line and the down converter which is formed in a lower layer of the external power supply line being both formed in a region of the semiconductor chip, which region extends in a direction; a peripheral circuit to which the internal power supply voltage is supplied from the down converter constructed of at least two peripheral circuit blocks which are symmetrically arranged on both sides of the region extending in the direction, and an internal power supply line which supplies the external power supply voltage, wherein the internal power supply line and the at least two peripheral circuit blocks to which blocks the internal power supply voltage is supplied are arranged so as to be adjacent to the region extending in the direction, and wherein the internal power supply voltage is supplied to the at least two peripheral circuit blocks by way of the internal power supply line.

According to a twelfth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first power supply voltage detecting circuit which, when a power supply voltage is higher than a first voltage, outputs a high level voltage, and when the power supply voltage is lower than the first voltage, outputs a low level voltage; and a second power supply voltage detecting circuit which when the power supply voltage is higher than a second voltage, outputs a high level voltage, and w