Semiconductor integrated circuit having discrete trap type memory cells Number:7,190,023 from the United States Patent and Trademark Office (PTO) owispatent A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.<H Semiconductor, integrated, Semiconductor, i, 7190023.html, Patent, pto, 7190023

Title: Semiconductor integrated circuit having discrete trap type memory cells

Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Patent Number: 7,190,023 Issued on 03/13/2007 to Kamigaki, et al.

Inventors: Kamigaki; Yoshiaki (Tokorozawa, JP), Minami; Shinichi (Kodaira, JP), Katayama; Kozo (Kokubunji, JP), Kato; Masataka (Koganei, JP)
Assignee: Renesas Technology Corp. (Tokyo, JP)

Appl. No.: 11/320,850

Filed: December 30, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
11126236	May., 2005	7012296
10633779	Sep., 2003	6894344
10377785	Mar., 2003	6674122
09660923	Sep., 2000	6531735

Foreign Application Priority Data


Sep 17, 1999 [JP]			11-263154
Sep 17, 1999 [JP]			11-263155
Mar 21, 2000 [JP]			2000-83246

Current U.S. Class: 257/316 ; 257/213; 257/288; 257/314; 257/315; 257/E27.103

Current International Class: H01L 29/788 (20060101)

References Cited [Referenced By]

U.S. Patent Documents


4185318	January 1980	Engeler et al.
4527259	July 1985	Watanabe
4554643	November 1985	Kuo
4868632	September 1989	Hayashi et al.
5357134	October 1994	Shimoji
5408115	April 1995	Chang
5467308	November 1995	Chang et al.
5763308	June 1998	Choi
5768192	June 1998	Eitan
5859459	January 1999	Ikeda
5877523	March 1999	Liang et al.
5923978	July 1999	Hisamune
6348387	February 2002	Yu
6424002	July 2002	Kondo et al.
6563151	May 2003	Shin et al.
6624465	September 2003	Chien et al.

Foreign Patent Documents


0 464664	Jan., 1992	EP

Other References

International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-523. cited by other .
IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part A, vol. 20, No. 2, Jun. 1997, pp. 182-189. cited by othe- r .
IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255. cite- d by other.

Primary Examiner: Andujar; Leonardo
Assistant Examiner: Quinto; Kevin
Attorney, Agent or Firm: Mattingly, Stanger, Malur & Brundidge, P.C.

Parent Case Text

This is a continuation application of U.S. Ser. No. 11/126,236, filed May 11, 2005 now U.S. Pat. No. 7,012,296 which is a continuation application of U.S. Ser. No. 10/663,779, filed Sep. 17, 2003 (now U.S. Pat. No. 6,894,344); which is a continuation of application U.S. Ser. No. 10/377,785, filed Mar. 4, 2003 (now U.S. Pat. No. 6,674,122), which is a continuation of U.S. Ser. No. 09/660,923, filed Sep. 13, 2000 (now U.S. Pat. No. 6,531,735).

Claims

What is claimed is:

1. A semiconductor device comprising: a plurality of memory cells each of which includes: a first diffusion region formed in a semiconductor substrate; a second diffusion region formed in the semiconductor substrate; a first gate electrode formed over a region of semiconductor substrate between the first and second diffusion regions; a second gate electrode formed over the region of semiconductor substrate between the first and second diffusion regions; a charge storage film formed over the region of semiconductor substrate between the first and second diffusion regions, having discrete traps, and located between the first and second gate electrodes; and a third gate electrode formed over the charge storage film; a word line coupled to the third gate electrodes of the plurality of memory cells which are arranged in a first direction; and a bit/source line coupled to first diffusion regions of the plurality of memory cells which are arranged in a second direction intersecting the first direction, wherein the first gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other, and wherein the second gate electrodes of the plurality of memory cells arranged in the second direction are coupled to each other.

2. A semiconductor device according to claim 1, wherein each of the first and second gate electrodes has a width smaller than a technology feature size.

3. A semiconductor device according to claim 1, wherein the charge storage film is a silicon nitride film.

4. A semiconductor device according to claim 1, wherein one of the plurality of memory cells shares the bit line/source line and the first diffusion region with a neighboring one of the plurality of memory cells.

5. A semiconductor device according to claim 1, wherein the bit/source line is a diffusion layer line.

6. A semiconductor device according to claim 1, wherein the first gate electrode is located closer to the first diffusion region then the second diffusion region; wherein the charge storage film has a first portion and a second portion to store two bits, the first portion being located closer to the first gate electrode than the second gate electrode and the second portion being located closerto the second gate electrode than the first gate electrode; wherein in a write operation to the first portion, current flows from the first diffusion region to the second diffusion region; and wherein in a read operation from the first portion, current flows from the first diffusion region to the second diffusion region.

7. A semiconductor device according to claim 6, wherein in an erase operation, electrons held in both of the first and second portions are extracted into the third gate electrode.

8. A semiconductor device comprising: a plurality of memory cells each of which includes: a first diffusion region formed in a semiconductor substrate: a second diffusion region formed in the semiconductor substrate; a first charge storage film having discrete traps and formed over a region of semiconductor substrate between the first and second diffusion regions; a second charge storage film having discrete traps and formed over the region of semiconductor substrate between the first and second diffusion regions; a first gate electrode formed over the first charge storage film; a second gate electrode formed over the second charge storage film; and a third gate electrode formed over the region of semiconductor substrate between the first and second diffusion regions and located between the first and second charge storage film; a word line coupled to the first and second gate electrodes of the plurality of memory cells which are arranged in a first direction; and a bit/source line coupled to the first diffusion regions of the plurality of memory cells which are arranged in a second direction intersecting the first direction.

9. A semiconductor device according to claim 8, wherein each of the first and second charge storage films is a silicon nitride film.

10. A semiconductor device according to claim 8, wherein one of the plurality of memory cells shares the bit line/source line and the first diffusion region with a neighboring one of the plurality of memory cells.

11. A semiconductor device according to claim 8, wherein the bit/source line is a diffusion layer line.

12. A semiconductor device according to claim 8, wherein the first charge storage film is located closer to the first diffusion region then the second diffusion region and the second charge storage film is located closer to the second diffusion region than the first diffusion region; wherein in a write operation to the first charge storage film, current flows from the second diffusion region to the first diffusion region; and wherein in a read operation from the first operation, current flows the first diffusion region to the second diffusion region.

13. A semiconductor device according to claim 12, wherein in an erase operation, electrons held in both of the first and second charge storage film are extracted into the third gate electrode.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a nonvolatile semiconductor memory device having multi-storage nonvolatile memory cells in which one memory cell transistor can store information of at least two bits, and further to a semiconductor integrated circuit such as a microcomputer and the like containing the nonvolatile semiconductor memory device.

A typical nonvolatile semiconductor memory device having nonvolatile memory cells is an EEPROM (electrically erasable and programmable read only memory), which can electrically perform program in a byte unit, or a block electrically erasable flash memory.

Any of the nonvolatile semiconductor memory devices is utilized in memory cards which can be easily carried and in devices which can be operated from a remote site, and the like because they can hold memory information without the supply of power, and they act as a data storage, a program storage and the like to store information in a nonvolatile fashion as the initial setting of the operation of the device.

While nonvolatile semiconductor memory devices have been widely used in the filed of computers, communication equipment, controllers, OA (office automation) equipment, consumer equipment and so on, recently, they are particularly applied to portable communication equipment, IC cards used as bank terminals, image storing mediums of camera and the like. As the markets for them are expanded and the systems therefor are developed, a higher programming speed, high density, and high multi-function are required to the nonvolatile semiconductor memory devices.

A conventional nonvolatile semiconductor memory device, that is, a conventional EEPROM and a conventional flash memory will be compared with each other.

Since the memory cell of the EEPROM often includes of two transistors, that is, a memory transistor such as a MNOS and the like and a switch transistor, it is suitable for multi-function while it is not suitable for high density. In contrast, since the memory cell of the flash memory includes only one transistor, it is suitable for high density while it is not suitable for multi-function. Thus, it can be said that the EEPROM and the flash memory are separately used in a field in which they can be advantageously used from the structure thereof.

As to a programming speed, both the EEPROM and the flash memory conventionally require about milliseconds because both of them employ any of a tunnel programming method and a hot-carrier programming method. The programming speed is incommensurably long as compared with a processing time of about nanoseconds required by CPUs (central processing units).

Since a memory cell, which aims at the same direction as the gist of the present invention, has been proposed, the structure of a memory cell which corresponds to the structure of the above memory cell will be shown in FIGS. 3 to 5 and an operation bias of a memory cell array is shown in FIGS. 6 to 9, prior to the description of the memory cell which will be provided by the inventors. While the structure of the memory cell shown in FIGS. 3 to 5 was presented by Dr. Nissan-Cohen in the invited talk of "Semiconductor Interface Specialist Conference: SISC, San Diego", in December 1998, it is not recorded as a document at present. The overall structure of the memory cell was clarified to the attendants by Dr. Boaz Eitan in the invited talk of "International Conference on Solid State Devices and Materials: SSDM, Tokyo", in September 1999 and the memory cell is called a NROM.

To describe the principle and operation of the memory, the memory includes one transistor type nonvolatile semiconductor memory including a gate insulating film having discrete traps, program is locally performed to the discrete traps by so-called hot carrier injection at a drain edge and read is performed utilizing charge trapped by the program as the source side of a transistor. That is, program and read are carried out by reversing a direction in which a current flows to the memory transistor (reverse read) as shown in FIG. 3. More specifically, in the operation of the memory transistor, the function of a source line is interchanged with the function of a bit line between program and read. Further, since program is locally performed to the discrete traps as shown in FIG. 4, it is possible to provide another edge in the channel of the memory transistor with a memory function in the same way. That is, another information is stored by completely reversing the operating direction of the memory transistor, whereby a so-called two bits/one transistor type high density memory cell can be realized. At present, a silicon nitride film is utilized as a material of the gate insulating film having the discrete traps. As shown in FIG. 5, when a technology feature size is represented by F, a size of a cell including the memory transistors may be regarded as 2F.sup.2 per bit while the size is 4F.sup.2 per transistor. It can be said that a dramatically high density is realized thereby when it is compared with a conventional flash memory which is said to be suitable for high density while it has a size per bit of 6F.sup.2 to 10F.sup.2.

Further, FIGS. 6 to 9 show a memory cell array and the erase, program and read operation biases thereof.

As to the erase, FIG. 6 shows word-line page erase and FIG. 7 shows block-area chip erase. The erase is performed in such a manner that a high voltage of 8 V is applied to a bit line diffusion layer, thereby causing so-called band-to-band tunneling and injecting holes. While FIGS. 6 and 7 show that only one of the edges of a channel is erased, it is possible to simultaneously erase both the edges of the channel.

FIG. 8 shows programming. Carriers (electrons), which have been made hot in the channel, are injected in a gate direction at a drain edge and are captured by the discrete traps in a gate insulating film. At this time, since the electrons are injected only into a very small region, charge for detection is approximately one-hundredth that of a conventional flash memory having a conductive poly silicon floating gate in a gate insulation layer as a charge storing section, which leads to reduction of a programming time. Accordingly, even if hot carriers are injected, high speed programming can be realized. Further, the insulating film is less degraded by program by the reduced amount of the injected charge. Furthermore, even if the insulating film is degraded, the charge only leaks from the spatial discrete traps of the portion of the insulating film where the degradation occurs and an amount of stored charge is not influenced thereby. Therefore, it is difficult for data retention characteristics to be subjected to attenuation by programming, whereby the reliability of a nonvolatile memory can be more improved.

Next, FIG. 9 shows a read operation. While read is carried out by detecting an amount of a channel current which depends on whether program is performed or not, an amount of the channel current of a transistor is regulated at a source edge. After all, whether program is carried out or not can be most sensitively detected when read is performed utilizing a side to be detected as a source edge. Therefore, it is preferable to employ reverse read in which a current direction in read is reversed from that during program.

Note that when information of 2 bits is stored in a one transistor type nonvolatile semiconductor memory and the presence or absence of program at both the edges of a channel is detected by reversing the operating direction of the memory each other, there arises a problem in a read margin for identifying a signal for two bits. In read, it cannot be avoided that a current-detection method of determining "1" and "0" of the signal by a magnitude of a current is employed and that a signal detection margin is narrowed because information of one of the bits affects a detected current. A report on analysis of the margin is found in Martino Lorenzini et al., "A Dual Gate Flash EEPROM Cell with Two-Bit Storage Capacity", IEEE Transactions on Components, Packaging, and Manufacturing Technology Part A, vol. 20, p 182 189, (1997).

As to program, while the method of injecting charge into the discrete traps in the gate insulating film of a drain side by channel hot electrons was described in FIG. 8, a method of injecting charge to the discrete traps in the gate insulating film of a source side will be described below as another method. An example, in which carrier charge is programmed to the discrete traps in a silicon nitride film by source side injection (SSI), is found in Kuo-Tung Chang et al., "A New SONOS Memory Using Source-Side Injection for Programming", IEEE Electron Device Letters, vol 19, p 253 255 (1998). FIG. 10 shows a cross section of the device.

The structure of the device is such that a memory transistor is formed on the gate electrode side of a selection transistor by a side wall gate technology. Hot carriers, which have been generated by being accelerated by a drain voltage 5 V in the channel of the selection transistor, behave such that at the moment the hot carriers are injected into the channel of a memory transistor, the hot carriers sense a high electric field (12 V) toward the gate direction at the source side of the memory transistor, are injected in a direction of the gate electrode and are captured by the discrete traps in a gate insulating film. At this time, a gate potential of the selection transistor is set slightly higher (1 V) than a threshold voltage and a channel current is in the saturated region of a low current. The hot carriers generated from a low current are effectively captured by the discrete traps in the gate insulating film. When the source side injection is compared with drain side injection by channel hot electrons as to an amount of channel current necessary to program, an amount of the channel current necessary to program in the source side injection is about one-thirtieth that in the drain side injection whereby reliability can be improved by the reduction of a programming time and an increase in the number of programming so that a programming system by the source side injection is effective. While the selection transistor (switch transistor) must be assembled in a memory cell in the source side injection, a problem resides in that how an increase in cell area can be suppressed.

An example of a memory cell of high density, in which a selection transistor (switch transistor) is assembled in a memory cell, will be described in relation to the present invention. There will be described the 2-bit/cell type high density nonvolatile semiconductor memory device shown in FIG. 11 in in which it is possible for one cell to have information of two bits by a dual way operation and one cell has two memory transistors, one switch transistor, and two diffusion-layer lines. The structure of the memory cell (DSG cell) exemplified in FIG. 11 was made distinct by Yale Ma et al., "A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories", IEDM 94, pp 57 60, the proceeding of "International Electron Device Meeting (IEDM)", 1994.

The 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) shown in FIG. 11 is arranged such that two memory cell transistors having poly-silicon floating gate electrodes 2'-1 and 2'-2 and control gate electrodes 3-1 and 3-2 are formed on a silicon substrate 1, diffusion layers 4-1 and 4-2, which are connected to a source line/bit line, are formed externally of the memory transistors, and a switch transistor, which has a switch gate electrode 8 to be connected to a word line 5, is formed between the two memory transistors. The two memory transistors share the one switch transistor that is formed therebetween by self-aligned diffusion, whereby it is taken into consideration not to increase the area thereof. Since the 2-bit/cell has such a structure that contact holes for metal lines are not formed in a memory cell array, the 2-bit/cell realizes high density with a 1.5 transistor per bit arranged by the self-aligned diffusion.

When the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) carries out program and read to the 2-bit memory in the one cell of FIG. 11, a direction of a current flowing in a channel for one bit is reversed with respect to that for the other bit. Memory information of 2 bits is stored in the different memory transistors. That is, operations for storing 2 bits in one cell are carried out in opposite directions symmetrically. While program is carried out by a hot carrier programming method, a high electric field can be realized also in a gate direction in addition to a conventional channel direction by the action of the switch transistor, whereby high speed can be realized by program performed by so-called source-side injection.

Further, the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) performs erase by a method of drawing out electrons from floating gate electrodes 2'-1 and 2'-2 by a high electric field applied between the diffusion layers 4-1 and 4-2 for the bit line and the source line that run in parallel with the gate electrodes 3-1 and 3-2 of FIG. 11. As a result, in the memory cell shown in FIG. 11, all the memory cells are erased along the bit line. This state is apparent from FIG. 12 that shows a bias relationship between a selected cell and an unselected cell in the memory cell array. That is, all the memory transistors (A1, C1, B1, and D1) disposed along both the sides of one column of bit lines are simultaneously erased so that programming cannot be carried out in a bit unit or a byte unit and erase is carried out in block-area.

SUMMARY OF THE INVENTION

A dramatically high degree of density is proposed by the memory cell (NROM) shown in FIGS. 3 to 5. In the memory cell, while necessary charge for program is reduced to about one-hundredth conventional one because the discrete traps in an insulating film are utilized. However, since program is carried out by channel hot carrier injection, a necessary program current is about 30 times source side injection. Further, disturb is applied to an unselected cell as read is accumulated, whereby a signal margin is liable to be deteriorated. Furthermore, as can be understood from a bias relationship in a memory cell array shown in FIGS. 6 to 9, since a virtual ground system, in which operation is carried out by interchanging a source line and a bit line, is employed, there is a possibility that even a surface current which is transmitted on the surface of a semiconductor is detected in addition to a channel current detected through a predetermined channel particularly during read.

FIG. 10 shows a memory transistor employing source side injection in which discrete traps in a gate insulating film are utilized. While the figure shows up to that a one-way operation method is employed with a source/drain fixed, it is not clarified how an actual memory cell array is organized.

In the memory cell (DSG) shown in FIGS. 11 and 12, since the gate electrode of a memory transistor runs in parallel with a source line/bit line as described in Description of Prior Art, it is impossible to perform word-line erse. Further, the conductive floating gate electrodes 2'-1 and 2'-2 serving as store areas include electrodes which are arranged independently of other memory cells.

Furthermore, in the memory cell of FIG. 11, the gate electrode 3-1 and 3-2 of the memory transistor are lined so as to cover the floating gate electrodes 2'-1 and 2'-2. As a result, a word line 5 which is across on the gate electrodes and the floating gate electrodes 2'-1 and 2'-2 cannot be subjected to stacked film processing utilizing self-aligned diffusion. Thus, the word line 5 must be stacked on the floating gate electrodes 2'-1 and 2'-2 by means of process alignment, whereby an area is increased by an alignment accuracy. It is reported that when a technology feature size is represented by "F", a cell area per bit of the memory cell of FIG. 11 is 5.4F.sup.2 as a result of an increase in area due to the alignment accuracy. While the memory cell of FIG. 11 realizes high density, its area is increased by 35% as compared with a memory cell having an area of 4F.sup.2 because it requires no alignment in processing.

Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit having a nonvolatile memory which has less possibility of detecting a surface current other than a channel current detected through a predetermined channel.

Another object of the present invention present invention is to make it possible to carry out word-line erase in multi-storage nonvolatile memory cells.

Still another object of the present invention is to provide a semiconductor integrated circuit capable of realizing multi-storage nonvolatile memory cells while suppressing an increase in chip area.

The present invention intends to provide a semiconductor integrated circuit having a nonvolatile semiconductor memory of high density, high speed and high reliability.

These and other objects and novel features of the present invention will become more apparent from following description of the specification taken in conjunction with the accompanying drawings.

The embodiments of the present invention disclosed in this application mainly have the following features.

That is, since a gate insulating film having discrete traps is used, a multi-storage cell is organized such that one memory transistor can store information of at least two bits by local programming, whereby stored charge for detection can be dramatically reduced as compared with that of conductive floating gate electrodes.

Since program is performed utilizing at least source side injection, a programming efficiency is increased as compared with that of channel hot electron drain side injection, a channel current necessary to program is reduced, and the number of programmable bits is increased, whereby a chip program time is reduced and the programmable number of times is increased.

A switch transistor, which is necessary to realize the source side injection, is formed in a memory cell together with a memory transistor by self-aligned diffusion, thereby suppressing an increase in area. Further, the line of the switch transistor is devised to shut off the flow of a surface current, which is flown due to a virtual ground, to a source line/bit line.

At least word-line program is permitted by connecting the gate electrode of the memory transistor to a word line.

In a memory cell including the memory transistor and the switch transistor, there is employed a method of drawing out stored charge to the memory gate electrode side of the memory transistor, that is, to the word line side as a method of securing the data retention characteristics of stored charge which is programmed by the source side injection and allowing erase. For this purpose, as to thicknesses of silicon oxide films disposed above and below the gate insulating film having the discrete traps, that is, a silicon nitride film, a thickness of the lower (bottom) oxide film is made thicker than that of the upper (top) oxide film.

The structures of several types of memory cells according to the embodiments of the present invention will be exemplified here. A first memory cell structure is such that each of memory cells includes one memory transistor, two switch transistors and two diffusion-layer lines. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrodes of the two switch transistors are extended along the source line and the bit line.

A second memory cell structure is such that each of memory cells includes one memory transistor, two switch transistors and two transistor inversion-layer lines. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the two transistor inversion-layer lines constitute a source line and a bit line, and the two switch transistors and the two transistor inversion-layer lines constituting the source line and the bit line share the memory gate electrode, respectively.

A third memory cell structure is such that each of memory cells includes one memory transistor, one switch transistor, one transistor inversion-layer line and one diffusion-layer line. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the one transistor inversion-layer line constitutes a source line, the one diffusion-layer line constitutes a bit line, and the one switch transistor and the one transistor inversion-layer line constituting the source line share the transistor gate electrode, respectively.

A fourth memory cell structure is such that each of memory cells includes two memory transistors, one switch transistor and two diffusion-layer lines. Each of the memory transistors includes a gate insulating film having discrete traps and a transistor gate electrode connected to a word line, the two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrode of the one switch transistor is extended along the source line and the bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view exemplifying a nonvolatile memory cell including one memory cell transistor and two switch transistors which is a basic arrangement of a nonvolatile memory cell employed by a semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 2 is a sectional view exemplifying a nonvolatile memory cell including two memory cell transistors and one switch transistor which is a basic arrangement of a nonvolatile memory cell employed by a semiconductor integrated circuit according to an embodiment of the present invention;

FIG. 3 is a view explaining a first program and read method of an NROM memory cell previously examined by the inventors;

FIG. 4 is a view explaining a second program and read method of the NROM memory cell previously examined by the inventors;

FIG. 5 is a plan view showing a layout of the NROM memory cell;

FIG. 6 is a view explaining a page erase operation of the NROM;

FIG. 7 is a view explaining a chip erase operation of the NROM;

FIG. 8 is a view explaining a program operation of the NROM;

FIG. 9 is a view explaining a read operation of the NROM;

FIG. 10 is a view explaining another cell previously examined by the inventors;

FIG. 11 is a view explaining sill another cell previously examined by the inventors;

FIG. 12 is a view explaining a relationship between a selected bias and a non-selected bias with respect to a memory cell;

FIG. 13 is a block diagram showing an example of a nonvolatile semiconductor memory device;

FIG. 14 is a sectional view showing a nonvolatile memory cell of a first embodiment according to the present invention with an attention paid to the first program and read method;

FIG. 15 is a sectional view showing the nonvolatile memory cell of a first embodiment according to the present invention with an attention paid to the second program and read method;

FIG. 16 shows a layout pattern of the memory cell of FIGS. 14 and 15;

FIG. 17 is a circuit diagram showing bias conditions of a first page erase operation of the memory cells of the first embodiment;

FIG. 18 is a circuit diagram showing bias conditions of a first chip erase operation of the memory cells of the first embodiment;

FIG. 19 is a circuit diagram showing bias conditions of a first program operation of the memory cells of the first embodiment;

FIG. 20 is a circuit diagram showing bias conditions of a first read operation of the memory cells of the first embodiment;

FIG. 21 is a circuit diagram showing bias conditions of a second page erase operation of the memory cells of the first embodiment;

FIG. 22 is a circuit diagram showing bias conditions of a second chip erase operation of the memory cells of the first embodiment;

FIG. 23 is a circuit diagram showing bias conditions of a second program operation of the memory cells of the first embodiment;

FIG. 24 is a circuit diagram showing bias conditions of a second read operation of the memory cells of the first embodiment;

FIG. 25 is a block diagram showing an example of a memory cell array and a peripheral circuit;

FIG. 26 is a typical flowchart of a memory operation;

FIG. 27 shows a layout pattern showing a first arrangement example (A) of the memory cell array including the memory cells of the first embodiment;

FIG. 28 is a circuit diagram showing the first arrangement example (A) of the memory cell array including the memory cells of the first embodiment;

FIG. 29 shows a layout pattern showing a second arrangement example (B) of the memory cell array including the memory cells of the first embodiment;

FIG. 30 shows a circuit showing the second arrangement example (B) of the memory cell array including the memory cells of the first embodiment;

FIG. 31 shows a layout pattern showing a third arrangement example (C) of the memory cell array including the memory cells of the first embodiment;

FIG. 32 shows a circuit showing the third arrangement example (C) of the memory cell array including the memory cells of the first embodiment;

FIG. 33 shows a layout pattern showing a fourth arrangement example (D) of the memory cell array including the memory cells of the first embodiment;

FIG. 34 shows a circuit showing the fourth arrangement example (D) of the memory cell array including the memory cells of the first embodiment;

FIGS. 35 to 40 are sectional views of a device at respective stages in a manufacturing process of memory cells of the first embodiment;

FIG. 41 is a sectional view showing a nonvolatile memory cell of a second embodiment according to the present invention with an attention paid to the first program and read method;

FIG. 42 is a sectional view showing the nonvolatile memory cell of the second embodiment according to the present invention with an attention paid to the second program and read method;

FIG. 43 shows a layout pattern of the nonvolatile memory cell of the second embodiment;

FIG. 44 shows a layout pattern of a memory cell array using the nonvolatile memory cells of the second embodiment;

FIGS. 45 to 50 are sectional views of a device at respective stages in a manufacturing process of memory cells of the second embodiment;

FIG. 51 is a sectional view of another device at a stage similar to that shown in FIG. 49 in the manufacturing process of the memory cell of the second embodiment;

FIG. 52 is a sectional view showing a nonvolatile memory cell of a third embodiment according to the present invention;

FIG. 53 shows a layout pattern showing a nonvolatile memory cell of the third embodiment according to the present invention;

FIG. 54 is a circuit diagram showing bias conditions of a page erase operation of the memory cells of the third embodiment;

FIG. 55 is a circuit diagram showing bias conditions of a chip erase operation of the memory cells of the third embodiment;

FIG. 56 is a circuit diagram showing bias conditions of a program operation of the memory cells of the third embodiment;

FIG. 57 is a circuit diagram showing bias conditions of a read operation of the memory cells of the third embodiment;

FIG. 58 shows a layout pattern showing a first arrangement example (A) of a memory cell array including memory cells of the third embodiment;

FIG. 59 is a circuit diagram showing the first arrangement example (A) of a memory cell array including memory cells of the third embodiment;

FIG. 60 shows a layout pattern showing a second arrangement example (B) of a memory cell array including memory cells of the third embodiment;

FIG. 61 a circuit diagram showing the second arrangement example (B) of a memory cell array including memory cells of the third embodiment;

FIG. 62 shows a layout pattern showing a third arrangement example (C) of a memory cell array including memory cells of the third embodiment;

FIG. 63 is a circuit diagram showing the third arrangement example (C) of the memory cell array including the memory cells of the third embodiment;

FIG. 64 shows a layout pattern showing a fourth arrangement example (D) of a memory cell array including memory cells of the third embodiment;

FIG. 65 is a circuit diagram showing the fourth arrangement example (D) of the memory cell array including the memory cells of the third embodiment;

FIGS. 66 to 69 are sectional views of a device at respective stages in a manufacturing process of the memory cells of the third embodiment;

FIG. 70 is a sectional view of another device at a stage similar to that shown in FIG. 69 in the manufacturing process of the memory cell of the third embodiment;

FIG. 71 is a sectional view showing a nonvolatile memory cell of a fourth embodiment according to the present invention;

FIG. 72 shows a layout pattern showing a nonvolatile memory cell of a fourth embodiment according to the present invention;

FIG. 73 is a circuit diagram showing bias conditions of a page erase operation of the memory cells of the fourth embodiment;

FIG. 74 is a circuit diagram showing bias conditions of a chip erase operation of the memory cells of the fourth embodiment;

FIG. 75 is a circuit diagram showing bias conditions of a SSI (source side injection) program operation of the memory cells of the fourth embodiment;

FIG. 76 is a circuit diagram showing bias conditions of a SSI read operation of the memory cells of the fourth embodiment;

FIG. 77 is a circuit diagram showing bias conditions of a DSI (drain side injection) program operation of the memory cells of the fourth embodiment;

FIG. 78 is a circuit diagram showing bias conditions of a DSI read operation of the memory cells of the fourth embodiment;

FIG. 79 shows a layout pattern showing a first arrangement example (A) of a memory cell array including the memory cells of the fourth embodiment;

FIG. 80 is a circuit diagram showing the first arrangement example (A) of the memory cell array including the memory cells of the fourth embodiment;

FIG. 81 shows a layout pattern showing a second arrangement example (B) of a memory cell array including the memory cells of the fourth embodiment;

FIG. 82 a circuit showing the second arrangement example (B) of the memory cell array including the memory cells of the fourth embodiment;

FIG. 83 shows a layout pattern showing a third arrangement example (C) of a memory cell array including the memory cells of the fourth embodiment;

FIG. 84 is a circuit diagram showing the third arrangement example (C) of the memory cell array including the memory cells of the fourth embodiment;

FIG. 85 shows a layout pattern showing a fourth arrangement example (D) of a memory cell array including the memory cells of the fourth embodiment;

FIG. 86 is a circuit diagram showing the fourth arrangement example (D) of the memory cell array including the memory cells of the fourth embodiment;

FIGS. 87 to 91 are sectional views of a device at respective stages in a manufacturing process of memory cells of the fourth embodiment;

FIGS. 92 to 94 are sectional views of a device at respective stages in a manufacturing process of memory cells according to a fifth arrangement of the present invention;

FIG. 95 is a perspective view of a memory cell according to a sixth embodiment of the present invention;

FIG. 96 is a cross sectional view of the memory cell of the sixth embodiment;

FIG. 97 shows a layout pattern of the memory cell of the sixth embodiment;

FIG. 98 is a circuit diagram showing voltage bias conditions of a memory operation of the memory cells of the sixth embodiment;

FIG. 99 shows a layout pattern showing a first arrangement example (A & B) of a memory cell array including memory cells of the sixth embodiment;

FIG. 100 shows a circuit diagram showing the first arrangement example (A & B) of the memory cell array including the memory cells of the sixth embodiment;

FIG. 101 shows a layout pattern showing a second arrangement example (C & D) of a memory cell array including the memory cells of the sixth embodiment;

FIG. 102 shows a circuit diagram showing the second arrangement example (C & D) of the memory cell array including the memory cells of the sixth embodiment;

FIGS. 103 to 108 are sectional views of a device at respective stages in a manufacturing process of memory cells of the sixth embodiment;

FIG. 109 is a cross-sectional view of a memory cell of a seventh embodiment according to the present invention;

FIGS. 110 to 114 are cross sectional views showing a device at respective stages in a manufacturing process of memory cells of a seventh embodiment;

FIG. 115 is a characteristic view showing a relationship between a read memory current and a memory gate voltage of the NROM shown in FIGS. 3 and 4;

FIG. 116 is a characteristic view showing a relationship between a read memory current and a memory gate voltage of the memory cells of the first, second and third embodiments;

FIG. 117 is a characteristic view showing a relationship between a read memory current and a memory gate voltage of the memory cells of the fourth and fifth embodiments;

FIG. 118 is a characteristic view showing a relationship between a read memory current and a memory gate voltage of the memory cells of the sixth and seventh embodiments;

FIG. 119 is a first timing chart of erase, program and read operations of the memory cells of the first, second and third embodiments;

FIG. 120 is a second timing chart of the erase, program and read operations of the memory cells of the first, second and third embodiments;

FIG. 121 is a first timing chart of erase, SSI and DSI program and read operations to the memory cells of the fourth and fifth embodiments;

FIG. 122 is a second timing chart of the erase, SSI and DSI program and read operations of the memory cells of the fourth and fifth embodiments;

FIG. 123 is a first timing chart of erase, SSI program and read operations of the memory cells of the fourth and fifth embodiments; and

FIG. 124 is a second timing chart of the erase, SSI program and read operations of the memory cells of the fourth and fifth embodiments.

DESCRIPTION OF THE EMBODIMENTS

A basic arrangement of a nonvolatile memory cell employed by a semiconductor integrated circuit according to the present invention is exemplified in FIG. 1, wherein the nonvolatile memory cell includes a memory transistor Trmc and selection transistors (switch transistors) Trsw disposed on both the side of the memory transistor Trmc. The memory transistor Trmc includes a gate insulating film 2 having discrete traps and a memory gate electrode (also referred to as a control gate electrode) 7, whereas the selection transistors Trsw include switch gate electrodes 6-1 and 6-2. The memory cell performs local program to the gate insulating film 2 having the discrete traps, which serves as a store area for storing charge, and is arranged as a multi-storage cell in which one memory cell stores information of at least 2 bits. The memory cell includes the switch transistors Trsw having the switch gate electrodes 6-1 and 6-2 for realizing source side injection, and the memory transistor Trmc is formed together with the selection transistors Trsw by self-aligned diffusion. The memory gate electrode of the memory transistor Trmc is connected to a word line 5.

FIG. 2 shows another basic arrangement of a nonvolatile memory cell employed by the semiconductor integrated circuit. The memory cell having the structure exemplified in FIG. 2 is arranged such that a selection transistor (switch transistor) Trsw having a switch gate 6 is formed on a substrate 1, memory transistors Trmc including gate insulating films 2-1 and 2-2 each having discrete traps and memory gate electrodes 7-1 and 7-2 are disposed on both the sides of the switch transistor Trsw, and diffusion layers 4-1 and 4-2, which are connected to a source line/bit line, are formed externally of the memory transistors Trmc. In the above structure, it is possible to perform word line program by connecting at least the memory gate electrodes 7-1 and 7-2 of the memory transistor Trmc to a word line 5.

The above-mentioned structures are the basic arrangement of the present invention and examples will be described below as embodiments of the present invention. It should be noted that the nonvolatile semiconductor memories provided by the present invention are conveniently referred to as an SEEPROM ("super" EEPROM) and a plurality of examples of the basic model, improved model, expanded model and modified model thereof will be identified by applying numbers and additional characters thereto in the embodiments of the present invention.

<Nonvolatile Semiconductor Memory Device>

A block arrangement of a nonvolatile semiconductor memory device will be described with reference to FIG. 13. The nonvolatile semiconductor memory device includes a memory cell array 51 in which memory cells are disposed in matrix. The memory cells disposed in the memory cell array 51 are arranged, for example, such that each column of source electrodes and drain electrodes is connected to a data line, each column of switch gate electrodes is disposed to a switch gate control line, and each row of memory gate electrodes is connected to a word line. The data lines of the memory cell array 51 are connected to a data load latch circuit 52 on one hand and to a Y-gate sense amplifier 53 on the other hand. The Y-gate sense amplifier 53 is arranged such that a Y address (column address) received by an address buffer 57 is decoded by a Y decoder 56 and the data line of the Y-gate sense amplifier 53 is selected in response to a selection signal formed by the decoded Y address, whereby data can be input and output between a selected data line and an input/output buffer circuit 54. Further, the word lines and the switch gate control lines are connected to a word/switch decoder 55. The word/switch decoder 55 decodes an address supplied from an address buffer 57 and creates a word line and switch control line selection signal. Further, a mode controller 58 controls a chip selection mode, read mode, program mode, and erase mode in accordance with an external command or a state of a strobe signal. At this time, in the program or erase mode, a high voltage, which is necessary for a program for programming and erasing, is generated from a power supply 59 through a high voltage generator 60. A high voltage, which is necessary to a data load timing controller 62 and an erase controller 63, is applied thereto through a data-protection circuit 61 so that data is not broken by a high voltage which may be generated by an accidental signal such as noise and the like. The erase controller 63 starts an erase operation in response to an instruction for selecting erase issued by the mode controller 58. Program data is latched by the data load latch circuit 52 from the input/output buffer circuit 54 and supplied from the data latch circuit 52 to the memory cell array 51 in synchronism with a timing of program controlled by the data load timing controller 62. The data load timing controller 62 interchanges a bit line and a source line in response to an internal timing. A time necessary to the program for the programming and erasing is incommensurably larger than the clock frequency of a microcomputer (also referred to as a micon). In such as case, the micon is isolated from a bus in the nonvolatile semiconductor memory device, and the completion of the program and erase operation, which is carried out by the control in the interior of a nonvolatile semiconductor memory, is applied to the outside by a program/erase detector 64 so that a control operation other than the control operation to the nonvolatile semiconductor memory can be permitted to the micon. In short, a ready/busy signal can be output to the outside. It is sufficient for the micon to perform access when the nonvolatile semiconductor memory is in a ready state in response to the ready/busy signal.

<First Embodiment of Memory Cell>

A memory cell structure, in which switch transistors Trsw are disposed on both the sides of a memory transistor Memory transistor Trmc, is employed as a first embodiment of a multi-storage nonvolatile memory cell in order to solve the problems of an increase in programming speed in program, read disturb during read, and an expansion of a dual-way signal read margin. While a certain amount of reduction of a degree of density cannot help being sacrificed by the provision of the switch transistors Trsw on both the sides of the memory transistor Trmc, FIGS. 14 to 16 exemplify a structure in which a reduction of the degree of density is suppressed utilizing self-aligning diffusion. It should be understood that the term "transistor" used in the specification is an expression conveniently used to make it easy to understand the structure of the multi-storage nonvolatile memory cell according to the present invention and does not mean a perfect transistor, and it is only an expression with an attention paid to a gate structure.

The memory cell shown in FIGS. 14 to 16 includes a memory transistor Trmc that is formed on a substrate 1 and includes a gate insulating film 2 having discrete traps and a memory gate electrode 7. The gate insulating film 2 having the discrete traps may include, for example, a silicon nitride film. Switch transistors Trsw, Trsw, which include switch gate electrodes 6-1 and 6-2, are formed on both the sides of the memory transistor Trmc, and diffusion layers 4-1 and 4-2, which are connected to a source line/bit line, are formed externally of the switch transistors Trsw. That is, the memory cell is arranged such that the memory transistor Trmc is buried between the switch transistors Trsw, Trsw on both the sides thereof, and the diffusion layers 4-1 and 4-2, which constitute bit line/source line are formed externally thereof. In the memory cell structure, the memory cell shares the bit line/source line with a neighboring memory cell. From the above structure, while one memory cell has an area of 8F.sup.2, an area for 1 bit thereof can be regarded as 4F.sup.2 because information of 2 bits is stored in the memory cell. Since an area of the smallest memory structure of conventional EEPROMs and flash memories is about 6F.sup.2, the size of the memory cell exemplified in FIGS. 14 to 16 is reduced as compared with the smallest memory structure.

To describe a program operation, a programming speed is greatly increased to the order of microseconds (.mu.sec) by the employment of a so-called source side injection. A reason why the speed is increased resides in that, for program, carriers are accelerated when they pass through the narrowed channel of the initial one of the switch transistors Trsw and the energy thereof is increased. Subsequently, the carriers injected into the channel of the memory transistor Trmc further sense a high bias applied to the memory transistor Trmc in a direction of the memory gate electrode and rapidly are injected into the gate insulating film 2 having the discrete traps and are captured by the discrete traps. It is contemplated that the source side injection is carried out in a very narrow region in a channel direction. However, when flied charge is captured by discrete traps and fixed at the positions of the traps, a position where the source side injection is carried out is changed steadily by the self-induced potential of the captured charge, and finally the charge is stored in the source region of the memory transistor while distributing in a certain degree of area. Further, an important point resulting from the great increase in programming speed resides not only in an advantage in application but also in that degradation during program due to hot carrier program is suppressed in proportion to the time of the program.

For reading, the switch transistors Trsw, Trsw of a half-select memory cell carry out an action for avoiding read disturb by eliminating an influence of read voltage. Further, it is possible to expand a signal detection margin by increasing a voltage of the switch gate electrode of the switch transistor Trsw on a read side. Note that while a direction of the channel current in the memory transistor is reversed each other in program and read in the one transistor type nonvolatile semiconductor memory shown in FIGS. 3 to 5, a direction of the channel current is unchanged also during read in the memory structure provided in FIGS. 14 to 16 because program is carried out on the source side.

FIGS. 17 to 20 show a first example of an operation bias when a cell array is made of memory cells provided by the present invention of FIGS. 14 to 16, and FIGS. 21 to 24 show a second embodiment of the operation bias. In any of the operation biases, the memory gate electrode 7 of the memory transistor Trmc is connected to word lines 5Li and 5Lj which are shown typically is Bit line/source lines 4Li, 4Lj and 4lk, which are typically shown, are disposed so as to intersect the word lines 5Li and 5Lj. Further, switch control lines 6Li to 6L1, which are typically shown and connected to the switch gate electrodes 6-1, 6-2 of the switch transistors Trsw on both the sides of the memory transistor Trmc, also intersect the word lines 5Li and 5Lj.

FIG. 17 shows a bias relationship in page mode erase. A relatively large bias of 9 V is applied to only the selected word line 5Lj and a 0 V is applied to all the other word lines. In the erase of a selected memory transistor, trapped electrons are drawn out to a memory gate electrode side by a large positive bias supplied from a memory gate side. The operation in FIG. 18 is carried out by imposing a positive bias of 9 V on all the word lines 5Li and 5Lj. That is, erase can be carried out in two types of erase, that is, in word-line erase (page erase) and in all the chips erase. FIG. 17 shows the word-line erase and FIG. 18 shows the chip erase.

FIG. 19 shows a program operation. A switch gate voltage on the source side of a memory cell to be selected is set to 1.5 V through the switching control line 6Li, a switch gate voltage on the source side thereof is set to 3 V through the control line 6Lj, and a voltage of the memory gate electrode of the memory transistor Trmc is set to 6 V through the word line 5Lj, whereby the program is carried out.

FIG. 20 shows a read operation. A 3 V is applied to the memory gate electrode of a memory cell to be selected through the word line 5Lj, a 3 V also is applied to the switch gate electrodes of the switch transistors on both the sides through the control lines 6Li and 6Lj, and a 1.5 V is applied to the bit line/source line 4Lj connected to the drain electrode thereof, whereby the read is carried out. Otherwise, in the read, the read margin of the 2 bit/cell can be expanded by applying 3 V as a gate voltage of the switch transistor to the source electrode side through the control line 6Li and by applying 4.5 V to the gate electrode of the switch transistor on the drain side through the control line 6Lj.

In the method shown in FIG. 21 to FIG. 24, the switch gate electrodes of the switch transistors Trsw of neighboring memory cells are short circuited. Erase, program and read operations are possible as shown in FIGS. 21 to 24. A definitive advantage of this method resides in that when the switch transistor has a side wall gate structure which is formed to have a size smaller than a minimum light-processing figure size, the switch transistor can be easily connected to a peripheral circuit, while this will be described later with reference to FIG. 44. In the read of FIG. 24, a gate voltage of the switch transistor on th