Semiconductor link processing using multiple laterally spaced laser beam spots with on-axis offset Number:7,435,927 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor link processing using multiple laterally spaced laser beam spots with on-axis offset

Abstract: Multiple laser beams selectively irradiate electrically conductive structures on or within a semiconductor substrate. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. One method propagates first and second laser beams along respective first and second propagation paths having respective first and second axes incident at respective first and second locations on or within the semiconductor substrate at a given time. The first and second locations are either on a structure in their respective rows or between two adjacent structures in their respective rows, which are distinct. The second location is offset from the first location by some amount in the lengthwise direction of the rows. The method moves the laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the rows with the laser beams.

Patent Number: 7,435,927 Issued on 10/14/2008 to Bruland,   et al.

---

Inventors:	Bruland; Kelly J. (Portland, OR), Baird; Brian W. (Oregon City, OR), Lo; Ho Wai (Portland, OR), Swaringen; Stephen N. (Rockwall, TX)
Assignee:	Electron Scientific Industries, Inc. (Portland, OR)
Appl. No.:	11/051,265
Filed:	February 4, 2005

---

Related U.S. Patent Documents

---

	Application Number	Filing Date	Patent Number	Issue Date
	60580917	Jun., 2004

---

Current U.S. Class:	219/121.69 ; 219/121.68; 219/121.76; 219/121.77
Current International Class:	B23K 26/38 (20060101); B23K 26/067 (20060101)
Field of Search:	219/121.76,121.77,121.68,121.69,121.78,121.79,121.8 359/202,203,204,223,225

---

References Cited [Referenced By]

---

U.S. Patent Documents

4083629	April 1978	Kocher et al.
4311360	January 1982	Hodson et al.
4532402	July 1985	Overbeck
4564739	January 1986	Mattelin
4701591	October 1987	Masaki et al.
4727381	February 1988	Bille et al.
4982166	January 1991	Morrow
5295014	March 1994	Toda
5300756	April 1994	Cordingley
5430816	July 1995	Furuya et al.
5473409	December 1995	Takeda et al.
5481407	January 1996	Smith et al.
5629790	May 1997	Neukermans et al.
5751585	May 1998	Cutler et al.
5837962	November 1998	Overbeck
5847960	December 1998	Cutler et al.
5933218	August 1999	Matsubara et al.
5998759	December 1999	Smart
6313433	November 2001	Sukman et al.
6324195	November 2001	Suzuki et al.
6368945	April 2002	Im
6385228	May 2002	Dane et al.
6407363	June 2002	Dunsky et al.
6416190	July 2002	Grier et al.
6423925	July 2002	Sukhman et al.
6433301	August 2002	Dunsky et al.
6462306	October 2002	Kitai et al.
6479788	November 2002	Arai et al.
6521866	February 2003	Arai et al.
6541731	April 2003	Mead et al.
6563082	May 2003	Terada et al.
6567219	May 2003	Tanaka
6574250	June 2003	Sun et al.
6580055	June 2003	Iso
6593542	July 2003	Baird et al.
6816294	November 2004	Unrath et al.
6841482	January 2005	Boyle
6849824	February 2005	Arai et al.
6875951	April 2005	Sakamoto et al.
6884668	April 2005	Yamazaki et al.
6902990	June 2005	Gottfried et al.
6951995	October 2005	Couch et al.
6972268	December 2005	Ehrmann et al.
6984802	January 2006	Kuroiwa et al.
2002/0000426	January 2002	Mead et al.
2002/0040893	April 2002	Arai et al.
2002/0050488	May 2002	Nikitin et al.
2002/0060210	May 2002	Terada et al.
2002/0117481	August 2002	Unrath et al.
2002/0162973	November 2002	Cordingley et al.
2002/0167581	November 2002	Cordingley et al.
2002/0170898	November 2002	Ehrmann et al.
2004/0173590	September 2004	Hata et al.
2005/0168715	August 2005	Kemper et al.
2005/0279736	December 2005	Bruland et al.
2005/0279739	December 2005	Bruland et al.
2005/0281102	December 2005	Bruland
2005/0282319	December 2005	Bruland et al.
2005/0282367	December 2005	Bruland et al.
2005/0282406	December 2005	Bruland et al.
2005/0282407	December 2005	Bruland et al.
2006/0205121	September 2006	Couch et al.
2007/0215820	September 2007	Cordingley et al.

Foreign Patent Documents

	10234943		Feb., 2004		DE
	2 331 038		May., 1999		GB
	55-081095		Jun., 1980		JP
	56-143434		Nov., 1981		JP
	62-086839		Apr., 1987		JP
	63-5891		Jan., 1988		JP
	63-136545		Jun., 1988		JP
	63-264286		Nov., 1988		JP
	63-302503		Dec., 1988		JP
	64-044295		Feb., 1989		JP
	01-289586		Nov., 1989		JP
	1-289586		Nov., 1989		JP
	02-063103		Mar., 1990		JP
	2-089586		Mar., 1990		JP
	02-089586		Mar., 1990		JP
	2-89586		Mar., 1990		JP
	2-137682		May., 1990		JP
	02-137682		May., 1990		JP
	3-297588		Dec., 1991		JP
	3-297588		Dec., 1991		JP
	04-098801		Mar., 1992		JP
	10-328873		Dec., 1998		JP
	11-19786		Jan., 1999		JP
	11-104863		Apr., 1999		JP
	11-104871		Apr., 1999		JP
	11-149317		Jun., 1999		JP
	11-245060		Sep., 1999		JP
	11-245073		Sep., 1999		JP
	2000-190087		Jul., 2000		JP
	2001-021931		Jan., 2001		JP
	2001-121279		May., 2001		JP
	2001-170788		Jun., 2001		JP
	2001-269790		Oct., 2001		JP
	2002-011588		Jan., 2002		JP
	2002-361464		Dec., 2002		JP
	2003-053561		Feb., 2003		JP
	2003-053575		Feb., 2003		JP
	2003-053576		Feb., 2003		JP
	2003-334684		Nov., 2003		JP
	2004-306101		Nov., 2004		JP
	2005-177788		Jul., 2005		JP
	WO2004/015747		Feb., 2004		WO

Other References

International Search Report, PCT/US05/21406, completed Aug. 7, 2006; mailed Oct. 12, 2006. cited by other . Kastelik et al., "High Dynamic Range, Bifrequency TeO2 Acousto-Optic Modulator," 7 Pure Appl. Opt. (1998), pp. 467-474. cited by other . Restriction Requirement, U.S. Appl. No. 11/051,262, Jul. 17, 2006. cited by other . Second Office Action, U.S. Appl. No. 11/051,262, Nov. 2, 2006. cited by other . First Office Action, U.S. Appl. No. 11/051,263, Oct. 17, 2006. cited by other . Second Office Action, U.S. Appl. No. 11/051,263, Apr. 25, 2007. cited by other . First Office Action, U.S. Appl. No. 11/051,958, Apr. 4, 2007. cited by other . Restriction Requirement, U.S. Appl. No. 11/051,261, Apr. 5, 2007. cited by other . Second Office Action, U.S. Appl. No. 11/051,261, Jul. 12, 2007. cited by other . PTO Filing, U.S. Appl. No. 10/107,890, Dec. 15, 2006. cited by other . PTO Filing, U.S. Appl. No. 10/107,890, Mar. 2, 2007. cited by other . PTO Filing, U.S. Appl. No. 10/107,890, Jun. 27, 2007. cited by other . PTO Filing, U.S. Appl. No. 11/247,541, Dec. 21, 2006. cited by other . PTO Filing U.S. Appl. No. 11/247,541, May 18, 2007. cited by other . Office Action, U.S. Appl. No. 11/247,541, Sep. 11, 2007. cited by other . Office action in U.S. Appl. No. 10/107,890, mailed Sep. 27, 2007. cited by other . Office action in U.S. Appl. No. 11/051,263, mailed Oct. 18, 2007. cited by other . Office action in U.S. Appl. No. 11/051,500, mailed Nov. 29, 2007. cited by other . Office action in U.S. Appl. No. 10/818,920, mailed Dec. 6, 2007. cited by other . Response to Office action and Terminal Disclaimer in U.S. Appl. No. 11/051,261, Jan. 11, 2008. cited by other . Office action in U.S. Appl. No. 10/107,890, Jan. 11, 2008. cited by other . Response to Office action in U.S. Appl. No. 11/051,262, Jan. 17, 2008. cited by other . Appeal Brief in U.S. Appl. No. 10/818,920, Feb. 29, 2008. cited by other . Response to Office action in U.S. Appl. No. 11/247,541, Mar. 5, 2008. cited by other . Office action in U.S. Appl. No. 11/051,262, May 27, 2008. cited by other . Office action in U.S. Appl. No. 11/051,261, May 28, 2008. cited by other . Office action in U.S. Appl. No. 11/052,000, Jun. 4, 2008. cited by other . Response to Office action in U.S. Appl. No. 11/051,262, May 9, 2008. cited by other . Third Office action in U.S. Appl. No. 11/051,261, May 1, 2008. cited by other . Response to Office action in U.S. Appl. No. 11/051,261, May 9, 2008. cited by other . Response to Office action and Terminal Disclaimer in U.S. Appl. No. 11/051,263, Apr. 16, 2008. cited by other . Office action in U.S. Appl. No. 11/051,262, Apr. 18, 2008. cited by other . Office action in U.S. Appl. No. 11/051,500, Jun. 16, 2008. cited by other . Office action in U.S. Appl. No. 11/247,541, Jun. 12, 2008. cited by other . Response to office action (Jun. 27, 2008) in U.S. Appl. No. 10/107,890. cited by other.

Primary Examiner: Evans; Geoffrey S
Attorney, Agent or Firm: Stoel Rives LLP

---

Parent Case Text

---

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. .sctn. 119 to U.S. Provisional Application No. 60/580,917, entitled "Multiple-Beam Semiconductor link Processing," filed Jun. 18, 2004, which is incorporated by reference herein in its entirety. Also incorporated by reference herein are the following commonly owned U.S. patent applications filed contemporaneously with this application: application Ser. No. 11/051,262, entitled "Semiconductor Structure Processing Using Multiple Laterally Spaced Laser Beam Spots Delivering Multiple Blows"; application Ser. No. 11/052,014, entitled "Semiconductor Structure Processing Using Multiple Laterally Spaced Laser Beam Spots with Joint Velocity Profiling"; application Ser. No. 11/051,500, entitled "Semiconductor Structure Processing Using Multiple Laser Beam Spots Spaced On-Axis Delivered Simultaneously"; application Ser. No. 11/052,000, entitled "Semiconductor Structure Processing Using Multiple Laser Beam Spots Spaced On-Axis to Increase Single-Blow Throughput"; application Ser. No. 11/051,263, entitled "Semiconductor Structure Processing Using Multiple Laser Beam Spots Spaced On-Axis on Non-Adjacent Structures"; and application Ser. No 11/051,958, entitled "Semiconductor Structure Processing Using Multiple Laser Beam Spots Spaced On-Axis with Cross-Axis Offset"; and application Ser. No. 11/051,261, entitled "Semiconductor Structure Processing Using Multiple Laser Beam Spots Overlapping Lengthwise on a Structure."

---

Claims

---

The invention claimed is:

1. A method for selectively irradiating structures on or within a semiconductor substrate using multiple laser beams, the structures being arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction, the method comprising: propagating a first laser beam along a first propagation path having a first axis incident at a first location on or within the semiconductor substrate at a given time, the first location being either on a structure in a first row of structures or between two adjacent structures in the first row; propagating a second laser beam along a second propagation path having a second axis incident at a second location on or within the semiconductor substrate at the given time, the second location being either on a structure in a second row of structures or between two adjacent structures in the second row, the second row being distinct from the first row, wherein the second location is offset from the first location by some amount in the lengthwise direction of the rows; and moving the first and second laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the first and second rows with the first and second laser beams respectively.

2. The method of claim 1, wherein structures in the first row are offset from structures in the second row in the lengthwise direction of the rows.

3. The method of claim 1, wherein structures in the first row are aligned with structures in the second row in the lengthwise direction of the rows, but the first location and the second location correspond to structures, in the respective first and second rows, that are offset from one another in the lengthwise direction of the rows.

4. The method of claim 1, wherein the first and second laser beams have respective first and second sets of optical properties, and wherein the first and second sets are different from one another.

5. The method of claim 1, further comprising: generating the first and second laser beams.

6. The method of claim 5, wherein the generating step comprises: generating the first and second laser beams from two respective lasers.

7. The method of claim 5, wherein the generating step comprises: generating a single laser beam from a single laser; and splitting the single laser beam to form the first and second laser beams.

8. The method of claim 5, wherein the generating step is commenced based upon a trigger signal.

9. The method of claim 8, wherein the trigger signal is generated based upon a timing signal.

10. The method of claim 8, wherein the trigger signal is generated based upon a comparison of one or more desired target locations and one or more of the first and second locations.

11. The method of claim 5, further comprising: selectively blocking the first laser beam from reaching the first location; and selectively blocking the second laser beam from reaching the second location.

12. The method of claim 5, wherein the first and second laser beams reach the workpiece at a substantially simultaneous time.

13. The method of claim 5, wherein the first and second laser beams reach the workpiece at different times.

14. The method of claim 1, wherein the first laser beam irradiates for a first time selected structures in the first row, and the second laser beam irradiates for a second time structures in the second row previously irradiated with the first laser beam.

15. The method of claim 1, further comprising: during the moving step, dynamically adjusting the relative spacing between the incident locations of the first and second laser beam axes on the semiconductor substrate.

16. The method of claim 15, wherein the adjustment of the relative spacing is in a direction substantially perpendicular to the lengthwise direction of the rows.

17. The method of claim 1, wherein the moving step comprises: moving the laser beam axes.

18. The method of claim 1, wherein the moving step comprises: moving the semiconductor substrate.

19. The method of claim 1, wherein the structures comprise electrically conductive links and the irradiation of a link results in severing that link.

20. The method of claim 1, wherein the structures comprise potential electrically conductive links and the irradiation of a link results in making an electrical connection in that link.

21. The method of claim 1, wherein the semiconductor substrate comprises multiple dies, and the first laser beam axis is incident upon one die on the semiconductor substrate and the second laser beam axis is incident upon a separate die on the semiconductor substrate.

22. The method of claim 1, wherein the first and second laser beams are pulsed laser beams.

23. The method of claim 1, wherein the first and second rows are adjacent.

24. The method of claim 23, wherein the first and second locations are separated by a sufficient distance to avoid a deleterious concentration of energy absorbed by the semiconductor substrate in the vicinity of the first and second locations.

25. A system for selectively irradiating structures on or within a semiconductor substrate using multiple laser beams, the structures being arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction, the system comprising: a means for propagating a first laser beam along a first laser beam propagation path having a first axis incident at a first location on or within the semiconductor substrate at a given time, the first location being either on a structure in a first row of structures or between two adjacent structures in the first row; a means for propagating a second laser beam along a second laser beam propagation path having a second axis incident at a second location on or within the semiconductor substrate at the given time, the second location being either on a structure in a second row of structures or between two adjacent structures in the second row, the second row being distinct from the first row, wherein the second location is offset from the first location by some amount in the lengthwise direction of the rows; and a means for moving the first and second laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the first and second rows with the first and second laser beams respectively.

26. A system for selectively irradiating structures on or within a semiconductor substrate using multiple laser beams, the structures being arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction, the system comprising: a laser source producing at least a first laser beam and a second laser beam; a first laser beam propagation path having a first axis incident at a first spot at a first location on or within the semiconductor substrate at a given time, the first location being either on a structure in a first row of structures or between two adjacent structures in the first row; a second laser beam propagation path having a second axis incident at a second spot at a second location on or within the semiconductor substrate at the given time, the second location being either on a structure in a second row of structures or between two adjacent structures in the second row, the second row being distinct from the first row, wherein the second location is offset from the first location by some amount in the lengthwise direction of the rows; and a motion stage that moves the first and second laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the first and second rows with the first and second laser beams respectively.

27. The system of claim 26, wherein the laser source comprises: respective first and second lasers.

28. The system of claim 26, wherein the laser source comprises: a laser; and a beam splitter disposed in both the first and second laser beam propagation paths between the laser and the semiconductor substrate.

29. The system of claim 26, further comprising: a first optical switch disposed in the first laser beam propagation path, the first optical switch capable of selectively passing or blocking the first laser beam from reaching the semiconductor substrate; and a second optical switch disposed in the second laser beam propagation path, the second optical switch capable of selectively passing or blocking the second laser beam from reaching the semiconductor substrate.

30. The system of claim 29, wherein the first and second optical switches are AOMs.

31. The system of claim 29, further comprising: a controller connected to the first and second optical switches, the controller setting the states of the first and second optical switches so as to irradiate only selected structures.

32. The system of claim 26, further comprising: a beam steering mechanism disposed in the first laser beam propagation path, whereby the first location can be adjusted.

33. The system of claim 26, further comprising: a beam steering mechanism disposed in the second laser beam propagation path, whereby the second location can be adjusted.

34. The system of claim 26, further comprising: a beam combiner disposed in both the first and the second laser beam propagation paths; and a focus lens disposed in both the first and the second laser beam propagation paths between the beam combiner and the semiconductor substrate.

35. The system of claim 26, further comprising: a first focus lens disposed in the first laser beam propagation path; and a second focus lens disposed in the second laser beam propagation path.

---

Description

---

TECHNICAL FIELD

This disclosure relates generally to manufacturing semiconductor integrated circuits and more particularly to the use of laser beams to process structures on or within a semiconductor integrated circuit.

BACKGROUND

During their fabrication process, ICs (integrated circuits) often incur defects for various reasons. For that reason, IC devices are usually designed to contain redundant circuit elements, such as spare rows and columns of memory cells in semiconductor memory devices, e.g., a DRAM (dynamic random access memory), an SRAM (static random access memory), or an embedded memory. Such devices are also designed to include particular laser-severable links between electrical contacts of the redundant circuit elements. Such links can be removed, for example, to disconnect a defective memory cell and to substitute a replacement redundant cell. Similar techniques are also used to sever links in order to program or configure logic products, such as gate arrays or ASICs (application-specific integrated circuits). After an IC has been fabricated, its circuit elements are tested for defects, and the locations of defects may be recorded in a database. Combined with positional information regarding the layout of the IC and the location of its circuit elements, a laser-based link processing system can be employed to remove selected links so as to make the IC useful.

Laser-severable links are typically about 0.5-1 microns (.mu.m) thick, about 0.5-1 .mu.m wide, and about 8 .mu.m in length. Circuit element in an IC, and thus links between those elements, are typically arranged in a regular geometric arrangement, such as in regular rows. In a typical row of links, the center-to-center pitch between adjacent links is about 2-3 .mu.m. These dimensions are representative, and are declining as technological advances allow for the fabrication of workpieces with smaller features and the creation of laser processing systems with greater accuracy and smaller focused laser beam spots. Although the most prevalent link materials have been polysilicon and like compositions, memory manufacturers have more recently adopted a variety of more conductive metallic link materials that may include, but are not limited to, aluminum, copper, gold nickel, titanium, tungsten, platinum, as well as other metals, metal alloys, metal nitrides such as titanium or tantalum nitride, metal silicides such as tungsten silicide, or other metal-like materials.

Conventional laser-based semiconductor link processing systems focus a single pulse of laser output having a pulse width of about 4 to 30 nanoseconds (ns) at each link. The laser beam is incident upon the IC with a footprint or spot size large enough to remove one and only one link at a time. When a laser pulse impinges a polysilicon or metal link positioned above a silicon substrate and between component layers of a passivation layer stack including an overlying passivation layer, which is typically 2000-10,000 angstrom (.ANG.) thick, and an underlying passivation layer, the silicon substrate absorbs a relatively small proportional quantity of infrared (IR) radiation and the passivation layers (silicon dioxide or silicon nitride) are relatively transparent to IR radiation. Infrared (IR) laser wavelengths (e.g., 0.522 .mu.m, 1.047 .mu.m, 1.064 .mu.m, 1.321 .mu.m, and 1.34 .mu.m) have been employed for more than 20 years to remove circuit links.

Present semiconductor link processing systems employ a single laser pulse focused into a small spot for link removal. Banks of links to be removed are typically arranged on the wafer in a straight row, an illustrative one of which is shown in FIG. 1. The row need not be perfectly straight, although typically it is quite straight. The links are processed by the system in a link run 120, which is also referred to as an on-the-fly ("OTF") run. During a link run, the laser beam is pulsed as a stage positioner passes the row of links across the focused laser spot location. The stage typically moves along a single axis at a time and does not stop at each link position. Thus the link run is a processing pass down a row of links in a generally lengthwise direction (horizontally across the page as shown.) Moreover, the lengthwise direction of the link run 120 need not be exactly perpendicular to the lengthwise direction of the individual links that constitute the row, although that is typically approximately true. Impingent upon selected links in the link run 120 is a laser beam whose propagation path is along an axis. The position at which that axis intersects the workpiece continually advances along the link run 120 while pulsing the laser to selectively remove links. The laser is triggered to emit a pulse and sever a link when the wafer and optical components have a relative position such that the pulse energy will impinge upon the link. Some of the links are not irradiated and left as unprocessed links 140, while others are irradiated to become severed links 150.

FIG. 2 illustrates a typical link processing system that adjusts the spot position by moving a wafer 240 in an XY plane underneath a stationary optics table 210. The optics table 210 supports a laser 220, a mirror 225, a focusing lens 230, and possibly other optical hardware. The wafer 240 is moved underneath in the XY plane by placing it on a chuck 250 that is carried by a motion stage 260.

FIG. 3 depicts the processing of the wafer 240. A conventional sequential link blowing process requires scanning the XY motion stage 260 across the wafer 240 once for each link run. Repeatedly scanning back and forth across the wafer 240 results in complete wafer processing. A machine typically scans back and forth processing all X-axis link runs 270 (shown with solid lines) before processing the Y-axis link runs 280 (shown in dashed lines). This example is merely illustrative. Other configurations of link runs and processing modalities are possible. For example it is possible to process links by moving the wafer, optics rail, or through beam deflection. In addition, link banks, and link runs may not be straight rows and may not be processed with continuous motion.

For this example, the primary system parameters that impact the time spent executing link runs, and thus throughput, are the laser pulse repetition frequency (PRF) and motion stage parameters such as stage acceleration, bandwidth, settling time, and the commanded stage trajectory. The commanded stage trajectory consists of acceleration and deceleration segments, constant velocity processing of link banks, and "gap profiling" or accelerating over large gaps between links to be processed in a link run. Most improvements to system throughput over the past several years have primarily focused upon enhancing the stage and laser parameters. Improvements in these areas will continue; however, practical limitations associated with these parameters make this a difficult way to achieve large throughput gains.

Increasing peak stage acceleration, for example, provides only a limited throughput improvement. Present motion stages are capable of moving a wafer with a full field travel, greater than 300 mm (millimeters), with 1 to 2 G accelerations, while maintaining a positional accuracy on the order of 100 nm (nanometers). Increasing stage acceleration introduces additional vibrations and generates heat, both of which can decrease system accuracy. Significantly increasing the stage acceleration and bandwidth, without diminishing the positional accuracy or increasing the system footprint, is a challenging and costly engineering endeavor, and the benefits of that effort would only be moderate.

Increasing the laser PRF, and hence link run velocity, is also undesirable for a number of reasons. First, there are unfavorable changes in the laser pulses that result from increasing the PRF. For a given laser cavity, as the inter-pulse period decreases, the laser pulse width increases. This may decrease the processing efficiency on some link structures. Higher laser PRFs are also associated with less energy stability, which also decreases processing efficiency. Higher laser PRFs can also result in lower pulse power, although that is usually not a problem when processing links that use a small spot size.

High laser PRFs are also undesirable when applied to semiconductor products that have a large link pitch. The combination of high PRF and large link pitch requires that a very high stage velocity be used for processing links. A high stage velocity requires more stage acceleration and deceleration and decreases the opportunity to take advantage of gaps of unprocessed links in a run. These effects diminish some of the throughput improvements from the higher link run velocity. A high stage velocity also requires a tighter timing tolerance when triggering the generation of laser pulses in order to maintain accuracy. Processing at high stage velocities may also not be possible if these velocities exceed some system specification, such as the maximum stage or position feedback sensor velocity.

Continued shrinkage of the feature sizes on semiconductor wafers will result in an increased number of links and link runs to process these wafers, further increasing wafer processing time, while future system throughput improvements of significant magnitude are unlikely to occur through improvements in stage acceleration performance or laser PRF.

SUMMARY

According to one embodiment, a method selectively irradiates structures (e.g., electrically conductive links) on or within a semiconductor substrate using multiple laser beams. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The method propagates a first laser beam along a first propagation path having a first axis incident at a first location on or within the semiconductor substrate at a given time. The first location is either on a structure in a first row of structures or between two adjacent structures in the first row. The method also propagates a second laser beam along a second propagation path having a second axis incident at a second location on or within the semiconductor substrate at the given time. The second location is either on a structure in a second row of structures or between two adjacent structures in the second row. The second row is distinct from the first row, and the second location is offset from the first location by some amount in the lengthwise direction of the rows. The method moves the first and second laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the first and second rows with the first and second laser beams respectively.

According to another embodiment, a system selectively irradiates electrically conductive structures on or within a semiconductor substrate using multiple laser beams. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The system comprises a laser source, a first laser beam propagation path, a second laser beam propagation path, and a motion stage. The laser source produces at least a first laser beam and a second laser beam. The first laser beam propagation path has a first axis incident at a first spot at a first location on or within the semiconductor substrate at a given time. The first location is either on a structure in a first row of structures or between two adjacent structures in the first row. The second laser beam propagation path has a second axis incident at a second spot at a second location on or within the semiconductor substrate at the given time. The second location is either on a structure in a second row of structures or between two adjacent structures in the second row. The second row is distinct from the first row, and the second location is offset from the first location by some amount in the lengthwise direction of the rows. The motion stage moves the first and second laser beam axes substantially in unison in the lengthwise direction of the rows relative to the semiconductor substrate, so as to selectively irradiate structures in the first and second rows with the first and second laser beams respectively.

As used herein: the term "on" means not just directly on but atop, above, over, or covering, in any way, partially or fully; the term "substantially" is a broadening term that means about or approximately but does not imply a high degree of closeness; and the term "adjacent" means next to or next in a series (e.g., the letter "F" is adjacent to "G" but not "H" in the alphabet) without implying physical contact.

Additional details concerning the construction and operation of particular embodiments are set forth in the following sections with reference to the below-listed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a row or bank of links being selectively irradiated with a laser spot scanning along the lengthwise direction of the bank.

FIG. 2 is a diagram of a link processing system.

FIG. 3 is an illustration of link runs on a semiconductor wafer.

FIG. 4 is a velocity profile plot of a single link run.

FIG. 5 is an illustration of various two-spot arrangements, according to various embodiments.

FIG. 6 is an illustration of two different cases of two link rows in relation to one another.

FIG. 7 is an illustration of two laterally spaced laser spots processing the two cases of FIG. 6, according to one embodiment.

FIG. 8 is an illustration of two-spot and three-spot examples of on-axis arrangements of laser spots, according to two embodiments.

FIG. 9 is an illustration of a two-spot on-axis arrangement of laser spots for processing a row in one pass, according to one embodiment.

FIG. 10 is an illustration of a two-spot on-axis arrangement of laser spots for processing a row in two passes, according to one embodiment.

FIGS. 11 and 12 are illustrations of two laterally spaced laser spots with relative steering in the lateral direction, according to one embodiment.

FIG. 13 is an illustration of two cases of a four-spot arrangement with both on-axis and cross-axis spacings, according to one embodiment.

FIG. 14 is a set of plots of laser pulse power versus time, according to one embodiment.

FIG. 15 is a block diagram of a multiple-spot laser processing system, according to one embodiment.

FIG. 16 is a block diagram of a two-spot laser processing system, according to one embodiment.

FIGS. 17-24 are diagrams of various implementations of a two-spot laser processing system, according to various embodiments.

FIG. 25 is a diagram of a system for combining multiple laser beams, according to one embodiment.

FIG. 26 is a diagram of a system for generating multiple laser beams, according to one embodiment.

FIG. 27 is a diagram of a multiple-lens laser processing system, according to one embodiment.

FIG. 28 is a diagram of a two-spot laser processing system with error correction capability, according to one embodiment.

FIG. 29 is a diagram of a two-spot laser processing system with independent beam steering, according to one embodiment.

FIG. 30 is a diagram of a two-spot laser processing system with energy calibration capability, according to one embodiment.

FIG. 31 is a diagram of a two-spot laser processing system with position calibration capability, according to one embodiment.

FIG. 32 is an illustration of a calibration target and two laser spots, according to one embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

With reference to the above-listed drawings, this section describes particular embodiments and their detailed construction and operation. The principles, methods, and systems disclosed below have general applicability for processing any structure on or within a semiconductor substrate using laser radiation for any purpose. While the examples and embodiments that follow are described in the context in which those structures are laser-severable links on or within an IC (e.g., memory device, logic device, optical or optoelectronic device including LEDs, and microwave or RF devices), other structures besides laser-severable links can be processed in the same or similar manner, and the teachings set forth herein are equally applicable to the laser processing of other types of structures, such as electrical structures that become conductive as a result of laser radiation, other electrical structures, optical or electro-optical structures, and mechanical or electro-mechanical structures (e.g., MEMS (micro electro-mechanical structures) or MOEMS (micro opto-electro-mechanical structures)). The purpose of the irradiation may be to sever, cleave, make, heat, alter, diffuse, anneal, or measure a structure or its material. For example, laser radiation can induce a state change in a structure's material, cause the migration of dopants, or alter magnetic properties--any of which could be used to connect, disconnect, tune, modify, or repair electrical circuitry or other structures.

As one skilled in the art will appreciate in light of this disclosure, certain embodiments are capable of achieving certain advantages over the known prior art, including some or all of the following: (1) increasing throughput, possibly by multiplicative factors, e.g., by a factor of 2, 3, 4, etc.; (2) decreasing floor space required for link processing equipment in a fabrication facility; (3) decreasing the time elapsing between scanning alignment targets and completing link processing, thereby (a) allowing less time for thermal drift of the components and structure of the semiconductor processing system, resulting in enhanced system accuracy, (b) enabling larger wafer processing fields, which results in longer link runs and an additional throughput improvement, and (c) permitting less frequent rescanning of alignment targets when thermal shifts are detected or when the time elapsed since their previous scan becomes too large, thus further enhancing throughput by reducing the number of operations necessary for accurate link processing; and (4) allowing beneficial relaxation of some present system parameters, such as XY stage acceleration and laser pulse repetition frequency, while still processing wafers at a rate that is equivalent or faster than present link processing systems. As an example of the latter advantage, lowering the stage acceleration requirements can reduce the thermal energy released into the system environment, reducing thermal shifts that occur during wafer processing; lower acceleration will also improve accuracy by reducing the excitation of system resonances and vibrations, resulting in smoother, gentler, more stable system operation; motion stages can also be selected with a lower cost, preferential mechanical configuration, greater simplicity, and no need for auxiliary cooling systems if a reduced acceleration is acceptable. As another example, a laser source with a lower PRF could be used for processing; lower PRF lasers have improved pulse properties such as faster rise time, enhanced pulse stability, increased peak pulse power, and shorter pulse width; lower PRF lasers may also be less costly and may be operable with smaller power supplies that generate less heat. These and other advantages of various embodiments will be apparent upon reading the remainder of this section.

I. Analysis of Link Run Processing Time

Measurements from the repair of typical DRAM wafers show that the time to execute link runs accounts for the majority of wafer processing time. Approximately 85% of total processing time may be spent executing link runs, and the remaining 15% is spent performing overhead tasks, such as moving the wafer to shift the cutting laser from the end of one link run to the start of the next link run, alignment, focusing, and computational overhead. Because the dominant component of link processing time is typically spent executing link runs, significant reductions in wafer processing time can result from reducing the time spent executing link runs.

FIG. 4 illustrates a link run velocity profile 410 corresponding to the processing of a link run 420. As used herein, the term "velocity profile" means velocity as a function of time or distance over a span of time or an interval of distance. Link run execution consists of a number of different operations. While processing a bank 430 of links with a tight pitch spacing (e.g., the center-to-center distance between adjacent links in the same bank), the laser beam axis advances relative to the wafer at a nearly constant velocity 440. Note that, although FIG. 4 shows an example in which the constant velocity 440 is the same for each link bank 430 in the link run 420, it is possible that different link banks 430 may have different constant velocities, such as when the pitch spacing differs from bank to bank in the same link run. When there is a large gap 450 between subsequent links in a link run, the system accelerates to span the gap 450 in less time and then decelerates near the end of the gap to reach a nominal velocity once again. That acceleration and deceleration result in a gap profile 460 in the link velocity profile 410. At the beginning of a link run, the system undergoes an initial acceleration 470 from a resting position followed by a period of settling 480. At the end of a link run, the system undergoes a deceleration 490 back down to zero velocity. Thus, the typical operations that the system performs during execution of a link run include ramping up the stage to constant velocity, settling, processing links at constant velocity, accelerating (gap profiling) over any large gaps, and ramping back down to zero velocity at the end of the run. FIG. 4 illustrates the effect of these operations on link run on-axis velocity. Note that while the link run 420 is depicted as a straight line through co-linear link banks, it is possible for the banks of links to not be in line. Link run 420 would then contain lateral position commands as well.

Insight into system improvements for reducing link run execution time are evident from the following simplified throughput prediction model. The model approximates the time required for link run execution. The model is not accurate for absolute time prediction because it does not fully model all system behavior, such as move profiling; however the relative impact of changing different processing parameters is correct. According to this model, the time required to process the links is T.sub.LR=N.sub.LR( D.sub.LR/ V.sub.LR+T.sub.accel+T.sub.settle+T.sub.decel- T.sub.gap savings). (1) In Equation (1), T.sub.LR is the total link run execution time and N.sub.LR is the total number of link runs. The terms in parenthesis can be lumped into three categories: (1) time spent to span all the link runs at constant velocity, (2) time spent to accelerate, settle, and decelerate during link runs, and (3) time saved by gap profiling.

The average time spent on a link run at constant velocity is described by D.sub.LR the average link run distance and V.sub.LR the average link run velocity. This velocity is typically V.sub.LR=P.sub.linkF.sub.laser where P.sub.link is fundamental link pitch spacing and F.sub.laser is the laser PRF.

A rearrangement of the terms of Equation (1) that pertain to constant link run velocity shows that the total time spent at constant velocity is T.sub.Vconst=N.sub.LR D.sub.LR/ V.sub.LR=D.sup.total/ V.sub.LR. This can be restated as follows: The total time required to process the link runs at constant velocit