Semiconductor memory circuit hard to cause soft error Number:6,807,081 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor memory circuit hard to cause soft error

Abstract: A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one .alpha.-particle passes through two N-channel MOS transistors, a soft error hard to occur.

Patent Number: 6,807,081 Issued on 10/19/2004 to Nii

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Inventors:	Nii; Koji (Hyogo, JP)
Assignee:	Renesas Technology Corp. (Tokyo, JP)
Appl. No.:	10/238,618
Filed:	September 11, 2002

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Foreign Application Priority Data

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Dec 07, 2001 [JP]			2001-373947

Current U.S. Class:	365/145 ; 365/156; 365/189.05; 365/230.05
Current International Class:	G11C 11/412 (20060101)
Field of Search:	365/154,156,189.05,230.05,49

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References Cited [Referenced By]

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U.S. Patent Documents

	4175290		November 1979		Harari
	4532609		July 1985		Iizuka
	4956815		September 1990		Houston
	5406107		April 1995		Yamaguchi
	5724292		March 1998		Wada
	6091626		July 2000		Madan
	6627690		September 2003		Hironaka
	6627960		September 2003		Nii et al.

Foreign Patent Documents

	57-12486		Jan., 1982		JP
	4-278290		Oct., 1992		JP

Primary Examiner: Ho; Hoai
Attorney, Agent or Firm: McDermott Will & Emery LLP

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Claims

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What is claimed is:

1. A semiconductor memory circuit formed on a SOI comprising: two inverters connected between first and second storage nodes, an input node of each inverter being connected to an output node of the other inverter, wherein said inverters each includes: plural first MOS transistors with a first conductivity type, connected in series between a line of a first power supply potential and the output node, and whose gate electrodes are all connected to the input node; and a MOS second transistor with a second conductivity type, connected between a line of a second power supply potential and the output node, and whose gate electrode is connected to the input node, wherein each said first MOS transistor has a body region provided beneath the sate electrode, and the body region of each said first MOS transistor is spaced apart from the body region of another said first MOS transistor.

2. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit is placed at an intersecting portion of a word line and first and second bit lines and further comprises: plural third MOS transistors connected in series between said first bit line and said first storage node, and becoming conductive in response to transition of said word line to select level; and plural fourth MOS transistors connected in series between said second bit line and said second storage node, and becoming conductive in response to transition of said word line to select level.

3. The semiconductor memory circuit according to claim 1, wherein the gate electrodes of said plural first MOS transistors extend at a right angle to each other.

4. The semiconductor memory circuit according to claim 1, wherein the gate electrodes of said plural first MOS transistors extend in the same direction along one straight line.

5. The semiconductor memory circuit according to claim 1, wherein the gate electrodes of said plural first MOS transistors extend in parallel to each other.

6. The semiconductor memory circuit according to claim 2, wherein the gate electrodes of the first MOS transistors, the second MOS transistor, the third MOS transistors and the fourth MOS transistors extend in the same direction as each other.

7. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit is formed on a surface of a first semiconductor layer of a first conductivity type, and surfaces of second and third semiconductor layers of a second conductivity type located on one side of said first semiconductor layer and on the other side thereof, respectively, said second MOS transistors of said two inverters are all formed on the surface of said first semiconductor layer, and said plural first MOS transistors of one of said two inverters are all formed on the surface of said second semiconductor layer, while said plural first MOS transistors of the other inverter are all formed on the surface of said third semiconductor layer.

8. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit is formed on a surface of a first semiconductor layer of a first conductivity type, and surfaces of second and third semiconductor layers of a second conductivity type located on one side of said first semiconductor layer and the other side thereof, respectively, said second MOS transistors of said two inverters are all formed on the surface of said first semiconductor layer, and said plural first MOS transistors of one of the two inverters are formed on said surfaces of second and third semiconductor layers in a distributed manner, and said plural first MOS transistors of the other inverter are formed on said surface of second and third semiconductor layers in a distributed manner.

9. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit is placed at an intersecting portion of a word line and first and second bit lines, a read word line and a read bit line are provided correspondingly to said semiconductor memory circuit, and said semiconductor memory circuit further comprises read circuits giving a logic level of one of said first and second storage nodes to said read bit line in response to transition of said read word line to select level.

10. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit is placed at an intersecting portion of a word line and first and second bit lines, a search line and a match line are provided correspondingly to said semiconductor memory circuit, and said semiconductor memory circuit further comprises a coincidence/non-coincidence detection circuit detecting whether or not a logic level of one of said first and second storage nodes coincides with a logic level given onto said search line to give a signal at a level corresponding to a result of the detection to said match line.

11. The semiconductor memory circuit according to claim 1, wherein said inverters each include plural third MOS transistors with a second conductivity type, and said second MOS transistor, connected in series between a line of the second power supply potential and the output node, and whose gate electrodes are all connected to the input node.

12. The semiconductor memory circuit according to claim 11, wherein said semiconductor memory circuit is placed at an intersecting portion of a word line and first and second bit lines and further comprises: plural fourth MOS transistors connected in series between said first bit line and said first storage node, and becoming conductive in response to transition of said word line to select level; and plural fifth MOS transistors connected in series between said second bit line and said second storage node, and becoming conductive in response to transition of said word line to select level.

13. The semiconductor memory circuit according to claim 11, wherein the gate electrodes of said plural first MOS transistors extend at a right angle to each other, and the gate electrodes of said plural third MOS transistors extend at a right angle to each other.

14. The semiconductor memory circuit according to claim 11, wherein the gate electrodes of said plural first MOS transistors extend in the same direction along one straight line, and the gate electrodes of said plural third MOS transistors extend in the same direction along another straight line.

15. The semiconductor memory circuit according to claim 11, wherein the gate electrodes of said plural first MOS transistors extend in parallel to each other, and the gate electrodes of said plural third MOS transistors extend in parallel to each other.

16. The semiconductor memory circuit according to claim 12, wherein the gate electrodes of said first MOS transistors, said third MOS transistors, said fourth MOS transistors and said fifth MOS transistors extend in the same direction as each other.

17. The semiconductor memory circuit according to claim 11, wherein said semiconductor memory circuit is formed on a surface of a first semiconductor layer of a first conductivity type, and surfaces of second and third semiconductor layers of a second conductivity type located on one side of said first semiconductor layer and the other side thereof, respectively, said plural third MOS transistors of said two inverters are all formed on the surface of said first semiconductor layer, and said plural first MOS transistors of one of said two inverters are all formed on the surface of said second semiconductor layer, while said plural first MOS transistors of the other inverter are all formed on the surface of said third semiconductor layer.

18. The semiconductor memory circuit according to claim 11, wherein said semiconductor memory circuit is formed on a surface of a first semiconductor layer of a first conductivity type, and surfaces of second and third semiconductor layers of a second conductivity type located on one side of said first semiconductor layer and the other side thereof, respectively, said plural first MOS transistors of one of said two inverters are formed on the surfaces of said second and third semiconductor layers in a distributed manner, and said plural first MOS transistors of the other inverter are formed on the surfaces of said second and third semiconductor layers in a distributed manner.

19. The semiconductor memory circuit according to claim 1, wherein said semiconductor memory circuit receives a clock signal and an input signal, and constructs a latch circuit latching a logic level of the input signal given to an input terminal, which is connected to the first storage node, in response to said clock signal.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory circuit, and particularly, to a semiconductor memory circuit equipped with two inverters in antiparallel connection.

2. Description of the Background Art

FIG. 25 is a circuit diagram showing a construction of a memory cell 80 of a prior art static random access memory (hereinafter referred to as SRAM). In FIG. 25, memory cell 80 includes: P-channel MOS transistors 81 and 82; and N-channel MOS transistors 83 to 86. P-channel MOS transistors 81 and 82 are connected, respectively, between a line of power supply potential VDD and a storage node N81, and between a line of power supply potential VDD and a storage node N82, and the gates thereof are connected to respective storage nodes N82 and N81. N-channel MOS transistors 83 and 84 are connected, respectively, between a line of ground potential GND and a storage node N81, and between a line of ground potential GND and a storage node N82, and the gates thereof are connected to respective storage nodes N82 and N81. N-channel MOS transistor 85 is connected between a bit line BL and storage node N81, and MOS transistor 86 is connected between a bit line /BL and storage node N82, and the gates thereof are both connected to a word line WL. MOS transistors 81 and 83 constitute an inverter giving an inverted signal of a signal of storage node N82 to storage node N81. MOS transistors 82 and 84 constitutes an inverter giving an inverted signal of a signal of storage node N81 to storage node N82. The two inverters are antiparallel-connected between storage nodes N81 and N82 to constitute a latch circuit.

When word line WL is driven to H level at select level, N-channel MOS transistors 85 and 86 become conductive. When one bit line (for example, BL) of bit lines BL and /BL is driven to H level, and in addition, the other bit line (/BL in this case) is driven to L level according to a write data signal, not only do MOS transistors 81 and 84 become conductive, but MOS transistors 82 and 83 also become non-conductive to thereby latch levels of storage nodes N81 and N82. When word line WL is driven to L level at non-select level, N-channel MOS transistors 85 and 86 become non-conductive to store a data signal into memory cell 80.

In read operation, after bit lines BL and /BL are precharged to H level, word line WL is driven to H level at select level. By doing so, a current flows out from bit line (/BL in this case) onto the line of ground potential GND through N-channel MOS transistors 86 and 84 to lower a potential of bit line /BL. By comparison between potentials on bit lines BL and /BL, storage data of memory cell 80 can be read out.

In such a memory cell 80, a so-called soft error has been easy to occur in company with recent progress to high level of integration and to low level of voltage of power supply. Herein, the term soft error is a phenomenon that .alpha.-particle radiation emitted from a trace of radioactive material contained in a package strikes a memory cell to invert storage data. This is considered because a soft error is easy to occur since with a higher level of integration, capacities of storage nodes N81 and N82 are smaller and power supply voltage is lowered.

SUMMARY OF THE INVENTION

It is accordingly a main object of the present invention to provide a semiconductor memory circuit, in which storage data is hard to be inverted even when the memory circuit is irradiated with .alpha.-particle radiation.

A semiconductor memory circuit according to the present invention includes: two inverters connected between first and second storage nodes, an input node of each inverter being connected to an output node of the other inverter, wherein the inverters each include: plural first transistors with a first conductivity type, connected in series between a line of a first power supply potential and the output node, and whose input electrodes are all connected to the input node; and a second transistor with a second conductivity type, connected in series between a line of a second power supply potential and the output node, and whose input electrode is connected to the input node. Therefore, since an inverter includes the plural first transistors, a capacity of a storage node is larger compared with a prior art case where an inverter includes one first transistor, making storage data hard to be inverted. Furthermore, unless one .alpha.-particle passes through the plural first transistors, storage data is not inverted; therefore, the storage data is harder to be inverted compared with a prior case where storage data was inverted by one .alpha.-particle passing through one first transistor.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit block diagram showing an overall configuration of SRAM according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of a memory cell shown in FIG. 1;

FIG. 3 is a view for describing an effect of the first embodiment;

FIGS. 4A to 4C are views and a representation for describing the effect of the first embodiment;

FIGS. 5A and 5B are plan views showing a layout of a memory cell of SRAM according to a second embodiment of the present invention;

FIGS. 6A and 6B are plan views showing a layout of a memory cell of SRAM according to a third embodiment of the present invention;

FIGS. 7A, 7B and 7C are plan views showing a layout of a memory cell of SRAM according to a fourth embodiment of the present invention;

FIG. 8 is a circuit diagram showing a configuration of a memory cell of SRAM according to a fifth embodiment of the present invention;

FIG. 9 is a circuit diagram showing a configuration of a memory cell of SRAM according to a sixth embodiment of the present invention;

FIGS. 10A and 10B are plan views showing a layout of a memory cell of SRAM according to a seventh embodiment of the present invention;

FIGS. 11A and 11B are plan views showing a layout of a memory cell of SRAM according to an eighth embodiment of the present invention;

FIGS. 12A and 12B are plan views showing a layout of a memory cell of SRAM according to a ninth embodiment of the present invention;

FIG. 13 is a circuit diagram showing a configuration of a memory cell of SRAM according to a tenth embodiment of the present invention;

FIG. 14 is a circuit diagram showing a configuration of a memory cell of SRAM according to an eleventh embodiment of the present invention;

FIGS. 15A and 15B are plan views showing a layout of a memory cell of SRAM according to a twelfth embodiment of the present invention;

FIGS. 16A, 16B and 16C are plan views showing a layout of a memory cell of SRAM according to a thirteenth embodiment of the present invention;

FIG. 17 is a circuit diagram showing a configuration of a memory cell of 2-port SRAM according to a fourteenth embodiment of the present invention;

FIGS. 18A, 18B and 18C are plan views showing a layout of a memory cell of 2-port SRAM according to a fifteenth embodiment of the present invention;

FIG. 19 is a circuit diagram showing a configuration of a memory cell of 2-port SRAM according to a sixteenth embodiment of the present invention;

FIG. 20 is a circuit diagram showing a configuration of a memory cell of 3-port SRAM according to a seventeenth embodiment of the present invention;

FIG. 21 is a circuit diagram showing a modification of the seventeenth embodiment of the present invention;

FIG. 22 is a circuit diagram showing a configuration of a memory cell of a content addressable memory according to an eighteenth embodiment of the present invention;

FIG. 23 is a circuit diagram showing a configuration of a memory cell of SRAM according to a nineteenth embodiment of the present invention;

FIG. 24 is a circuit diagram showing a configuration of a flip-flop circuit according to a twentieth embodiment of the present invention; and

FIG. 25 is a circuit diagram showing a configuration of a memory cell of prior art SRAM.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1 is a block diagram showing a configuration of SRAM according to a first embodiment of the present invention. In FIG. 1, SRAM includes: plural memory cells (MC) 1 (4 cells in this case for simplification in figure and description) arranged in a matrix: word lines WL provided correspondingly to respective rows; and bit line pairs BL and /BL provided correspondingly to respective columns.

Furthermore, SRAM includes: bit line loads 2, provided correspondingly to respective bit lines BL and /BL, and for charging corresponding bit line BL or /BL to a prescribed potential; equalizers 3, provided corresponding to respective bit line pairs BL and /BL, and each for equalizing potentials on a bit line pair BL and /BL with each other; and column select gates 4, provided correspondingly to respective bit line pairs BL and /BL, and each for connecting corresponding bit line pair BL and /BL to respective data input/output line pairs IO and /IO.

Bit line loads 2 each includes an N-channel MOS transistor diode-connected between a line of power supply potential VDD and one end of corresponding bit line BL or /BL. Equalizers 3 each includes a P-channel MOS transistor connected between corresponding bit line pair BL and /BL and receiving a bit line equalize signal /BLEQ at its gate. Column select gates 4 each includes: an N-channel MOS transistor connected between the other end of corresponding bit line BL and one end of data input/output line IO; and an N-channel MOS transistor connected between the other end of corresponding bit line /BL and one end of data input/output line /IO, wherein the gates of the two N-channel MOS transistors are connected to one end of a column select line CSL.

Furthermore, SRAM includes: a row decoder 5; a control circuit 6; a column decoder 7; a write circuit 8; and a read circuit 9. Row decoder 5 raises one word line WL of plural word lines WL to H level at select level according to a row address signal given externally. Control circuit 6 controls all of SRAM according to control signals given externally. Column decoder 7 raises one column select line CSL of plural column select lines to H level at select level according to a column address signal given externally.

Write circuit 8 and read circuit 9 are both connected to the other ends of data input/output line pair IO and /IO. Write circuit 8 writes a data signal DI given externally onto memory cell 1 selected by row decoder 5 and column decoder 7. Read circuit 9 outputs a read data signal DO from memory cell 1 selected by row decoder 5 and column decoder 7 to outside.

Then, description will be given of operation in SRAM shown in FIG. 1. In write operation, word line WL of a row designated by a row address signal is raised to H level at select level by row decoder 5 to activate memory cells 1 on the row. Then, column select line CSL of a column designated by a column address signal is raised to H level at select level by column decoder 7 to cause a column select gate 4 of the column to be conductive and to thereby connect one memory cell 1 activated to write circuit 8 through bit line pair BL and /BL, and data input/output line pair IO and /IO.

Write circuit 8 not only drives one data input/output line of data input/output lines IO and /IO to H level according to data signal DI given externally, but also drives the other input/output line to L level to write data onto memory cell 1. When word line WL and column select line CSL are lowered to L level, data is stored into memory cell 1.

In read operation, column select line CSL of a column designated by a column address signal is raised to H level at select level to cause column select gate 4 of the column to be conductive and to thereby connect bit line pair BL and /BL to read circuit 9 through data input/output line pair IO and /IO. Then, bit line equalize signal /BLEQ is driven to L level at activation level to cause equalizers 3 to be conductive and to thereby equalize potentials on bit line pairs BL and /BL with each other. After bit line equalize signal /BLEQ is driven to H level at deactivation level and to thereby cause equalizers 3 to be non-conductive, word line WL of a row corresponding to a row address signal is raised to H level at select level by row decoder 5 to activate memory cells 1 on the row. Thereby, a current flows into memory cell from one bit line of bit lines BL and /BL according to data stored in memory cell 1 to, in response, lower a potential on one data input/output line of data input/output lines IO and /IO. Read circuit 9 compares potentials on data input/output lines IO and /IO with each other to output a data signal DO at a logic level corresponding to a result of the comparison to outside.

FIG. 2 is a circuit diagram showing a configuration of memory cell 1. In FIG. 2, memory cell 1 includes: P-channel MOS transistors 11 and 12; N-channel MOS transistors 13 and 13', 14 and 14', 15 and 16; and storage nodes N1 and N2. P-channel MOS transistor 11 is connected between a line of power supply potential VDD and storage node N1, and P-channel MOS transistor 12 is connected between a line of power supply potential VDD and storage node N2 and the gates thereof are connected to respective storage nodes N2 and N1. N-channel MOS transistors 13 and 13' are connected in series between storage node N1 and a line of ground potential GND and the gates thereof are both connected to storage node N2. N-channel MOS transistors 14 and 14' are connected in series between storage node N2 and a line of ground potential GND and the gates thereof are both connected to storage node N1. MOS transistors 11, 13 and 13' constitute an inverter giving an inverted signal of a signal occurring on storage node N2 to storage node N1. MOS transistors 12, 14 and 14' constitute an inverter giving an inverted signal of a signal occurring on storage node N1 to storage node N2. The two inverters are antiparallel-connected between storage nodes N1 and N2 to constitute a latch circuit. N-channel MOS transistor 15 is connected between storage node N1 and bit line BL and the gate thereof is connected to word line WL. N-channel MOS transistor 16 is connected between storage node N2 and bit line /BL and the gate thereof is connected to word line WL.

Then, description will be given of operation of memory cell 1. In write operation, word line WL is driven to H level to cause N-channel MOS transistors 15 and 16 to be conductive and to thereby couple bit lines BL and /BL to respective storage nodes N1 and N2. Then, according to write data signal DI, not only is one bit line (for example, BL) of bit lines BL and /BL driven to H level, but the other bit line (/BL in this case) is also driven to L level. Thereby, not only do MOS transistors 11, 14 and 14' become conductive, but MOS transistors 12, 13 and 13' also become non-conductive to latch storage nodes N1 and N2 at H and L levels, respectively. When word line WL is driven to L level, N-channel MOS transistors 15 and 16 become non-conductive to end write of the data signal.

In read operation, word line WL is driven to H level to cause N-channel MOS transistors 15 and 16 to be conductive and to thereby couple bit lines BL and /BL to respective storage nodes N1 and N2. Thereby, a current flows onto the line of ground potential GND from a bit line (BL in this case) coupled to the node (for example, N1) held at L level of storage nodes N1 and N2 through N-channel MOS transistors 15, 13 and 13' to lower bit line BL to L level. Then, potentials on bit lines BL and /BL are compared with each other to output data signal DO at a level corresponding to a result of the comparison.

In the first embodiment, not only are two N-channel MOS transistors 13 and 13' connected in series between storage node N1 and the line of ground potential GND, but two N-channel MOS transistors 14 and 14' are also connected in series between storage node N2 and the line of ground potential GND. Therefore, since capacities of storage nodes N1 and N2 can be larger compared with a prior art practice, it can be prevented from occurring that logic levels of storage nodes N1 and N2 are inverted by electrons generated by .alpha.-particle radiation. Furthermore, in a case where memory cell 1 is formed on an SOI substrate, unless one .alpha.-particle passes through body regions of two N-channel MOS transistors (for example, 13 and 13') in a non-conductive state, stored data is not inverted; therefore, the storage data can be harder to be inverted compared with a practical case where if one .alpha.-particle passed through one N-channel MOS transistor (for example, 83) storage data was inverted, thereby, enabling improvement on soft error resistance.

Here, detailed description will be given of a reason why soft error resistance is improved by connecting two N-channel MOS transistors in series between a storage node and a line of ground potential GND. FIG. 3 is a sectional view showing N-channel MOS transistor 13 formed on a bulk silicon substrate. In FIG. 3, N-channel MOS transistor 13 has a structure in which a gate electrode 13g is formed on a surface of a P-type well PW with a gate insulating film 13i interposing therebetween and N.sup.+ -type diffusion layers are formed on both sides of gate electrode 13g. The N.sup.+ -type diffusion layer on one side of gate electrode 13g serves as a drain region 13d, while the N.sup.+ -type diffusion region on the other side of gate electrode 13g serves as a source region 13s.

An .alpha.-particle is identical with a nucleus of the helium (He.sup.++) atom; a positively charged bivalent particle and emitted during radioactive decay of a uranium-238 nucleus and a thorium-232 nucleus, present in a trace amount in the natural world. Since such uranium and thorium are included in a package for a chip, aluminum interconnects, a silicide electrode, a lead solder bump and others, .alpha.-particles are emitted from them. When .alpha.-particle radiation strikes drain region 13d of N-channel MOS transistor 13, many electron-hole pairs are generated in P-type well PW below drain region 13d and many electrons thereof flow into drain region 13d. Therefore, when a capacity of storage node N1 is small, a logic level of storage node N1 is inverted from H level to L level by electrons flowing into drain region 13d. However, in the first embodiment, since two N-channel MOS transistors 14 and 14' are connected in series to increase the capacity of storage node N1, it can be prevented from occurring that a logic level of storage node N1 is inverted.

FIGS. 4A to 4C are views showing states where N-channel MOS transistor 13 formed on an SOI substrate is irradiated with .alpha.-particle radiation. In FIGS. 4A to 4C, the SOI substrate has a structure in which a buried oxide film 18 is formed on a surface of a P-type silicon substrate 17 and a P-type silicon layer 19 is formed on buried oxide film 18. N-channel MOS transistor 13 has a structure in which gate electrode 13g is formed on a surface of P-type silicon layer 19 with gate insulating film 13i interposing therebetween and N.sup.+ -type diffusion layers are formed on both sides of gate electrode 13g. The N.sup.+ -type diffusion layer on one side of gate electrode 13g serves as drain region 13d, while the N.sup.+ -type diffusion layer on the other side of gate electrode 13g serves as source region 13s. P-type layer 19 below gate electrode 13g is called body region 13b.

In a case where N-channel MOS transistor 13 is formed on a bulk silicon substrate, irradiation of drain region 13d with .alpha.-particle radiation is problematic as described above, whereas in a case where N-channel MOS transistor 13 is formed on the SOI substrate, irradiation of drain region 13d with .alpha.-particle radiation is not problematic since a portion below drain region 13d is shielded by buried oxide film 18 covering P-type substrate. It is when .alpha.-particle radiation strikes body region 13b that a problem arises in a case where N-channel MOS transistor 13 is formed on the SOI substrate.

FIG. 4A shows a case where .alpha.-particle radiation strikes body region 13b from above N-channel MOS transistor 13. As shown in FIG. 4A, many electron-hole pairs are generated along a path of an .alpha.-particle. Electron-hole pairs generated in P-type silicon substrate 17 have no chance to be collected into P-type silicon layer 19 thereabove since P-type silicon substrate 17 and P-type silicon layer 19 are insulated from each other by buried oxide film 18. Of electron-hole pairs generated in body region 13b, electrons are immediately collected in drain region 13d by a voltage applied to drain region 13d. On the other hand, holes are, as shown in FIG. 4B, accumulated in a lower portion of body region 13b. As shown in FIG. 14C, since a body potential is raised by the accumulated holes, a potential barrier is lowered between the body region and the source region to thereby cause electrons to flow into the drain region from the source. Such a phenomenon, which is unique to an SOI device, is called a parasitic bipolar effect.

Therefore, when body region 13b is irradiated with .alpha.-particle radiation, N-channel MOS transistor 13 becomes conductive. However, since a probability that one .alpha.-particle passes through body regions 13b and 13'b of N-channel MOS transistors 13 and 13' is very low, soft error resistance of memory cell 1 of FIG. 2 is greatly improved compared with a prior art practice.

Second Embodiment

FIGS. 5A and 5B show a layout of a memory cell of SRAM according to a second embodiment of the present invention. The memory cell has the same configuration as memory cell 1 of FIG. 2, including P-channel MOS transistors 11 and 12; and N-channel MOS transistors 13, 13', 14, 14', 15 and 16. The memory cell is formed on an SOI substrate.

First of all, as shown in FIG. 5A, an N-type active layer NA is formed on part of a P-type region of the SOI substrate. Next, there are formed gate electrodes GE1 to GE3 extending in the X direction of the figure on a surface of P-type silicon layer; gate electrodes GE4 and GE5 extending in the Y direction of the figure from the surface of P-type silicon layer over to the surface of N-type active layer NA; a local interconnect LL1 extending in the X direction of the figure on the surface of P-type silicon surface; and a local interconnect LL2 extending in the X direction of the figure on the surface of N-type active layer NA.

Gate electrode GE1 constitutes a word line WL. Gate electrodes GE2 and GE3 are placed on a straight line in parallel to gate electrode GE1 in a region between gate electrode GE1 and N-type active layer NA. Gate electrode GE4 is coupled to one end portion of gate electrode GE2 at a right angle thereto. Gate electrode GE5 is coupled to one end portion of gate electrode GE3 at a right angle thereto. The other ends of gate electrodes GE2 and GE3 are placed facing each other. One end portion of local interconnect LL1 is coupled to the middle portion of gate electrode GE4 and the other end portion thereof extends near gate electrode GE5. One end portion of local interconnect LL2 is coupled to the middle portion of gate electrode GE5 and the other end thereof extends near gate electrode GE4.

Then, on the P-type silicon layer, not only is an N-type active layer NA1 of the shape of a L letter formed so as to traverse gate electrodes GE1, GE2 and GE4, but an N-type active layer NA2 of the shape of a L letter is also formed so as to traverse gate electrodes GE1, GE3 and GE5. Furthermore, on N-type active layer NA, not only is a P-type active layer PA1 formed so as to traverse gate electrode GE4, but a P-type active layer PA2 is also formed so as to traverse gate electrode GE5.

N-type active layer NA1 and gate electrode GE1, and N-type active layer NA2 and gate electrode GE1 constitute respective N-channel MOS transistors 15 and 16. N-type active layer NA1 and gate electrode GE2, and N-type active layer NA2 and gate electrode GE3 constitute respective N-channel MOS transistors 13 and 14. N-type active layer NA1 and gate electrode GE4, and N-type active layer NA2 and gate electrode GE5 constitute respective N-channel MOS transistors 13' and 14'. P-type active layer PA1 and gate electrode GE4, and P-type active layer PA2 and gate electrode GE5 constitute respective P-channel MOS transistors 11 and 12.

Then, as shown in FIG. 5B, metal interconnects ML1a to ML1g are formed using a first metal interconnection layer and furthermore, metal interconnects ML2a to ML2d extending in the Y direction of the figure are formed using a second metal interconnection layer. Metal interconnects ML1a and ML1b constitute parts of respective storage nodes N1 and N2. Each of metal interconnects ML1c to ML1f are used as a connection electrode. Power supply potential VDD is given onto metal interconnect ML1a. Metal interconnects ML2a and ML2b constitute respective bit lines BL and /BL. Ground potential GND is given to metal interconnects ML2c and ML2d.

One end portion of N-type active layer NA1 (the drain of N-channel MOS transistor 15) is connected to metal interconnect ML2a (bit line BL) through a contact hole CH1, metal interconnect ML1c and a via hole VH1. One end portion of N-type active layer NA2 (the drain of N-channel MOS transistor 16) is connected to metal interconnect ML2b (bit line /BL) through a contact hole CH2, metal interconnect ML1d and a via hole VH2.

A region (the drain of N-channel MOS transistor 13 and the source of N-channel MOS transistor 15) between gate electrodes GE1 and GE2 on N-type active layer NA1 is connected to metal interconnect ML1a (storage node N1) through contact hole CH3, the other end portion of local interconnect LL2 is connected to metal interconnect ML1a (storage node N1) through a contact hole CH7 and one end portion of P-type active layer PA1 (the drain of P-channel MOS transistor 11) is connected to metal interconnect ML1a (storage node N1) through contact hole CH10.

A region (the drain of N-channel MOS transistor 14 and the source of N-channel MOS transistor 16) between gate electrodes GE1 and GE3 on N-type active layer NA2 is connected to metal interconnect ML1b (storage node N2) through a contact hole CH4, the other end portion of local interconnect LL1 is connected to metal interconnect ML1b (storage node N2) through a contact hole CH8 and one end portion of P-type active layer PA2 (the drain of P-channel MOS transistor 12) is connected to metal interconnect ML1b (storage node N2) through contact hole CH11.

The other end portion of N-type active layer NA1 is connected to metal interconnect ML2c (a line of ground potential GND) through contact hole CH5, metal interconnect ML1e and via hole VH3. The other end portion of N-type active layer NA2 is connected to metal interconnect ML2d (a line of ground potential GND) through a contact hole CH6, metal interconnect ML1f and via hole VH4. The other end portion of P-type active layers PA1 is connected to metal interconnect ML1g (a line of power supply potential VDD) through a contact hole CH9, and the other end portion of P-type active layers PA2 is connected to metal interconnect ML1g (a line of power supply potential VDD) through a contact hole CH12. In such a manner, the memory cell is constructed.

In the second embodiment, not only are gate electrodes GE2 and GE4 of N-channel MOS transistors 13 and 13' placed so as to intersect with each other at a right angle, but gate electrodes GE3 and GE5 of N-channel MOS transistors 14 and 14' are also placed so as to intersect with each other at a right angle. In order to invert hold data in storage node N1 and N2, it is required that one .alpha.-particle passes through the body regions of N-channel MOS transistors 13 and 13' or one .alpha.-particle passes through the body regions of N-channel MOS transistors 14 and 14'. In order to produce such a situation associated with an .alpha.-particle, while it is necessary that an .alpha.-particle flies in a direction at an angle of 45 degrees to the X direction in a horizontal plane including the body regions of N-channel MOS transistors 13, 13', 14 and 14' to strike the body region of N-channel MOS transistor 13, 13', 14 or 14', a probability of such a collision of an .alpha.-particle is extremely lower compared with a probability that an .alpha.-particle flies in any direction to strike one N-channel MOS transistor 83 or 84. Therefore, it can be prevented from occurring that hold data in storage nodes N1 and N2 is inverted, thereby enabling improvement on soft error resistance. Note that since a probability that two or more .alpha.-particles strike N-channel MOS transistors 13 and 13' or 14 and 14' simultaneously is very low, the probability is outside a necessity for consideration to be given. Furthermore, since the memory cell can be constituted of two metal interconnection layers, reduction in fabrication cost can be realized.

Third Embodiment

FIGS. 6A and 6B show a layout of a memory cell of SRAM according to a third embodiment of the present invention. The memory cell has the same configuration as memory cell 1 of FIG. 2, including P-channel MOS transistors 11 and 12; and N-channel MOS transistors 13, 13', 14, 14', 15 and 16. The memory cell is formed on an SOI substrate.

First of all, as shown in FIG. 6A, N-type active layer NA is formed on part of a P-type silicon layer of the SOI substrate. Then, there are formed gate electrode GE1 extending in the X direction of the figure on a surface of the P-type silicon layer and gate electrodes GE2 and GE3 extending in the Y direction of the figure from the surface of the P-type silicon layer over to N-type active layer NA. Gate electrode GE1 constitutes a word line WL. One end portions of gate electrodes GE2 and GE3 are placed facing one side of electrode GE1.

Then, on the P-type silicon layer, not only is N-type active layer NA1 formed from the one end portion of gate electrode GE2 over to the other side of gate electrode GE1, but N-type active layer NA2 is also formed from the one end portion of gate electrode GE3 over to the other side of gate electrode GE1. Furthermore, on the P-type silicon layer, an N-type active layer NA3 of the shape of a letter S is formed so as to traverse gate electrodes GE3 and GE2 from one side of gate electrode GE3, then traverse gate electrodes GE2 and GE3, and furthermore traverse gate electrodes GE3 and GE2. Moreover, on N-type active layer NA, two P-type active layers PA1 and PA3 are formed so as to traverse gate electrodes GE2 and GE3.

N-type active layer NA1 and gate electrode GE1, and N-type active layer NA2 and gate electrode GE1 constitute respective N-channel MOS transistors 15 and 16. N-type active layer NA3 and gate electrode GE2 constitute N-channel MOS transistors 14 and 14'. N-type active layer NA3 and gate electrode GE3 constitute N-channel MOS transistors 13 and 13'. P-type active layer PA1 and gate electrode GE2 constitute P-channel MOS transistor 12. P-type active layer PA2 and gate electrode GE3 constitute P-channel MOS transistor 11.

Then, as shown in FIG. 6B, metal interconnects ML1a to ML1e are formed using a first metal interconnection layer and moreover, metal interconnects ML2a to ML2d extending in the Y direction of the figure are formed using a second metal interconnection layer. Ground potential GND is given onto metal interconnect ML1a. Each of metal interconnects ML1b to ML1e are used as a connection electrode. Metal interconnects ML2a and ML2b constitute respective bit lines BL and /BL. Power supply potential VDD is given to metal interconnects ML2c and ML2d.

One end portion of N-type active layer NA1 (the drain of N-channel MOS transistor 15) is connected to metal interconnect ML2a (bit line BL) through contact hole CH1, metal interconnect ML1b and via hole VH1. One end portion of N-type active layer NA2 (the drain of N-channel MOS transistor 16) is connected to metal interconnect ML2b (bit line /BL) through contact hole CH2, metal interconnect ML1c and via hole VH2. The middle portion of N-type active layer NA3 (the sources of N-channel MOS transistors 13' and 14') is connected to metal interconnect ML1a (a line of ground potential GND) through contact hole CH6.

One end portion of P-type active layer PA1 (the source of P-channel MOS transistor 12) is connected to metal interconnect ML2c (a line of power supply potential VDD) through contact hole CH8, metal interconnect ML1d and via hole VH3. One end portion of P-type active layer PA2 (the source of P-channel MOS transistor 11) is connected to metal interconnect ML2d (a line of power supply potential VDD) through contact hole CH11, metal interconnect ML1e and via hole VH4.

The other end portion of N-type active layer NA1 (the source of N-channel MOS transistor 15) and one end of gate electrode GE2 are connected to each other through a plug layer in contact hole CH3, the other end portion of N-type active layer NA2 (the source of N-channel MOS transistor 16) and one end portion of gate electrode GE3 through a plug layer in contact hole CH4, one end portion of N-type active layer NA3 (the drain of N-channel MOS transistor 14) and gate electrode GE3 through a plug layer in contact hole CH5, the other end portion of N-type active layer NA3 (the drain of N-channel MOS transistor 13) and gate electrode GE2 through a plug layer in contact hole CH7, the other end portion of P-type active layer PA1 (the drain of P-channel MOS transistor 12) and gate electrode GE3 through a plug layer in contact hole CH9, and the other end portion of P-type active layer PA2 (the drain of P-channel MOS transistor 11) and gate electrode GE2 through a plug layer in contact hole CH10.

In the third embodiment, not only is gate electrode GE3 of N-channel MOS transistors 13 and 13' placed on a straight line, but gate electrode GE2 of N-channel MOS transistors 14 and 14' is also placed on a straight line. Therefore, in order to invert storage data in storage nodes N1 and N2, while it is required that an .alpha.-particle flies in the Y direction in a horizontal plane including the body regions of N-channel MOS transistors 13, 13', 14 and 14', and in addition strikes the body region of N-channel MOS transistor 13, 13', 14 or 14', a probability of such collision is lower than in a case where in the second embodiment, an .alpha.-particle strikes the body regions of N-channel MOS transistors 13 and 13' or 14 and 14' since widths of gate electrodes GE2 and GE3 are narrower than a width of N-type active layer NA3. Therefore, it can be prevented from occurring that hold data in storage nodes N1 and N2 is inverted, thereby enabling improvement on soft error resistance. Furthermore, since the storage nodes can be constituted with a two metal interconnection layer, reduction in fabrication cost can be realized.

Fourth Embodiment

FIGS. 7A, 7B and 7C are plan views showing a layout of a memory cell of SRAM according to a fourth embodiment of the present invention. The memory cell has the same configuration as memory cell 1 of FIG. 2, including P-channel MOS transistors 11 and 12; and N-channel MOS transistors 13, 13', 14, 14' 15 and 16. The memory cell is formed on an SOI substrate.

First of all, as shown in FIG. 7A, N-type active layer NA is formed on part of a P-type silicon layer of the SOI substrate. Then, there are formed 3 gate electrodes GE1 to GE 3 extending in the X direction of the figure on a surface of the P-type silicon layer on one side of N-type active layer NA; 2 gate electrodes GE4 and GE5 extending in the X direction of the figure on a surface of N-type active layer NA; gate electrodes GE6 to GE8 extending in the X direction of the figure on a surface of P-type active layer on the other side of N-type active layer NA; local interconnect LL1 extending in the Y direction of the figure along the boundary portion between N-type active layer NA and a P-type silicon layer on the one side thereof; and local interconnect LL2 extending in the Y direction of the figure along the boundary portion between N-type active layer NA and a P-type silicon layer on the other side thereof.

Each set of Gate electrodes GE1, GE2 and GE3; GE4 and GE5; and GE6, GE7 and GE8 is placed such that the electrodes are in parallel to each other. Each set of gate electrodes GE1, GE4 and GE6; GE2 and GE7; and GE3, GE5 and GE8 is placed such that the electrodes are on a straight line. Each of gate electrodes GE1, GE2 and GE4, and local line LL1 is mutually connected therebetween. Each of gate electrodes GE5, GE7 and GE8, and local line LL2 is mutually connected therebetween.

Then, on the P-type silicon layer, not only is N-type active layer NA1 formed so as to traverse gate electrodes GE1 to GE3, but N-type active layer NA2 is also formed so as to traverse gate electrodes GE6 to GE8. Furthermore, on N-type active layer NA, P-type active layers PA1 and PA2 are formed so as to traverse gate electrodes GE4 and GE5.

N-type active layer NA1 and gate electrode GE1 constitute N-channel MOS transistor 13', N-type active layer NA1 and gate electrode GE2 constitute N-channel MOS transistor 13 and N-type active layer NA1 and gate electrode GE3 constitute N-channel MOS transistor 15. N-type active layer NA2 and gate electrode GE6 constitute N-channel MOS transistor 16, N-type active layer NA2 and gate electrode GE7 constitute N-channel MOS transistor 14 and N-type active layer NA2 and gate electrode GE8 constitute N-channel MOS transistor 14'. P-type active layer PA1 and gate electrode GE4 constitute P-channel MOS transistor 11. P-type active layer PA2 and gate electrode GE5 constitute P-channel MOS transistor 12.

Then, as shown in FIGS. 7B and 7C, metal interconnects ML1a to ML1j are formed using a first metal interconnection layer, then, metal interconnects ML2a to ML2g are formed using a second metal interconnection layer and furthermore, metal interconnect ML3 is formed using a third metal interconnection layer. Metal interconnects ML1a and ML1b constitute parts of respective storage nodes N1 and N2. Each of metal interconnects ML1c to ML1j are used as a connection electrode. Power supply potential VDD is given to metal interconnect ML2a and ground potential GND is given to metal interconnects ML2d and ML2e. Metal interconnects ML2b and ML2c constitutes respective bit lines BL and /BL. Metal interconnect ML3 constitutes word line WL.

One end portion of N-type active layer NA1 (the source of N-channel MOS transistor 13') is connected to metal interconnect ML2d (a line of ground potential GND) through contact hole CH1, metal interconnect ML1c and via hole VH1. One end portion of N-type active layer NA2 (the source of N-channel MOS transistor 14') is connected to metal interconnect ML2e (a line of ground potential GND) through contact hole CH14, metal interconnect ML1j and via hole VH8.

A region (the drain of N-channel MOS transistor 13 and the source of N-channel MOS transistor 15) between gate electrodes GE6 and GE7 of N-type active layer NA1 is connected to metal interconnect ML1a through contact hole CH2, one end portion of P-type active layer PA1 is connected to metal interconnect ML1a through contact hole CH7 and local interconnect LL2 is connected to metal interconnect ML1a through contact hole CH10. A region (the drain of N-channel MOS transistor 14 and the source of N-channel MOS transistor 16) between gate electrodes GE6 and GE7 of N-type active layer NA2 is connected to metal interconnect ML1b through contact hole CH13, one end portion of P-type active layer PA2 is connected to metal interconnect ML1b through contact holes CH8 and local interconnect LL1 is connected to metal interconnect ML1b through contact hole CH5.

Gate electrode GE3 is connected to metal interconnect ML3 (word line WL) through contact hole CH3, metal interconnect ML1f, via hole VH4, metal interconnect ML2f and vial hole VH9. Gate electrode GE6 is connected to metal interconnect ML3 (word line WL) through contact hole CH12, metal interconnect ML1g, via hole VH5, metal interconnect ML2g and vial hole VH10.

The other end portion of N-type active layer NA1 is connected to metal interconnect ML2b (bit line BL) through contact hole CH4, metal interconnect ML1h and via hole VH6. The other end portion of N-type active layer NA2 is connected to metal interconnect ML2c (bit line/BL) through contact hole CH11, metal interconnect ML1e and via hole VH3.

In the fourth embodiment, N-type active layer NA is placed in the middle, not only are N-channel MOS transistors 13 and 13' formed on the one side thereof, but N-channel MOS transistors 14 and 14' are also formed on the other side, and not only word line WL is formed in the X direction, but bit lines BL and /BL are also formed in the Y direction. Therefore, a shape of the memory cell can be long from side to side, thereby enabling bit lines BL and /BL shorter in length. Accordingly, improvements can be achieved on a speed in a read/write operation and reduction in power consumption since capacities of bit lines BL and /BL and values of interconnect resistance thereof can be smaller.

Furthermore, directions of the gate electrodes of all transistors 11 to 13, 13', 14, 14', 15 and 16 are the same as each other, fluctuations in characteristic caused by fluctuations in parameters in fabrication such as misalignment of a mask can be restricted to low levels and furthermore easy control of a finish size of a gate length can be realized.

Furthermore, not only is N-type active layer NA1 of N-channel MOS transistors 13 and 13' placed on a straight line, but N-type active layer NA2 of N-channel MOS transistors 14 and 14' is also placed on a straight line. Therefore, in order to invert hold data in storage nodes N1 and N2, while it is required that an .alpha.-particle flies in the Y direction in a horizontal plane including the body regions of N-channel MOS transistors 13, 13', 14 and 14' and in addition strikes body regions of N-channel MOS transistors 13 and 13', 14 or 14', a probability of such a collision is very low. Accordingly, it can be prevented from occurring that hold data in storage nodes N1 and N2 is inverted, thereby enabling improvement on soft error resistance.

Fifth Embodiment

FIG. 8 is a circuit diagram showing a configuration of a memory cell 21 of SRAM according to a fifth embodiment of the present invention. In FIG. 8, an aspect in which the memory cell 21 is different from memory cell 1 of FIG. 2 is that N-channel MOS transistors 13' and 14' are deleted therefrom, but P-channel MOS transistors 11' and 12' are added thereto.

P-channel MOS transistors 11' and 11 are connected in series between a line of power supply potential VDD and storage node N1 and the gates thereof are connected to storage node N2. P-channel MOS transistors 12' and 12 are connected in series between a line of power supply potential VDD and storage node N2 and the gates thereof are connected to storage node N1. N-channel MOS transistor 13 is connected between a line of ground potential GND and storage node N1 and the gate thereof is connected to storage node N2. N-channel MOS transistor 14 is connected between a line of ground potential GND and storage node N2 and the gate thereof is connected to storage node N1.

N-channel MOS transistors 11, 11' and 13 constitute an inverter giving an inverted signal of a signal held in storage node N2 to storage node N1. N-channel MOS transistors 12, 12' and 14 constitute an inverter giving an inverted signal of a signal held in storage node N1 to storage node N2. The other parts of the configuration and operation are the same as corresponding parts of the configuration and operation of memory cell 1 of FIG. 2; therefore none of descriptions thereof is repeated.

In the fifth embodiment, not only are P-channel MOS transistors 11 and 11' connected in series between storage node N1 and the line of power supply potential VDD, but two P-channel MOS transistors 12 and 12' are also connected in series between storage node N2 and the line of power supply potential VDD. Accordingly, since capacities of storage nodes N1 and N2 can be larger compared with a prior art practice, it can be prevented from occurring that logic levels of storage nodes N1 and N2 are inverted by electrons generated by .alpha.-particle radiation. Furthermore, in a case where memory cell 21 is formed on an SOI substrate, unless one .alpha.-particle passes through the body regions of two P-channel MOS transistors (for example, 11 and 11') in a non-conductive state, storage data is not inverted, therefore, the storage data can be harder to be inverted compared with a prior art case where if one .alpha.-particle passed through one P-channel MOS transistor (for example, 81), storage data was inverted, thereby enabling improvement on soft error resistance.

Sixth Embodiment

FIG. 9 is a circuit diagram showing a configuration of a memory cell 22 of SRAM according to a sixth embodiment of the present invention. In FIG. 9, an aspect in which memory cell 22 is different from memory cell 1 of FIG. 2 is that P-channel MOS transistors 11' and 12' are added thereto.

P-channel MOS transistors 11' and 11 are connected in series between a line of power supply potential VDD and storage node N1 and the gates thereof are both connected to storage node N2. P-channel MOS transistors 12' and 12 are connected in series between a line of power supply potential VDD and storage node N2 and the gates thereof are both connected to storage node N1.

MOS transistors 11, 11', 13 and 13' constitute an inverter giving an inverted signal of a signal held in storage node N2 to storage node N1. MOS transistors 12, 12', 14 and 14' constitute an inverter giving an inverted signal of a signal held in storage node N1 to storage node N2. The other parts of the configuration and operation are the same as corresponding parts of the configuration and operation of memory cell 1 of FIG. 2; therefore none of descriptions thereof is repeated.

In the sixth embodiment, the same effect as in the first and fifth embodiment is obtained.

Seventh Embodiment

FIGS. 10A and 10B are plan views showing a layout of a memory cell of SRAM according to a seventh embodiment of the present invention and to be compared with FIGS. 5A and 5B. The memory cell has the same configuration as memory cell 22 of FIG. 9, including P-channel MOS transistors 11, 11', 12 and 12'; and N-channel MOS transistors 13, 13', 14, 14' 15 and 16. The memory cell is formed on an SOI substrate.

Referring to FIGS. 10A and 10B, an aspect in which the memory cell is different from memory cell of FIGS. 5A and 5B is that gate electrodes GE6 and GE7 are added thereto and each of P-type active layers PA1 and PA2 are formed in the shape of a letter L.

Gate electrodes GE6 and GE7 are formed on a surface of N-type active layer NA and extend in the X direction of the figure. One end portions of gate electrodes GE6 and GE7 are connected to the other end portions of respective electrodes GE4 and GE5. The other end portions of electrodes GE6 and GE7 are facing each other. P-type active layer PA1 is formed on a surface of N-type active layer NA in the shape of a letter of L so as to traverse gate electrodes GE4 and GE6. P-type active layer PA2 is formed on the surface of N-type active layer NA in the shape of a letter of L so as to traverse gate electrodes GE5 and GE7. Gate electrodes GE4 and P-type active layer PA1 constitute P-channel MOS transistor 11' and gate electrodes GE6 and P-type active layer PA1 constitute P-channel MOS transistor 11. Gate electrodes GE5 and P-type active layer PA2 constitute P-channel MOS transistor 12' and gate electrodes GE7 and P-type active layer PA2 constitute P-channel MOS transistor 12.

One end portion of P-type active layer PA1 (the source of P-channel MOS transistor 11') is connected to metal interconnect ML1g (a line of power supply potential VDD) through contact hole CH9. The other end portion of P-type active layer PA1 (the drain of P-channel MOS transistor 11) is connected to metal interconnect ML1a (storage node N1) through contact hole CH10. One end portion of P-type active layer PA2 (the source of P-channel MOS transistor 12') is connected to metal interconnect ML1g (a line of power supply potential VDD) through contact hole CH12. The other end portion of P-type active layer PA2 (the drain of P-channel MOS transistor 12) is connected to metal interconnect ML1b (storage node N2) through contact hole CH11. The other part of the configuration is the same as corresponding part of the configuration of the memory cell of FIGS. 5A and 5B; therefore none of descriptions thereof is repeated.

In the seventh embodiment, each set of the gate electrodes GE2 and GE5 of N-channel MOS transistors 13 and 13', the gate electrodes GE3 and GE5 of N-channel MOS transistors 14 and 14', the gate electrodes GE6