Semiconductor memory device Number:6,828,612 from the United States Patent and Trademark Office (PTO) owispatent

Title: Semiconductor memory device

Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell.multidot.two cells/bit method has a twin cell structure employing a one-intersection 6F.sup.2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

Patent Number: 6,828,612 Issued on 12/07/2004 to Miyatake,   et al.

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Inventors:	Miyatake; Shinichi (Ome, JP); Kajigaya; Kazuhiko (Iruma, JP); Miyazawa; Kazuyuki (Hidaka, JP); Sekiguchi; Tomonori (Tama, JP); Takemura; Riichiro (Tokyo, JP); Sakata; Takeshi (Hino, JP)
Assignee:	Hitachi, Ltd. (Tokyo, JP) Hitachi ULSI Systems Co., Ltd. (Tokyo, JP) Elpida Memory, Inc. (Tokyo, JP)
Appl. No.:	388639
Filed:	March 17, 2003

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Foreign Application Priority Data

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Mar 15, 2002 [JP]			2002-071254

Current U.S. Class:	257/296 ; 365/149; 365/189.05
Field of Search:	257/296 365/149,189.05

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References Cited [Referenced By]

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U.S. Patent Documents

	1502334		July 1924		Cain
	2002/0003728		January 2002		Honigschmid et al.
	2003/0039158		February 2003		Horiguchi et al.

Foreign Patent Documents

	54-28252		Sep., 1979		JP
	55157194		Dec., 1980		JP
	61034790		Feb., 1986		JP
	07130172		May., 1995		JP
	08222706		Aug., 1996		JP
	2001-143463		May., 2001		JP

Primary Examiner: Ngo ; Ngan V.
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP

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Claims

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What is claimed is:

1. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit-line pair; a sense amplifier connected to said bit-line pair and amplifying a potential of said bit-line pair: a data-line pair for transmitting the potential of said bit-line pair; and a switch circuit between said bit-line pair and said data-line pair, wherein one of said bit-line pair is connected to said first dynamic memory cell and the other of said bit-line pair is connected to said second dynamic memory cell, and wherein said switch circuit includes a pair of transistors each having a gate connected to said bit-line pair and a source-drain path connected to said data-line pair.

2. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit line pair; a sense amplifier connected to said bit-line pair and amplifying a potential of said bit-line pair; a data-line pair for transmitting the potential of said bit-line pair; and a switch circuit between said bit-line pair and said data-line pair, wherein one of said bit-line pair is connected to said first dynamic memory cell and the other of said bit-line pair is connected to said second dynamic memory cell, and wherein, said switch circuit is controlled so that before said sense amplifier starts amplifying a readout signal read out from said first and second dynamic memory cells, said readout signal starts being transmitted to said data-line pair.

3. The semiconductor memory device according to claim 2, wherein, before said readout signal read out to said bit-line pair is amplified by said sense amplifier, the signal transmitted to said data-line pair starts being amplified by the amplifier connected to said data line pair.

4. The semiconductor memory device according to claim 1 or 2, wherein said first and second dynamic memory cells are controlled by the same word line.

5. The semiconductor memory device according to claim 1 or 2, wherein said first and second dynamic memory cells are controlled by a plurality of word lines.

6. The semiconductor memory device according to claim 1 or 2, wherein the signal read out from said first and second dynamic memory cells includes complementary data corresponding to a logic "1" and a logic "0".

7. The semiconductor memory device according to claim 3, wherein said amplifier is composed of a differential amplifier in which a compensation circuit, which operates to compensate characteristic difference in a pair transistor receiving a differential input, is added.

8. The semiconductor memory device according to claim 3, wherein said amplifier is composed of a differential amplifier including a pair transistor, and each gate of said pair transistor is formed in a ring shape to reduce the characteristic difference in said pair transistor receiving a differential input.

9. The semiconductor memory device according to claim 1, wherein said pair of transistors constitutes a differential amplifier.

10. The semiconductor memory device according to claim 2, wherein said switch circuit is composed of a differential amplifier.

11. The semiconductor memory device according to claim 9 or 10, wherein said differential amplifier has a compensation circuit added therein, the compensation circuit operating to compensate the characteristic difference in the pair transistor receiving a differential input.

12. The semiconductor memory device according to claim 9 or 10, wherein said differential amplifier includes a pair transistor receiving a differential input, and each gate of said pair transistor is formed in a ring shape to reduce the characteristic difference in said pair transistor.

13. The semiconductor memory device according to claim 1 or 2, wherein said memory cells are arranged in matrix at positions corresponding to the intersections between said bit-line pair and a word line forming a gate electrode of said transistor, and when a half pitch of said word line is defined as F, a pitch of each bit line of said bit-line pair is larger than 2F and smaller than 4F.

14. The semiconductor memory device according to claim 13, wherein an active region in a substrate, on which a source, channel and drain of each of said transistors are formed, is obliquely formed relative to a direction of said bit-line pair.

15. The semiconductor memory device according to claim 1 or 2, wherein parasitic capacitance of one bit line of said bit-line pair is five times as large as or less than capacitance of said capacitor.

16. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit line pair; a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage; a data-line pair for transmitting signals of said bit-line pair; and a switch circuit connected between said bit-line pair and said data-line pair, wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit line pair is connected to said second dynamic memory cell, and wherein a level of said first voltage or said second voltage is applied to a back-gate region of said transistor.

17. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit-line pair; a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage; a data-line pair for transmitting signals of said bit-line pair; and a switch circuit connected between said bit-line pair and said data-line pair, wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell, and wherein a voltage lower than said first voltage or higher than said second voltage is applied to a back-gate region of said transistor.

18. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit-line pair; a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage; a data-line pair for transmitting signals of said bit-line pair; and a switch circuit connected between said bit-line pair and said data-line pair, wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell, wherein a level of said second voltage is applied to a back-gate region of said transistor, and wherein a precharge potential of said bit-line pair is set to said first voltage.

19. A semiconductor memory device comprising: a first and second dynamic memory cells each including one transistor and one capacitor, both of the first and second dynamic memory cells being to be selected; a bit-line pair; a sense amplifier which is connected to said bit-line pair and to which a first voltage and a second voltage smaller than said first voltage are applied to amplify a potential of said bit-line pair in directions of said first voltage and said second voltage; a data-line pair for transmitting signals of said bit-line pair; and a switch circuit connected between said bit-line pair and said data-line pair, wherein one bit line of said bit-line pair is connected to said first dynamic memory cell and the other bit line of said bit-line pair is connected to said second dynamic memory cell, wherein a voltage higher in level than said second voltage is applied to a back-gate region of said transistor, and wherein a precharge potential of said bit-line pair is set to said first voltage.

20. The semiconductor memory device according to any one of claims 16, 17, 18 and 19, wherein said first and second dynamic memory cells are controlled by the same word line.

21. The semiconductor memory device according to any one of claims 16, 17, 18 and 19, wherein said first and second dynamic memory cells are controlled by a plurality of word lines.

22. The semiconductor memory device according to any one of claims 16, 17, 18, and 19, wherein said memory cells are arranged in matrix at positions corresponding to the intersections between said bit-line pair and a word line forming a gate electrode of said transistor, and when a half pitch of said word line is defined as F, a pitch of each bit line of said bit-line pair is larger than 2F and smaller than 4F.

23. The semiconductor memory device according to claim 22, wherein an active region in a substrate, on which a source, channel and drain of said transistor are formed, is obliquely formed relative to a direction of said bit-line pair.

24. The semiconductor memory device according to any one of claims 16, 17, 18 and 19, wherein a potential of a back-gate of a transistor other than those forming said memory cells is set to a level of said second voltage or lower, or a level of said first voltage or higher.

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Description

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BACKGROUND OF THE INVENTION

The present invention relates to s semiconductor memory device, and more particularly to a technique effectively applied to a semiconductor memory device such as a DRAM etc. adopting a connection method, which is called a two cells/bit method employing a so-called one-intersection cell.

According to examinations by the inventors of the present invention, the following techniques are available for the DRAM as an example of the semiconductor memory device.

For example, with respect to the DRAM, there are an open bit-line method and a folded bit-line method as methods of connecting a sense amplifier and a bit-line pair. The former open bit-line method is one in which two bit lines to be connected to one sense amplifier are separately connected on both sides to put the sense amplifier therebetween. By the open bit-line method, a so-called one-intersection memory cell structure is formed in which memory cells MC are connected to all of the intersections between the bit-line pair BL and /BL and a word line WL. The theoretical minimum cell area of the one-intersection memory cell is 4F.sup.2 (2F.times.2F) in terms of a memory-cell-area representing method employing the value "F" of half the pitch of the word line. As a typical example of the one-intersection memory cell, the one having an area of about 6F.sup.2 (2F.times.3F) has been reported in the academic conference. The latter folded bit-line method is one in which two bit lines to be connected to one sense amplifier are folded and connected in the same direction relative to the sense amplifier. In the folded bit-line method, a so-called two-intersection memory cell structure is formed in which the memory cells MC are connected to half of the intersections between the bit-line pair BL and /BL and the word line WL. The theoretical minimum cell area of the two-intersection memory cell is 8F.sup.2 (4F.times.2F) in terms of the memory-cell-area representing method employing the value "F" of half the pitch of the word line.

The former open bit-line method has a high risk of obtaining error information from the memory cell since the fluctuation in a word line potential is applied to only one of the bit-line pair due to parasitic capacitance applied between the word line and the bit line. In contrast to this, the latter folded bit-line method can cancel the noise between the bit lines since the fluctuation in a word line potential (noise) is equally applied to both of the bit-line pair via the parasitic capacitance applied between the word line and the bit line. Consequently, the folded bit-line method is one suitable for the DRAM that detects and amplifies the voltage of small signal from the memory cell and, for example, is more frequently used in the DRAM of 64 kbit or lager.

Meanwhile, in DRAM employing the connection method called a two cells/bit method, there is a connection method generally called a two-intersection cell.multidot.two cells/bit method among the connection methods of the memory cells arranged at the intersections between the word lines and the bit lines. This two-intersection cell.multidot.two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a first word line; a second memory cell is connected to the intersection between the other of the bit-line pair and a second word line; and the two memory cells correspond to one bit.

Additionally, a memory cell of the one-intersection cell.multidot.two cells/bit method is also proposed similarly. This one-intersection cell.multidot.two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a word line; a second memory cell is connected to the intersection between the other of the bit-line pair and the same word line; and the two memory cells correspond to one bit.

Note that as techniques concerning the above-mentioned DRAM employing the one-intersection cell.multidot.two cells/bit method, there are recited, for example, Japanese Patent Laid-Open Nos. 61-34790, 55-157194, 8-222706 (U.S. Pat. No. 5,661,678 corresponding thereto), and 2001-143463 (U.S. Pat. No. 6,344,990 corresponding thereto) and Japanese Patent Publication No. 54-28252 (GB patent No. 1,502,334 corresponding thereto), etc. Also, as a technique concerning the DRAM of the two-intersection cell.multidot.two cells/bit method, Japanese Patent Laid-Open No. 7-130172 is disclosed.

SUMMARY OF THE INVENTION

Meanwhile, as a result of examination by the inventors about the techniques for the DRAM as described above, the followings have been found.

For example, in a one cell-bit method, since the signal amount on a "H" side is decreased depending on a refresh period, a bit-line signal amount before the amplification of the bit line cannot be used in a high-speed reading method that is read out by a direct sense method. Also, since the one-intersection cell method of the one cell/bit must employ the open bit-line method, array noises become a problem, whereby a reduction in the signal amount is an object to be solved.

As a premise of the present invention examined by the inventors, the two cells/bit method employing the above-mentioned 8F.sup.2 (4F.times.2F) will be described with reference to FIGS. 22 and 23. FIG. 22 is a connection diagram showing the state of the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers. FIGS. 23A and 23B are a schematic plan view and a schematic sectional view which show a twin cell structure of the memory cell, respectively.

In the two cells/bit method employing the 8F.sup.2 (4F.times.2F), the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers are shown in FIG. 22, wherein bit lines BL and /BL are not adjacent to each other and alternately arranged and these two lines are connected to a sense amplifier SA as a bit-line pair BL and /BL. There are a plurality of bit-line pairs BL and /BL connected in this manner, and the sense amplifiers SA are alternately connected to and arranged on the right and left ends of each bit-line pair. Further, each memory cell MC is arranged at positions corresponding to half the ones of the intersections between the bit-line pair BL and /BL and the word line WL.

The two cells/bit method employing the 8F.sup.2 (4F.times.2F) is, as shown in FIG. 23A, constituted to include: a plurality of folded-type bit-line pairs BL and /BL arranged in parallel to each other; a plurality of word lines WL orthogonal to the plurality of bit-line pairs BL and /BL; memory cells MC arranged at position corresponding to half the ones of the intersections between the respective bit-line pairs BL and /BL and the respective word lines WL; and the like. Also, active regions AA on the silicon substrate, in which the source, channel and drain of the transistor of the memory cell MC are formed, are formed in parallel to the bit-line pairs BL and /BL. Note that a portion corresponding to one cell of the memory cell MC is shown by the dash lines.

Further, in the sectional structure thereof, as shown in FIG. 23B, the transistor of the memory cell MC is formed on the active region AA in a P well PWEL of the silicon substrate, wherein: a gate electrode is connected to the word line WL; a source electrode is connected via a storage node contact SCT to a storage node SN to be the other of the electrode of the capacitor; and a drain electrode is connected to the bit-line pair BL and /BL via a bit contact BCT. The storage node SN is arranged at the above and opposite point thereof, and constitutes a capacitor between other plurality of capacitors and a plate PL to be one of the electrode common thereto.

Particularly, in the structure of the two cells/bit method employing the 8F.sup.2 (4F.times.2F), when the half pitch of the word line WL is defined as F, the pitch of the bit-line pair BL and /BL is 2F and that of the word line WL is 2F. Since one memory cell is formed with the pitch equivalent to that of the two word lines WL, the area of one cell of the memory cell is 8F.sup.2 and that of two cells/bit is 16F.sup.2. Accordingly, it becomes a problem to reduce the increase of the area of the memory cell per one bit in face of the recent advancement of higher integration.

Consequently, an object of the present invention is to provide a semiconductor memory device such as DRAM etc., which can realize high integration and ultra-high speed operation and largely reduce power consumption during a information maintaining period, by suppressing an increase in the area of a memory cell, obtaining ultra-high speed reading, and further achieving a long refresh period at the time of a self refresh.

The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

The typical ones of the inventions disclosed in this application will be briefly described as follows.

More specifically, a semiconductor memory device according to the present invention comprises: a plurality of folded-type bit-line pairs arranged in parallel to each other; a plurality of word lines orthogonal to these; and dynamic memory cells each composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between the plurality of bit-line pairs and the plurality of word lines, wherein one electrode of the capacitor is connected to a common electrode together with those of other plurality of capacitors arranged in matrix, the other electrode thereof is connected to a source electrode of the transistor, a drain electrode of the transistor is connected to the bit-line pair, and a gate electrode thereof is connected to the word line, and wherein, in a structure in which there is connected a circuit for performing the writing of memory information to the memory cell, or the reading of memory information from the memory cell, or the refresh of the memory information of the memory cell in response to the plurality of bit-line pairs, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F when a half pitch of the word line is defined as F. Alternatively, the semiconductor memory device is one which includes a plurality of word lines not orthogonal to the plurality of bit-line pairs.

Also, a semiconductor memory device according to the present invention comprises: a plurality of dynamic memory cells which is composed of one transistor and one capacitor and is to be simultaneously selected; a bit-line pair to which the plurality of selected memory cells are connected; a sense amplifier for amplifying the potential of the bit-line pair to a predetermined "H" and "L" levels; and a pair of MOSFETs in which each of the bit-line pairs is inputted to gates thereof and drains thereof are connected to the data-line pair. In this structure, the plurality of memory cells are simultaneously selected, and signals are read out from the plurality of memory cells to the bit-line pair corresponding to the plurality of memory cells, and the signals read out to the bit-line pair are transmitted to the data line before the amplification by the sense amplifier connected to the bit-line pair.

Also, the semiconductor memory device according to the present invention is one in which: a plurality of dynamic memory cells each composed of one transistor and one capacitor are simultaneously selected; complementary signals are read out to the bit-line pair corresponding to the memory cells; and the potential of the bit-line pair is amplified to the predetermined "H" and "L" levels by the sense amplifier connected to the bit-line pair, wherein the potential of the substrate, on which the back-gate of the transistor is formed, is equal to either of the predetermined "H" or "L" level. Alternatively, the potential of the substrate, on which the back-gate of the transistor is formed, is set to be lower than the voltage of the predetermined "H" level or higher than that of the predetermined "L" level. Alternatively, the semiconductor memory device according to the present invention is one obtained by combining them, that is, one in which the precharge potential of the bit-line pair is made equal to a predetermined "L" or "H" level which is reverse to the potential of the substrate, or equal to a predetermined "L" or "H" level on the side having larger one of the potential difference between the potential of the substrate and its precharge potential.

More specifically, the semiconductor memory device according to the present invention realizes the method of the high-speed reading by using, as a two cells/bit method, the one-intersection cell which is advantageous to high integration. Note that the two-intersection cell too can be used as the two cells/bit method. However, it is not suitable for the high integration, and further the waste occurs such that two of the word lines must be simultaneously selected.

Also, in the present invention, the two memory cells of the DRAM are used as one bit and operated by the folded bit-line method in spite of the one-intersection cell. This can reduce the array noise, whereby it becomes sufficient to start up just one word line to be selected.

Furthermore, the "L" data are certainly stored in either of the two memory cells. The "H"/"L" signal is complementarily outputted to the bit-line pair at the time of the readout. However, in the case where the "H" signal is considered to be the reference of the "L" signal, if the "L" signal amount is ensured, its signal can be read out. This "L" data is transmitted to the main amplifier before the operation of the sense amplifier by the direct sense method, and then sensed. It is unnecessary to completely write the power voltage also in the "H" writing voltage. If the "L" data are complete, it can be easily read out. This allows for the large improvement of the refresh characteristic, the improvement in the soft error resistance, and the low-voltage high-speed operation.

Also, the occupancy of the memory cell is 1/2 due to the two cells/bit method. However, in the case of the one-intersection cell, the memory cell of about 12F.sup.2 (twice of 6F.sup.2) is obtained in a typical example. Therefore, the increase of the cell area can be suppressed to about 1.5 times as small as that of the two cells/bit method using the 8F.sup.2 cell with the same F value. Furthermore, in the ultra-high speed DRAM, the number of array divisions is increased and the occupancy of the cell becomes about 30%. Therefore, the increase of the cell area can be reduced to about 15%.

Further, if this method is applied to the two cells/bit method employing a VDL precharge method which is effective to the low-voltage operation (e.g., bit line amplitude of 1.2 V or lower), the dummy cell for the reference becomes unnecessary, thereby using the "L" signal amount by 100%. Also, the voltage-increasing power source (VPP) becomes unnecessary for the control of the precharge circuit, and the high-speed bit-line amplification operation can be performed even if a sense-amplifier overdrive method is not used.

As described above, according to the semiconductor memory device of the present invention, (i) even if the "H" data is reduced by the refresh, the "L" data is left. Therefore, it is also possible to operate the main amplifier by the direct sense of the "L" signal. (ii) The readout of the "L" data is more rapid than that of the "H" data, thereby allowing for the high-speed and stable operation. (iii) Since the full writing of the "H" data is unnecessary, the word-line-voltage increasing level can be reduced. (iv) The current consumption in the VPP voltage-increasing circuit can be reduced and the noise generated at the time of operating the VPP generator circuit can be reduced. (v) The bit-line pair has a completely symmetric structure owing to the operation of the folded bit-line method and the noise in the array including the non-selected word-line noise can be completely canceled even in the case of the one-intersection memory cell. (vi) It is possible to largely improve the period of the refresh time and the soft error resistance by the readout of the "L" data.

As a result, the "L" data are certainly stored in either of the cells in the two cells/bit method. Accordingly, data on the side of the "L" has the readout speed higher than the "H" data, thereby allowing for ensuring the signal amount more stably. Additionally, in the operation of the folded bit-line method, the bit lines are arranged on the same array side, thereby allowing for canceling the substrate noises and the plate noises. Furthermore, since the wrap-around noises form the non-selected word line is also caused on the bit-line pair, the loss of the signal amount is prevented. Due to the advantages as described above, it is possible to obtain the stable bit-line signal on the "L" side. If it is directly read out, the data can be transmitted to the output buffer before the driving of the bit line.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1A is a schematic plan view showing a twin cell structure of a memory cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view showing a twin cell structure of a memory cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 2A is a schematic plan view showing another twin cell structure of a memory cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 2B is a schematic cross-sectional view showing another twin cell structure of a memory cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 3A is a connection diagram showing a connection configuration between bit-line pairs and sense amplifiers in a semiconductor memory device according an embodiment of the present invention.

FIG. 3B is a connection diagram showing another connection configuration between bit-line pairs and sense amplifiers in a semiconductor memory device according an embodiment of the present invention.

FIG. 4A is a connection diagram showing a connection configuration of word lines in a semiconductor memory device according an embodiment of the present invention.

FIG. 4B is a connection diagram showing another connection configuration of word lines in a semiconductor memory device according an embodiment of the present invention.

FIG. 5A is a waveform diagram showing a direct sense

+twin cell method in a semiconductor memory device according to an embodiment of the present invention.

FIG. 5B is a circuit diagram showing a direct sense+twin cell method in a semiconductor memory device according to an embodiment of the present invention.

FIG. 6A is a waveform diagram showing another direct sense+twin cell method in a semiconductor memory device according to an embodiment of the present invention.

FIG. 6B is a circuit diagram showing another direct sense+twin cell method in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7A is a connection diagram showing a simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7B is a connection diagram showing another simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7C is a connection diagram showing another simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7D is a connection diagram showing another simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7E is a connection diagram showing another simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7F is a connection diagram showing another simultaneous selection method of a plurality of memory cells in a semiconductor memory device according to an embodiment of the present invention.

FIG. 8A is a circuit diagram showing a preamplifier of a main amplifier with a threshold-voltage offset compensation function in a semiconductor memory device according to an embodiment of the present invention.

FIG. 8B is a circuit diagram showing a latch-type amplifier of a main amplifier with a threshold-voltage offset compensation function in a semiconductor memory device according to an embodiment of the present invention.

FIG. 9 is a waveform diagram showing an operation of a main amplifier with a threshold-voltage offset compensation function in a semiconductor memory circuit according to an embodiment of the present invention.

FIG. 10 is a characteristic diagram showing an effect of threshold-voltage offset compensation in a semiconductor memory device according to an embodiment of the present invention.

FIG. 11 is a circuit diagram showing a direct sense circuit with a threshold-voltage offset compensation function in a semiconductor memory device according to an embodiment of the present invention.

FIG. 12A is a circuit diagram showing the principal part of the compensation operation of a direct sense circuit with a threshold-voltage offset compensation function in a semiconductor memory device according to an embodiment of the present invention.

FIG. 12B is a waveform diagram showing the compensation operation of a direct sense circuit with a threshold-voltage offset compensation function in a semiconductor memory device according to an embodiment of the present invention.

FIG. 13A is a plan view showing a layout of a pair of MOSFETs with a differential amplifier input in a semiconductor memory device according to an embodiment of the present invention.

FIG. 13B is a plan view showing another layout of a pair of MOSFETs with a differential amplifier input in a semiconductor memory device according to an embodiment of the present invention.

FIG. 14A is a circuit diagram showing a potential relationship upon holding memory-cell information charges in a semiconductor memory device according to an embodiment of the present invention.

FIG. 14B is a circuit diagram showing a potential relationship upon holding memory cell data charges in a semiconductor memory device according to an embodiment of the present invention.

FIG. 14C is a circuit diagram showing a potential relationship upon holding a memory cell data charge in a semiconductor memory device according to an embodiment of the present invention.

FIG. 15A is a waveform diagram showing a potential relationship upon holding memory cell data charges in a semiconductor memory device according to an embodiment of the present invention.

FIG. 15B is a waveform diagram showing a potential relationship upon holding memory cell data charges in a semiconductor memory device according to an embodiment of the present invention.

FIG. 15C is a waveform diagram showing a potential relationship upon holding memory cell data charges in a semiconductor memory device according to an embodiment of the present invention.

FIG. 16 is a waveform diagram showing an operation waveform and a potential relationship (substrate potential=0 V) upon reading memory cell information in a semiconductor memory device according to an embodiment of the present invention.

FIG. 17 is a waveform diagram showing an operation waveform and a potential relationship (substrate potential=0.1 V) upon reading memory cell information in a semiconductor memory device according to an embodiment of the present invention.

FIG. 18A is a characteristic diagram showing a relationship of a readout signal amount to a storage node potential upon being read in a semiconductor memory device according to an embodiment of the present invention.

FIG. 18B is a circuit diagram showing a relationship of a readout signal amount to a storage node potential upon being read in a semiconductor memory device according to an embodiment of the present invention.

FIG. 19 is a waveform diagram showing a relationship of a readout signal amount to a storage node potential upon being read in a semiconductor memory device according to an embodiment of the present invention.

FIG. 20 is a circuit diagram showing a back gate potential of a transistor in a semiconductor memory device according to an embodiment of the present invention.

FIG. 21 is a characteristic diagram showing a current-voltage characteristic of a diode in a semiconductor memory device according to an embodiment of the present invention.

FIG. 22 is a connection diagram showing a connection configuration between bit-line pairs orthogonal to word lines and sense amplifiers in a semiconductor memory device examined as the premise of the present invention.

FIG. 23A is a schematic plan view showing a twin cell structure of a memory cell in a semiconductor memory device examined as the premise of the present invention.

FIG. 23B is a schematic cross-sectional view showing a twin cell structure of a memory cell in a semiconductor memory device examined as the premise of the present invention.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same functions are denoted by the same reference symbols throughout the drawings for describing the embodiment and the repetitive description thereof will be omitted.

The semiconductor memory device according to an embodiment of the present invention is applied to, for example, a DRAM employing a one-intersection two cells/bit method, and, though not particularly limited, is formed on one semiconductor substrate like single crystal silicon by a known semiconductor manufacturing technique. Particularly, the DRAM according to the embodiment is characterized by: 1. a twin cell structure employing a one-intersection 6F.sup.2 cell; 2. a direct sense+twin cell method; and 3. a substrate potential VSS+twin cell method, etc. and they will be sequentially described below.

1. Twin cell structure employing one-intersection 6F.sup.2 cell

1-1. Twin cell Structure of Memory Cell

FIGS. 1A and 1B are drawings showing a twin cell structure of a memory cell and are a schematic plan view and a schematic sectional view, respectively. Note that FIG. 1B is illustrated in view of a capacitor to be formed on the upper layer thereof in a sectional structure taken along the line b-b' in FIG. 1A and also an illustration of an insulating film is omitted. In this case, an example where the one-intersection 6F.sup.2 cell is used will be described.

As shown in FIG. 1, in the twin cell structure employing the one-intersection 6F.sup.2 cell, memory cells MC are arranged at positions corresponding to all of the intersections between the bit-line pairs BL and /BL and the word lines WL, the area of one cell is 6F.sup.2 (2F.times.3F), and the area of the two cells/bit is 12F.sup.2.

This twin cell structure comprises: a plurality of folded-type bit-line pairs BL and /BL arranged in parallel to each other; a plurality of word lines WL orthogonal to the plurality of bit-line pairs BL and /BL; dynamic type memory cells MC, which are composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between the plurality of bit-line pairs BL and /BL and the plurality of the word lines WL; and the like. Note that the portion corresponding to one cell of the memory cell MC is shown by the dash lines.

In the memory cell MC, the plate PL to be one electrode of the capacitor is connected to a common electrode together with one electrode of each of other plurality of capacitors arranged, in matrix, and a storage node SN to be the other electrode of the capacitor is connected to a source electrode of the transistor, and a drain electrode of the transistor is connected to the bit-line pair BL and /BL, and a gate electrode of the transistor is connected to the word line WL.

Particularly, in this twin cell structure, the bit-line pitch of the bit-line pair BL and /BL is larger than 2F and smaller than 4F when the half pitch of the word line WL is defined as F. The example where the pitch of the word line WL is 2F and those of the bit line BL and /BL are 3F is shown in FIG. 1A.

Active regions AA on the silicon substrate, in which the source, channel and drain of the transistor of the memory cell MC are formed, are obliquely formed relative to a direction of the bit-line pairs BL and /BL.

Also, the capacitor is formed above the bit-line pair BL and /BL via an insulating film. Additionally, a wiring layer forming the word line WL is composed of, for example, a laminated film of polysilicon and metal, or a metal film. A wiring layer for forming the bit-line pair is composed of, for example, a metal film.

More concretely, in the twin cell structure as shown in FIG. 1B, the transistor of the memory cell MC is formed on the active region AA in the P well PWEL of the silicon substrate, wherein: the gate electrode is connected to the word line WL; the source electrode is connected via the storage node contact SCT to the storage node SN to be the other electrode of the capacitor; and the drain electrode is connected via the bit contact BCT to the bit-line pair BL and /BL. The storage node SN is arranged at a position opposite to the upper portion thereof, and constitutes the capacitor between other plurality of capacitors and a plate PL to be one electrode common thereto.

Note that, though not shown, a circuit, which performs the writing of the memory information to the memory cell MC, the readout of the memory data from the memory cell MC, or the refresh of the memory information of the memory cell MC in response to the plurality of bit line pairs BL and /BL, is connected to the plurality of bit-line pairs BL and /BL.

1-2. Another twin Cell Structure of Memory Cell

FIGS. 2A and 2B show another twin cell structure of a memory cell, and are a schematic plan view and a schematic sectional view, respectively. Note that FIG. 2B is illustrated in view of a capacitor to be formed on the upper layer in a sectional structure taken along the line b-b' in FIG. 2A and an illustration of an insulating film is omitted. In this case, an example where the one-intersection 6F.sup.2 cell is used will be described.

As shown in FIGS. 2A and 2B, in the twin cell structure employing the one-intersection 6F.sup.2 cell, similarly to FIGS. 1A and 1B, the memory cells MC are arranged at positions corresponding to all of the intersections between the bit-line pairs BL and /BL and the word lines WL, and the area of one cell is 6F.sup.2 (2F.times.3F), and the area of the two cells/bit is 12F.sup.2. However, the structure in FIGS. 2A and 2B is different from that in FIGS. 1A and 1B in the arrangement of the bit-line pairs BL and /BL and the active regions AA relative to the word lines WL.

More specifically, the twin cell structure in FIGS. 2A and 2B is constituted to include: the plurality of folded-type bit-line pairs BL and /BL arranged in parallel to each other; the plurality of word lines WL not orthogonal to the plurality of bit-line pairs BL and /BL; the dynamic memory cells MC composed of one transistor and one capacitor and arranged in matrix at positions corresponding to the intersections between the plurality of bit-line pairs BL and /BL and the plurality of the word lines WL; and the like. In this structure, the plurality of word lines WL and the active regions AA are orthogonal, and the bit-line pairs BL and /BL are obliquely formed relative to the direction of the active regions AA.

Particularly, also in this twin cell structure, the pitch of the bit-line pair BL and /BL is larger than 2F and smaller than 4F when the half pitch of the word line WL is defined as F. The example, in which the pitch of the word line WL is 2F and that of each of the bit lines BL and /BL is 3F, is shown in FIGS. 2A and 2B. Since other structure is the same as that in FIGS. 1A and 1B, the detailed description thereof is omitted here.

1-3. Connection Configuration Between Bit-Line Pair and Sense Amplifier

FIGS. 3A and 3B are connection diagrams showing the connection configuration between the bit-line pairs and the sense amplifiers, and exemplify the cases where the bit-line pair is composed of the bit lines adjacent thereto and where the bit-line pair is composed of the bit lines not adjacent thereto, respectively.

As shown in FIG. 3A, in the case where the bit-line pair BL and /BL is composed of the adjacent bit lines, the bit lines BL and /BL are arranged side by side and these two bit lines function as a bit-line pair BL and /BL and are connected to the sense amplifier SA. There are the plurality of bit-line pairs BL and /BL connected in this manner and the sense amplifier SA is connected to each of them. These sense amplifiers SA are alternately arranged on the right and left ends of the bit-line pairs BL and /BL. Also, the memory cells MC are arranged at all of the intersections between the bit-lines BL and /BL and the word lines WL.

As shown in FIG. 3B, in the case where the bit-line pair BL and /BL is composed of the unadjacent bit lines, the bit lines BL and /BL are arranged every other line without adjacency, and these two bit lines function as a bit-line pair BL and /BL and are connected to the sense amplifier SA. There are the plurality of bit-line pairs BL and /BL connected in this manner and the sense amplifiers SA are alternately arranged and connected to the right and left ends of each of the bit-line pairs BL and /BL. For example, in FIG. 3B, a bit line BL(a), a bit line BL(b), a bit line /BL(a), a bit line /BL(b), . . . are arranged in this order, and the bit lines BL(a) and /BL(a) are connected to the sense amplifier SA(a) on the right end and the bit lines BL(b) and /BL(b) are connected to the sense amplifier SA(b) on the left end.

1-4. Connection Configuration of Word Line

FIGS. 4A and 4B are connection diagrams showing the connection configuration of the word lines, and respectively exemplify the cases where the word lines include main word lines and secondary word lines each having a backed structure, and where the word lines include main word lines and secondary word lines, the secondary word line being driven in response to the signal of the main word line.

As shown in FIG. 4A, in the case where the word lines WL include the main word lines MWL and secondary word lines SWL each having a backed structure, the word lines WL are constituted by: the secondary word lines SWL composed of a wiring layer for forming the gate electrode of the transistor of the memory cell MC; and the main word lines MWL which back the secondary word line SWL at several points and are composed of a wiring layer other than that of the secondary word line SWL. For example, in FIG. 4A, the secondary word line SWL is backed by the main word line MWL at every eight memory cells MC connected to the four bit-line pairs BL and /BL.

As shown in FIG. 4B, in the case where the word lines WL include main word lines MWL and secondary word lines SWL and the secondary word line SWL is driven in response to the signal of the main word line MWL, the word lines WL are formed by: the relatively long main word lines MLW; and the relatively short secondary word lines SWL which are driven by a driving circuit for receiving the signal of the main word line MWL and constitute the gate electrode of the transistor of the memory cell MC. For example, in FIG. 4B, a driving circuit including a gate circuit NAND is arranged at every eight memory cells MC connected to the four bit-line pairs BL and /BL, and each of the memory cells MC connected to the secondary word lines SWL is driven by the driving circuit. The signals from the main word line MWL and the driving control signal are inputted to the gate circuit NAND of the driving circuit.

According to the twin cell structure employing the one-intersection 6F.sup.2 cell as described above, the following advantages can be obtained.

(1) Because of the 6F.sup.2 cell structure, the area of the one bit is not more than 12F.sup.2. Therefore, the area of the memory cell MC is reduced by about 25% in comparison to that of the two cells of the 8F.sup.2 cell structure with the same F value. More specifically, if the pitch of the bit-line pair BL and /BL is smaller than 4F, there is the area-reducing effect thereof larger than that of the two cells of the 8F.sup.2 cell structure. In general, if the F values are equal, easiness of the fabricating of the memory cells MC is also equal.

(2) The simultaneous selection of the two memory cells connected to all of the bit-line pairs BL and /BL becomes possible by activating only one word line WL. In contrast, in the case of the 8F.sup.2, the activation of two word lines WL is needed. Accordingly, there are the advantages of the reduction in power noises and power consumption due to the reduction of a load current at the time of selecting the word line WL.

Also, the following advantages can be achieved in comparison to a method for enlarging the area of the memory cell MC to increase signal charge amounts (folded bit line/open bit line double method).

(1) In the operation of the folded bit line method, the completely symmetric structure thereof can be attained. This is because the memory cells MC are provided at all of the intersections between the bit-line pairs BL and /BL and the word lines WL. In this manner, it is possible to completely cancel array noises including the noises of the non-selected word line. Further, the bit-line capacitance including the capacitors is completely balanced also in amplifying the bit line. Accordingly, it is possible to realize the speed-up and stability of a reading operation from the memory cell MC.

(2) It is always possible to maintain data at both voltage levels of "H"/"L" regardless of the "0"/"1" of the data. This can provide high resistance to a junction leakage, so that margins at the high-speed (=high-temperature) operation can be enlarged. Further, since soft error resistance is improved, it is advantageous in applications to an ultra high-speed operation such as cache.

(3) It is always possible to simultaneously read both the signals of "H"/"L" regardless of "1"/"1" of the data. Accordingly, due to the small data pattern dependency, the stable and high-speed operation can be performed.

As described above, according to the twin cell structure employing the one-intersection 6F.sup.2 cell, it is possible to provide the minimum memory cell area among those that can realize the equivalent performance.

2. Direct sense+twin cell method

2-1. Direct sense+twin cell method

FIGS. 5A and 5B are views showing a direct sense+twin cell method, and illustrate a waveform diagram and a circuit diagram thereof, respectively.

As shown in FIGS. 5A and 5B, the direct sense+twin cell method is constituted so that: the word line WL and a column-selection line YS are almost simultaneously selected; a readout signal is transmitted to data-line pairs (local I/O lines LIO and /LIO and main I/O lines MIO and /MIO) before the amplification in the sense amplifier SA; and the amplification of global I/O lines GIO and /GIO is started before the amplification in the sense amplifier SA.

As shown in FIG. 5B, this direct sense+twin cell method has one transistor T and one capacitor Cs, and is constituted to include: a plurality of dynamic memory cells MC to be simultaneously selected; the bit-line pair BL and /BL to which the plurality of selected memory cells MC are connected; the sense amplifier SA which amplifies the potential of the bit-line pair BL and /BL to a predetermined "H" and "L" levels; and a pair of MOSFETs Q1 and Q2 having gates to which the respective bit-line pair BL and /BL are inputted and drains connected to the data-line pair (LIO and /LIO).

Furthermore, the drains of the pair of MOSFETs Q1 and Q2 is respectively connected to the sources of a pair of MOSFETs Q3 and Q4 whose gates are driven by the column-selection line YS, and the sources thereof are connected to the drain of a MOSFET Q5 commonly driven by a read-enable control line RE. Also, the drains of the pair of MOSFETs Q3 and Q4 are connected to the local I/O lines LIO and /LIO, respectively. Further, the source of the MOSFET 5 is connected to the ground potential VSS. These plurality of MOSFETs Q1 to Q5 functioning as a direct sense circuit are composed of a differential amplifier which transmits, to the local I/O lines LIO and /LIO, the signal being read from the bit-line pair BL and /BL.

The local I/O lines LIO and /LIO connected to the direct sense circuit are further connected to the main I/O lines MIO and /MIO via a pair of MOSFETs Q6 and Q7 driven by the read-enable control line REB. This main I/O lines MIO and /MIO are connected to a main amplifier MA and further connected to an output buffer OB via global I/O lines GIO and /GIO.

Also, the gates of the plurality of memory cells MC, each composed of one transistor T and one capacitor Cs and selected simultaneously, are connected to the same word line WL. Furthermore, the word line WL is connected to a driving circuit D, and the plurality of memory cells MC are controlled by the driving circuit D through the same word line WL. For example, as shown in FIG. 5B, the memory cell MC1 is connected to the intersection between one bit line BL of the bit-line pair and the word line WL1, and the memory cell MC2 is connected to the intersection between the other bit line /BL of the bit-line pair and the same word line WL1.

Note that parasitic capacitance Cb is included in the bit-line pair BL and /BL, and the parasitic capacitor Cb is set to about five times as large as the capacitance of the capacitor Cs or smaller. Also, the elements of parasitic resistance and parasitic capacitance are included also in the local I/O lines LIO and /LIO and the main I/O lines MIO and /MIO.

The direct sense+twin cell method has, as shown in FIG. 5A, a readout operation of: starting up the read-enable control line RE (the read-enable control line REB is started down); sequentially starting up the word line WL and the column-selection line YS to simultaneously select the plurality of memory cells MC; reading out the signal from the plurality of memory cells MC to the bit-line pair BL and /BL corresponding to the plurality of memory cells MC; and transmitting, to the local I/O lines LIO and /LIO and the main I/O lines MIO and /MIO, the signal read out at the bit-line pair BL and /BL before the amplification by the sense amplifier SA connected to the bit-line pair BL and /BL. The signal read out from the plurality of memory cells MC includes both pieces of complementary data corresponding to "1" and "0".

Additionally, before the signal read out at the bit-line pair BL and /BL is amplified by the sense amplifier SA, the amplification of the signal transmitted to the main I/O lines MIO and /MIO is started by the main amplifier MA connected to the main I/O lines MIO and /MIO. Then, the signal is transmitted from the main amplifier MA to the output buffer OB via the global I/O lines GIO and /GIO and outputted from the output buffer OB.

2-2. Another Direct Sense+Twin Cell Method

FIGS. 6A and 6B show another direct sense+twin cell method, and are a waveform diagram and a circuit diagram thereof, respectively.

As shown in FIGS. 6A and 6B, in another direct sense+twin cell method, similarly to FIGS. 5A and 5B, the word line WL and the column-selection line YS are almost simultaneously selected, the readout signal is transmitted to the data-line pair (local I/O lines LIO and /LIO and main I/O lines MIO and /MIO) before the amplification by the sense amplifier SA, and the amplification of the global I/O lines GIO and /GIO is started before the amplification by the sense amplifier SA. However, the constitution in FIGS. 6A and 6B is difference from that in FIGS. 5A and 5B in the control of the memory cell MC by the word line WL.

More specifically, in the direct sense+twin cell method shown in FIG. 6, each gate of the plurality of memory cells MC selected simultaneously and composed of one transistor T and one capacitor Cs is connected to the plurality of word lines WL. Furthermore, the word lines WL are connected to the driving circuit D, and the plurality of memory cells MC are controlled by the driving circuit D through the plurality of word lines WL. For example, as shown in FIG. 6, the memory cell MC1 is connected to the intersection between one bit line BL of the bit-line pair and the word line WL1, and the memory cell MC2 is connected to the intersection between the other bit line /BL of the bit-line pair and another word line WL2.

As shown in FIG. 6B, since the readout operation of this direct sense+twin cell method is identical to that shown in FIG. 5, the description thereof is omitted here.

2-3. Method of Simultaneous Selection of a Plurality of Memory Cells

FIGS. 7A to 7F is each a connection diagram showing the method of the simultaneous selection of a plurality of memory cells. FIGS. 7A, 7B. 7c, 7D, 7E and 7F show a two-cell simultaneous selection method, another two-cell simultaneous selection method, still another two-cell simultaneous selection method, a four-cell simultaneous selection method, another four-cell simultaneous selection method, and still another four-cell simultaneous selection method, respectively.

The example in FIG. 7A illustrates the case where one word line WL is to be a selection object, in the structure in which each bit-line pair BL and /BL is connected to one side of each sense amplifier SA and the memory cells MC are connected to all of the intersections between the bit-line pairs BL and /BL and the word lines WL, respectively. In this case, for example, the two memory cells MC11a and MC11b, each connected to the bit-line pair BL1 and /BL1, are simultaneously selected by the same word line WL1.

The example in FIG. 7B illustrates the case where two word lines WL, each one end of which is commonly connected, are to be the selection objects, in the structure in which each bit-line pair BL and /BL is connected to one side of each sense amplifier SA and the memory cells MC are connected to half of the intersections between these bit-line pairs BL and /BL and the word lines WL, respectively. In this case, for example, the two memory cells MC11 and MC21, connected respectively to the bit line BL1 and /BL1, are simultaneously selected by the two word lines WL1 and WL2, each one end of which is commonly connected.

The example in FIG. 7C illustrates the case where two word lines WL, each arranged on both sides of each of the sense amplifiers, are to be selection objects, in the structure in which each bit-line pair BL and /BL is connected to both sides of each sense amplifier SA and the memory cells MC are connected to all of the intersections between the bit-line pairs BL and /BL and the word lines WL, respectively. In this case, for example, the two memory cells MC11 and MC21, each connected to the bit-line pair BL1 and /BL1, are simultaneously selected by the two word lines WL1 and WL2, each of which is arranged on both sides of each sense amplifier.

The example in FIG. 7D illustrates the case where one word line WL is to be a selection object, in the structure in which each folded-type bit-line pair BL and /BL is connected to one side of each sense amplifier SA and the memory cells MC are connected to all of the intersections between the folded-type bit-line pairs BL and /BL and the word lines WL, respectively. In this case, for example, the four memory cells MC11a, MC11b, MC11c, and MC11d, each connected to the folded-type bit-line pair BL1 and /BL1, are simultaneously selected by the same word line WL1.

The example in FIG. 7E illustrates the case where two word lines WL, each one end of which is commonly connected, are to be selection objects, in the structure in which each bit-line pair BL and /BL is connected to one side of each sense amplifier SA and the memory cells MC are connected to all