Title: Semiconductor memory device and portable electronic apparatus
Abstract: A semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
Patent Number: 7,023,731 Issued on 04/04/2006 to Hamaguchi, et al.
| Inventors:
|
Hamaguchi; Koji (Tenri, JP);
Nawaki; Masaru (Nara, JP);
Morikawa; Yoshinao (Ikoma, JP);
Iwata; Hiroshi (Ikoma-gun, JP);
Shibata; Akihide (Nara, JP)
|
| Assignee:
|
Sharp Kabushiki Kaisha (Osaka, JP)
|
| Appl. No.:
|
849481 |
| Filed:
|
May 18, 2004 |
Foreign Application Priority Data
| May 20, 2003[JP] | 2003-141753 |
| Current U.S. Class: |
365/185.14; 365/185.28; 365/185.29 |
| Current Intern'l Class: |
G11C 16/04 (20060101) |
| Field of Search: |
365/18514,185.28,185.29,185.33
|
References Cited [Referenced By]
U.S. Patent Documents
| 5424979 | Jun., 1995 | Morii.
| |
| 5463757 | Oct., 1995 | Fandrich et al.
| |
| 5509134 | Apr., 1996 | Fandrich et al.
| |
| 6046936 | Apr., 2000 | Tsujikawa et al.
| |
| 6556479 | Apr., 2003 | Makuta et al.
| |
| 6643725 | Nov., 2003 | Kozakai et al.
| |
| Foreign Patent Documents |
| 5-304277 | Nov., 1993 | JP.
| |
Other References
Office Action mailed Jun. 1, 2005 for U.S. Appl. No. 10/851,709, filed May 20, 2004.
|
Primary Examiner: Phung; Anh
Attorney, Agent or Firm: Morrison & Foerster LLP
Claims
What is claimed is:
1. A semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in a matrix;
a plurality of terminals for accepting commands at least including commands related
to programming and erasing operations on the memory cell array issued by an external user;
a command interface circuit for interfacing between the external user and the
memory cell array;
a write state machine for controlling the programming and erasing operations
on the memory cell array; and
an output circuit for outputting an internal signal to the plurality of terminals, wherein
the write state machine generates a ready signal indicating that the write state
machine is not operating when the ready signal is active and indicating that the
write state machine is operating when the ready signal is inactive, and an idle
signal indicating that the write state machine is suspending the erasing operation
when the idle signal is active, and includes a status register indicative of a
status of the write state machine,
the command interface circuit includes a user state machine for controlling an
operation of the write state machine via control signals including a program control
signal and an erase control signal,
the user state machine analyzes a command accepted via the plurality of terminals,
makes the program control signal active in the case where the command is a program
command, makes the erase control signal active in the case where the command is
an erase command, and makes the program control signal and the erase control signal
inactive in the case where the command is not a valid command, thereby preventing
an unexpected influence on the write state machine,
the memory cell includes a gate electrode formed over a semiconductor layer via
a gate insulating film, a channel region disposed below the gate electrode, diffusion
regions disposed on both sides of the channel region and having a conductive type
opposite to that of the channel region, and memory functional elements formed on
both sides of the gate electrode and having the function of retaining charges,
the memory functional element is formed by at least any one of an insulating
film including an insulator having the function of retaining charges, an insulating
film including at least one conductor or semiconductor dot, and an insulating film
including a ferroelectric film of which inner charge is polarized by an electric
field and in which the polarized state is held, and
the programming or erasing operation to selected one of the memory functional
elements formed on both sides of the gate electrode can be executed independently
from the other unselected one by controlling each voltage applied to the diffusion
regions and the gate electrode.
2. The semiconductor memory device according to claim 1, wherein
the command interface circuit includes an output selection state machine for
controlling information output from the output circuit to the external user, and
the output selection state machine analyzes the commands, the ready signal and
the idle signal, in the case where the ready signal is inactive, generates a first
output control signal so that a signal is not connected to the output circuit irrespective
of the command and, in the case where the ready signal is active, when the idle
signal is active and the command requests for information from the memory cell
array, generates a second output control signal for connecting data from the memory
cell array to the output circuit.
3. The semiconductor memory device according to claim 2, further comprising:
a signature signal indicative of signature information of the semiconductor memory
device, wherein
the output selection state machine analyzes the command, the ready signal and
the idle signal and, in the case where the ready signal is active, when the idle
signal is inactive and the command is a command for outputting the signature information,
generates a third output control signal for connecting the signature signal to
the output circuit.
4. The semiconductor memory device according to claim 1, further comprising:
a test mode latch circuit for storing a test mode start bit which permits start
of execution of a test mode when active and prevents start of execution of the
test mode when inactive, wherein
the command interface circuit includes a test state machine for controlling the
test mode latch circuit, and
the test state machine is connected to the plurality of terminals and the write
state machine, analyzes the command to determine whether the command is a command
of starting execution of the test mode or not, and responds to a command of starting
execution of the test mode by making the test mode start bit active.
5. The semiconductor memory device according to claim 1, wherein
the command interface circuit includes a first latch circuit having an input
terminal connected to the erase control signal and having an output terminal connected
to the write state machine, and a second latch circuit having an input terminal
connected to the program control signal and having an output terminal connected
to the write state machine.
6. The semiconductor memory device according to claim 1, wherein
the memory functional element is formed so that at least a part thereof overlaps
with a part of the diffusion region.
7. The semiconductor memory device according to claim 1, wherein
the memory functional element includes a film having the function of retaining
charges, and
a surface of the film having the function of retaining charges is disposed almost
parallel with a surface of the gate insulating film.
8. The semiconductor memory device according to claim 7, wherein
the film having the function of retaining charges is disposed almost parallel
with a side face of the gate electrode.
9. The semiconductor memory device according to claim 7, wherein
the memory functional element includes an insulating film for separating between
the film having the function of retaining charges and the channel region or the
semiconductor layer, and
the insulating film is thinner than the gate insulating film and has a thickness
of 0.8 nm or more.
10. The semiconductor memory device according to claim 7, wherein
the memory functional element includes an insulating film for separating between
the film having the function of retaining charges and the channel region or the
semiconductor layer, and
the insulating film is thicker than the gate insulating film and has a thickness
of 20 nm or less.
11. A display comprising the semiconductor memory device according to claim 1.
12. A portable electronic apparatus comprising the semiconductor memory device
according to claim 1.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, a display and
a portable electronic apparatus. More specifically, the present invention relates
to a semiconductor memory device in which field-effect transistors each including
a memory functional element having the function of retaining charges or polarization
are arranged, and to a display and a portable electronic apparatus each having
such a semiconductor memory device.
2. Description of the Related Art
Conventionally, a flash memory is typically used as a nonvolatile memory.
In a flash memory, as shown in FIG. 30, a floating gate
902, an insulating
film
907 and a word line (control gate)
903 are formed in this order
on a semiconductor substrate
901 via a gate insulating film. On both sides
of the floating gate
902, a source line
904 and a bit line
905
are formed by a diffusion region, thereby configuring a memory cell. A device isolation
region
906 is formed around the memory cell (see, for example, JP-A 05-304277 (1993)).
The memory cell stores information in accordance with an amount of charges in
the floating gate
902. In a memory cell array configured by arranging memory
cells, by selecting a specific word line and a specific bit line and applying a
predetermined voltage, an operation of rewriting/reading a desired memory cell
can be performed.
In such a flash memory, when the amount of charges in the floating gate changes,
a drain current (Id)-gate voltage (Vg) characteristic as shown in FIG. 31 is exhibited.
When the amount of negative charges in the floating gate increases, the threshold
increases and the Id-Vg curve shifts almost in parallel in the Vg increasing direction.
In such a flash memory, however, the insulting film
907 which separates
the floating gate
902 from the word line
903 is necessary from the
viewpoint of functions and, in order to prevent leakage of charges from the floating
gate
902, it is difficult to reduce the thickness of the gate insulating
film. Consequently, it is difficult to effectively reduce the thickness of the
insulating film
907 and the gate insulating film, and it disturbs reduction
in the size of the memory cell.
SUMMARY OF THE INVENTION
The present invention has been achieved in consideration of the problems, and
its object is to provide a finer semiconductor memory device and a portable electronic apparatus.
In order to achieve the object, the present invention provides a semiconductor
memory device including: a memory cell array in which memory cells are arranged
in a matrix; a plurality of terminals for accepting commands at least including
commands related to programming and erasing operations on the memory cell array
issued by an external user; a command interface circuit for interfacing between
the external user and the memory cell array; a write state machine for controlling
the programming and erasing operations on the memory cell array; and an output
circuit for outputting an internal signal to the plurality of terminals, wherein
the write state machine generates a ready signal indicating that the write state
machine is not operating when the ready signal is active and indicating that the
write state machine is operating when the ready signal is inactive, and an idle
signal indicating that the write state machine is suspending the erasing operation
when the idle signal is active, and includes a status register indicative of a
status of the write state machine, the command interface circuit includes a user
state machine for controlling an operation of the write state machine via control
signals including a program control signal and an erase control signal, the user
state machine analyzes a command accepted via the plurality of terminals, makes
the program control signal active in the case where the command is a program command,
makes the erase control signal active in the case where the command is an erase
command, and makes the program control signal and the erase control signal inactive
in the case where the command is not a valid command, thereby preventing an unexpected
influence on the write state machine, and the memory cell includes a gate electrode
formed over a semiconductor layer via a gate insulating film, a channel region
disposed below the gate electrode, diffusion regions disposed on both sides of
the channel region and having a conductive type opposite to that of the channel
region, and memory functional elements formed on both sides of the gate electrode
and having the function of retaining charges.
In the semiconductor memory device according to the present invention, the memory
cell includes a gate electrode formed over a semiconductor layer via a gate insulating
film, a channel region disposed below the gate electrode, diffusion regions disposed
on both sides of the channel region and having a conductive type opposite to that
of the channel region, and memory functional elements formed on both sides of the
gate electrode and having the function of retaining charges. A memory function
of the memory functional element and a transistor operation function of the gate
insulating film are separated from each other. Consequently, it is easy to suppress
the short channel effect by thinning the gate insulating film while maintaining
the sufficient memory function. Further, a value of current flowing between the
diffusion regions changes by rewriting more largely than that in the case of an
EEPROM. Therefore, it facilitates discrimination between the programming state
and the erasing state of the semiconductor memory device.
Further, the memory cell in the semiconductor memory device according to
the present invention can be formed by a process which is very compatible with
a normal transistor forming process on the basis of the configuration. Therefore,
as compared with the case of using a conventional flash memory as a nonvolatile
memory cell and configuring the semiconductor memory device having a peripheral
circuit which is usually made by a transistor, the number of masks and the number
of processes can be dramatically reduced. Consequently, the yield in manufacturing
of the semiconductor memory device having both the memory cell and the peripheral
circuit can be improved. Accordingly, the manufacturing cost is reduced and a very-reliable,
cheap semiconductor memory device can be obtained.
Further, by employing the write state machine which is generally employed
by a conventional flash memory, optimizes and automates a complicated inner procedure
in the programming and erasing operations and executes the procedure and, further,
providing the command state machine for performing a proper control on the write
state machine in order to reliably perform the programming and erasing operations
on the memory cell array in the semiconductor memory device according to the present
invention and assure the electric characteristics such as the data retaining characteristic
and reliability, the interface between the external user and the memory cell array
is simplified by a command input, and acceptance of various commands including
commands related to the programming and erasing operations on the memory cell array
issued by the external user and the complicated programming and erasing algorithm
on the memory cell array can be performed automatically.
Further, by regulating a command input to the semiconductor memory device
according to the present invention from the external user, the memory cell array
can be prevented from being erroneously programmed or erased.
Further, in the semiconductor memory device according to the present invention,
the command interface circuit includes an output selection state machine for controlling
information output from the output circuit to the external user, and the output
selection state machine analyzes the command, the ready signal and the idle signal,
in the case where the ready signal is inactive, generates a first output control
signal so that a signal is not connected to the output circuit irrespective of
the command and, in the case where the ready signal is active, when the idle signal
is active and the command requests for information from the memory cell array,
generates a second output control signal for connecting data from the memory cell
array to the output circuit.
The semiconductor memory device according to the present invention further includes
a signature signal indicative of signature information of the semiconductor memory
device, wherein the output selection state machine analyzes the command, the ready
signal and the idle signal and, in the case where the ready signal is active, when
the idle signal is inactive and the command is a command for outputting the signature
information, generates a third output control signal for connecting the signature
signal to the output circuit.
The semiconductor memory device according to the present invention further includes
a test mode latch circuit for storing a test mode start bit which permits start
of execution of a test mode when active and p prevents start of execution of the
test mode when inactive, wherein the command interface circuit includes a test
state machine for controlling the test mode latch circuit, and the test state machine
is connected to the plurality of terminals and the write state machine, analyzes
the command to determine whether the command is a command of starting execution
of the test mode or not, and responds to a command of starting execution of the
test mode by making the test mode start bit active.
In the semiconductor memory device according to the present invention, the command
interface circuit includes a first latch circuit having an input terminal connected
to the erase control signal and having an output terminal connected to the write
state machine, and a second latch circuit having an input terminal connected to
the program control signal and having an output terminal connected to the write
state machine.
The semiconductor memory device according to the present invention can provide
an interface between the external user and a mechanism for performing programming
of the memory cell array or the like, an interface for controlling reading of information
from the memory cell array, and an interface for a test function which is system controlled.
The present invention also provides a display and a portable electronic apparatus
each having the semiconductor memory device.
With such a configuration, in the case of using the semiconductor memory device
of the present invention for storing information for correcting variations in display
after a display panel is manufactured, uniform picture quality can be obtained
in products of the displays. Moreover, the process of simultaneously forming the
memory cell and the logic circuit is simple, so that the manufacturing cost can
be suppressed and the operation speed can be improved by high-speed reading operation.
Thus, the cheap and high-performance display and the portable electronic apparatus
can be obtained.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic sectional view showing a main part of a memory cell (first
embodiment) in a semiconductor memory device of the present invention;
FIGS. 2A and 2B are schematic sectional views each showing a main part of a
modification of the memory cell (first embodiment) in the semiconductor memory
device of the present invention;
FIG. 3 is a diagram showing a programming operation of the memory cell (first
embodiment) in the semiconductor memory device of the present invention;
FIG. 4 is a diagram showing the programming operation of the memory cell (first
embodiment) in the semiconductor memory device of the present invention;
FIG. 5 is a diagram showing an erasing operation of the memory cell (first embodiment)
in the semiconductor memory device of the present invention;
FIG. 6 is a diagram showing the erasing operation of the memory cell first embodiment)
in the semiconductor memory device of the present invention;
FIG. 7 is a diagram showing a reading operation of the memory cell (first embodiment)
in the semiconductor memory device of the present invention;
FIG. 8 is a schematic sectional view showing a main part of a memory cell (second
embodiment) in the semiconductor memory device of the present invention;
FIG. 9 is an enlarged schematic sectional view showing a main part of FIG. 8;
FIG. 10 is an enlarged schematic sectional view showing a main part of a modification
of FIG. 8;
FIG. 11 is a graph showing electric characteristics of the memory cell (second
embodiment) in the semiconductor memory device of the present invention;
FIG. 12 is a schematic sectional view showing a main part of a modification
of the memory cell (second embodiment) in the semiconductor memory device of the
present invention;
FIG. 13 is a schematic sectional view showing a main part of a memory cell (third
embodiment) in the semiconductor memory device of the present invention;
FIG. 14 is a schematic sectional view showing a main part of a memory cell (fourth
embodiment) in the semiconductor memory device of the present invention;
FIG. 15 is a schematic sectional view showing a main part of a memory cell (fifth
embodiment) in the semiconductor memory device of the present invention;
FIG. 16 is a schematic sectional view showing a main part of a memory cell (sixth
embodiment) in the semiconductor memory device of the present invention;
FIG. 17 is a schematic sectional view showing a main part of a memory cell (seventh
embodiment) in the semiconductor memory device of the present invention;
FIG. 18 is a schematic sectional view showing a main part of a memory cell (eighth
embodiment) in the semiconductor memory device of the present invention;
FIG. 19 is a graph showing electric characteristics of a memory cell (ninth
embodiment) in the semiconductor memory device of the present invention;
FIG. 20 is a circuit diagram showing a configuration example of a memory cell
array in a semiconductor memory device (tenth embodiment) of the present invention;
FIG. 21 is a schematic sectional view showing a main part of a normal transistor;
FIG. 22 is a block diagram showing a configuration example of a peripheral circuit
part for interfacing between an external user and a memory cell array in a semiconductor
memory device (eleventh embodiment) of the present invention;
FIG. 23 is a block diagram showing a configuration example of a command state
machine in the semiconductor memory device (eleventh embodiment) of the present invention;
FIG. 24 is a list showing the relations between states of the command state
machine and output signals in the semiconductor memory device (eleventh embodiment)
of the present invention;
FIG. 25 is a state transition diagram showing responses of a user state machine
logic in the command state machine in the semiconductor memory device (eleventh
embodiment) of the present invention;
FIG. 26 is a state transition diagram showing operations of an output selection
state machine logic in the command state machine in the semiconductor memory device
(eleventh embodiment) of the present invention;
FIG. 27 is a state transition diagram showing operations of a test state machine
logic in the command state machine in the semiconductor memory device (eleventh
embodiment) of the present invention;
FIG. 28 is a schematic configuration diagram of a liquid crystal display (twelfth
embodiment) in which the semiconductor memory device of the present invention is assembled;
FIG. 29 is a schematic configuration diagram of a portable electronic apparatus
(thirteenth embodiment) in which the semiconductor memory device of the present
invention is assembled;
FIG. 30 is a schematic sectional view showing a main part of a conventional
flash memory; and
FIG. 31 is a graph showing electric characteristics of the conventional flash memory.
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor memory device according to the present invention is mainly configured
by a memory cell array in which memory cells are arranged in a matrix, a plurality
of terminals for accepting commands at least including commands of programming
and erasing operations on the memory cell array issued by the external user, a
command interface circuit for interfacing between the external user and the memory
cell array, a write state machine for controlling the programming and erasing operations
on the memory cell array, and an output circuit for outputting internal signals
to the plurality of terminals.
A memory cell is mainly configured by a semiconductor layer, a gate insulating
film, a gate electrode, a channel region, a diffusion region and a memory functional
element. Herein, the channel region is usually a region having the same conductive
type as that of the semiconductor layer and denotes a region immediately below
the gate electrode. The diffusion region denotes a region having a conductive type
opposite to that of the channel region.
Specifically, although the memory cell of the present invention may
be configured by a region of a first conductive type as a diffusion region, a region
of a second conductive type as a channel region, a memory functional element disposed
across the boundary of the regions of the first and second conductive types, and
an electrode provided via a gate insulating film, it is proper that the nonvolatile
memory cell of the present invention is configured by a gate electrode formed on
a gate insulating film, two memory functional elements formed on both sides of
the gate electrode, two diffusion regions disposed on the sides of the gate electrode
opposite to the memory functional elements, and a channel region disposed below
the gate electrode.
Preferably, the semiconductor device of the present invention is formed
as the semiconductor layer on the semiconductor substrate, more preferably, on
a well region of the first conductive type formed in the semiconductor substrate.
The semiconductor substrate is not particularly limited as long as it can be
used for a semiconductor device. For example, a bulk substrate made of an element
semiconductor such as silicon or germanium or a compound semiconductor such as
silicon germanium, GaAs, InGaAs, ZnSe, or GaN can be mentioned. As a substrate
having a semiconductor layer on its surface, various substrates such as an SOI
(Silicon on Insulator) substrate, an SOS substrate and a multilayer SOI substrate,
or a glass or plastic substrate having thereon a semiconductor layer may be used.
In particular, a silicon substrate and an SOI substrate having a silicon layer
on its surface are preferable. The semiconductor substrate or semiconductor layer
may be single crystal (formed by, for example, epitaxial growth), polycrystal,
or amorphous although an amount of current flowing therein varies a little.
On the semiconductor layer, preferably, a device isolation region is formed.
Further,
a single layer or multilayer structure may be formed by a combination of devices
such as a transistor, a capacitor and a resistor, a circuit formed by the devices,
a semiconductor device, and an interlayer insulating film. The device isolation
region can be formed by any of various device isolation films such as an LOCOS
film, a trench oxide film and an STI film. The semiconductor layer may be of the
P or N conductive type. In the semiconductor layer, preferably, at least one well
region of the first conductive type (P or N type) is formed. As impurity concentration
in the semiconductor layer and the well region, impurity concentration which is
within a known range in this field can be used. In the case of using the SOI substrate
as the semiconductor layer, the well region may be formed in the surface semiconductor
layer or a body region may be provided below a channel region.
The gate insulating film is not particularly limited as long as it can be usually
used for a semiconductor device. For example, a single-layer film or a multilayer
film of an insulating film such as a silicon oxide film or a silicon nitride film,
and a high-dielectric-constant film such as an aluminum oxide film, a titanium
oxide film, a tantalum oxide film, or a hafnium oxide film can be used. Particularly,
a silicon oxide film is preferred. A proper thickness of the gate insulating film
is, for example, about 1 to 20 nm, preferably, about 1 to 6 nm. The gate insulating
film may be formed only immediately below the gate electrode or formed so as to
be larger (wider) than the gate electrode.
The gate electrode is formed in a shape which is usually used for a semiconductor
device or a shape having a recess in a lower end on the gate insulating film. Although
it is preferable that the gate electrode be formed in an integral form without
being separated by a single-layer or multilayer conductive film, the gate electrode
may be also disposed in a state where it is separated by a single-layered or multilayer
conductive film. The gate electrode may have a sidewall insulating film on its
sidewalls. The gate electrode is not particularly limited as long as it is used
for a semiconductor device. The gate electrode is formed by a single-layer or multilayer
film made by a conductive film, for example, polysilicon, a metal such as copper
or aluminum, a high-refractory metal such as tungsten, titanium or tantalum, and
a silicide or the like with the high refractory metal. A proper film thickness
of the gate electrode is, for example, about 50 to 400 nm. Under the gate electrode,
a channel region is formed.
Preferably, the gate electrode is formed only on the sidewalls of the
memory functional element or does not cover the top portion of the memory functional
element. By such arrangement, a contact plug can be disposed closer to the gate
electrode, so that reduction in the size of the memory cell is facilitated. It
is easy to manufacture the memory cell having such simple arrangement, so that
the yield in manufacturing can be improved.
The memory functional element has at least the function of retaining charges
(hereinafter, described as "charge retaining function"). In other words, the memory
functional element has the function of accumulating and retaining charges, the
function of trapping charges, or the function of holding a charge polarization
state. The function is exhibited, for example, when the memory functional element
includes a film or region having the charge retaining function. Elements having
the function are: silicon nitride; silicon; a silicate glass including impurity
such as phosphorus or boron; silicon carbide; alumina; a high dielectric material
such as hafnium oxide, zirconium oxide or tantalum oxide; zinc oxide; ferroelectric;
metals, and the like. Therefore, the memory functional element can be formed by,
for example, a single-layer or multilayer structure of: an insulating film including
a silicon nitride film; an insulating film having therein a conductive film or
a semiconductor layer; an insulating film including at least one conductor or semiconductor
dot; or an insulating film including a ferroelectric film of which inner charge
is polarized by an electric field and in which the polarized state is held. Particularly,
the silicon nitride film is preferable for the reasons that the silicon nitride
film can obtain a large hysteretic characteristic since a number of levels of trapping
charges exist. In addition, the charge retention time is long and a problem of
charge leakage due to occurrence of a leak path does not occur, so that the retaining
characteristics are good. Further, silicon nitride is a material which is normally
used in an LSI process.
By using the insulating film including a film having the charge retaining function
such as a silicon nitride film as the memory functional element, reliability of
retention of information can be increased. Since the silicon nitride film is an
insulator, even in the case where a charge leak occurs in part of the silicon nitride
film, the charges in the whole silicon nitride film are not lost immediately. In
the case of arranging a plurality of sidewall memory cells, even if the distance
between the memory cells is shortened and neighboring memory functional elements
come into contact with each other, unlike the case where the memory functional
elements are made of conductors, information stored in the memory functional elements
is not lost. Further, a contact plug can be disposed closer to the memory functional
element. In some cases, the contact plug can be disposed so as to overlap with
the memory functional element. Thus, reduction in the size of the memory cell is facilitated.
In order to increase the reliability of retention of information, the film having
the charge retaining function does not always have to have a film shape. Preferably,
films having the charge retaining function exist discretely in an insulating film.
Specifically, it is preferable that the films having the charge retaining function
in the shape of dots be spread in a material which is hard to retain charges, for
example, in a silicon oxide.
In the case of using a conductive film or semiconductor layer as the charge retaining
film, preferably, the conductive film or semiconductor layer is disposed via an
insulating film so that the charge retaining film is not in direct contact with
the semiconductor layer (semiconductor substrate, well region, body region, source/drain
regions or diffusion region) or a gate electrode. For example, a lamination structure
of the conductive film and the insulating film, a structure in which conductive
films in the form of dots are spread in the insulating film, a structure in which
the conductive film is disposed in a part of a sidewall insulating film formed
on sidewalls of the gate, and the like can be mentioned.
It is preferable to use the insulating film having therein the conductive film
or semiconductor layer as a memory functional element for the reason that an injection
amount of charges into the conductor or semiconductor can be freely controlled
and multiple values can be easily obtained.
Further, it is preferable to use the insulating film including at least
one conductor or semiconductor dot as the memory functional element for the reason
that it becomes easier to perform programming and erasing by direct tunneling of
charges, and reduction in power consumption can be achieved.
Alternatively, as a memory functional element, a ferroelectric film
such as PZT or PLZT in which the polarization direction changes according to the
electric field may be used. In this case, charges are substantially generated in
the surface of the ferroelectric film by the polarization and are held in that
state. It is therefore preferable since the ferroelectric film can obtain a hysteresis
characteristic similar to that of a film to which charges are supplied from the
outside of the film having the memory function and which traps charges. In addition,
it is unnecessary to inject charges from the outside of the film in order to retain
charges in the ferroelectric film, and the hysteresis characteristic can be obtained
only by the polarization of the charge in the film, so that programming/erasing
can be performed at high speed.
As the insulating film configuring the memory functional element, a film having
a region of suppressing escape of charges or the function of suppressing escape
of charges is appropriate. One of films having the function of suppressing escape
of charges is a silicon oxide film.
The charge retaining film included in the memory functional element is disposed
on both sides of the gate electrode directly or via an insulating film, and is
disposed on the semiconductor layer (semiconductor substrate, well region, body
region or source/drain region or diffusion region) directly or via a gate insulating
film. Preferably, the charge retaining film on both sides of the gate electrode
is formed so as to cover all or part of the sidewalls of the gate electrode directly
or via the insulating film. In an application example, in the case where the gate
electrode has a recess in its lower end, the charge retaining film may be formed
so as to completely or partially bury the recess directly or via an insulating film.
The diffusion regions can function as source and drain regions and have the conductive
type opposite to that of the semiconductor layer or well region. In the junction
between the diffusion region and the semiconductor layer or well region, preferably,
impurity concentration is high for the reason that hot electrons or hot holes are
generated efficiently with low voltage, and high-speed operation can be performed
with lower voltage. The junction depth of the diffusion region is not particularly
limited but can be properly adjusted in accordance with the performance or the
like of a semiconductor memory device to be obtained. In the case of using an SOI
substrate as a semiconductor substrate, the diffusion region may have a junction
depth smaller than the thickness of the surface semiconductor layer. Preferably,
the diffusion region has junction depth almost the same as the thickness of the
surface semiconductor layer.
The diffusion region may be disposed so as to overlap an end of the gate electrode,
so as to match an end of the gate electrode, or so as to be offset from the gate
electrode end. The case where the diffusion region is offset is particularly preferable
because easiness of inversion of the offset region below the charge retaining film
largely changes in accordance with an amount of charges accumulated in the memory
functional element when voltage is applied to the gate electrode, the memory effect
increases, and a short channel effect is reduced. However, when the diffusion region
is offset too much, drive current between the diffusion regions (source and drain)
decreases conspicuously. Therefore, it is preferable that the offset amount, that
is, the distance from one of the gate electrode terminals to the closer diffusion
area in the gate length direction be shorter than the thickness of the charge retaining
film extending in the direction parallel with the gate length direction. It is
particularly important that at least a part of the film or region having the charge
retaining function in the memory functional element overlaps with a part of the
diffusion region. This is because the essence of the memory cell as a component
of the semiconductor memory device of the present invention is to rewrite stored
information by an electric field which is applied across the memory functional
element in accordance with the voltage difference between the gate electrode which
exists only in the sidewall portion of the memory functional element and the diffusion region.
Apart of the diffusion region may extend at a level higher than the surface
of the channel region, that is, the lower face of the gate insulating film. In
this case, it is proper that, on the diffusion region formed in the semiconductor
substrate, the conductive film is laminated so as to be integrated with the diffusion
region. The conductive film is made of a semiconductor such as polysilicon or amorphous
silicon, silicide, the above-mentioned metals, high-refractory metals, or the like.
In particular, polysilicon is preferred. Since impurity diffusion speed of polysilicon
is much faster than that of the semiconductor layer, it is easy to make the junction
depth of the diffusion region in the semiconductor layer shallow and to suppress
the short channel effect. In this case, preferably, a part of the diffusion region
is disposed so as to sandwich at least a part of the memory functional element
in cooperation with the gate electrode.
The memory cell of the present invention can be formed by a normal semiconductor
process in accordance with, for example, a method similar to the method of forming
the sidewall spacer having the single-layer or multilayer structure on the sidewalls
of the gate electrode. Specific examples are: a method of forming the gate electrode,
after that, forming a single-layer film or multilayer film including the charge
retaining film such as a film having the function of retaining charges (hereinafter,
described as "charge retaining film"), charge retaining film/insulating film, insulating
film/charge retaining film, or insulating film/charge retaining film/insulating
film, and etching back the formed film under proper conditions so as to leave the
films in a sidewall spacer shape; a method of forming an insulating film or charge
retaining film, etching back the film under proper conditions so as to leave the
film in the sidewall spacer shape, further forming the charge retaining film or
insulating film, and similarly etching back the film so as to leave the film in
the sidewall spacer shape; a method of applying or depositing an insulating film
material in which particles made of a charge retaining material are spread on the
semiconductor layer including the gate electrode, and etching back the material
under proper conditions so as to leave the insulating film material in a sidewall
spacer shape; and a method of forming a gate electrode, after that, forming the
single-layer film or multilayer film, and patterning the film with a mask. According
to another method, before the gate electrode is formed, the charge retaining film,
charge retaining film/insulating film, insulating film/charge retaining film, insulating
film/charge retaining film/insulating film, or the like is formed. An opening is
formed in a region which becomes the channel region of the films, a gate electrode
material film is formed on the entire surface, and the gate electrode material
film is patterned in a shape including the opening and larger than the opening.
In the case of configuring the memory cell array by arranging memory cells of
the present invention, the best mode of the memory cell satisfies all of the following
requirements: (1) the gate electrodes of a plurality of memory cells are integrated
and have the function of a word line, (2) the memory functional elements are formed
on both sides of the word line, (3) an insulator, particularly, a silicon nitride
film retains charges in the memory functional element, (4) the memory functional
element is configured by an ONO (Oxide Nitride Oxide) film and the silicon nitride
film has a surface almost parallel with the surface of the gate insulating film,
(5) a silicon nitride film in the memory functional element is isolated from a
word line and a channel region by a silicon oxide film, (6) the silicon nitride
film in the memory functional element and a diffusion region overlap with each
other, (7) the thickness of the insulating film separating the silicon nitride
film having the surface which is almost parallel with the surface of the gate insulating
film from the channel region or semiconductor layer and the thickness of the gate
insulating film are different from each other, (8) an operation of programming/erasing
one memory cell is performed by a single word line, (9) there is no electrode (word
line) having the function of assisting the programming/erasing operation on the
memory functional element, and (10) in a portion in contact with the diffusion
region immediately below the memory functional element, a region of high concentration
of impurity whose conductive type is opposite to that of the diffusion region is
provided. It may be sufficient for the memory cell to satisfy at least one of the requirements.
A particularly preferable combination of the requirements is that, for example,
(3) an insulator, particularly, a silicon nitride film holds charges in the memory
functional element, (6) the insulating film (silicon nitride film) in the memory
functional element and the diffusion region overlap with each other, and (9) there
is no electrode (word line) having the function of assisting the programming/erasing
operation on the memory functional element.
In the case where the memory cell satisfies the requirements (3) and (9), it
is
very useful for the following reasons. First, the bit line contact can be disposed
closer to the memory functional element on the word line sidewall or even when
the distance between memory cells is shortened, a plurality of memory functional
elements do not interfere with each other, and stored information can be held.
Therefore, reduction in the size of the memory cell is facilitated. In the case
where the charge retaining region in the memory functional element is made of a
conductor, as the distance between memory cells decreases, interference occurs
between the charge retaining regions due to capacitive coupling, so that stored
information cannot be held.
In the case where the charge retaining region in the memory functional element
is made of an insulator (for example, a silicon nitride film), it becomes unnecessary
to make the memory functional element independent for each memory cell. For example,
the memory functional elements formed on both sides of a single word line shared
by a plurality of sidewall memory cells do not have to be isolated for each memory
cell. The memory functional elements formed on both sides of one word line can
be shared by a plurality of memory cells sharing the word line. Consequently, a
photo etching process for isolating the memory functional element becomes unnecessary,
and the manufacturing process is simplified. Further, a margin for positioning
in the photolithography process and a margin for film reduction by etching become
unnecessary, so that the margin between neighboring memory cells can be reduced.
Therefore, as compared with the case where the charge retaining region in the memory
functional element is made of a conductor (for example, polysilicon film), even
when the memory functional element is formed at the same microfabrication level,
a memory cell occupied area can be reduced. In the case where the charge retaining
region in the memory functional element is made of a conductor, the photo etching
process for isolating the memory functional element for each memory cell is necessary,
and a margin for positioning in the photolithography process and a margin for film
reduction by etching are necessary.
Moreover, since the electrode having the function of assisting the programming
and erasing operations does not exist on the memory functional element and the
device structure is simple, the number of processes decreases, so that the yield
in manufacturing can be increased. Therefore, it facilitates formation with a transistor
as a component of a logic circuit or an analog circuit, and a cheap semiconductor
memory device can be obtained.
The present invention is more useful in the case where not only the requirements
(3) and (9) but also the requirement (6) are satisfied. Specifically, by overlapping
the charge retaining region in the memory functional element with the diffusion
region, programming and erasing can be performed with a very low voltage. Specifically,
with a low voltage of 5 V or less, the programming and erasing operations can be
performed. The action produces a very large effect also from the viewpoint of circuit
designing. Since it becomes unnecessary to generate a high voltage in a chip unlike
a flash memory, a charge pumping circuit requiring a large occupation area can
be omitted or its scale can be reduced. Particularly, when a memory of small-scale
capacity is provided for adjustment in a logic LSI, as for an occupied area in
a memory, an occupation area of peripheral circuits for driving a memory cell is
dominant more than that of a memory cell. Consequently, omission or down sizing
of the charge pumping circuit for a memory cell is most effective to reduce the
chip size.
On the other hand, in the case where the requirement (3) is not satisfied, that
is, in the case where a conductor retains charges in the memory functional element,
even if the requirement (6) is not satisfied, specifically, even if the conductor
in the memory functional element and the diffusion region do not overlap with each
other, programming operation can be performed. This is because that the conductor
in the memory functional element assists programming operation by capacitive coupling
with the gate electrode.
In the case where the requirement (9) is not satisfied, specifically, in the
case
where the electrode having the function of assisting the programming and erasing
operations exists on the memory functional element, even if the requirement (6)
is not satisfied, specifically, even if the insulator in the memory functional
element and the dimension region do not overlap with each other, programming operation
can be performed.
In the semiconductor memory device of the present invention, a transistor may
be connected in series with one of or both sides of a memory cell, or the memory
cell may be mounted on the same chip with a logic transistor. In such a case, the
semiconductor device of the present invention, particularly, the memory cell can
be formed by a process having high compatibility with a process of forming a normal
standard transistor such as a transistor or a logic transistor, so that they can
be formed simultaneously. Therefore, a process of forming both the memory cell
and a transistor or a logic transistor is very simple and, as a result, a cheap
embedding device can be obtained.
In the semiconductor memory device of the present invention, the memory cell
can
store information of two or more values in one memory functional element. Thus,
the memory cell can function as a memory cell for storing information of four or
more values. The memory cell may store binary data only. The memory cell is also
allowed to function as a memory cell having the functions of both a selection transistor
and a memory transistor by a variable resistance effect of the memory functional element.
The semiconductor memory device of the present invention can be widely applied
by being combined with a logic device, a logic circuit or the like to: a data processing
system such as a personal computer, a note-sized computer, a laptop computer, a
personal assistant/transmitter, a mini computer, a workstation, a main frame computer,
a multiprocessor/computer, or a computer system of any other type; an electronic
component configuring the data processing system, such as a CPU, a memory or a
data memory device; a communication apparatus such as a telephone, a PHS, a modem
or a router; an image display apparatus such as a display panel or a projector;
a business apparatus such as a printer, a scanner or a copier; an image pickup
apparatus such as a video camera or a digital camera; an entertainment apparatus
such as a game machine or a music player; an information apparatus such as a portable
information terminal, a watch or an electronic dictionary; a vehicle-mounted apparatus
such as a car navigation system or a car audio system; an AV apparatus for recording/reproducing
information such as a motion picture, a still picture or music; an appliance such
as a washing machine, a microwave, a refrigerator, a rice cooker, a dish washer,
a vacuum cleaner or an air conditioner; a health managing apparatus such as a massage
machine, a bathroom scale or a manometer; and an electronic apparatus such as a
portable memory device such as an IC card or a memory card. Particularly, it is
effective to apply the semiconductor memory device to portable electronic apparatuses
such as portable telephone, portable information terminal, IC card, memory card,
portable computer, portable game device, digital camera, portable motion picture
player, portable music player, electronic dictionary and watch. The semiconductor
memory device of the present invention may be provided as at least a part of a
control circuit or a data storing circuit of an electronic apparatus or, if necessary,
detachably assembled.
Embodiments of the semiconductor memory device, the display and the portable
electronic apparatus according to the present invention will be described below
with reference to the drawings.
First Embodiment
A semiconductor memory device of a first embodiment has a memory cell
1
as shown in FIG. 1.
The memory cell
1 has a gate electrode
104 formed on a P-type well
region
102 formed on the surface of a semiconductor substrate
101
via a gate insulating film
103. On the top face and side faces of the gate
electrode
104, a silicon nitride film
109 having a trap level of
retaining charges and serving as a charge retaining film is disposed. In the silicon
nitride film
109, parts of both sidewalls of the gate electrode
104
serve as memory functional elements
105a and
105b for
actually retaining charges. The memory functional element refers to a part in which
charges are actually accumulated by rewriting operation in the memory functional
element or the charge retaining film. In the P-type well region
102 on both
sides of the gate electrode
104, N-type diffusion regions
107a
and
107b functioning as a source region and a drain region, respectively,
are formed. Each of the diffusion regions
107a and
107b
has an offset structure. Specifically, the diffusion regions
107a
and
107b do not reach a region
121 below the gate electrode
104, and offset regions
120 below the charge retaining film configure
a part of the channel region.
The memory functional elements
105a and
105b for
substantially retaining charges are side wall parts of the gate electrode
104.
Therefore, it is sufficient that the silicon nitride film
109 is formed
only in regions corresponding to the parts (see FIG. 2A). The memory functional
elements
105a and
105b may have a structure in which
particles
111 made of conductor or semiconductor having a nanometer size
are distributed in an insulating film
112 (see FIG. 2B). When the size of
the particle
111 is less than 1 nm, the quantum effect is too large and
it becomes difficult for charges to tunnel dots. When the size exceeds 10 nm, however,
a noticeable quantum effect does not appear at room temperature. Therefore, the
diameter of the particle
111 lies preferably in the range from 1 nm to 10
nm. Further, the silicon nitride film
109 serving as a charge retaining
film may be formed in the side wall spacer shape on side faces of the gate electrode
(see FIG. 3).
The principle of the programming operation of the memory cell will be described
with reference to FIGS. 3 and 4. The case where whole memory functional elements
131a and
131b have the function of retaining charges
will be described. "Programming" denotes here injection of electrons into the memory
functional elements
131a and
131b when the memory cell
is of the N channel type. Hereinafter, on assumption that the memory cell is of
the N channel type, description will be given.
In order to inject electrons (to program) into the second memory functional element
131b, as shown in FIG. 3, the first diffusion region
107a
of the N-type is set as the source electrode, and the second diffusion region
107b of the N-type is set as the drain electrode. For example, 0
V is applied to the first diffusion region
107a and the P-type well
region
102, +5 V is applied to the second diffusion region
107b,
and +5 V is applied to the gate electrode
104. With such voltage parameters,
an inversion layer
226 extends from the first diffusion region
107a
(source electrode), but does not reach the second diffusion region
107b
(drain electrode), so that a pinch-off point is generated. Electrons are accelerated
from the pinch-off point to the second diffusion region
107b (drain
electrode) by high electric field and become so-called hot electrons (conductive
electrons of high energy). The hot electrons are injected into the second memory
functional element
131b, thereby performing programming. Since hot
electrons are not generated in the vicinity of the first memory functional element
131a, programming is not performed.
On the other hand, in order to inject electrons (to program) into the first memory
part
131a, as shown in FIG. 4, the second diffusion region
107b
is set as the source electrode, and the first diffusion region
107a
is set as the drain electrode. For example, 0 V is applied to the second diffusion
region
107b and the P-type well region
102, +5 V is applied
to the first diffusion region
107a, and +5 V is applied to the gate
electrode
104. As described above, by interchanging the source and drain
regions in the case of injecting electrons into the second memory functional element
131b, programming can be performed by injecting electrons into the
first memory functional element
131a.
The principle of erasing operation of the memory cell will now be described with
reference to FIGS. 5 and 6.
In a first method of erasing inform
