Title: Semiconductor memory device
Abstract: A main control circuit generates a plurality of main control signals of different phases to local control circuits. The local control circuits produce row-related control signals greater in number than the main control signals in accordance with these main control signals. A semiconductor memory device can be easily adapted to change in bank structure, and can perform a fast and stable operation with a low current consumption.
Patent Number: 6,888,776 Issued on 05/03/2005 to Watanabe, et al.
| Inventors:
|
Watanabe; Naoya (Hyogo, JP);
Nishino; Aiko (Hyogo, JP);
Dosaka; Katsumi (Hyogo, JP)
|
| Assignee:
|
Renesas Technology Corp. (Tokyo, JP);
Mitsubishi Electric Engineering Company Limited (Tokyo, JP)
|
| Appl. No.:
|
077833 |
| Filed:
|
February 20, 2002 |
Foreign Application Priority Data
| Sep 06, 2000[JP] | 2000-270060 |
| Sep 04, 2001[JP] | 2001-267765 |
| Current U.S. Class: |
365/230.06; 365/194; 365/230.03; 365/233 |
| Intern'l Class: |
G11C 008/00 |
| Field of Search: |
365/23006,233,221,194,230.03
|
References Cited [Referenced By]
U.S. Patent Documents
| 5761148 | Jun., 1998 | Allan et al.
| |
| 5875149 | Feb., 1999 | Oh et al.
| |
| 5986964 | Nov., 1999 | Ariki et al.
| |
| 6111808 | Aug., 2000 | Khang et al.
| |
| 6366515 | Apr., 2002 | Hidaka.
| |
| 6477108 | Nov., 2002 | Arimoto et al.
| |
| 6538953 | Mar., 2003 | Hidaka.
| |
| 6563759 | May., 2003 | Yahata et al.
| |
| 6600779 | Jul., 2003 | Sawada et al.
| |
| Foreign Patent Documents |
| 10-050958 | Feb., 1998 | JP.
| |
Other References
"Figure 9 SLDRAM Functional Block Diagram", IEEE Micro, Nov./Dec. 1997, pp. 38-39.
"A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized
Using a Memory Generator", Yabe et al., 1998 IEEE International Solid-State Circuits
Conference, Digest of Technical Papers, pp. 72-73.
|
Primary Examiner: Dinh; Son T.
Attorney, Agent or Firm: McDermott Will & Emery LLP
Parent Case Text
This application is a continuation-in-part of Ser. No. 09/839,401, filed Apr.
23, 2001, now abandoned.
Claims
1. A semiconductor memory device comprising:
a memory array including a plurality of memory cells arranged in rows and columns;
main control circuitry for producing a plurality of main control signals having
different phases in response to a row-related instructing signal instructing an
operation related to row selection in said memory array; and
sub-control circuitry receiving said plurality of main control signals, for producing
sub-control signals greater in number than said plurality of main control signals,
said sub-control signals being signals for controlling the operation instructed
by said row-related instructing signal.
2. The semiconductor memory device according to claim 1, further comprising a
plurality of banks activated independently of each other, wherein
said plurality of main control signals are independent of a signal specifying
a bank among said plurality of banks.
3. The semiconductor memory device according to claim 1, wherein
said main control circuitry includes a plurality of control signal generating
circuits activated sequentially to produce said plurality of main control signals
in response to said row-related instructing signal.
4. The semiconductor memory device according to claim 1, wherein
said memory array is divided into a plurality of memory blocks each having a
plurality of memory cells,
said sub-control circuitry includes a plurality of sub-control circuits provided
corresponding to said plurality of memory blocks, and
said plurality of main control signals are transferred to said plurality of sub-control
circuits with a same line load, respectively.
5. The semiconductor memory device according to claim 1, wherein
said main control circuitry includes:
a first control circuit for activating a first main control signal in response
to a row selection instruction by said row-related instructing signal,
a second control circuit for activating a second main control signal in response
to activation of said first main control signal, and deactivating said second main
control signal in response to deactivation of said first main control signal, and
a third control circuit for activating a third main control signal in response
to activation of said second main control signal, and deactivating said third main
control signal in response to deactivation of said second main control signal;
and
said first control circuit deactivates said first main control signal in response
to activation of said third main control signal.
6. The semiconductor memory device according to claim 5, further comprising:
a first delay circuit arranged between the first and second control circuits,
for delaying said first main control signal for application to said second control
circuit;
a second delay circuit arranged between the second and third control circuits
for delaying said second main control signal for application to said third control
circuit; and
a third delay circuit arranged between the third and first control circuits for
delaying activation of said third main control signal for application to said first
control circuit.
7. The semiconductor memory device according to claim 6, wherein the first, second
and third delay circuits have delay times set individually and independently.
8. The semiconductor memory device according to claim 1, further comprising:
an address input circuit for taking in and buffering an externally applied address
signal to produce an internal address for application to said sub-control circuitry.
9. The semiconductor memory device according to claim 8, wherein
said memory array is divided into a plurality of memory blocks each having a
plurality of memory cells,
said sub-control circuitry includes a plurality of sub-control circuits provided
corresponding to said plurality of memory blocks, respectively,
each of said plurality of sub-control circuits includes a block decode circuit
for receiving and decoding a plurality of block address bits included in said internal
address, and
said block decode circuit includes;
an input circuit for producing complementary address bits from each of said block
address bits,
a switch circuit for selecting one of said complementary address bits for each
block address bit, and
a decode circuit for decoding address bits received from the switch circuit to
produce a block select signal for selecting a corresponding memory block.
10. The semiconductor memory device according to claim 1, wherein
said memory array is divided into a plurality of memory blocks each having a
plurality of memory cells,
said sub-control circuitry includes a plurality of sub-circuits provided corresponding
to said plurality of memory blocks, respectively, and
each of said plurality of sub-control circuits includes;
a block decode circuit for decoding a block address included in said internal
address to produce a block select signal specifying a corresponding memory block,
and
a local control signal generating circuit for taking in the plurality of main
control signals sent from said main control circuitry, and producing said plurality
of sub-control signals when the block select signal generated from said block decode
circuit is active.
11. The semiconductor memory device according to claim 10, wherein
each said sub-control circuit includes;
a first buffer circuit for taking in a first main control signal among said plurality
of main control signals and producing a first internal main control signal in response
to activation of said block select signal,
a second buffer circuit for taking in a second main control signal among said
plurality of main control signals and producing a second internal main control
signal in response to activation of said first internal main control signal received
from said first buffer circuit, and
at least one buffer circuit provided corresponding to a remaining main control
signal(s) among said plurality of main control signals for taking in a corresponding
main control signal(s), and producing an internal main control signal(s) in response
to activation of an internal main control signal on a preceding stage.
12. The semiconductor memory device according to claim 1, wherein
said main control circuitry includes a delay adjustment circuit for adjusting
a delay between said plurality of main control signals, and
said sub-control circuitry produces said plurality of sub-control signals in
accordance with the main control signals sent from said main control circuit and
subjected to delay adjustment through the delay adjustment circuit.
13. The semiconductor memory device according to claim 1, wherein
said sub-control circuitry includes a switch circuit for changing a relationship
between said plurality of main control signals and said plurality of sub-control
signals.
14. The semiconductor memory device according to claim 1, wherein
said main control circuitry includes a circuit for adjusting an active period
of at least one of said plurality of main control signals in accordance with a
test control signal activated in a test mode.
15. A semiconductor memory device comprising:
a memory array including a plurality of memory cells arranged in rows and columns;
main control circuitry for producing a plurality of main control signals having
different phases in response to a data access instructing signal instructing an
operation related to data accessing in said memory array; and
sub-control circuitry receiving said plurality of main control signals, for producing
sub-control signals for controlling the operation instructed by said data access
instrucing signal.
16. The semiconductor memory device according to claim 15, wherein, each said
main control signal having a first edge and a second edge changing in opposite
directions; and
said sub-control circuitry produces said sub-control signals in accordance with
common edges of the first and second edges of the main control signals.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly
to a semiconductor memory device having a large storage capacity. In particular,
the present invention relates to row-related control circuitry for controlling
a row selecting operation in a refresh operation mode and a normal operation mode
of a clock synchronous DRAM (Dynamic Random Access Memory) used, e.g., in a DRAM
integrated on a common chip together with a logic or the like.
2. Description of the Background Art
FIG. 79 schematically shows a whole structure of a conventional clock synchronous
semiconductor memory device. In FIG. 79, the clock synchronous semiconductor memory
device includes a plurality of sub-memory arrays SMA
0-SMA
3, row decoders
RD
0-RD
3 provided corresponding to sub-memory arrays SMA
0-SMA
3
for selecting rows of memory cells in corresponding sub-memory arrays, respectively,
a column decoder CDA provided for sub-memory arrays SMA
0 and SMA
2
for producing a column select signal for selecting columns in these sub-memory
arrays, a column decoder CDB provided corresponding to sub-memory arrays SMA
1
and SMA
3 for producing the column select signal for selecting columns in
these sub-memory arrays, a data path DPA for transmitting data to and from memory
cells in the column selected by column decoder CDA, and a data path DPB for transmitting
data to and from memory cells in the column selected by column decoder CDB. Each
of data paths DPA and DPB includes data input circuitry (an input buffer and a
write buffer) and data output circuitry (an output buffer and a preamplifier).
Sub-memory arrays SMA
0 and SMA
1 form a bank BA#
1,
and sub-memory arrays SMA
2 and SMA
3 form a bank BA#
0. Commonly
to banks BA#
1 and BA#
0, there is arranged a main control circuit
MCK that operates in synchronization with a clock signal CLK to receive an address
signal ADD and a command CMD instructing an operation mode, and produces an operation
control signal for banks BA#
0 and BA#
1. For bank BA#
0, a sub-control
circuit SCK
0 is provided. For bank BA#
1, a sub-control circuit SCK
1
is provided. Main control circuit MCK produces an operation control signal for
a designated bank in accordance with a bank address included in address signal
ADD. Sub-control circuits SCK
0 and SCK
1 produce control signals for
performing designated operations in accordance with the main operation control
signal received from main control circuit MCK. These sub-control circuits SCK
0
and SCK
1 operate independently of each other in accordance with the operation
control signal received from main control circuit MCK.
As shown in FIG. 79, the memory array is divided into two banks BA#
0 and
BA#
1 so as to be activated and deactivated independently of each other in
accordance with sub-control circuits SCK
0 and SCK
1, respectively.
Therefore, the data access can be made to the banks in an interleaved manner, so
that a penalty upon page switching is not caused, and fast access can be performed.
FIG. 80 schematically shows a structure of sub-memory arrays SMA
0-SMA
3
shown in FIG.
79. Sub-memory arrays SMA
0-SMA
3 have the same
structure, and therefore, FIG. 80 shows only one sub-memory array as a representative.
In FIG. 80, sub-memory array SMA includes a plurality of memory blocks MB
0-MB
7,
a sense amplifier bands SAB
1-SAB
7 arranged between memory blocks
MB
0-MB
7, and sense amplifier bands SAB
0 and SAB
8 arranged
outside memory blocks MB
0 and MB
7, respectively.
In memory block MB
0, memory cells are arranged in rows and columns. In
sense amplifier bands SAB
0-SAB
8, sense amplifier circuits are arranged
corresponding to the columns of corresponding memory blocks MB
0-MB
7.
Sense amplifier bands SAB
0-SAB
8 have a so-called "alternately arranged,
shared sense amplifier structure", in which the sense amplifier circuits are arranged
alternately on the opposite sides of the columns of the corresponding memory blocks,
and each sense amplifier circuit is shared between the adjacent memory blocks.
In the sub-memory array SMA, the row selecting operation is performed on a block
basis. One of the memory blocks is designated by the block select signal produced
in accordance with the block address includes in address signal ADD, and the row
selection is performed in the selected memory block. Since sub-memory array SMA
is divided into the plurality of memory blocks MB
0-MB
7, each of sub-control
circuits SCK
0 and SCK
1 is divided into local control circuits corresponding
to memory blocks MB
0-MB
7.
As shown in FIG. 80, a block dividing operation or a partial activation is performed
in sub-memory array SMA and the memory blocks in an unselected state are maintained
in a precharged state for reducing a current consumption.
For arranging the sub-memory array shown in FIG. 80, sense amplifier band SAB
8
of bank BA#
1 and sense amplifier band SAB
0 of bank BA#
0 are
arranged adjacently to each other on a boundary between banks BA#
0 and BA#
1.
Thus, the sense amplifier band of each bank can be activated and deactivated independently
of those of the other bank.
FIG. 81 schematically shows a structure for a portion related to sub-control
circuits SCK
0 and SCK
1 shown in FIG.
79. Sub-memory array
SMA
2 included in bank BA#
0 includes memory blocks MB
00-MB
07.
Sub-memory array SMA
0 of bank BA#
1 includes memory blocks MB
10-MB
17.
The sense amplifier bands are arranged on the opposite sides of these memory blocks
MB
00-MB
07 and MB
10-MB
17 in the column direction. In
FIG. 81, these sense amplifier bands are depicted as rectangular regions, respectively.
Sub-control circuit CK
0 includes local control circuits LCK
00-LCK
07
provided corresponding to memory blocks MB
00-MB
07, respectively,
and sub-control circuit CK
1 includes local control circuits LCK
10-LCK
17
provided corresponding to memory blocks MB
10-MB
17, respectively.
Main control circuit MCK produces a row-related control signal group BRC and
a predecode block address signal PDA for the banks in accordance with externally
applied command CMD and address signal ADD, and also produces internal clock signal
CLK in accordance with an externally applied clock signal ECLK. Internal clock
signal CLK generated from main control circuit MCK is applied commonly to local
control circuits LCK
00-LCK
07 and LCK
10-LCK
17. Row-related
control signal group BRC for the banks includes a row-related control signal BR
0
for bank BA#
0 and a row-related control signal BR
1 for bank BA#
1.
Row-related control signal BR
0 is applied commonly to local control circuits
LCK
00-LCK
07, and row-related control signal BR
1 is applied
commonly to local control circuits LCK
10-LCK
17.
A predecode block address signal PBA is produced by predecoding a block address
included in externally applied address signal ADD. Predecode block address signal
PBA of 6 bits includes a predecode block address signal group PBG
0 of 2
bits and a predecode block address signal group of 4 bits, and is applied commonly
to banks BA#
0 and BA#
1. In FIG. 81, since each of banks BA#
0
and BA#
1 includes eight memory blocks, the predecode block address of 6
bits is produced. Predecode block address group PBG
0 of 2 bits designates
the memory blocks in an upper or lower half in each of banks BA#
0 and BA#
1.
Predecode block address group PBG
1 of 4 bits designates one memory block
among these memory blocks in the upper half and the lower half in each of the banks.
Therefore, each of local control circuits LCK
00-LCK
07 and LCK
10-LCK
17
receives one bit in each of these predecode block address bit groups PBG
0
and PBG
1.
Predecode block address signal PBA commonly designates the memory blocks
in banks BA#
0 and BA#
1. In accordance with row-related control signal
group BRC for the banks, the row-related control signals for the bank designated
by the bank address included in address signal ADD is activated, and the operation
related to row selection is performed in an activated bank.
For simplifying the figure, structures of sub-memory arrays SMA
1 and SMA
3
are not shown in FIG.
81. These sub-memory arrays SMA
1 and SMA
3
have structures similar to those of sub-memory arrays SMA
0 and SMA
2,
and local control circuits LCK
00-LCK
07 and LCK
10-LCK
17
controls the row selecting operation therein.
Each of data paths DPA and DPB includes a write driver, a preamplifier and a
data I/O buffer, and transmits data to and from the memory cell on a column selected
by column decoder CDA.
As shown in FIG. 81, the row selection is performed on a block basis in each
of
banks BA#
0 and BA#
1, so that unselected memory blocks can be maintained
in the precharged state, and the current consumption can be reduced.
The address signal (referred to as a "word line address signal", hereinafter)
for designating a word line must be applied commonly to all the memory blocks,
or commonly to local control circuits LCK
00-LCK
07 and LCK
10
and LCK
17.
FIG. 82 shows an example of a structure of an input buffer in main control circuit
MCK. Main control circuit MCK takes in externally applied command CMD and address
signal ADD in synchronization with external clock signal ECLK (internal clock signal
CLK). In FIG. 82, input buffer IB includes: an inverter IV that inverts clock signal
(internal clock signal) CLK; a transmission gate XF
1 that is turned on to
pass input signal IN when clock signal CLK is at L-level; an inverter latch IL
1
that latches the signal passing through transmission gate XF
1; a transmission
gate XF
2 that is turned on to pass the signal latched by inverter latch
IL
1 when clock signal CLK is at H-level; and an inverter latch IL
2
that latches the signal passing through transmission gate XF
2 for producing
an internal output signal OUT.
Transmission gates XF
1 and XF
2 are CMOS transmission gates,
respectively, and are turned on/off in synchronization with clock signal CLK and
a complementary clock signal generated from inverter IV. An operation of input
buffer IB shown in FIG. 82 will now be described with reference to a signal waveform
diagram shown in FIG.
83.
When clock signal CLK is at L-level, transmission gate XF
1 is conductive,
and inverter latch IN
1 latches input signal IN. Meanwhile, transmission
gate XF
2 is non-conductive, and output signal OUT does not change.
When clock signal CLK rises to H-level, transmission gate XF
1 is turned
off, and input signal IN does not affect the latched signal of inverter latch IL
1.
When clock signal CLK rises to H-level, transmission gate XF
2 is responsively
turned on, and the signal latched by inverter latch IL
1 is transmitted to
inverter latch IL
2, so that output signal OUT is produced. Accordingly,
output signal OUT changes in synchronization with the rising of clock signal CLK.
Input buffer IB shown in FIG. 82 is provided in main control circuit MCK for
each of address signal ADD and command CMD. Internal signals are produced in synchronization
with rising of clock signal CLK, and therefore, the internal signals change in
synchronization with the rising of clock signal CLK if a setup/hold time to clock
signal CLK is ensured. Therefore, it is not necessary to consider a skew between
these input signals, and it is possible to set the start timing of the internal
operations faster.
FIG. 84 schematically shows line loads of the internal clock signal, row-related
control signal and the predecode block address signal. In FIG. 84, internal clock
signal CLK is transmitted by a clock driver DRV
0 via a signal line SGL
0.
Row-related control signal BR (BR
0 or BR
1) is transmitted by a drive
circuit DRV
1 through a signal line SGL
1. Predecode block address
signal PB is transmitted by a drive circuit DRV
2 via a signal line SGL
2.
As shown in FIG. 81, the internal clock signal must be applied commonly to local
control circuits LCK
00-LCK
07 and LCK
10-LCK
17, and therefore,
signal line SGL
0 have the largest load capacitance C
0.
As for the row-related control signal BR, since all the local control circuits
of the corresponding bank are coupled thereto, signal line SGL
1 have a second
largest load capacitance C
1.
As for predecode block address signal PB, the local control circuits for the
two
memory blocks are connected in each bank to predecode block address signal bit
group PBG
1, so that the signal lines for the predecode block address signal
bit group PBG
1 has the smallest load capacitance C
2. For predecode
block address signal group PBG
0, four local control circuits are connected
in each bank to the signal lines for transmitting the predecode block address signal
group PBG
0. Therefore, a repeater may be arranged between the banks, whereby
the load of the driver can be reduced, and the line load thereof can be made smaller
than that for the row-related control signal. Since these signal lines SGL
0-SGL
2
have different line load capacitances C
0-C
2, their signal transmission
delay times are different from each other, resulting in skews between these signals.
In particular, these signals are transmitted unidirectionally along the column
direction from main control circuit MCK toward local control circuit LCK
17
at the remotest position. Therefore, a difference in signal transmission delay
time also occurs between local control circuit LCK
00 nearest to main control
circuit MCK and local control circuit LCK
17 remotest therefrom, and therefore
a difference occurs in magnitude of the skew between the both.
FIG. 85 schematically shows a timing relationship among the input signals of
local control circuits LCK
00 and LCK
17 as well as the externally
applied signals, i.e., clock signal ECLK, address signal ADD and command CMD.
Main control circuit MCK is supplied with external clock signal ECLK, address
signal ADD and command CMD. In synchronization with rising of external clock signal
ECLK, main control circuit MCK takes in externally applied address signal ADD and
command CMD, and produces predecode block address signal PBA and row-related control
signal BR (BR
0 or BR
1). For local control circuit LCK
00 nearest
to main control circuit MCK, the smallest phase difference occurs between internal
clock signal CLK and external clock signal ECLK. Main control circuit MCK produces
row-related control signal BR
0 and predecode block address signal PBA in
synchronization with internal clock signal CLK, for transmission to local control
circuit LCK
00.
In local control circuit LCK
00, signal line SGL
0 transmitting internal
clock signal CLK has large interconnection capacitance C
0, and internal
clock signal CLK arrives at local control circuit LCK
00 with a slight delay
to arrival of predecode block address signal PBA and row-related control signal
BR
0. In this case, however, the interconnection lines of these signals are
short so that a skew between predecode block address signal PBA and internal clock
signal CLK is small. If local control circuit LCK
00 performs an operation
synchronized with internal clock signal CLK at the above described timing, the
setup time of the predecode block address signal PBA is insufficient so that a
malfunction may occur.
In local control circuit LCK
17 remotest from main control circuit MCK,
internal clock signal CLK is transmitted with the largest delay due to the long
interconnection length. Likewise, the delay times of row-related control signal
BR
1 and predecode block address signal PBA are larger than those for local
control circuit LCK
00, but are smaller than that of internal clock signal
CLK to the local control circuit LCK
7. In this case, a large phase difference
occurs between predecode block address signal PBA and internal clock signal CLK,
and thus a large skew occurs. In local control circuit LCK
17, therefore,
it is impossible to advance a timing for starting an internal operation, and the
fast operation is impossible.
The operation start timing in each local control circuit may be determined depending
on the distance from main control circuit MCK. However, such individual determination
scheme complicates the circuit design. As external clock signal ECLK becomes faster,
the timing adjustment time becomes an extremely short time, so that the timing
adjustment must be performed extremely exactly. For the operation stability, the
operation timing of the internal circuits may be determined in accordance with
the worst skew conditions of local control circuit LCK
17 remotest from main
control circuit MCK. However, such a scheme based on the worst case makes the fast
operation impossible.
In predecode block address signal PBA, predecode block address bit groups PBG
0
and PBG
1 are different in line load and delay time. Therefore, the timing
at which all the predecode block address bits are made definite differs for different
local control circuits, and an accurate decoding may not be performed.
FIG. 86 shows schematically a structure of main control circuit MCK. In FIG.
86, main control circuit MCK includes: a clock buffer
900 which receives
externally applied clock signal ECLK, and produces internal clock signal CLK; a
command input buffer
902 which takes in externally applied command CMD in
synchronization with internal clock signal CLK from clock buffer
900; a
row address input buffer
904 which takes in externally applied address signal
ADD in synchronization with internal clock signal CLK; a row-related control signal
generating circuit
905 which decodes the command received from command input
buffer
902 in synchronization with internal clock signal CLK, and produces
a row-related control signal BR
0 for bank BA#
0 in accordance with
the result of decoding; a row-related control signal generating circuit
906
which decodes the command received from command input buffer
902 in synchronization
with internal clock signal CLK, and produces a row-related control signal BR
1
for bank BA#
1 in accordance with the result of decoding; and a column related
control circuit
908 which decodes the command received from command input
buffer
902 in synchronization with internal clock signal CLK, and controls
the operation of circuits related to data access (column selection).
Row-related control signal generating circuits
905 and
906
receive a bank address BAD from row address input buffer
904, and activates
the row-related signal generating circuit provided for the bank designated by bank
address BAD. Row-related control signal BR
0 for bank BA#
0 includes
a row address decode enable signal RADE<
0>, a word line drive
timing signal RXT<
0>, a bit line isolation instructing signal
BLI<
0>, a bit line equalize instructing signal BLEQ<
0>
and sense amplifier activating signals SON<
0> and SOP<
0>.
Likewise, row-related control signal BR
1 for bank BA#
1 includes the
corresponding signals RADE<
1>, RXT<
1>, BLI<
1>,
BLEQ<
1>, SON<
1> and SOP<
1>.
According to the configuration shown in FIG. 86, column-related control
circuit
908 controls data path DP performing input/output of data. However,
column-related control circuit
908 also controls the operation of column
decoders provided for banks BA#
0 and BA#
1. Data path DP includes
a write driver, a preamplifier, a data input buffer and a data output buffer.
As shown in FIG. 86, main control circuit MCK includes row-related control signal
generating circuits
905 and
906 corresponding to banks B#
0
and BA#
1, respectively. For providing more banks, therefore, the row-related
control signal generating circuits must be increased in number, and therefore,
a layout of the row-related control signal generating circuits in main control
circuit MCK must be changed. Therefore, main control circuit MCK must be re-designed
depending on a bank configuration. When the load on the signal line changes in
re-designing, further re-design is required for adjusting an inter-signal skew.
Therefore, it is difficult to accommodate the change in bank structure. If the
banks increase in number, the row-related control signal generating circuits increase
in number, and the signal lines for transmitting the row-related control signals
increase in number, so that the interconnection region and the area occupied by
the circuits increase, and the chip size increases.
In general, a storage capacity required for an embedded DRAM merged with a logic
on a common chip depends on its application purpose, and it is required to change
the number of memory blocks in accordance with the required storage capacity. In
the embedded DRAM, memory cells store information in the form of electric charges
accumulated in capacitors. Therefore, a refresh operation for rewriting or restoring
the stored information of the memory cells must be performed periodically. If the
memory blocks are variable in number as described above, a power is wasted in the
refresh operation, and an access efficiency is lowered as well.
FIG. 87 schematically shows a structure of a portion related to refresh of one
sub-memory array SMA. In FIG. 87, sub-memory array SMA includes, e.g., 12 memory
blocks MB
0-MB
11. In each of memory blocks MB
0-MB
11,
512 word lines WL are arranged.
Local control circuits LCK
0-LCK
11 are arranged corresponding
to memory blocks MB
0-MB
11, respectively. Local control circuits LCK
0-LCK
11
control operations related to row selection in corresponding memory blocks MB
0-MB
11,
respectively. FIG. 87 representatively shows a block decoder BD, which produces
a block select signal for selecting the corresponding memory block. Word line driver
groups WDG
0-WDG
11 are provided corresponding to memory blocks MB
0-MB
11,
respectively. Word line driver groups WDG
0-WDG
11 drive the word lines,
which are selected in accordance with word line select signals applied from corresponding
local control circuits LCK
0-LCK
11, to the selected state, respectively.
Each of word line driver groups WDG
0-WDG
11 includes word line
drivers arranged corresponding to word lines in corresponding one among memory
blocks MB
0-MB
11. The word line driver includes a main word line driver
and a sub-word line driver if word line WL in the memory block is formed into a
hierarchical word line structure. The sub-word line drivers are arranged corresponding
to the sub-word lines, respectively, and are distributed in the corresponding memory
block. The main word line driver is arranged corresponding to the main word line,
and is located on one side of the corresponding memory block. For the sake of simplicity,
FIG. 87 shows the word line driver group (main word line drivers) arranged on one
side of the memory block.
For generating a block address for designating the memory block, there are provided:
an address input buffer
910 which takes in an externally applied address
signal ext<
11:
0> of 12 bits in synchronization with clock
signal CLK; a refresh counter
912 performing a count operation in synchronization
with a refresh activating signal REF that is rendered active for a predetermined
period in response to the refresh instruction signal applied from a command decoder
shown in FIG. 86, and generating a refresh address QA<
11:
0>;
a multiplexer
914 which selects one of the internal address signal applied
from address input buffer
910 and read address bits QA<
11:
0>
applied from refresh counter
912 in accordance with refresh activating signal
REF; and inverters IV
2-IV
0 which invert block address signal RA<
11:
9>
of 3 bits received from multiplexer
914 to produce a complementary internal
address signal. Multiplexer
914 applies an address signal RA<
8:
0>
of 9 bits to a row decoder of a local control circuit (not shown).
Refresh counter
912 increments or decrements its refresh count value
(refresh address) in synchronization with rising or falling of clock signal CLK
when refresh activating signal REF is active.
In the structure shown in FIG. 87, the block address signal is formed of three
bits RA<
11:
9>, and two memory blocks are simultaneously
selected in twelve memory blocks MB
0-MB
11. In the arrangement shown
in FIG. 87, a block address "000" is allocated to memory blocks MB
0 and
MB
6, a block address "001" is allocated to memory blocks MB
1 and
MB
7, and a block address "010" is allocated to memory blocks MB
2
and MB
8.
Also, a block address "011" is allocated to memory blocks MB
3 and MB
9,
and a block address "100" is allocated to memory blocks MB
4 and MB
10.
A block address "101" is allocated to memory blocks MB
5 and MB
11.
When the refresh is executed in this structure, therefore, word lines WL are
simultaneously driven to the selected state in the two memory blocks. If refresh
counter
912 are configured to accommodate 16 memory blocks, count value
QA<
11:
9> of this block address must return to the initial
block address "000" after changing from "000" to "101". For applying refresh counter
912 to the structure including 16 memory blocks, a block address of four
bits must be generated. Depending on a required specification, the refresh is executed
on a memory block basis (i.e., a memory block at a time) or is executed in a unit
of two memory blocks (i.e., two memory blocks at a time). In order to adapt to
various specifications, a block address signal of four bits is required for executing
the refresh on the memory block basis.
Therefore, if refresh counter
912 of the above structure is used,
the count value of refresh counter
912 must be counted up from "110
—00000
0001" to "1111
—1111 1111" when the refreshing for memory blocks
MB
5 and MB
1 is completed. Thus, a refresh command must be successively
input until the count-up of refresh counter
912. Thus, in spite that refreshing
of the memory cells in the whole space of sub-memory array SMA is completed by
counting up refresh address QA<
11:
0> from "000
—000000000"
to "101
—111111111", the refresh command must be further applied
(512×2) times for setting the refresh address to the initial value.
Accordingly, in the structure formed of 12 memory blocks, the refresh
command must be applied (512×8=4 K) times in total although the refresh of
memory cells in the whole space is completed by applying the refresh command (512×6=3
K) times. Therefore, it is necessary to input the refresh command, which does not
cause the refresh but is used merely for operating the refresh counter. During
this period of input of refresh command, external access is impossible, and in
addition, refresh counter
912 wastes the power.
It may be considered to provide refresh counter
912 with a reset circuit
for resetting the count value to an initial value of "000 000 000" when the count
value reaches "101
—111111111". However, such reset circuit can
be employable only for a structure formed of 12 memory blocks, and cannot be employed
for a structure of 16 memory blocks.
If the number of memory blocks is equal to an integer of a power of 2, input
of
an unnecessary refresh command can be prevented by resetting the count value of
refresh counter
912 at the time of change in any one of block address bits
RA<
11:
9>. However, if the number of memory blocks is equal
to, e.g., 12, and is not equal to an integer of a power of 2, as shown in FIG.
87, it is required to program the address of the final refresh memory block in
the refresh sequence using a fuse program circuit or the like, for resetting refresh
counter
912 in accordance with matching/mismatching between the block address
bits output from refresh counter
912 and the programmed refresh block address.
A layout area of a fuse element is larger than that of a transistor element. Also,
the fuse program circuit requires a large layout area for preventing short-circuit
due to a fragment produced upon blowing off the fuse. Therefore, if the fuse program
circuit is used, a circuit scale of the refresh counter increases, and an area
occupied by the refresh counter increases.
If the number of memory blocks increases to 16 in the structure shown in FIG.
87, the number of bank address signal bits increases to 4 bits, so that it is necessary
to change the combination of the block address signal bits for selecting a block
decoder BD. Accordingly, for changing the input of the address signal of block
decoder BD in each local control circuit, an interconnection pattern must be changed
in accordance with the number of memory blocks, resulting in a problem that the
memory blocks cannot be expanded easily. In other words, it becomes difficult to
change the number of memory blocks by optimising the layout of word line driver
group WDG and local control circuit LCK for one memory block, and repeating this
optimised layout. The interconnection layout of the block address signal bits must
be changed in accordance with change in number of the memory blocks. As a result,
it is impossible to adapt to the change in number of memory blocks and thus change
in storage capacity without difficulty.
In the case of changing the refresh cycle in accordance with a required specification,
i.e., changing the number of word line(s) to be selected simultaneously in the
refresh operation, the greatest block address of the refresh address counter also
changes, and the block address in the refresh operation for the memory blocks must
be changed. Therefore, it is impossible to accommodate for the change in refresh
cycle, similarly to the above case.
For ensuring reliability of the semiconductor memory device, the semiconductor
memory device must be tested after production. For this test, the test control
signal must be applied in synchronization with a clock signal if the semiconductor
memory device is of a clock synchronous type. Timing margins of each external signal
and data for the clock signal as well as access times can be tested in the semiconductor
memory device of the clock synchronous type described above.
However, it is impossible to test a timing margin for to an internal control
signal when internally selecting a memory cell. For example, it is impossible to
measure a so-called RAS precharge time tRP through measurement of a time period
required for internal precharge. In this case, the minimum measurable unit time
of the RAS precharge time is equal to one clock cycle time of the clock signal
even if the precharge command instructing the precharge and the row active command
instructing the memory cell selection are successively applied. This is because
the command is applied in synchronization with the clock signal. With a fast operable
tester, the clock cycle period can be reduced, and the internal timing can be measured.
However, such a fast test apparatus is expensive, and increases a test cost per
device so that the semiconductor memory device becomes expensive.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device with an
improved main control circuit, which can overcome the foregoing problems.
Another object of the invention is to provide a semiconductor memory device,
which can be flexibly adapted to change in bank structure.
Still another object of the invention is to provide a semiconductor memory
device, in which a skew between signals does not change regardless of a position
of a memory block.
Yet another object of the invention is to provide a semiconductor memory device,
which can reduce a signal interconnection area.
Further another object of the invention is to provide a semiconductor memory
device of a multi-bank structure, which has a reduced chip size, and can operate stably.
A further object of the invention is to provide a semiconductor memory device,
which can suppress increase in area of interconnections for main control signals
even if banks increase in number.
A still further object of the invention is to provide a semiconductor memory
device,
in which a structure of main control circuit is independent of a bank configuration.
A further object of the invention is to provide a semiconductor memory device
provided
with a refresh-related circuit, which can efficiently refresh a memory array of
an arbitrary storage capacity.
A further object of the invention is to provide a refresh-related circuit, which
can efficiently perform a refresh operation without requiring an additional circuit
and change in circuit configuration even if the number of memory blocks and/or
the number of word lines change.
A further object of the invention is to provide a semiconductor memory device,
which can easily implement various refresh cycles.
A further object of the invention is to provide a semiconductor memory device,
which can reduce power consumption during a standby state.
A further object of the invention is to provide a semiconductor memory device,
which allows accurate measuring of internal operation timing.
A further object of the invention is to provide a semiconductor memory device,
which allows accurate measuring of internal operation timing with a slow test apparatus.
A semiconductor memory device according to the present invention includes: a
main
control circuit for producing a plurality of main control signals different in
phase from each other in response to a row-related instructing signal instructing
an operation related to row selection; and a sub-control circuit receiving the
plurality of main control signals, for producing sub-control signals greater in
number than the plurality of main control signals. These sub-control signals are
signals for controlling an operation instructed by the row-related instructing signal.
A semiconductor memory device according to a second aspect of the present invention
includes a plurality of memory blocks each having a plurality of memory cells each
requiring storage data refreshed periodically.
A semiconductor memory device according to the second aspect of the invention
further
includes a refresh address generating circuit for generating a refresh address
signal designating a memory cell to be refreshed in accordance with a refresh instruction
instructing refresh of the memory cell data. The refresh address signal includes
a refresh block address signal designating a memory block to be refreshed among
said plurality of memory blocks.
The semiconductor memory device according to the second aspect of the invention
further includes block select circuits arranged corresponding to the plurality
of memory blocks, and each producing a refresh block select signal indicating whether
the corresponding memory block is selected or not, in accordance with the refresh
address signal. The refresh address generating circuit includes a reset signal
producing circuit for producing a reset signal for resetting a refresh block address
signal generated by said refresh address generating circuit to an initial value
in accordance with at least the refresh block select signal.
The plurality of main control signals are produced in accordance with the row-related
instructing signal, and these main control signals different in phase are converted
into the sub-control signals by the sub-control circuit. Thus, it is not necessary
to generate a large number of signals by the main control circuit, and control
signal lines between the main control circuit and the sub-control circuit can be
reduced in number. Accordingly, the area occupied by the signal interconnection
lines can be reduced.
These main control signals are produced merely in accordance with the row-related
instructing signal, and the main control signal common to the plurality of banks
can be produced. Neither the reduction in interconnection area nor the change in
number and structure of banks requires the change in structure of the main control
circuit, so that it is possible to accommodate for the change in bank configuration flexibly.
With the main control signal and an address signal equal in line load, signal
transmission delay of each signal line can be made equal to those of other signal
lines, and an inter-signal skew can be reduced. Even if a signal transmission delay
occurs, the delay of signal in each sub-control circuit can be equal to that in
other sub-control circuits, and the inter-signal skews in the sub-control circuits
can be equal to each other. Therefore, the signal timing can be easily adjusted,
and a stably operating semiconductor memory device can be achieved.
By adjusting an active period of the main control signal in accordance with the
test control signal, it is possible to adjust an activation period and timing of
the sub-control signal produced from the main control signal. Thereby, the internal
operation parameter can be measured. In particular, the semiconductor memory device
may be supplied with the test control signal, which is produced asynchronously
to the clock signal, so that various operation parameters can be measured while
changing internal operation conditions, with a slow test apparatus.
The refresh address signal generated by the refresh address generating circuit
is reset to the initial value in accordance with at least the refresh block select
signal for a specific memory block applied from the block select circuit provided
for each of the memory blocks. Thereby, it is possible to set the refresh address
generated by the refresh address generating circuit to an initial value in accordance
with the refresh block select signal of the final memory block in the refresh sequence.
Accordingly, it is not necessary to provide a complicated circuit arrangement such
as a program circuit in the refresh address generating circuit. Regardless of the
number of memory blocks, it is not necessary to change the structure of the refresh
address generating circuit in accordance with the storage capacity. Further, the
number of times of refreshing can be easily set in accordance with the number of
memory cells to be refreshed. It is not necessary to input unnecessarily a refresh
command, and it is possible to suppress increase in power consumption as well as
decrease in access efficiency. Further, it is easy to accommodate for a change
in storage capacity.
When the internal address signal line is statically driven, the internal address
signal is fixed at the refresh address except the period of access in the normal
operation mode. Thereby, charging and discharging of the internal address signal
line can be prevented so that the power consumption can be reduced. Further, the
power consumption of the block decoder can be reduced.
The foregoing and other objects, features, aspects and advantages of the present
invention will become more apparent from the following detailed description of
the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically shows a structure of a main portion of a semiconductor
memory device according to a first embodiment of the invention;
FIG. 2 schematically shows a structure of a semiconductor integrated circuit
device containing a semiconductor memory device according to the invention;
FIG. 3 shows more specifically a structure of a main control circuit and a local
control circuit shown in FIG. 1;
FIG. 4 is a signal waveform diagram representing an operation of the circuits
shown in FIG. 3;
FIG. 5 shows more specifically a structure of a sense amplifier and a memory
block shown in FIG. 3;
FIG. 6 schematically shows a structure of an output portion of the main control
circuit and an input portion of the local control circuit in the first embodiment
of the invention;
FIG. 7 is a signal waveform diagram representing an operation of the structure
shown in FIG. 6;
FIG. 8 shows an example of a structure of an address input circuit shown in
FIG. 3;
FIGS. 9A-9C schematically illustrate an effect of the structure shown in FIG. 6;
FIG. 10A shows a structure of a main row activation control circuit shown in
FIG. 3, and FIG. 10B is a signal waveform diagram representing an operation of
the circuit shown in FIG. 10A;
FIG. 11A shows a modification of the main row activation control circuit, and
FIG. 11B is a signal waveform diagram representing an operation of the circuit
of FIG. 11A;
FIG. 12A shows a structure of a main precharge control circuit shown in FIG.
3, and FIG. 12B is a signal waveform diagram representing an operation of the circuit
shown in FIG. 12;
FIG. 13A shows a modification of the main precharge control circuit, and FIG.
13B is a signal waveform diagram representing an operation of the circuit of FIG. 13A;
FIG. 14 schematically illustrates an effect of the structures shown in FIGS.
10A and 12A;
FIG. 15A shows a structure of a delay circuit shown in FIG. 12, and FIG. 15B
shows a modification of a delay value setting circuit shown in FIG. 15A;
FIG. 16 shows a structure of a second modification of the delay value setting
circuit shown in FIG. 15A;
FIG. 17 shows a structure of a third modification of the delay value setting
circuit shown in FIG. 15A;
FIG. 18 shows a structure of a local control circuit shown in FIG. 3;
FIG. 19 is a signal waveform diagram representing an operation of a circuit
shown in FIG. 18;
FIG. 20 shows signal waveforms in high speed operation of the circuit shown
in FIG. 18;
FIG. 21 shows a structure of a block address decoder shown in FIG. 3;
FIG. 22 shows a structure of a first modification of the block address decoder
shown in FIG. 21;
FIG. 23 shows a structure of a select circuit shown in FIG. 22;
FIG. 24 schematically shows a structure of a second modification of a block
address decoder shown in FIG. 21;
FIG. 25 shows a structure of a third modification of a block address decoder
shown in FIG. 24;
FIG. 26 shows a sequence for generating a plurality of main control signal sets;
FIG. 27 schematically shows a structure of a main control circuit implementing
an operation sequence shown in FIG. 26;
FIG. 28A shows a structure of an ACT counter shown in FIG. 27, FIG. 28B shows
a structure of a latch 92 shown in FIG. 28A, and FIG. 28C shows a structure
of a latch 93 s
