Title: Semiconductor substrate and process for its production
Abstract: The present invention provides a semiconductor substrate comprising a semiconductor layer 3 formed on a supporting substrate 1 with interposition of an insulating layer 2 therebetween, wherein a mark is formed in a region other than a surface region of the semiconductor layer; and a process for producing the semiconductor substrate.
Patent Number: 6,953,948 Issued on 10/11/2005 to Sakaguchi
| Inventors:
|
Sakaguchi; Kiyofumi (Kanagawa-ken, JP)
|
| Assignee:
|
Canon Kabushiki Kaisha (Tokyo, JP)
|
| Appl. No.:
|
178361 |
| Filed:
|
June 25, 2002 |
Foreign Application Priority Data
| Jan 07, 2000[JP] | 2000-001478 |
| Current U.S. Class: |
257/48; 257/347; 257/797 |
| Intern'l Class: |
H01L 023/58 |
| Field of Search: |
257/48,347,797
|
References Cited [Referenced By]
U.S. Patent Documents
| 5256578 | Oct., 1993 | Corley et al.
| |
| 5371037 | Dec., 1994 | Yonehara.
| |
| 5374564 | Dec., 1994 | Bruel.
| |
| 5451886 | Sep., 1995 | Ogita et al.
| |
| 5458755 | Oct., 1995 | Fujiyama et al.
| |
| 5466631 | Nov., 1995 | Ichikawa et al.
| |
| 5532520 | Jul., 1996 | Haraguchi et al.
| |
| 5821562 | Oct., 1998 | Makita et al.
| |
| 5856229 | Jan., 1999 | Sakaguchi et al.
| |
| 5869386 | Feb., 1999 | Hamajima et al.
| |
| 5952694 | Sep., 1999 | Miyawaki et al.
| |
| 6004405 | Dec., 1999 | Oishi et al.
| |
| 6121064 | Sep., 2000 | Lasky et al.
| |
| 6313014 | Nov., 2001 | Sakaguchi et al.
| |
| 6350703 | Feb., 2002 | Sakaguchi et al.
| |
| Foreign Patent Documents |
| 0311087 | Apr., 1989 | EP.
| |
| 0311087 | Apr., 1989 | EP.
| |
| 0 867 917 | Sep., 1998 | EP.
| |
| 5-211128 | Aug., 1993 | JP.
| |
| 6-196379 | Jul., 1994 | JP.
| |
| 7-302889 | Nov., 1995 | JP.
| |
| 8-037 137 | Feb., 1996 | JP.
| |
| 2608351 | Feb., 1997 | JP.
| |
| 9-153603 | Jun., 1997 | JP.
| |
| 11-45840 | Feb., 1999 | JP.
| |
| 11-176708 | Jul., 1999 | JP.
| |
| 94-14237 | Jun., 1994 | KR.
| |
| 395041 | Jun., 2000 | TW.
| |
Primary Examiner: Jackson; Jerome
Attorney, Agent or Firm: Fitzpatrick, Cella, Harper & Scinto
Parent Case Text
This application is a division of application Ser. No. 09/749,730, filed Dec.
28, 2000 now abandoned.
Claims
1. A semiconductor substrate comprising a semiconductor layer formed on a supporting
substrate with interposition of an insulating layer therebetween,
wherein a mark for identification of the semiconductor substrate is formed on
a bevelled surface of the peripheral region of the supporting substrate at which
the semiconductor layer is not present, and
wherein the semiconductor substrate is a bonding SOI substrate, and the mark
is formed on the surface where bonding is not conducted.
2. A semiconductor substrate comprising a semiconductor layer formed on a supporting
substrate with interposition of an insulating layer therebetween,
wherein a mark for identification of the semiconductor substrate is formed on
a bevelled surface of the peripheral region of the supporting substrate at which
the semiconductor layer is not present, and
wherein the semiconductor substrate is a bonding SOI substrate, and the mark
is formed on the surface outside a position corresponding to a contact edge.
3. A semiconductor substrate comprising a semiconductor layer formed on a supporting
substrate with interposition of an insulating layer therebetween,
wherein a mark for identification of the semiconductor substrate is formed on
a bevelled surface of the peripheral region of the supporting substrate at which
the semiconductor layer is not present, and
wherein the semiconductor substrate is a bonding SOI substrate, and the mark
is formed on the surface outside a position corresponding to a contact edge or
a bonding edge.
4. A semiconductor substrate comprising a semiconductor layer formed on a supporting
substrate with interpositon of an insulating layer therebetween,
wherein a mark for identification of the semiconductor substrate is formed on
a bevelled surface of a peripheral region of the supporting substrate at which
the semiconductor layer is not present, and wherein the semiconductor substrate
is a bonding SOI substrate.
5. A semiconductor substrate comprising a semiconductor layer formed on a supporting
substrate with interposition of an insulating layer therebetween,
wherein a mark for identification of the semiconductor substrate is formed on
a bevelled surface of a peripheral region of the supporting substrate.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor substrate for use in production
of a semiconductor integrated circuit device such as semiconductor memories, microprocessors,
and system LSIs; and a process for production thereof. In particular, the present
invention relates to a semiconductor substrate having thereon a mark for identification
of the semiconductor substrates and the like, and a process for production thereof.
2. Related Background Art
The semiconductor substrate includes mirror-wafers which are a disk-shaped substrate
produced by slicing an ingot and have at least one face polished, and epitaxial
wafers constituted of a mirror-wafer and a semicrystalline semiconductor layer
formed on the mirror-wafer.
On the other hand, an SOI technique is widely known which forms a single-crystalline
semiconductor layer on an insulator or on a substrate having an insulating layer.
This product is called a silicon-on-insulator, or a semiconductor-on-insulator.
The semiconductor substrate formed thereby is called an SOI substrate or an SOI wafer.
Three processes below are typical for producing SOI substrates:
(1) A SIMOX process (separation by ion-implanted oxygen) which forms an SiO
2
layer by oxygen ion implantation into an Si single-crystalline substrate.
(2) A smart cut process which comprises the steps of implanting hydrogen ions
into an Si single-crystalline substrate, bonding another substrate, heat-treating
it to grow microbubbles formed in the ion-implanted layer, and separating the Si
single-crystalline substrate. The SOI substrate produced by this process is known
as Unibond. The detail thereof is disclosed in Japanese Patent Application Laid-Open
No. 5-211128 and its corresponding U.S. Pat. No. 5,374,564.
A modification of this process is known which comprises the steps of implanting
hydrogen ions by hydrogen plasma into an Si single-crystalline substrate, bonding
another substrate thereon, and applying high-pressure nitrogen gas to the side
wall of the bonded substrates to separate the Si single-crystalline substrate at
the ion-implanted layer.
(3) A still another process for SOI substrate production is a process for transferring
a porous semiconductor layer formed on a porous body onto another substrate. This
process is known to give a highest quality of the SOI substrate since the semiconductor
layer can be formed by epitaxial growth on a porous body. Specific example are
disclosed in Japanese Patent No. 2,608,351 and its corresponding U.S. Pat. No.
5,371,037, Japanese Patent Application Laid-Open No. 7-302889 and its corresponding
U.S. Pat. No. 5,856,229, and Japanese Patent No. 2,877,800 and its corresponding
EP 0,867,917. The process shown in these patent and applications is advantageous
in that the thickness of the SOI layer is uniform, crystal defect density can readily
be decreased, the surface of the SOI layer has a good flatness, the equipment for
the production is inexpensive, a wide range of the SOI film thickness from several
hundred Å to about 10 μm can be produced with one equipment, and so forth.
When wafers pass through the production step of semiconductor integrated circuit
devices (device step), it is preferable that the wafers are identified individually.
The identification of the wafers is highly effective in managing the step history
of the individual wafers, and is utilized in failure analysis, optimization of
the step, production control, and so forth. The identification of mirror wafers
can be conducted using a mark formed on the wafer surface with a laser beam.
FIG. 18 shows a cross section of a wafer after thus laser marking. The region
of the surface of the wafer irradiated with laser beam is melted to become a recessed
portion, and the wafer material repelled out from the recessed portion by melting
solidifies on the periphery of the recessed portion in a shape of a somma as shown
in FIG.
18. For example, in the case where the laser having a power of 220
mW is applied in dot onto the surface of a silicon wafer, the maximum diameter
X
1 of the deformed region ranges from 0.04 mm to 0.05 mm, the diameter X
2
of the recessed portion at the center ranges from 0.02 mm to 0.03 mm, the depth
Y
1 of the recessed portion ranges from 2 μm to 3 μm, and the
height Y
2 of the protruded portion ranges from 0.5 μm to 1.0 μm.
These dimensions vary depending on the laser power. In practice, laser beam is
applied in pulse to form many dots partially overlapped or separately, thereby
picturing a mark. The wafer material to be the somma may be disappear. It is possible
that the mark without the somma is formed by adjusting laser power, laser frequency
or shot counts of laser. Shallow mark with somma may be formed by low power laser.
High power laser forms deep mark without somma by scattering or spreading the material
to be the somma. The mark on the mirror wafer is usually constituted from about
10 alphanumerical characters, and denotes a specific ID number of each of the wafers.
This is a normal method which is prescribed by the International Standard of SEMI.
Such a laser marking method is assumed for usual Si mirror wafers, and the marking
position is also prescribed in the SEMI Standard.
FIG. 19 is a top view of a mirror wafer
21 having a mark formed thereon,
and FIG. 20 is a sectional view of the mirror wafer
21 at and around the
mark. For example, in a 8-inch wafer as shown in FIG. 19 with a notch
12
placed upward, taking the center
100 of the wafer as the origin (0,0) of
an x-y coordinate, the aforementioned SEMI Standard prescribes that a mark
4
should be formed in a marking region
24 where X ranges from -9.25 to +9.25
mm, Y ranges from +93.7 to +96.5 mm, that is, in a rectangular region
24
in the height L
2 being 2.8 mm, the length L
1 being 18.5 mm.
If this standard is applied to the SOI wafer, the marking range comes to the
surface
region of the semiconductor layer (SOI layer) on the insulating layer.
FIG. 21 is a top view of an SOI wafer having the mark formed thereon. FIG. 22
is a sectional view at and around the mark. The laser output level and other conditions
of the laser are prescribed for Si mirror wafers not to cause splash of particles.
Therefore, in the marking on an SOI wafer according to the above SEMI standard,
particles are generated and a dot diameter changes in some cases due to its multilayer
structure and the action of a heat-accumulating layer of SiO
2.
In the case of deep mark, change of dot diameter is more seriously. FIG. 23 shows
schematically this state. For example, in the case where a laser beam is projected
onto an SOI wafer having an SOI layer of 100 to 200 nm thick, a buried insulating
layer of 100 to 200 nm thick under the same laser irradiation conditions as in
the case of FIG. 18, the diameter X
1 of the inner protruded portion is about
0.045 mm, the diameter X
2 of the recessed portion is about 0.04 mm, the
distance X
3 between the inner protruded portion and the outer protruded
portion ranges from 0.02 to 0.03 mm, the depth Y
1 of the recessed portion
ranges from 2.5 to 3.0 μm, the height Y
2 of the inner protruded portion
ranges from 1.0 to 1.5 μm, and the height Y
3 of the outer protruded
portion ranges from 0.8 to 1.5 μm. Incidentally, the depth Y
1 of the
recessed portion, and the heights Y
2 and Y
3 are indicated as approximate values.
In formation of the mark on the SOI layer surface, it is observed that the recessed
portion constituting marked characters becomes bold and particles
25 are
splashed around the characters, as shown in FIG.
23. The conditions of not
causing the splashing of particles depend on the SOI layer structure and the thickness
of the respective layers, so that the setting conditions therefor are complicated
and laborious. Furthermore, when the laser has a lower output level that the particle
splashing is retarded, the depth of the recessed portion formed by the laser irradiation
becomes smaller, thereby rendering the reading of the mark difficult.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor substrate which
has a readable mark and can be easily marked without causing deposition of splashed
particles, and to provide also a process for producing the semiconductor substrate.
According to an aspect of the present invention, there is provided a semiconductor
substrate having a semiconductor layer formed on a supporting substrate with interposition
of an insulating layer therebetween, wherein a mark is formed on a region other
than a surface region of the semiconductor layer.
According to another aspect of the present invention, there is provided
a process for producing a semiconductor substrate having a semiconductor layer
formed on a supporting substrate with interposition of an insulating layer therebetween,
the process comprising a step of forming a mark on a region other than a surface
region of the semiconductor layer.
According to still another aspect of the present invention, there is provided
a semiconductor substrate having a semiconductor layer formed on a supporting substrate
with interposition of at least one layer therebetween, wherein a mark is formed
on a region other than a surface region of the semiconductor layer.
According to a further aspect of the present invention, there is provided
a process for producing a semiconductor substrate having a semiconductor layer
formed on a supporting substrate with interposition of at least one layer therebetween,
the process comprising a step of forming a mark on a region other than a surface
region of the semiconductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a top view of a part of a semiconductor substrate according to an
embodiment of the present invention.
FIG. 2 is a sectional view of a part of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 3 is a top view of a part of another semiconductor substrate according
to an embodiment of the present invention.
FIG. 4 is a sectional view of a part of another semiconductor substrate according
to an embodiment of the present invention.
FIG. 5 is a top view of a part of a semiconductor substrate according to an
embodiment of the present invention.
FIG. 6 is a sectional view of a part of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 7 is a sectional view of a part of bonded substrates according to an embodiment
of the present invention.
FIGS. 8A, 8B, 8C, 8D, 8E and 8F are sectional
views explaining production steps of a semiconductor substrate according to an
embodiment of the present invention.
FIG. 9 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 10 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 11 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 12 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIGS. 13A, 13B, 13C, 13D, 13E and 13F are
sectional views explaining production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIGS. 14A, 14B, 14C, 14D and 14E are sectional
views explaining a production steps of a semiconductor substrate according to an
embodiment of the present invention.
FIG. 15 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 16 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 17 is a flow chart of production steps of a semiconductor substrate according
to an embodiment of the present invention.
FIG. 18 is a cross-sectional view showing the shape of a laser mark.
FIG. 19 is a top view of a part of a semiconductor substrate.
FIG. 20 is a cross-sectional view of a part of a semiconductor substrate.
FIG. 21 is a top view of a part of an SOI substrate.
FIG. 22 is a cross-sectional view of a part of an SOI substrate.
FIG. 23 is a cross-sectional view showing the shape of a laser mark.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
I. Constitution of Semiconductor Substrate
Embodiments of the semiconductor substrate according to the present invention
is described below.
Embodiment 1
FIG. 1 is a top view of a part of a semiconductor substrate according to the
present invention. FIG. 2 is a cross-sectional view of the semiconductor substrate
taken along the line
2—
2 of FIG.
1.
An SOI substrate is constituted of a supporting substrate
1 such as a
single-crystalline
silicon wafer, a buried insulating layer
2 such as of silicon oxide, and
a semiconductor layer (SOI layer)
3 such as a single-crystalline silicon layer.
In a surface region
5 of the semiconductor layer
3, a semiconductor
device for an integrated circuit and the like is formed. A mark
4 is formed
in a region
6 which is a nearly flat region of the surface of peripheral
region
13 of the semiconductor substrate. The substrate has a notch
12.
The edge of the surface region
5 of the SOI layer
3 (i.e., inside
border line of the peripheral region) is indicated by the circle of a radius R
2.
The outer peripheral edge (outside border line of the peripheral region) of the
substrate is indicated by the circle of a radius R
1. The region between
the circle of the radius R
2 and the circle of the radius R
1 is the
peripheral region
13.
In more detail, general SOI wafers available at present usually have a region
having a width of several millimeters inward from the outer peripheral edge of
the wafer, in which a device is not formed. This region is called "edge exclusion".
In a SIMOX, for example, the SOI layer in the region having a width of several
millimeters inward from the outer peripheral edge may have a thickness of an off-specification
or other detects caused by the nonuniformity of ion implantation.
In a bonding SOI wafer, a region having a width of several millimeters from the
outer peripheral edge of a wafer is not bonded owing to sagging of the peripheral
portion of an original wafer as a starting material, whereby the region has no
SOI structure. Further, since the edge line of the SOI layer is not smooth, patterning
is sometimes conducted to remove a part of the SOI layer to bring artificially
the edge thereof inward.
In marking on such an SOI wafer, the mark should be formed on a region having
no SOI structure. Therefore, on bonded wafers having no SOI layer in the peripheral
region, the marking is conducted on the peripheral region
13 as shown in
FIGS. 1 and 2. This method is advantageous in that the marking can be conducted
in a less number of the steps and that the number of the chips obtainable in the
SOI region is not decreased, in comparison with the SOI layer removal method.
Embodiment 2
FIG. 3 is a top view of a part of a semiconductor substrate according to the
present invention. FIG. 4 is a cross-sectional view of the semiconductor substrate
taken along the line
4—
4 of FIG.
3.
A semiconductor layer (SOI layer)
3 and a insulating layer
2 are
partially hollowed and removed to form an exposed region
14, where a part
of the supporting substrate
1 is exposed, inside the edge of the semiconductor
layer
3, namely on a region (internal region) excluding the peripheral region
13 from the supporting substrate
1.
The mark
4 is made on this exposed region
14. Although in FIG.
3 the mark
4 is constituted of alphabets, the mark
4 may be a bar
code, a numeral, a character, a symbol, or combination thereof.
The edge (inside border line of the peripheral region) of the surface region
5 of the SOI layer
3 is shown by a circle line of radius R
2.
The outer peripheral edge (outside border line of the peripheral region) of the
substrate is shown by the circle of a radius R
1. In this Embodiment, the
mark is formed inside the circle of a radius R
2.
The semiconductor substrate according to this Embodiment is produced through
the steps of preparing a semiconductor substrate such as an SOI wafer, masking
the semiconductor substrate except the region for formation of the exposed region
14, removing the portion of the semiconductor layer
3 from the region
not masked for exposed region formation by etching or the like, removing the underlying
insulating layer
2 by etching or the like to expose the surface of the semiconductor,
and forming a mark by laser irradiation or the like on the exposed region
14,
whereby an SOI substrate is obtained as shown in FIGS. 3 and 4.
Embodiment 3
In this Embodiment, the mark is formed on the back surface of the supporting substrate.
In this Embodiment, the mark is formed on the back surface of a supporting substrate
of the SOI substrate in the same manner as the marking on the front surface of
a mirror wafer as shown in FIGS. 19 and 20.
Since the mark is made on the back surface of the supporting substrate, the
effective area of the SOI layer on the front surface of the supporting substrate
is not decreased.
Embodiment 4
FIGS. 5 and 6 illustrate the structure of the peripheral region marked and
its vicinity in a semiconductor substrate.
FIG. 5 is a top view of the peripheral region and its vicinity. FIG. 6 is a
sectional view of the peripheral region and its the vicinity.
Numeral
34 denotes an edge of a buried insulating layer
2.
Numeral
35 denotes an edge of SOI layer
3. In this Embodiment, the
edge
34 of the insulating layer
2 is extended to the outside of the
edge
35 of the SOI layer
3. Thereby, under-etching of the insulating
layer
2 by cleaning or the like with a cleaning solution having an etching
property can be prevented to retard chipping of the SOI layer. However, this is
not essential. More preferably, the corner of the SOI layer
3 or of the
buried insulating layer
2 may be worked to round it off or to make the angle obtuse.
The mark
4 is formed in an outer part in the peripheral region
13.
In FIG. 5, the mark
4 is made outside an imaginary line
33′.
The imaginary line
33′ is explained by reference to FIG.
7.
FIG. 7 is a sectional view of bonded substrates produced by bonding two substrate
for preparing a bonding SOI substrate. In FIG. 7, the mark
4 is made outside
the position indicated by the numeral
33. The mark
4 is formed on
a flat surface of the peripheral region
13. The flat surface is not contacted
with the wafer
30. A part of the mark
4 may be formed on a bevelled
surface of the peripheral region. In the bonded state of the two substrates, the
edge of the bonding interface is at the position indicated by the numeral
32,
which position is called "contact edge". Thereafter, the bonded substrates are
heat-treated (or bonding-annealed) to increase the bonding strength of the substrates,
whereby the edge of the bonding interface moves outward to the position indicated
by the numeral
33 to increase the area of the bonding interface.
Later, the unnecessary portion of the substrate
30 is removed to make
the substrate
30 thinner to obtain the SOI substrate. On the surface of
the supporting substrate
1 of the resulting SOI substrate, the original
position of the bonding edge
33 is indicated by the imaginary line
33′,
and the original position of the contact edge
32 is indicated by the imaginary
line
32′.
Numeral
31 shows an intended position corresponding to the edge
35
of the completed SOI layer
3. The distance L
31 from the outer peripheral
edge of the supporting substrate
1 is preferably not more than 3 mm, more
preferably as small as possible in a range of 3 mm or less.
The position of the contact edge
32 is determined depending on the shape
of the outer peripheral portion of the used substrates
1 and
30 after
beveling: the distance L
32 between the outer peripheral edge of the supporting
substrate
1 and the contact edge
32 varies depending on the beveled
shape of the outer peripheral portion. Similarly the bonding edge
33 is
shifted slightly.
If roughness or a foreign particle is present in the vicinity of the contact
edge
32 of the substrate-bonding face, the bonding is difficultly carried out
in the vicinity to cause slight inward shifting of the contact edge
32 as
well as of the bonding edge
33. In such a case, the edge of the strongly
bonded region is moved inward, which forces the edge
35 of the SOI layer
3 to move inward to a position where a sufficient bonding strength can be
achieved, thereby preventing shortening of the distance L
31.
The mark in the present invention can be formed at a portion between the outer
peripheral edge of the supporting substrate and the edge of the SOI layer, more
preferably outside the position
32′ corresponding to the contact
edge
32. Also preferably, the mark is formed outside the position
33′
corresponding to the bonding edge
33.
Preferably also, only the portion of the bonding edge
33 or the
contact edge
32 for mark formation is moved inward locally and the mark
is made thereon without decreasing the effective area of the SOI layer.
Embodiments of the semiconductor substrate according to the present invention
are explained above. The present invention is not limited thereto, and includes
substitution of the constituting element to an equivalent provided that the objects
of the present invention can be achieved.
The supporting substrate useful in the present invention may be a semiconductor
substrate of Si, Ge, SiC, GaAs, GaAlAs, GaN, InP, or the like, but is not limited
thereto, provided that a mark can be formed on the surface thereof.
The insulating layer useful in the present invention may be composed of at least
one of silicon oxide, silicon nitride, silicon oxide nitride, and the like. The
insulating layer may be constituted of a single layer or a lamination of plural
layers. The thickness of the insulating layer may be in the range from 1 nm to
10 μm.
The semiconductor layer useful in the present invention is formed from at least
one semiconductor including Si, Ge, SiC, GaAs, GaAlAs, GaN, InP and the like. The
semiconductor layer may be of a single layer or a lamination of plural layers.
The thickness of the semiconductor layer may be in the range from 1 nm to 10 μm.
The shape of the semiconductor substrate of the present invention is not limited
to the notched wafer as shown in FIG. 1, but may be other shape of a wafer such
as a wafer having an orientation flat. The SOI substrate for use in the present
invention may be a nonbonding substrate such as a SIMOX wafer, but is preferably
a bonding SOI substrate.
The region for the marking may be near the notch or the orientation flat, or
at the position opposing thereto, or may be at any other position.
The mark is formed in the peripheral region as mentioned above. Preferably, the
mark is formed therein on a flat portion or slightly inclined portion formed by
beveling. Otherwise, the mark may be formed on a portion exposed by partial removal
of the semiconductor layer.
The marking can be conducted by Nd:YAG laser, CO
2 lager, or the like,
or by use of a diamond pen.
The mark may be constituted of at least one of numerals, characters, symbols,
and bar codes, and the like, or combination thereof. The characters include alphabet,
Japanese kana, and Greek characters.
For a special use, the SEMI standard need not be applied. The numerals, characters,
symbols, and the like for constituting the mark may be arranged in a line or in
a curve along the outer peripheral edge of the wafer. In the case where the peripheral
region formed by removal of the semiconductor layer is narrow, or where the number
of digits of the mark is large, the mark is preferably arranged in a curve along
the outer peripheral edge not to interfere the SOI layer.
The marked wafers may be packed up and shipped without further treatment, or
may be packed up after washing or inspection and shipped. Otherwise, the marked
wafers may be introduced to a device production step without treatment or after
cleaning or inspection.
II. Process for Producing Semiconductor Substrate
Embodiments of the process is described below for producing the above
semiconductor substrate according to the present invention.
The process for producing the semiconductor substrate according to the present
invention comprises the steps of preparing a semiconductor substrate having a semiconductor
layer formed on a supporting substrate with interposition of an insulating layer
therebetween, and forming a mark on a region other than the surface region of the
semiconductor layer.
The semiconductor substrate useful in the present invention is described above.
The preferred semiconductor substrate includes nonbonding SOI substrates having
an insulating layer formed by oxygen and/or nitrogen ion implantation and heat
treatment; bonding SOI substrates produced by ion-implanting hydrogen and/or inert
gas onto a first substrate, bonding the first substrate to a second substrate as
a supporting substrate, and separating the bonded substrates at a separation layer
having been formed by the above ion implantation; and bonding SOI substrates having
a semiconductor layer formed by transferring a nonporous semiconductor layer formed
on a porous layer onto a supporting substrate.
Another process for producing the semiconductor substrate according to the
present invention comprises a step of marking on a supporting substrate such as
a so-called handle wafer before formation of an SOI structure.
Embodiment 5
A process for producing a semiconductor substrate is explained with reference
to
FIGS. 8A to
8F and
9.
A first substrate
30 such as a single-crystalline silicon wafer is anodized
to form a porous layer
37 such as a porous silicon layer on the surface.
Further, if necessary, the inside wall of the pores of the porous silicon is thermally
oxidized to form a protective silicon oxide film. Then the openings on the surface
of the porous layer
37 are sealed by heat treatment in a hydrogen atmosphere.
On the porous layer
37, a nonporous semiconductor layer
38 such
as a single-crystalline silicon layer is formed by epitaxial growth by CVD or the
like. This semiconductor
38 layer is a layer to be transferred, that is,
becomes a transferred layer. Further, if necessary, an insulating layer
39
is formed by thermal oxidation of the first substrate
30. Thus a structure
as shown in FIG. 8A is produced through the steps S
11 and S
12 in
FIG.
9.
Then a second substrate such as a single-crystalline silicon wafer is prepared
in the step S
21. Marking is conducted on the surface of the peripheral portion
thereof in the step S
22. If necessary, the surface of the second substrate
may be thermally oxidized to form an insulating layer. Otherwise, the marking may
be made on the back surface of the second substrate at its any position. Primary
process for producing a single-crystalline silicon wafer comprises the steps of
slicing a silicon ingot, lapping, etching and polishing. Deep mark is formed prior
to lapping or etching. Shallow mark is formed prior to polishing.
The two substrates are bonded together in the step S
13 as shown in FIG.
8B. The strength of the bonding may be increased by heat treatment in an
oxidative atmosphere or the like. In the case where the marking is conducted on
the front surface, the mark is preferably formed outside the contact edge or outside
the bonding edge in the step S
13.
In the step S
14, the unnecessary portion of the first substrate is removed.
Specifically, as shown in FIG. 8C, the nonporous portion
36 of the back
surface side of the first substrate is removed from the bonded substrates by at
least one of the methods of grinding, polishing, etching, and separation. Then,
the porous layer
37 remaining on the surface (formerly the back surface)
of the semiconductor
38 bonded to the second substrate is removed by polishing,
etching, or hydrogen annealing, or is made nonporous. Thus the transfer of the
semiconductor layer
38 is completed.
In the step S
15, the peripheral portion of the SOI substrate is formed.
Specifically, as shown in FIG. 8E, the exposed surface of the semiconductor layer
38 is covered by an etching mask of a sealing material, photoresist, or
the like. Then the peripheral portion of the semiconductor layer
38 is removed
by etching so that the edge of the semiconductor layer
38 for forming the
SOI layer is brought to the position
31 shown in FIGS. 5 to
7. Further,
the peripheral portion of the insulating layer
39 is also removed by etching
or polishing.
In such a manner, an SOI substrate is prepared as shown in FIG.
8F. The
mark on the SOI substrate is formed at the position shown in FIGS. 1,
2,
5 and
6.
Embodiment 6
Another process for producing a semiconductor substrate is explained with
reference to FIG.
10.
This Embodiment is different from the above Embodiment 5 in that the marking
is conducted between the steps of removing unnecessary portions of the first substrate.
In the same manner as in Embodiment 5, a first substrate after the steps S
11
and S
12 is bonded to an unmarked second substrate (Step S
13).
In the step S
14, a part of the unnecessary portions of the first substrate
is removed. Specifically, as shown in FIG. 8C, the nonporous portion
36
on the back surface side of the first substrate is removed by at least one of the
methods of grinding, polishing, etching, and separation.
Then in the step S
15, the marking is conducted at the peripheral portion
of the front surface side of the second substrate. Even if foreign matters splashed
by the marking deposit onto the front surface of the second substrate, the splashed
matters are removed from the front surface in the subsequent step of removing the
porous layer
37. Therefore, the surface region of the semiconductor layer
for forming the SOI layer is not soiled with the foreign matter. Otherwise, the
marking may be conducted on the back surface side of the second substrate.
In the subsequent step of S
16, the porous layer
37 remaining on
the surface (formerly the back surface) of the semiconductor layer
38 bonded
to the second substrate is removed by polishing, etching, or hydrogen annealing,
or is made nonporous. Thus the transfer of the semiconductor layer
38 is completed.
Then in the step S
17, the peripheral portion of the SOI substrate is formed.
In such a manner, an SOI substrate is obtained as shown in FIG.
8F. The
mark on the SOI substrate is formed at the position as shown in FIGS. 1,
2,
5 and
6.
Embodiment 7
Still another process for producing a semiconductor substrate is explained
with reference to FIG.
11.
This Embodiment is different from the above Embodiment 5 in that the marking
is conducted after the step of removing unnecessary portions of the first substrate
and before the step of formation of peripheral portion.
In the same manner as in Embodiment 5, a first substrate after the steps S
11
and S
12 is bonded to an unmarked second substrate (Step S
13).
In the step S
14, a part of the unnecessary portion of the first substrate
is removed. Specifically, as shown in FIG. 8C, the nonporous portion
36
on the back surface side of the first substrate is removed by the methods of grinding,
polishing, etching, separation, or the like. Then, as shown in FIG. 8D, the porous
layer
37 remaining on the surface (formerly the back surface) of the semiconductor
layer
38 bonded to the second substrate is removed by polishing, etching,
or hydrogen annealing, or is made nonporous. Thus the transfer of the semiconductor
layer
38 is completed.
In some cases in the above-mentioned separation of the nonporous portion, the
interface between the porous layer and the semiconductor layer
38 may be
cracked, thereby allowing the porous layer to be separated together with the nonporous
portion from the semiconductor layer
38. After this separation, in some
cases, there is no remaining porous layer on the semiconductor layer
38.
Then, in the step S
15, the marking is conducted at the peripheral portion
of the front surface side of the second substrate with a mask MK covering the surface
region of the semiconductor
38, as shown in FIG.
8E. In the marking,
even if foreign matters splashed by the marking operation deposit onto the front
surface of the second substrate, the splashed matters are removed in the subsequent
step of removing the mask MK from the front surface side. Therefore, the surface
region of the semiconductor layer for forming the SOI layer is not soiled by foreign
matters. Otherwise, the marking may be conducted on the back surface side of the
second substrate.
In the subsequent step S
16, the peripheral portion of the SOI substrate
is formed using the mask MK.
In such a manner, an SOI substrate is obtained as shown in FIG.
8F. The
mark on the SOI substrate is formed at the position as shown in FIGS. 1,
2,
5 and
6.
Embodiment 8
A further process for producing a semiconductor substrate is explained with reference
to FIG.
12.
This Embodiment is different from the above Embodiment 7 in that the marking
is conducted after formation of the peripheral portion with the mask MK kept covering
in the same manner as in Embodiment 7 and without peeling the mask MK.
Thus in this Embodiment, an SOI substrate is also prepared as shown in FIG.
8F. The mark on the SOI substrate is formed at the position shown in FIGS.
1,
2,
5 and
6.
Embodiment 9
A process for producing a bonding semiconductor substrate is explained which
employs
an ion-implanted layer as a separation layer, with reference to FIGS. 13A to
13F.
A first substrate
30 such as a single-crystalline silicon wafer is thermally
oxidized at the surface to form an insulating layer
39 such as a silicon
oxide layer. Thereto, inert gas ions such as hydrogen ions, helium ions, and neon
ions are implanted to a predetermined depth to form an ion-implanted layer
40
where the concentration of the implanted ions is locally high. The portion positioned
on the ion-implanted layer
40 is a layer to be transferred, that is, becomes
a transferred layer. FIG. 13A shows the structure of the first substrate
30
thus obtained.
Separately, a second substrate such as a single-crystalline wafer is
prepared. A marking is conducted on the peripheral portion of the front surface,
or the marking may be conducted on the back surface side of the second substrate.
The first substrate and the second substrate are bonded together so that the
semiconductor layer
38 is placed inside, thereby obtaining a structure as
shown in FIG.
13B.
The bonded substrates are then heat-treated at a temperature ranging from 400
to 600° C. or higher to increase the bonding strength and simultaneously cause
cracking in the ion-implanted layer
40. Thereby the portion
36 of
the first substrate comes off from the bonded substrates, and the semiconductor
layer
38 is transferred onto the second substrate as shown in FIG.
13C.
The exposed separation surface of the semiconductor layer
38 is polished.
In this step, the peripheral portions of the layers
38 and
39 may
be removed simultaneously to obtain the structure shown in FIG.
13D. Otherwise,
hydrogen annealing may be conducted instead of the polishing, or the polishing
and the hydrogen annealing are successively conducted. It is preferable that annealing
for enhancing bonding strength is performed prior to polishing or subsequent to polishing.
Then, the peripheral portion of the SOI substrate is formed. Specifically,
as shown in FIG. 13E, the exposed surface of the semiconductor layer
38
is covered by an etching mask MK made of a sealing material, photoresist, or the
like. The peripheral portion of the semiconductor layer
38 is removed by
etching so that the edge of the semiconductor layer
38 for forming the SOI
layer is brought to the position
31 shown in FIGS. 5 to
7. Further,
the peripheral portion of the insulating layer
39 is also removed by etching
or polishing.
In such a manner, an SOI substrate is obtained as shown in FIG.
13F. The
mark on the SOI substrate is formed at the position as shown in FIGS. 1,
2,
5 and
6.
After the step of FIG. 13C, the step of FIG. 13E may be conducted by omitting
the step of FIG.
13D.
Embodiment 10
This Embodiment is conducted in the same manner as in Embodiment 9 except that
the timing of the marking is changed, that is, the marking is conducted in a peripheral
region on the front surface of the supporting substrate with using the mask MK
in the covering state as shown in FIG. 13E before removal of the peripheral portion
of the semiconductor layer
38.
Thus an SOI substrate is obtained as shown in FIG.
13F. The mark on the
SOI substrate is formed at the position as shown in FIGS. 1,
2,
5
and
6. Otherwise the marking may be conducted on the back surface of the
supporting substrate. In the case that polishing or cleaning can remove particles
generated by marking, masking step is not required.
Embodiment 11
This Embodiment is conducted in the same manner as in Embodiment 9 except that
the timing of the marking is changed, that is, the marking is conducted in a peripheral
region on the front surface of the supporting substrate with using the mask MK
in the covering state as shown in FIG. 13E after removal of the peripheral portion
of the semiconductor layer
38 before removal of the mask MK.
Thus an SOI substrate is obtained as shown in FIG.
13F. The mark on the
SOI substrate is formed at the position as shown in FIGS. 1,
2,
5
and
6. Otherwise the marking may be conducted on the back surface of the
supporting substrate.
Embodiment 12
A process of producing a semiconductor substrate with a non-bonding method is
explained
with reference to FIGS. 14A to
14E and
15.
In the step S
11 of FIG. 15, a semiconductor substrate
1 such as
a single-crystalline wafer is prepared as shown in FIG.
14A.
In the step S
12 of FIG. 15, the marking is conducted on the peripheral
region on the front surface side of the semiconductor substrate. Otherwise, the
marking may be conducted on the back surface side of the semiconductor substrate.
Then, the surface of the semiconductor substrate
1 is thermally oxidized
to form an insulating layer
41 such as a silicon oxide layer, as shown in
FIG.
14B.
In the step S
13 of FIG. 15, insulator-forming ions such as oxygen ions
are implanted to a predetermined depth to form an ion-implanted layer where the
concentration of the implanted ions is locally high. This substrate is heat-treated
to form a buried insulating layer
2 composed of a compound of the implanted
oxygen and silicon. The portion of the semiconductor layer
3 on this insulating
layer
2 becomes an SOI layer. The resulting SOI substrate has a structure
as shown in FIG.
14C.
In the step S
14 of FIG. 15, the unnecessary portion of the insulating
layer
41 at least on the surface side of the SOI layer is removed to obtain a
marked SOI substrate. When the marking is conducted on the front side surface,
the marked portion is also made to have the SOI structure having recessed and protruded
portions by the ion implantation and the heat treatment after the marking, thereby
enabling identification of the mark from the front surface side. In this case,
the step of FIG. 14D need not be conducted.
As a modification of this Embodiment, the ion implantation may be conducted in
a region excluding the marked portion to form a marked portion not having the SOI
structure on the peripheral portion of the front surface side.
Embodiment 13
A process of producing a semiconductor substrate is explained with reference
to
FIGS. 14A to
14E and
16. This Embodiment is conducted in the same
manner as in Embodiment 12 except that the timing of the marking is changed.
In the step S
11 of FIG. 16, a semiconductor substrate
1 such as
a single-crystalline wafer is prepared as shown in FIG.
14A.
Then, the surface of the semiconductor substrate
1 is thermally oxidized
to form an insulating layer
41 such as a silicon oxide layer as shown in
FIG.
14B.
In the step S
12 of FIG. 16, insulator-forming ions such as oxygen ions
are implanted to the substrate in a predetermined depth to form an ion-implanted
layer where the concentration of the implanted ions is locally high. This substrate
is heat-treated to form a buried insulating layer
2 composed of a compound
consisting of the implanted oxygen and silicon. The semiconductor layer
3
positioned on this insulating layer
2 becomes an SOI layer. The resulting
SOI substrate has a structure as shown in FIG.
14C.
In the step S
13 of FIG. 16, as shown in FIG. 14D, a mask MK is applied
and, if necessary, the insulating layer
41 is removed, and the marking is
conducted. The mark is formed such that the recessed portion of the mark reaches
the lower portion of the insulating layer
2 through the semiconductor layer
3.
In the step S
14 of FIG. 16, the mask MK and unnecessary insulating layer
41 are removed to obtain an SOI substrate as shown in FIG.
14E.
In this Embodiment, since the SOI layer is protected by the mask, even when splash
of the particles is caused by laser marking, the soiling by splash of the particles
can be prevented.
Embodiment 14
A process of producing a semiconductor substrate is explained with reference
to
FIG.
17. This Embodiment is conducted in the same manner as in Embodiment
13 except that the timing of the marking is changed.
The steps S
11 and S
12 of FIG. 17 are conducted in the same manner
as in Embodiment 13.
In the step S
13 of FIG. 17, the unnecessary insulating layer
41
is removed from the semiconductor as shown in FIG. 14E to obtain an SOI substrate.
In the step S
14 of FIG. 17, the surface region of the semiconductor layer
is covered with a mask, and the marking is conducted in the peripheral region on
the front surface side of the SOI substrate. The mark is formed such that the recessed
portion of the mark reaches the lower portion of the insulating layer
2
through the semiconductor layer
3.
In this Embodiment, since the SOI layer is protected by the mask, even when splash
of the particles is caused by laser marking, the soiling by splash of the particles
can be prevented.
Embodiment 15
A process of production of a bonding semiconductor substrate is explained with
reference to FIGS. 8A to
8F.
A single-crystalline substrate of a P-type or N-type having a specific resistance
of 0.01 Ω.cm is prepared as a first substrate. This substrate is anodized
in an HF-containing solution to form a porous layer
37 as a separation layer.
The anodization conditions for forming the porous layer
37 consisting
of porous silicon as a single layer are exemplified as below:
- Current density: 7 (mA.cm-2)
- Anodization solution:
- Hydrofluoric acid:water:ethanol=1:1:1
- Time: 11 (minutes)
- Porous layer thickness: 12 (μm)
The thickness of the porous layer can be varied in the range from several hundred
μm to about 0.1 μm by adjusting the anodization time.
In formation of porous layer constituted of plural porous silicon layers, the
first step and the second step of the anodization may be conducted under the conditions
as below:
First step
- Current density: 7 (mA.cm-2)
- Anodization solution:
- Hydrofluoric acid:water:ethanol=1:1:1
- Time: 5 (minutes)
- First porous layer thickness: 5.5 (μm)
Second step
- Current density: 30 (mA.cm-2)
- Anodization solution:
- Hydrofluoric acid:water:ethanol=1:1:1
- Time: 10 (seconds)
- Second porous layer thickness: 0.2 (μm)
The first porous silicon layer formed firstly as the surface layer by anodization
at a lower current density is employed for formation of a high-quality epitaxial
Si layer, and the second porous silicon layer formed secondly as the lower layer
by anodization at a higher current density is employed for facilitating the separation,
the two porous layers having different functions. Therefore, the thickness of the
porous Si layer formed is not limited to the above, but may range from several
hundred μm to about 0.1 μm. In addition to the above two layers, third
layer or more layers may be formed thereon.
This substrate is oxidized at 300 to 600° C. in an oxygen atmosphere to
cover the inside walls of the holes of the porous silicon with a protection film
composed of a thermal oxidation film. The surface of the porous layer
37
is treated with hydrofluoric acid to remove only the oxide film on the surface
of the porous layer
37 while the oxide film on the inside walls of the holes
is kept unremoved. On the porous silicon, single-crystalline silicon is grown epitaxially
by CVD (chemical vapor deposition). The growth conditions are shown below.
| |
|
| |
Source gas: |
SiH2Cl2/H2 |
| |
Gas flow rate: |
0.5/180 L/min |
| |
Gas pressure: |
1.1 × 104 Pa (about 80 Torr) |
| |
Temperature: |
950° C. |
| |
Growth rate: |
0.3 μm/min |
| |
|
Prior to the epitaxial growth, the porous layer
37 is heat-treated (prebaked)
in a hydrogen atmosphere in the epitaxial growth chamber. This heat treatment is
necessary for improving the quality of the crystal of an epitaxial growth layer
38. Actually, the crystal defects of the epitaxial growth layer
38
can be decreased to not more than 10
4 cm
-2. The resulting
epitaxial growth layer
38 is employed later as the transferred layer.
On the surface of this epitaxial growth layer, an SiO
2 layer of 20
nm to 2 μm thick is formed as an insulating layer
39 by thermal oxidation.
Thus the structure is obtained as shown in FIG.
8A.
The surface of the insulating layer
39 and a surface of a separately prepared
second Si substrate are brought into contact with each other, and the contacted
substrates are heat-treated at a temperature of 1100° C. for 2 hours to cause
bonding of the substrates, whereby the structure as shown in FIG. 8B is obtained.
From the resulting multilayered structure, the porous layer
37 is removed
to obtain an SOI substrate which comprises the second substrate
1 and the
epitaxial growth layer
38 transferred thereon. For this, the portion
36
of the first Si substrate is removed by grinding, polishing, etching or the like
to expose the porous layer
37, and then the porous layer
37 is removed
by etching. Otherwise, the multilayered structure is separated at the porous layer
37, and if the porous portion remains on the separation face of the epitaxial
growth layer
38 transferred onto the second substrate
1, the porous
portion is removed by etching, hydrogen annealing or the like.
