Single transistor vertical memory gain cell Number:7,149,109 from the United States Patent and Trademark Office (PTO) owispatent A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.<H transistor, vertical, Single, transist, 7149109.html, Patent, pto, 7149109

Title: Single transistor vertical memory gain cell

Abstract: A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Patent Number: 7,149,109 Issued on 12/12/2006 to Forbes

Inventors: Forbes; Leonard (Corvallis, OR)
Assignee: Micron Technology, Inc. (Boise, ID)

Appl. No.: 10/929,307

Filed: August 30, 2004

Current U.S. Class: 365/174 ; 365/185.05; 365/185.18; 365/185.2

Current International Class: G11C 11/34 (20060101); G11C 7/00 (20060101)

Field of Search: 365/174,145,185.05,185.18,185.2

References Cited [Referenced By]

U.S. Patent Documents


4130892	December 1978	Gunckel et al.
4826780	May 1989	Takemoto et al.
4970689	November 1990	Kenney
4999811	March 1991	Banerjee
5006909	April 1991	Kosa
5017504	May 1991	Nishimura et al.
5021355	June 1991	Dhong et al.
5042011	August 1991	Casper et al.
5066607	November 1991	Banerjee
5078798	January 1992	Nicolson et al.
5122986	June 1992	Lim
5220530	June 1993	Itoh
5280205	January 1994	Green et al.
5291438	March 1994	Witek et al.
5308783	May 1994	Krautschneider et al.
5329481	July 1994	Seevinck et al.
5378914	January 1995	Ohzu et al.
5381302	January 1995	Sandhu et al.
5385853	January 1995	Mohammad
5414288	May 1995	Fitch et al.
5448513	September 1995	Hu et al.
5478772	December 1995	Fazan
5506166	April 1996	Sandhu et al.
5519236	May 1996	Ozaki
5574299	November 1996	Kim
5627785	May 1997	Gilliam et al.
5707885	January 1998	Lim
5719409	February 1998	Singh et al.
5732014	March 1998	Forbes
5793686	August 1998	Furutani et al.
5815432	September 1998	Naffziger et al.
5854500	December 1998	Krautschneider
5897351	April 1999	Forbes
5909618	June 1999	Forbes et al.
5936274	August 1999	Forbes et al.
5937296	August 1999	Arnold
5959327	September 1999	Sandhu et al.
5966319	October 1999	Sato
5973356	October 1999	Noble et al.
5991225	November 1999	Forbes et al.
5995419	November 1999	Trimberger
5998820	December 1999	Chi et al.
5999442	December 1999	Van Der Sanden et al.
5999455	December 1999	Lin et al.
6030847	February 2000	Fazan et al.
6031263	February 2000	Forbes et al.
6072209	June 2000	Noble et al.
6077745	June 2000	Burns, Jr. et al.
6097065	August 2000	Forbes et al.
6104061	August 2000	Forbes et al.
6111286	August 2000	Chi et al.
6118152	September 2000	Yamaguchi et al.
6124729	September 2000	Noble et al.
6143636	November 2000	Forbes et al.
6150687	November 2000	Noble et al.
6153468	November 2000	Forbes et al.
6172390	January 2001	Rupp et al.
6172901	January 2001	Portacci
6191448	February 2001	Forbes et al.
6204115	March 2001	Cho
6238976	May 2001	Noble et al.
6246083	June 2001	Noble
6249020	June 2001	Forbes et al.
6249460	June 2001	Forbes et al.
6282115	August 2001	Furukawa et al.
6307775	October 2001	Forbes et al.
6316309	November 2001	Holmes et al.
6350635	February 2002	Noble et al.
6384448	May 2002	Forbes
6399979	June 2002	Noble et al.
6456535	September 2002	Forbes et al.
6492233	December 2002	Forbes et al.
6501116	December 2002	Kisu et al.
6504201	January 2003	Noble et al.
6531730	March 2003	Sandhu et al.
6538916	March 2003	Ohsawa
6549453	April 2003	Wong
6556471	April 2003	Chappell et al.
6560139	May 2003	Ma et al.
6566682	May 2003	Forbes
6611451	August 2003	Houston
6624033	September 2003	Noble
6625057	September 2003	Iwata
6661042	December 2003	Hsu
6680864	January 2004	Noble
6686624	February 2004	Hsu
6710465	March 2004	Song et al.
6727141	April 2004	Bronner et al.
6750095	June 2004	Bertagnoll et al.
6838723	January 2005	Forbes
6940761	September 2005	Forbes
6943083	September 2005	Forbes
6956256	October 2005	Forbes
6975531	December 2005	Forbes
7030436	April 2006	Forbes
2001/0028078	October 2001	Noble
2001/0030338	October 2001	Noble
2001/0032997	October 2001	Forbes et al.
2001/0053096	December 2001	Forbes et al.
2002/0098639	July 2002	Kisu et al.
2002/0126536	September 2002	Forbes et al.
2003/0001191	January 2003	Forbes et al.
2003/0129001	July 2003	Kisu et al.
2003/0155604	August 2003	Sandhu et al.
2003/0205754	November 2003	Forbes et al.
2004/0026728	February 2004	Yoshida et al.
2004/0041236	March 2004	Forbes
2005/0012130	January 2005	Forbes
2005/0024936	February 2005	Forbes
2005/0032313	February 2005	Forbes
2005/0068828	March 2005	Forbes
2005/0094453	May 2005	Forbes
2005/0263763	December 2005	Bhattacharyya
2005/0265069	December 2005	Forbes
2006/0028859	February 2006	Forbes
2006/0043411	March 2006	Bhattacharayya

Foreign Patent Documents


61140170	Jun., 1986	JP
5226661	Sep., 1993	JP

Other References

Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM Journal of Research & Development, 39(1-2), (Jan.-Mar. 1995), 167-188. cited by other .
Blalock, T. N., et al., "An Experimental 2T Cell RAM with 7 NS Access Time at Low Temperature", 1990 Symposium on VLSI Circuits. Digest of Technical Papers, (1990), 13-14. cited by other .
Kim, Wonchan, "A low-voltage multi-bit DRAM cell with a built-in gain stage", ESSCIRC 93. Nineteenth European Solid-State Circuits Conference. Proceedings, (1993),37-40. cited by other .
Kim, W., "An Experimental High-Density DRAM Cell with a Built-in Gain Stage", IEEE Journal of Solid-State Circuits, 29(8), (Aug. 1994),978-981. cited by other .
Krautschneider, W H., et al., "Fully scalable gain memory cell for future DRAMs", Microelectronic Engineering, 15(1-4), (Oct. 1991),367-70. cited by other .
Krautschneider, F., "Planar Gain Cell for Low Voltage Operation and Gigabit Memories", Symposium on VLSI Technology Digest of Technical Papers, (1995),139-140. cited by other .
Mukai, M., et al., "A novel merged gain cell for logic compatible high density DRAMs", 1997 Symposium on VLSI Technology. Digest of Technical Papers, (Jun. 10-12, 1997),155-156. cited by other .
Mukai, M, et al., "Proposal of a Logic Compatible Merged-Type Gain Cell for High Density Embedded . . . ", IEEE Transactions on Electron Devices, (Jun. 1999),1201-1206. cited by other .
Ohsawa, T., "Memory design using one-transistor gain cell on SOI", IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002),152-455. cited by other .
Okhonin, S., "A SOI capacitor-less 1T-DRAM concept", 2001 IEEE International SOI Conference. Proceedings, IEEE. 2001, (2000),153-4. cite- d by other .
Rabaey, Jan M., "Digital integrated circuits : a design perspective", Upper Saddle River, N.J. : Prentice Hall, (1996),585-590. cited by other .
Shukuri, S., "A conplementary gain cell technology for sub-1 V supply DRAMs", International Electron Devices Meeting 1992. Technical Digest, (Cat. No.92CH3211-0),(1992),1006-9. cited by other .
Shukuri, S., "A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAMs", IEEE Transactions on Electron Devices, 41(6), (Jun. 1994),926-931. cited by other .
Shukuri, S., "Super-Low Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell", Symposium on VLSI Technology. Digest of Technical Papers, (1993),23-24. cited by other .
Sunouchi, K., et al., "A self-amplifying (SEA) cell for future high density DRAMs", International Electron Devices Meeting 1991. Technical Digest, (1991),465-8. cited by other .
Takato, H., et al., "Process Integration Trends for Embedded DRAM", ULSI Process Integration. Proceedings of the First International Symposium (Electrochemical Society Proceedings vol. 99-18, (1999),107-19. cited by other .
Terauchi, M., "A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs", 1993 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, Japan,(1993),21-22. cited by other .
Wann, Hsing-Jen, "A Capacitorless DRAM Cell on SOI Substrate", International Electron Devices Meeting 1993. Technical Digest, (Dec. 5-8, 1993),635-638. cited by other.

Primary Examiner: Dinh; Son T.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. Ser. No. 10/231,397 filed on Aug. 29, 2002, which application is herein incorporated by reference.

Claims

What is claimed is:

1. A method for operating a memory cell, comprising: providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; and modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate.

2. The method of claim 1, wherein the method includes storing a first state on the floating body, wherein storing a first state on the floating body includes: grounding the floating body back gate and the source; and applying a positive voltage to both the gate and the drain.

3. The method of claim 2, wherein grounding and applying include causing avalanche breakdown such that holes are generated and collect on the floating body region.

4. The method of claim 1, wherein the method includes storing a charge on the floating body, wherein storing a charge on the floating body includes: biasing the source to a positive potential; grounding the floating body back gate; and applying a negative potential to the gate.

5. The method of claim 4, wherein biasing, grounding and applying include driving the floating body region and a source drain junction to a reverse bias.

6. The method of claim 1, wherein the method includes increasing a capacitance of the floating body region and enabling a charge storage on the floating body region.

7. The method of claim 1, wherein providing a vertical transistor includes providing an n-channel MOS transistor (NMOS).

8. The method of claim 1, wherein the method further includes providing a standby state, wherein the standby state includes: applying a negative voltage to the gate; and driving the floating body region to a negative potential by virtue of a capacitive coupling of the floating body region to the gate.

9. The method of claim 1, wherein method includes storing a second state on the floating body, wherein storing a second state on the floating body includes: grounding the floating body back gate and the source; applying a positive voltage to the gate; and applying a negative voltage to the drain.

10. A method for operating a memory cell, comprising: providing a vertical transistor having a source, a drain, and a floating body region therebetween, a gate opposing the floating body region and separated therefrom by a gate oxide on a first side of the vertical transistor, and a floating body back gate opposing the body region on a second side of the vertical transistor; modulating a threshold voltage and a conductivity of the vertical transistor using the floating body back gate; storing a first state on the floating body, including: grounding the floating body back gate and the source; and applying a positive voltage to both the gate and the drain; storing a second state on the floating body, including: grounding the floating body back gate and the source; applying a positive voltage to the gate; and applying a negative voltage to the drain; providing a standby state, wherein the standby state includes: applying a negative voltage to the gate; and driving the floating body region to a negative potential by virtue of a capacitive coupling of the floating body region to the gate.

11. The method of claim 10, further comprising reading a stored memory state, including sensing a drain current.

12. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region; and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising: applying a reference potential to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region; and storing a second memory state, including forward biasing a junction between the drain and floating body region of the vertical transistor to remove collected holes in the floating body region.

13. The method of claim 12, wherein operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region includes driving the gate with a positive potential while driving the dram with a positive potential.

14. The method of claim 12, wherein forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region includes driving the gate with a positive potential while driving the drain with a negative potential.

15. The method of claim 12, further comprising holding a memory state, including driving the gate with a negative potential.

16. The method of claim 15, wherein driving the gate with a negative potential drive the floating body region to a negative potential due to capacitive coupling between the gate and the floating body region.

17. The method of claim 12, further comprising reading a stored memory state, including sensing a drain current, wherein the first memory state with holes collected in the floating body region results in a larger drain current than the second memory state with holes removed from the floating body region.

18. The method of claim 12, further comprising applying a reference voltage to the floating body back gate.

19. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region; and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising: applying a reference potential to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region, including driving the gate with a positive potential while driving the drain with a positive potential; and storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region, including driving the gate with a positive potential while driving the drain with a negative potential.

20. The method of claim 19, wherein driving the gate with a positive potential includes applying a pulse of approximately 1 V to the gate, driving the drain with a positive potential includes applying a pulse of approximately 1.5 V to the drain, and driving the drain with a negative potential includes applying a pulse of approximately -0.5 V to the drain.

21. The method of claim 19, further comprising holding a memory state, including applying a potential of about -1 V to the gate.

22. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region; and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising: applying a reference voltage to the floating body back gate; storing a first memory state, including operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region; storing a second memory state, including forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region; holding a memory state, including driving the gate to lower a potential of the floating body region through capacitive coupling between the floating body region and the gate; and reading a stored memory state, including sensing a drain current.

23. The method of claim 22, further comprising applying the reference voltage to the source.

24. The method of claim 22, wherein: operating the vertical transistor to induce avalanche breakdown and collect holes in the floating body region includes driving the gate with a positive potential while driving the drain with a positive potential; and forward biasing a junction between the drain and floating body region to remove collected holes in the floating body region includes driving the gate with a positive potential while driving the drain with a negative potential.

25. The method of claim 22, wherein holding a memory state further includes applying a positive voltage to the source when the gate is driven to a negative voltage.

26. A method for operating a memory cell that includes a vertical transistor with a source, a drain, and a floating body region therebetween, a gate opposing the floating body region; and a floating body back gate opposing the body region on a second side of the vertical transistor, the method comprising: storing a first memory state, including: applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region; and applying a positive potential to the gate and to the drain to induce avalanche breakdown and hole collection in the floating body region; reading the stored first state in the memory cell, including sensing a drain current indicative of stored charge in the floating body region; storing a second memory state, including: applying a ground potential to the floating body back gate which is capacitively coupled to the floating body region; applying a positive potential to the gate while applying a negative potential to the drain; and maintaining a stored state during standby, including applying a negative potential to the gate to lower the potential of the floating body region.

27. The method of claim 26, wherein maintaining a stored state during standby further includes applying a positive potential to the source.

Description

This application is related to the following co-pending, commonly assigned U.S. patent application: "Merged MOS-Bipolar Capacitor Memory Cell," U.S. Ser. No. 10/230,929 filed Aug. 29, 2002, of which disclosure is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and in particular to a single transistor vertical memory gain cell.

BACKGROUND OF THE INVENTION

An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).

DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.

FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. Each cell 100 contains a storage capacitor 140 and an access field effect transistor or transfer device 120. For each cell, one side of the storage capacitor 140 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 140 is connected to the drain of the transfer device 120. The gate of the transfer device 120 is connected to a signal known in the art as a word line 180. The source of the transfer device 120 is connected to a signal known in the art as a bit line 160 (also known in the art as a digit line). With the memory cell 100 components connected in this manner, it is apparent that the word line 180 controls access to the storage capacitor 140 by allowing or preventing the signal (representing a logic "0" or a logic "1") carried on the bit line 160 to be written to or read from the storage capacitor 140. Thus, each cell 100 contains one bit of data (i.e., a logic "0" or logic "1").

In FIG. 2 a DRAM circuit 240 is illustrated. The DRAM 240 contains a memory array 242, row and column decoders 244, 248 and a sense amplifier circuit 246. The memory array 242 consists of a plurality of memory cells 200 (constructed as illustrated in FIG. 1) whose word lines 280 and bit lines 260 are commonly arranged into rows and columns, respectively. The bit lines 260 of the memory array 242 are connected to the sense amplifier circuit 246, while its word lines 280 are connected to the row decoder 244. Address and control signals are input on address/control lines 261 into the DRAM 240 and connected to the column decoder 248, sense amplifier circuit 246 and row decoder 244 and are used to gain read and write access, among other things, to the memory array 242.

The column decoder 248 is connected to the sense amplifier circuit 246 via control and column select signals on column select lines 262. The sense amplifier circuit 246 receives input data destined for the memory array 242 and outputs data read from the memory array 242 over input/output (I/O) data lines 263. Data is read from the cells of the memory array 242 by activating a word line 280 (via the row decoder 244), which couples all of the memory cells corresponding to that word line to respective bit lines 260, which define the columns of the array. One or more bit lines 260 are also activated. When a particular word line 280 and bit lines 260 are activated, the sense amplifier circuit 246 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line 260 by measuring the potential difference between the activated bit line 260 and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.

The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density. As component density has increased, cell capacitance has had to be decreased because of the need to maintain isolation between adjacent devices in the memory array. However, reduction in memory cell capacitance reduces the electrical signal output from the memory cells, making detection of the memory cell output signal more difficult. Thus, as the density of DRAM devices increases, it becomes more and more difficult to obtain reasonable storage capacity.

As DRAM devices are projected as operating in the gigabit range, the ability to form such a large number of storage capacitors requires smaller areas. However, this conflicts with the requirement for larger capacitance because capacitance is proportional to area. Moreover, the trend for reduction in power supply voltages results in stored charge reduction and leads to degradation of immunity to alpha particle induced soft errors, both of which require that the storage capacitance be even larger.

In order to meet the high density requirements of VLSI cells in DRAM cells, some manufacturers are utilizing DRAM memory cell designs based on non-planar capacitor structures, such as complicated stacked capacitor structures and deep trench capacitor structures. Although non-planar capacitor structures provide increased cell capacitance, such arrangements create other problems that effect performance of the memory cell. For example, trench capacitors are fabricated in trenches formed in the semiconductor substrate, the problem of trench-to-trench charge leakage caused by the parasitic transistor effect between adjacent trenches is enhanced. Moreover, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate which functions as one of the storage plates of the trench capacitor. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a soft error.

Another approach has been to provide DRAM cells having a dynamic gain. These memory cells are commonly referred to as gain cells. For example, U.S. Pat. No. 5,220,530 discloses a two-transistor gain-type dynamic random access memory cell. The memory cell includes two field-effect transistors, one of the transistors functioning as write transistor and the other transistor functioning as a data storage transistor. The storage transistor is capacitively coupled via an insulating layer to the word line to receive substrate biasing by capacitive coupling from the read word line. This gain cell arrangement requires a word line, a bit or data line, and a separate power supply line which is a disadvantage, particularly in high density memory structures.

The inventors have previously disclosed a DRAM gain cell using two transistors. (See generally, L. Forbes, "Merged Transistor Structure for Gain Memory Cell," U.S. Pat. No. 5,732,014, issued 24 Mar. 1998, continuation granted as U.S. Pat. No. 5,897,351, issued 27 Apr. 1999). A number of other gain cells have also been disclosed. (See generally, Sunouchi et al., "A self-Amplifying (SEA) Cell for Future High Density DRAMs," Ext. Abstracts of IEEE Int. Electron Device Meeting, pp. 465 468 (1991); M. Terauchi et al., "A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMS," VLSI Tech. Symposium, pp. 21 22 (1993); S. Shukuri et al., "Super-Low-Voltage Operation of a Semi-Static Complementary Gain RAM Memory Cell," VLSI Tech. Symposium pp. 23 24 (1993); S. Shukuri et al., "Super-low-voltage operation of a semi-static complementary gain DRAM memory cell," Ext. Abs. of IEEE Int. Electron Device Meeting, pp. 1006 1009 (1992); S. Shukuri et al., "A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAM's," IEEE Trans. on Electron Devices, Vol. 41, pp. 926 931 (1994); H. Wann and C. Hu, "A Capacitorless DRAM Cell on SOI Substrate," Ext. Abs. IEEE Int. Electron Devices Meeting, pp. 635 638; W. Kim et al., "An Experimental High-Density DRAM Cell with a Built-in Gain Stage," IEEE J. of Solid-State Circuits, Vol. 29, pp. 978 981 (1994); W. H. Krautschneider et al., "Planar Gain Cell for Low Voltage Operation and Gigabit Memories," Proc. VLSI Technology Symposium, pp. 139 140 (1995); D. M. Kenney, "Charge Amplifying trench Memory Cell," U.S. Pat. No. 4,970,689, 13 Nov. 1990; M. Itoh, "Semiconductor memory element and method of fabricating the same," U.S. Pat. No. 5,220,530, 15 Jun. 1993; W. H. Krautschneider et al., "Process for the Manufacture of a high density Cell Array of Gain Memory Cells," U.S. Pat. No. 5,308,783, 3 May 1994; C. Hu et al., "Capacitorless DRAM device on Silicon on Insulator Substrate," U.S. Pat. No. 5,448,513, 5 Sep. 1995; S. K. Banerjee, "Method of making a Trench DRAM cell with Dynamic Gain," U.S. Pat. No. 5,066,607, 19 Nov. 1991; S. K. Banerjee, "Trench DRAM cell with Dynamic Gain," U.S. Pat. No. 4,999,811, 12 Mar. 1991; Lim et al., "Two transistor DRAM cell," U.S. Pat. No. 5,122,986, 16 Jun. 1992).

Recently a one transistor gain cell has been reported as shown in FIG. 3. (See generally, T. Ohsawa et al., "Memory design using one transistor gain cell on SOI," IEEE Int. Solid State Circuits Conference, San Francisco, 2002, pp. 152 153). FIG. 3 illustrates a portion of a DRAM memory circuit containing two neighboring gain cells, 301 and 303. Each gain cell, 301 and 303, is separated from a substrate 305 by a buried oxide layer 307. The gain cells, 301 and 303, are formed on the buried oxide 307 and thus have a floating body, 309-1 and 309-2 respectively, separating a source region 311 (shared for the two cells) and a drain region 313-1 and 313-2. A bit/data line 315 is coupled to the drain regions 313-1 and 313-2 via bit contacts, 317-1 and 317-2. A ground source 319 is coupled to the source region 311. Wordlines or gates, 321-1 and 321-2, oppose the floating body regions 309-1 and 309-2 and are separated therefrom by a gate oxide, 323-1 and 323-2.

In the gain cell shown in FIG. 3 a floating body, 309-1 and 309-2, back gate bias is used to modulate the threshold voltage and consequently the conductivity of the NMOS transistor in each gain cell. The potential of the back gate body, 309-1 and 309-2, is made more positive by avalanche breakdown in the drain regions, 313-1 and 313-2, and collection of the holes generated by the body, 309-1 and 309-2. A more positive potential or forward bias applied to the body, 309-1 and 309-2, decreases the threshold voltage and makes the transistor more conductive when addressed. Charge storage is accomplished by this additional charge stored on the floating body, 309-1 and 309-2. Reset is accomplished by forward biasing the drain-body n-p junction diode to remove charge from the body.

Still, there is a need in the art for a memory cell structure for dynamic random access memory devices, which produces a large amplitude output signal without significantly increasing the size of the memory cell to improve memory densities.

SUMMARY OF THE INVENTION

The above mentioned problems with conventional memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A high density vertical single transistor gain cell is realized for DRAM operation.

In one embodiment of the present invention, a gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor. The floating body back gate includes a capacitor plate and forms a capacitor with the floating body. The capacitor is operable to increase a capacitance of the floating body and enables charge storage on the floating body. Thus, the floating body back gate is operable to modulate the threshold voltage and conductivity of the vertical transistor.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating conventional dynamic random access memory (DRAM) cells.

FIG. 2 is a block diagram illustrating a DRAM device.

FIG. 3 illustrates a portion of a DRAM memory