State retention within a data processing system Number:7,365,596 from the United States Patent and Trademark Office (PTO) owispatent

Title: State retention within a data processing system

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Patent Number: 7,365,596 Issued on 04/29/2008 to Padhye,   et al.

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Inventors:	Padhye; Milind P. (Austin, TX), Chun; Christopher K. Y. (Austin, TX), Moughanni; Claude (Austin, TX)
Assignee:	Freescale Semiconductor, Inc. (Austin, TX)
Appl. No.:	10/819,383
Filed:	April 6, 2004

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Current U.S. Class:	327/544 ; 327/200; 327/215; 327/219; 327/333
Current International Class:	G05F 1/10 (20060101)
Field of Search:	327/200,201,202,203 326/93,94,95

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References Cited [Referenced By]

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U.S. Patent Documents

5075570	December 1991	Shewchuk et al.
5162667	November 1992	Yasui et al.
5270581	December 1993	Nakamura
6141237	October 2000	Eliason et al.
6195754	February 2001	Jardine et al.
6246265	June 2001	Ogawa
6255862	July 2001	Kumagai et al.
6291869	September 2001	Ooishi
6362675	March 2002	Alwais
6424196	July 2002	Pomet
6433586	August 2002	Ooishi
6525984	February 2003	Yamagata et al.
6635934	October 2003	Hidaka
6643208	November 2003	Yamagata et al.
6774663	August 2004	Moreaux et al.
7215188	May 2007	Ramaraju et al.
2002/0159305	October 2002	Yoo et al.
2003/0067322	April 2003	Stan et al.
2004/0061135	April 2004	Ikeno et al.

Foreign Patent Documents

	1 098 324		May., 2001		EP

Other References

Zyuban, Victor et al.; "Low Power Integrated Scan-Retention Mechanism"; ISLPED '02; Aug. 12-14, 2002; pp. 98-102; ACM (18 page related presentation included). cited by other . Shigematsu, Satoshi et al.; "A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits"; IEEE Journal of Solid-State Circuits; Jun. 1997; pp. 861-869; vol. 32, No. 6; IEEE. cited by other . Levy, Paul S. et al. "Power-Down Integrated Circuit Cuilt-In Self-Test Structures"; 1991 IEEE VLSI Test Symposium; 1991; IEEE. cited by other . Padhye, filed concurrently. cited by other . PCT application PCT/EP03/00435, Chun, filed Jan. 17, 2003. cited by other.

Primary Examiner: Lam; Tuan T.
Assistant Examiner: Nguyen; Hiep
Attorney, Agent or Firm: Chiu; Joanna G. Noonan; Michael P.

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Claims

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What is claimed is:

1. A circuit comprising: a first power domain including circuitry coupled to receive a first power supply signal; and a second power domain including circuitry coupled to receive both the first power supply signal and a second power supply signal, the second power domain including a buffer, the buffer comprising: a first buffer portion coupled to receive the second power supply signal, the first buffer portion including a buffer data input; and a second buffer portion coupled to receive the first power supply signal, the second buffer portion including a buffer data output, wherein one of the first and second power supply signals is configured to be selectively enabled independently from the other of the first and second power supply signals; wherein: each of the first and second buffer portions includes a data path portion coupled in series between the buffer data input and the buffer data output; the second buffer portion includes a feedback portion which is coupled to receive a power gate indicator to enable the feedback portion during a power saving mode; and the data path portion of the first buffer portion is an inverter which is disabled by the power gate indicator during the power saving mode.

2. The circuit of claim 1 further comprising a gate circuit coupled to receive the first power supply signal and to selectively provide the second power supply signal.

3. The circuit of claim 1 wherein the first power supply signal is provided to the circuit substantially continuously during operation of the circuit and the second power supply signal is derived from the first power supply signal and is provided to the circuit during a non-power saving mode of operation.

4. The circuit of claim 3 wherein the first and second power supply signals are designed to have substantially similar voltages during non-power saving operation.

5. The circuit of claim 1 further comprising a memory, wherein the buffer input is coupled to receive an output signal from the memory.

6. The circuit of claim 1, wherein the feedback portion is disabled during normal operation.

7. A circuit comprising: a first power domain including circuitry coupled to receive a first power supply signal; and a second power domain including circuitry coupled to receive both the first power supply signal and a second power supply signal, the second power domain including a buffer, the buffer comprising: a first buffer portion coupled to receive the second power supply signal, the first buffer portion including a buffer data input; and a second buffer portion coupled to receive the first power supply signal, the second buffer portion including a buffer data output, wherein one of the first and second power supply signals is configured to be selectively enabled independently from the other of the first and second power supply signals; wherein: the first buffer portion comprises a first data path inverter having a data input coupled to the buffer data input, a data output coupled to the second buffer portion, and an enable control input; the second buffer portion comprises: a second data path inverter having a data input coupled to the output of the first inverter and a data output coupled to the buffer data output; a feedback inverter having a data input coupled to the buffer data output, a data output coupled to the data input of the second inverter, and an enable control input, wherein each of the enable control inputs of the first data path inverter and the feedback inverter are coupled to receive a power gating control signal to alternately enable one of the first data path inverter and the feedback inverter while disabling the other of the first data path inverter and the feedback inverter.

8. The circuit of claim 1, wherein the feedback portion is disable during normal operation.

9. A circuit comprising: a gate circuit coupled to receive and gate a first power supply signal to controllably provide a second power supply signal; a plurality of buffer cells, each buffer cell comprising: a buffer input; a buffer output; an inverter having an inverter input coupled to the buffer input, the inverter being coupled to receive the second power supply signal, the inverter having an inverter output; and a latch having a latch input coupled to the inverter output and a latch output coupled to the buffer output, the latch being coupled to receive the first power supply signal, and wherein, during normal operation, at least a portion of the latch is disabled and only a single inverter output of the latch is coupled to the buffer output.

10. The circuit of claim 9 further comprising: a state retention controller coupled to provide a power control signal to the gate circuit, the gate circuit coupling the first power supply signal to the second power supply signal such that the first and second power supply signals have a substantially equal potential responsive to the power control signal having a first value, the gate circuit decoupling the first power supply signal from the second power supply signal to disable circuitry powered by the second power supply signal responsive to the power control signal having a second value.

11. The circuit of claim 10 wherein the state retention controller is coupled to receive a power gate request signal, the power gate request signal initiating a first mode of operation of the circuit with a first power gate request value, the power gate request signal initiating a second mode of operation of the circuit with a second power gate request value, the second mode of operation of the circuit being designed to consume less power than the first mode of operation of the circuit.

12. A circuit comprising: a first power domain including circuitry coupled to receive a first power supply signal; and a second power domain including circuitry coupled to receive both the first power supply signal and a second power supply signal, the second power domain including a buffer, the buffer comprising: a first buffer portion coupled to receive the second power supply signal, the first buffer portion including a buffer data input; and a second buffer portion coupled to receive the first power supply signal, the second buffer portion including a buffer data output, wherein one of the first and second power supply signals is configured to be selectively enabled independently from the other of the first and second power supply signals; wherein: the first buffer portion comprises a first data path inverter; and the second buffer portion comprises a second data path inverter having a data input coupled to a data output of the first data path inverter, the second buffer portion further comprising state setting circuitry for setting a state of the buffer responsive to receiving a state retention signal at a state retention data input, wherein the state retention signal represents one of a desired logic value of the state of the buffer or an inverse of the desired value of the state of the buffer.

13. The circuit of claim 12 wherein the state retention signal is disabled when a power gate indicator signal has a first value indicating a non-power saving mode of operation for the buffer.

14. The circuit of claim 12 wherein the state retention signal is programmable.

15. The circuit of claim 12 wherein the state retention signal is hardwired to a particular logic value.

16. The circuit of claim 12 wherein the first data path inverter is coupled to receive a power gate indicator signal at a control input; and the state setting circuitry comprises an inverter coupled to receive the state retention signal at a state retention data input and coupled to receive an inverted power gate indicator signal at an state retention control input.

17. The circuit of claim 12 wherein the state setting circuitry comprises: a transistor having a first current handling terminal coupled to the data input of the second data path inverter, a second current handling terminal coupled to receive the state retention signal, the state retention signal being a power supply signal, and a control terminal coupled to be controlled according to a power gate indicator signal.

18. The circuit of claim 17 wherein the first data path inverter is coupled to receive the power gate indicator signal at an enable input; the transistor is a pull-down transistor having a control terminal coupled to receive the power gate indicator signal; and the power supply signal is coupled to a ground potential.

19. The circuit of claim 17 wherein the first data path inverter is coupled to receive the power gate indicator signal at an enable input; the transistor is a pull-up transistor having a control terminal coupled to receive an inverted power gate indicator signal; and the power supply signal is coupled to .sub.VDD.

20. A circuit comprising: a first power domain including circuitry coupled to receive a first power supply signal; and a second power domain including circuitry coupled to receive both the first power supply signal and a second power supply signal, the second power domain including a buffer, the buffer comprising: a first buffer portion coupled to receive the second power supply signal, the first buffer portion including a buffer data input; and a second buffer portion coupled to receive the first power supply signal, the second buffer portion including a buffer data output, wherein one of the first and second power supply signals is configured to be selectively enabled independently from the other of the first and second power supply signals; wherein: each of the first and second buffer portions includes a data path portion coupled in series between the buffer data input and the buffer data output; the data path portion of the first buffer portion is an inverter and the data path portion of the second buffer portion comprises at least a portion of a latch; and only a single inverter output of the second data path portion provides the buffer data output.

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Description

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FIELD OF THE INVENTION

The present invention relates generally to data processing systems, and more specifically, to state retention within a data processing system.

RELATED ART

Lower power consumption has been gaining importance in data processing systems, due, for example, to wide spread use of portable and handheld applications. For example, for handheld devices, battery life is a very important parameter. Handheld devices are typically off (e.g., in an idle or deep sleep mode) for a significant portion of time, consuming only leakage power. Therefore, reducing leakage current is becoming an increasingly important factor in extending battery life.

One method of reducing leakage current of the devices is to increase the threshold voltage. However, simply increasing the threshold voltage of a devices may result in unwanted consequences such as slowing the device down and limiting circuit performance.

Another method of reducing leakage current is to power gate, or cut off power to certain blocks. However, in doing so, the state of the circuit blocks is lost. In many circuit blocks, though, state retention is needed in order to prevent loss of important information and allow for proper circuit operation and performance. Therefore, a need exists for improved circuitry and methods for state retention during, for example, idle or deep sleep modes, which may therefore help in reducing leakage power and extending battery life.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:

FIG. 1 illustrates, in block diagram form, a data processing system in accordance with one embodiment of the present invention;

FIG. 2 illustrates, in partial block diagram form and partial schematic form, a state retention flip-flop in accordance with one embodiment of the present invention;

FIGS. 3-6 illustrate tables corresponding to operation of various embodiments of state retention flip-flops, such as the state retention flip-flop of FIG. 2, in accordance with various embodiments of the present invention;

FIG. 7 illustrates, in schematic form, a state retention buffer in accordance with one embodiment of the present invention;

FIG. 8 illustrates a table corresponding to operation of the state retention buffer of FIG. 7, in accordance with one embodiment of the present invention;

FIG. 9 illustrates, in schematic form, a state retention buffer in accordance with another embodiment of the present invention;

FIG. 10 illustrates a table corresponding to operation of the state retention buffer of FIG. 9, in accordance with one embodiment of the present invention;

FIGS. 11 and 12 illustrate timing diagrams illustrating operation of the data processing system of FIG. 1, in accordance with various embodiments of the present invention;

FIG. 13 illustrates, in flow diagram form, a method for state retention, in accordance with one embodiment of the present invention;

FIG. 14 illustrates, in schematic form, a state retention buffer in accordance with another embodiment of the present invention;

FIG. 15 illustrates a table corresponding to operation of the state retention buffer of FIG. 14, in accordance with one embodiment of the present invention;

FIG. 16 illustrates, in schematic form, a state retention buffer in accordance with another embodiment of the present invention; and

FIG. 17 illustrates a table corresponding to operation of the state retention buffer of FIG. 16, in accordance with one embodiment of the present invention.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

As used herein, the term "bus" is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

The terms "assert" or "set" and "negate" (or "deassert" or "clear") are used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one. Therefore, each signal described herein may be designed as positive or negative logic, where negative logic can be indicated by a bar over the signal name or an asterix (*) following the name. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

As will be discussed herein, power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer, as will be described below, allow for state retention with minimal additional circuitry while still reducing leakage current. Also described herein are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, one embodiment uses a hardware method to enter a deep sleep mode and retain state while another embodiment uses a combination of hardware and software to enter a deep sleep mode and retain state.

FIG. 1 illustrates a data processing system 100 in accordance with one embodiment of the present invention. Data processing system 100 includes a voltage regulator 102, a transistor 104, a clock controller 116, a state retention controller 118, sleep domain functional circuitry 124, and running domain functional circuitry 128. Voltage regulator 102 provides continuous VDD (VDDC) 130 and VDD 132 wherein VDDC 130 and VDD 132 are coupled via transistor 104. That is, a first current electrode of transistor 104 is coupled to VDDC 130 and a second current electrode of transistor 104 is coupled to VDD 132. A control electrode of transistor 104 is coupled to receive a power gate control signal (VDD control 110) from state retention controller 118. In the illustrated embodiment, transistor 104 is a PMOS transistor. VDDC 130 is provided to state retention controller 118, clock controller 116, sleep domain functional circuitry 124, and running domain functional circuitry 128. VDD 132 is provided to sleep domain functional circuitry 124. Clock controller 116 receives a reference clock, refclk 112, provides a sleep domain clock, sclk 122, to sleep domain functional circuitry 124 and a running domain clock, rclk 126, to running domain functional circuitry 128, and communicates with state retention controller 118 via bidirectional clk control signals 134. State retention controller 118 receives a power gate request (PG req 114) and provides a power gate indicator signal (PG 120) to sleep domain functional circuitry 124. Note that data processing system 100 may be located all on a same integrated circuit, or, alternatively, data processing system 100 may be located on any number of integrated circuits or may be implemented with both integrated circuit elements and discrete circuit elements. Data processing system 100 may be any type of data processing system, such as, for example, a microprocessor, digital signal processor, etc., or any type of information processing system. Also note that in the illustrated embodiment of data processing system 100, signals such as VDD control 110, PG 120, and PG req 114 are described as positive logic signals.

In operation, data processing system 100 includes VDDC 130 (which may also be referred to as a continuous power supply signal) and VDD 132 (which may also be referred to as a gated power supply signal) to provide power to various portions of data processing system 100. In the illustrated embodiment, VDDC 130 is generated by voltage regulator 102, as known in the art, such that VDDC 130 is a controllably regulated power supply signal. When VDD 132 is coupled to VDDC 130 (via transistor 104, when VDD control 110 is a logic level 0), then VDD 132 is approximately the same as VDDC 130, and both provide power to portions of data processing system 100. When VDD control 110 is a logic level 1, then VDD 132 is decoupled from VDDC 130, such that only VDDC 130 provides power to portions of data processing system 100, thus power gating VDD 132 (i.e. removing power to those portions of circuitry coupled to VDD 132). Note that in alternate embodiments, different circuitry may be used to implement the functionality of transistor 104 such that, depending on VDD control 110, either both VDDC 130 and VDD 132 provide power to data processing system 100, or VDDC 130, but not VDD 132, provides power to data processing system 100. For example, other switching elements or gate circuits may be used, or any combination of elements may be used.

In the illustrated embodiment, data processing system 100 includes both sleep domain functional circuitry 124 and running domain functional circuitry 128. Sleep domain functional circuitry 124 includes circuitry whose clocks may be removed during low power modes such as when data processing system 100 is in a deep sleep mode or is in an idle mode. During those times when the clocks (e.g. SCLK 122) are off, power may also be removed from portions of the circuitry to help reduce leakage current. For example, in the illustrated embodiment, sleep domain functional circuitry receives both VDDC 130 and VDD 132, wherein, during normal or full power operation, VDD control 110 is set to a logic level 0 by state retention controller 118 in order to couple VDD 132 to VDDC 130. Therefore, during normal or full power operation, both VDDC 130 and VDD 132 provide power to sleep domain circuitry 124. However, during a low power mode (with, for example, sclk 122 turned off), VDD control 110 may be set to a logic level one in order to decouple VDD 132 from VDDC 130, thus gating off VDD 132. In this case, only portions of sleep domain functional circuitry 124 (those portions which, for example, retain state information) are powered by VDDC 130 while the remaining portions which are coupled to VDD 132 are powered down. As will be described below, sleep domain functional circuitry 124 may include modified flip-flops and buffers which, in combination with VDDC 130, may be used to retain state within sleep domain functional circuitry 124.

Running domain functional circuitry 128 includes circuitry which may not be placed in a deep sleep mode and therefore continuously receives a clock (e.g. rclk 126) and power (VDDC 130). This circuitry may include, for example, a real time clock that needs to constantly remain powered, or other circuitry such as a deep sleep module (which can periodically wake up data processing system 100 to check for activity, such as, for example, calls or messages), an interrupt buffer (which detects activity, such as, for example, key presses), and other blocks which monitor data processing system 100 or provide critical functions which should not be turned off. This circuitry may therefore include non state-retentive devices, such as non state-retentive flip-flops and buffers (which may operate as normal flip-flops and buffers as known in the art today). In one embodiment, rclk 126 is a continuous clock which is not turned off during a low power mode. In one embodiment, rclk 126 is a slower clock than sclk 122 (where rclk 126 may be, for example, a 32 kHz clock, and sclk 122 may be, for example, a 13 MHz clock). Therefore, unlike sclk 122 which may be turned on or off, rclk 126 is typically not turned off. Since running domain functional circuitry 128 is continuously running, it remains continuously powered, and thus receives only VDDC 130 since its power will not be gated, unlike those portions of sleep domain functional circuitry 124 which receive VDD 132.

Although FIG. 1 has been illustrated as having two distinct functional circuitry blocks, it should be understood that data processing system 100 may include any number of sleep domain circuitry regions and running domain circuitry regions. For example, in one embodiment, sleep domain circuitry and running domain circuitry are not physically separate blocks, but instead are integrated with each other, receiving sclk 122, rclk 126, VDD 130, and VDDC 132, as needed. Also note that the circuitry within sleep domain functional circuitry 124 and running domain functional circuitry 128 may include any type of circuitry to perform any type of function, as needed by data processing system 100. Also, in alternate embodiments, data processing system 100 may include any number and type of power domain circuitries (in addition to the sleep and running domain functional circuitries). Therefore, data processing system 100 may be designed in a variety of different ways for a variety of different applications. The functional circuitry of data processing system 100 will therefore not be discussed in more detail herein except to the extent necessary to describe operation of the state retention portions.

Clock controller 116 generates sclk 122 and rclk 126, as needed, based on refclk 112. In one embodiment, refclk 112 is generated by a crystal oscillator which may be located on a same integrated circuit as data processing system 100 or external to data processing system 100. Therefore, based on controls from state retention controller 118 (via, for example, clk control signals 134) and control information from other power management modules (not shown), if present, clock controller 116 is able to turn off sclk 122 or otherwise modify sclk 122 and rclk 126, as needed. Note that clock controller 116 receives VDDC 130 so that it may continue to control sclk 122 and rclk 126 as needed, even during low power modes.

State retention controller 118 may be used to ensure that state is properly retained when entering a low power mode such as a deep sleep mode or idle mode. For example, in the illustrated embodiment, state retention controller 118 receives a PG req 114. This request can be a signal generated from a power management module (not shown) or any other circuitry within data processing system 100 which indicates to state retention controller 118 when power gating is needed. PG req 114 can also correspond to a value stored in memory (such as, for example, a bit) that is controllable by software running on data processing system 100. Alternatively, PG req 114 may be received from a source external to data processing system 100. In response to receiving PG req 114, state retention controller 118, via clk control signals 134, indicates to clock controller 116 that sclk 122 is to be shut down in order to enter a low power mode in which the power will be gated off to portions of sleep domain functional circuitry 124. State retention controller 118 also indicates to sleep domain functional circuitry 124, via PG 120, that power gating is to be performed. Therefore, in one embodiment, state retention controller 118, in response to receiving acknowledgement from clock controller 116 that sclk 122 has been turned off (or, after a predetermined amount of time after indicating to clock controller 116 that sclk 122 is to be turned off), may assert PG 120 such that portions of sleep domain functional circuitry 124 may be powered down and may also set VDD control 110 to a logic level one to decouple VDD 132 from VDDC 130. Operation of clock controller 116 and state retention controller 118 will be described in more detail below in reference to the timing diagrams of FIGS. 11-12 and the flow diagram of FIG. 13.

FIG. 2 illustrates one embodiment of a state retention flip-flop 200 (which may also be referred to as state-retentive flip-flop 200). In the illustrated embodiment, flip-flop 200 is a master-slave flip-flop which includes a master portion 202 coupled to slave portion 204. Flip-flop 200 includes a switch 208 having a first terminal coupled to receive an input, D, and a second terminal coupled to a first terminal of a switch 210 and an input to an inverter 214. Switch 208 has a first control terminal which receives e and a second control terminal which receives eb (the inverse of e). Switch 210 has a second terminal coupled to an output of inverter 212, a first control terminal which receives f, and a second terminal which receives fb (the inverse of f). An output of inverter 214 and an input of inverter 212 are coupled to a first terminal of a switch 216. A first control terminal of switch 216 receives g and a second control terminal of switch 216 receives gb (the inverse of g). A second terminal of switch 216 is coupled to a first terminal of a switch 218 and an input of an inverter 222. A first control terminal of switch 218 receives h, and a second control terminal of switch 218 receives hb (the inverse of h). A second terminal of switch 218 is coupled to an output of inverter 220. An input of inverter 220 is coupled to an output of inverter 222 which provides an output, Q. Therefore, note that master 202 includes at least one circuit element (e.g. inverter 214) and slave 204 includes at least one circuit element (e.g. inverter 222) which are coupled in series with the input and output nodes (e.g. corresponding to D and Q, respectively) of flip-flop 200. That is, each of the at least one circuit elements of master 202 and slave 204 are in a data path from an input to an output of flip-flop 200.

Flip-flop 200 also includes a switch controller 206 which receives an sclk (such as sclk 122), a PG signal (such as PG 120), and VDDC (such as VDDC 130), and provides, in one embodiment, e, eb, f, fb, g, gb, h, and hb. In an alternate embodiment, switch controller 206 may provide e, f, g, and h, and eb, fb, gb, and hb can each be obtained by providing e, f, g, and g through an inverter, respectively. Inverters 212 and 214 receive VDD1 and inverters 222 and 220 receive VDD2. Master portion 202 includes switch 210 and inverters 212 and 214, and slave portion 204 includes switch 218 and inverters 220 and 222.

Note that a switch may also be referred to as a transmission gate or a pass gate. If a switch is on or closed (i.e. the pass gate is enabled), then the first and second terminals of the switch are coupled to each other such that the value at one of its terminals is passed to the other of its terminals. If the switch is off or open (i.e. the pass gate disabled), then the first and second terminals of the switch are decoupled from each other such that the value at one of its terminals is not passed to the other. In the illustrated embodiment of FIG. 2, it is assumed that the switches are turned on by asserting e, f, g, and h (and thus deasserting eb, fb, gb, and hb, respectively) and turned off by deasserting e, f, g, and h (and thus asserting eb, fb, gb, and hb, respectively). Therefore, note that in one embodiment, a switch state of a switch refers to whether the switch is on or off (i.e. closed or open, respectively), such that a first switch state may refer to the switch being on or closed and a second switch state may refer to the switch being off or open, or vice versa.

In operation, flip-flop 200 receives an input D, and provides the value of D as the output Q. For example, operation of flip-flop 200 will first be discussed in reference to FIGS. 3 and 6 where it will be assumed that flip-flop 200 is a positive edge flip-flop (with respect to sclk). As illustrated in the table of FIG. 6, where flip-flop 200 is known to be a positive edge flip-flop, VDD1 (in master portion 202) is coupled to VDD (such as VDD 132) and VDD2 (in slave portion 204) is coupled to VDDC (such as VDDC 130). Referring now to FIG. 3, during normal operation, when PG is deasserted (i.e. set to 0), then both VDD1 and VDD2 provide power to the inverters because during normal operation, VDD is coupled to VDDC (via, for example, transistor 104) such that VDD is approximately equal to VDDC. Therefore, when PG is deasserted, flip-flop 200 operates as a normal positive edge flip-flop. That is, when sclk is 0, switches 208 and 218 are on and switches 210 and 216 are off such that the value of D is transmitted through switch 208, via inverter 214, to the first terminal of switch 216. However, since switch 216 is off, this value is not transmitted to the input of inverter 222. The value in slave 204 stored by the latch formed by inverters 220 and 222 with switch 218 being on remains as output Q. When sclk is 1, switches 210 and 216 are on and switches 208 and 218 are off such that the value of D is stored in master 202 by the latch formed by inverters 212 and 214 with switch 210 being on. The value previously at the output of inverter 214 is transmitted via inverter 222 as output Q such that the previous value of D now appears as output Q.

However, when flip-flop 200 is to be power gated (such as in a low power mode or other power managed mode) then sclk is turned off and VDD1 no longer supplies power to inverters 212 and 214 in master 202 since VDD is decoupled from VDDC. In order to retain state, VDD2, which is provided by VDDC, still provides power to inverters 220 and 222 in slave 204. Therefore, referring to FIG. 3, when PG is asserted (set to 1), switches 208 and 218 are on and switches 210 and 216 are off such that the state of flip-flop 200 is maintained in slave 204. In this manner, state is retained in slave 204 (isolated from master 202 by switch 216) while power can be removed from master 202, thus reducing leakage power consumed by flip-flop 200. That is, during power gating, flip-flop 200 expends less power than during normal operation. Also, note that when PG is asserted, sclk is indicated as a "don't care" since it no longer affects operation of flip-flop 200. That is, when PG is asserted, flip-flop 200 operates independently of sclk. Therefore, switch controller 206 may be designed in a variety of different ways to implement the functionality of the table of FIG. 3, where switch controller 206 is powered by VDDC such that it is not powered down during the low power mode.

Operation of flip-flop 200 will now be discussed in reference to FIGS. 4 and 6 where it will be assumed that flip-flop 200 is a negative edge triggered flip-flop (with respect to sclk). Again, flip-flop 200 receives an input D which is eventually provided as output Q. As illustrated in the table of FIG. 6, where flip-flop 200 is known to be a negative edge flip-flop, VDD1 (in master portion 202) is coupled to VDDC (such as VDDC 130) and VDD2 (in slave portion 204) is coupled to VDD (such as VDD 132). Referring now to FIG. 4, during normal operation, when PG is deasserted (i.e. set to 0), both VDD1 and VDD2 provide power to the inverters because during normal operation, VDD is coupled to VDDC (via, for example, transistor 104) such that VDD is approximately equal to VDDC. Therefore, when PG is deasserted, flip-flop 200 operates as a normal negative edge flip-flop. That is, when sclk is 0, switches 210 and 216 are on and switches 208 and 218 are off such that the previous value of D is now stored in master 202 by the latch formed by inverters 212 and 214 with switch 210 being on. The value in master 202, at the output of inverter 214, is also transmitted via switch 216 and provided via inverter 222 as Q. Therefore, the previous value of D is stored in master 202 and provided as output Q. When sclk is 1, switches 210 and 216 are off and switches 208 and 218 are on such that the value of D is transmitted via switch 208 and inverter 214 to the first terminal of switch 216. However, since switch 216 is off, this value is not transmitted through switch 216 to slave 204. Slave 204 continues to store the previous output value of Q in the latch formed by inverters 220 and 222 with switch 218 being on.

However, when flip-flop 200 is to be power gated (such as in a low power mode or other power managed mode) then sclk is turned off and VDD2 no longer supplies power to inverters 220 and 222 in slave 204 since VDD is decoupled from VDDC. In order to retain state, VDD1, which is provided by VDDC, still provides power to inverters 212 and 214 in master 202. Therefore, referring to FIG. 4, when PG is asserted (set to 1), switches 208 and 218 are off and switches 210 and 216 are on such that the state of flip-flop 200 is maintained in master 202. In this manner, state is retained in master 202 (isolated from slave 204 by switch 216) while power can be removed from slave 204, thus reducing leakage power consumed by flip-flop 200. That is, during power gating, flip-flop 200 expends less power than during normal operation. Note that when PG is asserted, sclk is indicated as a "don't care" since it no longer affects operation of flip-flop 200. That is, when PG is asserted, flip-flop 200 operates independently of sclk. Therefore, switch controller 206 for a negative edge flip-flop may be designed in a variety of different ways to implement the functionality of the table of FIG. 4, where switch controller 206 is powered by VDDC such that it is not powered down during the low power mode.

Therefore, as described above, depending on whether the flip-flop is designed as a positive or negative edge flip-flop, the state can be retained in the slave portion or master portion of the flip-flop, respectively. That is, for a positive edge flip-flop, the clock provided to the flip-flop (such as, e.g., sclk) stops in a first state when entering a low power mode (where, for example, this first state may be a logic level zero). In this case, at the point the clock stops, the slave portion of the flip-flop contains the state that is to be retained. Thus the slave portion (e.g. slave 204) receives VDDC. Similarly, for a negative edge flip-flop, the clock provided to the flip-flop (such as, e.g., sclk) stops in a second state when entering a low power mode (where, for example, this second state may correspond to a logic level one). In this case, at the point the clock stops, the master portion of the flip-flop contains the state that is to be retained. Thus, the master portion (e.g. master 202) receives VDDC.

In some cases, it is not known in which state flip-flop 200 will be when the clock is stopped. That is, it is not known in which state the clock provided to the flip-flop (such as, e.g., sclk) will be in when stopped. In these cases, it will not be known which portion (master 202 or slave 204) will be holding the desired state information at the time sclk is stopped. Therefore, operation of flip-flop 200 will be discussed in reference to FIGS. 5 and 6 which illustrates the case where flip-flop 200 is in an unknown state. For example, in the case of a ripple counter, it may be unknown in which state some of the flip-flops are in at the time sclk is stopped; however, it is still desirable to save state information. The ripple counter is only one example of circuitry having an unknown state flip-flop. That is, other types of circuitries may use flip-flops where the state of the flip-flop will be unknown when the sclk is stopped. In these type of cases, as illustrated in the table of FIG. 6, both VDD1 and VDD2 are provided by VDDC such that power is not removed from either the slave or master portions of flip-flop 200.

For example, referring to FIG. 5, it is assumed that flip-flop 200, during normal operation (when PG is deasserted or set to 0), operates as a positive edge triggered flip-flop as discussed above in reference to FIG. 3. However, note that in alternate embodiments, a flip-flop of unknown state may be a negative edge flip-flop in which, during normal operation, it will operate as a negative edge flip-flop, as discussed above in reference to FIG. 4. When PG is asserted (i.e. set to 1), and sclk turned off, switches 210 and 218 are turned on and switches 208 and 216 are turned off such that state can be retained. That is, with switch 210 being on, master 202 includes a latch formed by inverters 212 and 214. Similarly, with switch 218 being on, slave 204 includes a latch formed by inverters 220 and 222, where slave 204 is isolated from master 202 by switch 216 being off and master 202 is isolated from other inputs by switch 208 being off. Furthermore, power is not removed from any of inverters 212, 214, 220, and 222. In this manner, regardless of which state flip-flop 200 is in, the state is retained. That is, regardless of whether master 202 or slave 204 currently holds the state of flip-flop 200 when sclk is turned off, the state is saved because the current state of both master 202 and slave 204 is saved. Therefore, for these cases, switch controller 206 can be designed using any type of circuitry to implement the functionality of the table of FIG. 5.

Therefore, it can be appreciated how the use of a modified state retention flip-flop such as flip-flop 200 may be used to retain state and reduce leakage power. Depending on the type of flip-flop in a design (positive edge, negative edge, or whether it will be in an known state), VDD and VDDC can be used appropriately. In some cases, VDDC will only be provided to one of the master or slave portions, and in other cases, VDDC may be provided to both master and slave portions. Note also that in the illustrated embodiment, flip-flop 200 includes two series coupled latches (e.g. master 202 and slave 204) which are capable of retaining state and reducing or inhibiting power loss without the need for additional latches.

Alternate embodiments may use the switches and power supplies differently, as needed. For example, for testing purposes, one embodiment may use a testing mode, indicated to switch controller 206 via, for example, a test mode signal (not shown). When the test mode signal is asserted, switch controller may turn on switches 208 and 216 and turn off switches 210 and 218 such that the input D is routed directly to output Q without being stored in any latches. Also, note that in alternate embodiments, flip-flop 200 may be designed differently. For example, in one embodiment, switch 210 and inverter 212 may be implemented as a tri-state inverter (also referred to as a tristatable inverter) where when switch 210 is to be enabled, the tri-state inverter will operate as an inverter, outputting a 1 or 0 based on its input, and when switch 210 is to be disabled, the output of the tri-state inverter will be a high impedance (corresponding to switch 210 being off). The same modification can be made to inverter 220 and switch 218. Also, other types of circuitry or elements may be used to implement switches 208, 210, 216, and 218. That is, in the illustrated embodiment, they are implemented as pass gates having an NMOS and PMOS transistor coupled together. However, in alternate embodiments, they may be implemented differently.

Therefore, in one embodiment, a state-retentive flip-flop includes input and output nodes and two latches. The two latches include a master latch and a slave latch, each including a circuit element coupled in series with the input and output nodes, a first one of the latches being configured to retain a state of the flip-flop during a power managed mode in which power is decoupled from a second one of the latches. In another embodiment, a state-retentive flip-flop includes input and output nodes and two latches. The two latches include a master latch and a slave latch, each including a circuit element coupled in series with the input and output nodes, a first one of the latches being coupled to operate using a first power supply signal and a second one of the latches being coupled to operate using a second power supply signal, the second power supply signal being a controllably regulated power supply signal. In yet another embodiment, a state-retentive slip-flop includes an input node, an output node, a master including a plurality of circuit elements, and a slave including a plurality of circuit elements, where the input node, the at least one circuit element of the master, the at least one circuit element of the slave, and the output node are coupled in series, and where at least a first circuit element from at least one of the master and the slave is configured to receive power during a power managed mode in which power is decoupled from at least a second circuit element from at least one of the master and the slave. In yet another alternate embodiment, a circuit includes a state-retentive flip-flop which includes a data path from an input to an output, a master loop circuit having a first circuit element in the data path and coupled to receive data from the input, a slave loop circuit having a second circuit element in the data path and coupled to receive data from the first circuit element and to provide data to the output, and state retention control means. The state retention control means includes means for enabling the master loop circuit to retain a state of the flip-flop, means for enabling the slave loop circuit to retain a state of the flip-flop, or means for enabling both the master and the slave loop circuits to retain a state of the flip-flop.

FIG. 7 illustrates an example of a state retention buffer 300 in accordance with one embodiment of the present invention. State retention buffer 300, in response to PG 120, is able to be power gated in order to reduce leakage power while retaining the current state. State retention buffer 300 receives an input A (which may also be referred to as a buffer data input) and provides an output Y (which may also be referred to as a buffer data output). State retention buffer 300 includes an inverter 302 having an input to receive A and an output coupled to an input of an inverter 304 and an output of an inverter 306. An output of inverter 304 provides output Y and is coupled to an input of inverter 306. An inverted enable input of inverter 302 is coupled to receive PG (such as, for example, PG 120) and is coupled to an input of an inverter 308. An output of inverter 308 is coupled to an inverted enable input of inverter 306. Inverter 302 receives VDD, and inverters 304, 306, and 308 receive VDDC. Therefore, a first buffer portion (e.g. inverter 302) receives a first power supply signal (e.g. VDD) while a second buffer portion (e.g. inverters 304, 306, and 308) receives a second power supply signal (e.g. VDDC).

Operation of state retention buffer 300 will be described in reference to the table of FIG. 8. During normal operation, when PG is deasserted, when a 1 is received as the input A, then 1 is provided as the output Y. Similarly, when 0 is received as the input A, then 0 is provided as the output Y. That is, referring to FIG. 7, when PG is deasserted (i.e. a logic level 0), then inverter 302 is enabled while inverter 306 is disabled. In this manner, the input A is provided via inverters 302 and 304 (also referred to as data path inverters) to provide output Y. Also, when PG is deasserted, all inverters 302, 304, 308, and 306 are powered since VDD is coupled to VDDC (via, for example, transistor 104 of FIG. 1) and is therefore approximately equal to VDDC. However, when PG is asserted (i.e. set to a logic level 1) for power gating, such as during a low power mode, then the output Y retains its state (and input A can be treated as a "don't care" since it no longer affects operation of state retention buffer 300). That is, whatever Y is at the time PG is asserted, then Y remains at this value. Referring to FIG. 7, when PG is asserted (i.e. a logic level one), inverter 302 is disabled and inverter 306 is enabled. Also, once PG is asserted, VDD can be decoupled from VDDC, such that only inverters 304, 306, and 308 remain powered. Therefore, inverter 302 no longer receives power, thus reducing leakage power. While PG is asserted, the value at output Y is maintained by the latch formed by inverters 304 and 306. Note also that inverter 308, coupled between the inverted enable inputs of inverters 302 and 306, ensure that inverters 302 and 306 are not enabled at the same time, to prevent data contention issues at the output of inverter 302. However, in alternate embodiments, inverter 308 may not be present, or other circuitry may be used to prevent data contention. Therefore, note that state retention buffer 300 may be used to maintain the state of output Y during power gating. Note also that the state of output Y need not be known. That is, regardless of whether output Y is a 0 or 1 during power gating, the state is maintained since output Y is simply fed back, via inverter 306, to the input of inverter 304.

FIG. 9 illustrates a state retention buffer 400 in accordance with another embodiment of the present invention. State retention buffer 400 is similar to state retention buffer 300; however, it may be used when the state to be maintained is known. State retention buffer 400 receives an input A (which may also be referred to as a buffer data input) and provides an output Y (which may also be referred to as a buffer data output). State retention buffer 400 includes an inverter 402 having an input to receive A and an output coupled to an input of an inverter 404 and an output of an inverter 406. An output of inverter 404 provides output Y. An input of inverter 306 receives a state retention input S. An inverted enable input of inverter 402 is coupled to receive PG (such as, for example, PG 120) and is coupled to an input of an inverter 408. An output of inverter 408 is coupled to an inverted enable input of inverter 406. Inverter 402 receives VDD, and inverters 404, 406, and 408 receive VDDC. Therefore, a first buffer portion (e.g. inverter 402) receives a first power supply signal (e.g. VCC) while a second buffer portion (e.g. inverters 404, 406, and 408) receives a second power supply signal (e.g. VDDC).

Operation of state retention buffer 400 will be described in reference to the table of FIG. 10. During normal operation, when PG is deasserted, when a 1 is received as the input A, then 1 is provided as the output Y. Similarly, when 0 is received as the input A, then 0 is provided as the output Y. That is, referring to FIG. 9, when PG is deasserted (i.e. a logic level 0), then inverter 402 is enabled while inverter 406 is disabled. In this manner, the input A is provided via inverters 402 and 404 (also referred to as data path inverters) to provide output Y. Also, when PG is deasserted, all inverters 402, 404, 408, and 406 are powered since VDD is coupled to VDDC (via, for example, transistor 104 of FIG. 1) and is therefore approximately equal to VDDC. Note that when PG is deasserted, the state retention input S is treated as a "don't care," in that it does not affect operation of state retention buffer 400 when PG is not asserted.

However, when PG is asserted (i.e. set to a logic level 1) for power gating, such as during a low power mode, then the state is retained by providing state retention input S as output Y (and A may treated as a "don't care" since it no longer affects operation of state retention buffer 400). Therefore, in this embodiment, S can be set to whatever value is desired at the output of state retention buffer 400 during power gating. For example, if it is known what the state of retention buffer 400 will be when PG is asserted, then S can be set accordingly such that it is provided as output Y during power gating. In this manner, the state circuitry (such as, e.g., inverter 406) sets a state of the buffer responsive to receiving S and the inverted power gate indicator signal (e.g. PG). In one embodiment, S is hardwired, such as, for example, via a transistor, to provide a logic level 1 or 0 to the input of inverter 406. Alternatively, S may be a programmable value set by software (such as corresponding to a stored bit) or hardware (such as via programmable fuses).

Therefore, referring to FIG. 9, when PG is asserted (i.e. a logic level one), inverter 402 is disabled and inverter 406 is enabled. Also, once PG is asserted, VDD can be decoupled from VDDC, such that only inverters 404, 406, and 408 remain powered. Therefore, inverter 402 no longer receives power, thus reducing leakage power. While PG is asserted, the value at output Y is provided by state retention in put S via inverters 406 and 404. Note also that inverter 408, coupled between the inverted enable inputs of inverters 402 and 406, ensure that inverters 402 and 406 are not enabled at the same time, to prevent data contention issues at the output of inverter 402. However, in alternate embodiments, inverter 408 may not be present, or other circuitry may be used to prevent data contention. Therefore, note that state retention buffer 400 may be used to maintain the state of output Y during power gating with the use of state retention input S, such as when the state of output Y is known.

FIG. 14 illustrates a state retention buffer 500 in accordance with another embodiment of the present invention. State retention buffer 500 may be used when the state to be maintained is known to be a logic level zero, and thus a hardwired pull-up transistor may be used to maintain the state. State retention buffer 500 receives an input A (which may also be referred to as a buffer data input) and provides an output Y (which may also be referred to as a buffer data output). State retention buffer 500 includes an inverter 502 having an input to receive A and an output coupled to an input of an inverter 504. An output of inverter 504 provides output Y. An inverted enable input of inverter 502 is coupled to receive PG (such as, for example, PG 120) and is coupled to an input of an inverter 508. State retention buffer 500 also includes a pull-up transistor 510 having a first current electrode (also referred to as a first current handling terminal) coupled to the input of inverter 504 and a second current electrode (also referred to a second current handling terminal) coupled to VDDC. An output of inverter 508 is coupled to a control electrode (also referred to as a control terminal) of pull-up transistor 510. Inverter 402 receives VDD, and inverters 504 and 408 receive VDDC. Therefore, a first buffer portion (e.g. inverter 502) receives a first power supply signal (e.g. VCC) while a second buffer portion (e.g. inverters 404 and 408) receives a second power supply signal (e.g. VDDC). Also, note that in this embodiment, the second current electrode of transistor 510 is coupled to a state retention input S, which, in this embodiment, corresponds to VDDC.

Operation of state retention buffer 500 will be described in reference to the table of FIG. 15. During normal operation, when PG is deasserted, when a 1 is received as the input A, then 1 is provided as the output Y. Similarly, when 0 is received as the input A, then 0 is provided as the output Y. That is, referring to FIG. 14, when PG is deasserted (i.e. a logic level 0), then inverter 502 is enabled and pull-up transistor 510 is off (since the value at its control electrode is a logic level 1). In this manner, the input A is provided via inverters 502 and 504 (also referred to as data path inverters) to provide output Y. Also, when PG is deasserted, all inverters 502, 504, and 508 are powered since VDD is coupled to VDDC (via, for example, transistor 104 of FIG. 1) and is therefore approximately equal to VDDC.

However, when PG is asserted (i.e. set to a logic level 1) for power gating, such as during a low power mode, then the state is retained by pull-up transisto