System and method for testing circuitry using an externally generated signature Number:7,131,046 from the United States Patent and Trademark Office (PTO) owispatent

Title: System and method for testing circuitry using an externally generated signature

Abstract: A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.

Patent Number: 7,131,046 Issued on 10/31/2006 to Volkerink,   et al.

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Inventors:	Volkerink; Erik H. (San Jose, CA), Khoche; Ajay (Cupertino, CA), Hilliges; Klaus D. (Mountain View, CA)
Assignee:	Verigy IPco (Singapore, SG)
Appl. No.:	10/308,323
Filed:	December 3, 2002

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Current U.S. Class:	714/732
Current International Class:	G01R 31/28 (20060101)
Field of Search:	714/732,735,736,724,718,719

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References Cited [Referenced By]

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U.S. Patent Documents

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	6363506		March 2002		Karri et al.
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Other References

Abramovici, Miron et al., "Digital Systems Testing and Testable Design," IEEE Press, 1990, pp. 432-449. cited by other . Bassett, Robert W. et al., "Low-Cost Testing of High-Desnity Logic Components," IEEE Press, 1990, pp. 15-28. cited by other . U.S. Appl. No. 09/802,440, filed Mar. 9, 2001, Khoche et al. cited by othe- r . U.S. Appl. No. 10/155,651, filed May 24, 2002, Volkerink et al. cited by other.

Primary Examiner: Kerveros; James C.

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Claims

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What is claimed is:

1. An off-chip test system comprising: means for inputting test data to a chip under test; means for receiving output data from said chip under test responsive to said input test data; means for generating a signature for at least a portion of said received output data, wherein said received output data is divided into a plurality of windows each comprising a predetermined number of bits and wherein said means for generating a signature generates a signature for each of said plurality of windows; means for comparing said generated signature with an expected signature; and means for storing information to an error map log if said generated signature fails to match with said expected signature.

2. The off-chip test system of claim 1 wherein said means for storing information does not require further interaction with said chip under test after determining that said generated signature fails to match said expected signature for acquiring said information to be stored to said error map log.

3. The off-chip test system of claim 1 wherein said means for comparing comprises: means for comparing said generated signature for a first window with an expected signature for said first window.

4. The off-chip test system of claim 3 wherein said means for storing information comprises: means for storing information to an error map log about at least said first window, if said generated signature for said first window fails to match with said expected signature for said first window.

5. The off-chip test system of claim 1 wherein said chip under test comprises circuitry on a semiconductor wafer, arid said off-chip test system is arranged external to said wafer.

6. The off-chip test system of claim 1 wherein said chip under test is a packaged chip, and said off-chip test system is arranged external to said packaged wafer.

7. The off-chip test system of claim 1 further comprising: means for masking at least a portion of said received output data from being used in generating said signature.

8. The off-chip test system of claim 1 further comprising: means for storing mask data identifying bits of said received output data to be masked, wherein said mask data is compressed.

9. The off-chip test system of claim 8 further comprising: means for decompressing said mask data.

10. The off-chip test system of claim 8 further comprising: means for compressing said mask data.

11. The off-chip test system of claim 1 wherein said means for storing information to said error map log stores said at least a portion of said received output data used for generating said signature that fails to match with said expected signature.

12. The system of claim 1 wherein the input test data comprises at least one input test pattern, and wherein the plurality of windows each comprises a predetermined number of output bits that are output responsive to a single input test pattern.

13. The system of claim 1 wherein the input test data comprises a plurality of different input test patterns, and wherein the plurality of windows each comprises a predetermined number of output bits that are output responsive to different input test patterns.

14. A system for testing circuitry, said system comprising: automated test equipment external to said circuitry that is at least temporarily communicatively coupled to said circuitry, wherein said automated test equipment comprises a communicative interface for inputting test data to said circuitry, a communicative interface for receiving output data from said circuitry responsive to said input test data, logic operable to determine a plurality of windows of the received output data, logic operable to generate a signature for each of the plurality of windows, compare logic for comparing a generated signature with an expected signature, and logic for storing information to an error map log if a generated signature fails to match an expected signature.

15. The system of claim 14 wherein said circuitry comprises circuitry on a semiconductor wafer.

16. The system of claim 14 wherein said logic for storing said information to an error map log does not require further interaction with said circuitry after detection of a generated signature failing to match an expected signature.

17. The system of claim 14 wherein said information stored to an error map log comprises said at least a portion of the received output data used for generating said signature that failed to match the expected signature.

18. The system of claim 14 wherein said automated test equipment further comprises: logic for masking at least a portion of the received output data from being used is in generating the signature.

19. The system of claim 18 wherein said automated test equipment further comprises: data storage communicatively coupled thereto that comprises mask data identifying bits of the received output data to be masked, wherein said mask data is compressed.

20. The system of claim 19 wherein said automated test equipment further comprises: logic for decompressing the mask data.

21. The system of claim 14 further comprising: logic for determining whether generated signatures fail to match expected signatures for a predetermined number of different windows, wherein said logic for storing information to an error map log performs said storing responsive to the determining logic determining that generated signatures fail to match expected signatures for the predetermined number of different windows.

22. A method for testing circuitry, said method comprising: inputting test data to circuitry under test; receiving, at an external test device, output data from said circuitry under test responsive to said input test data; dividing said received output data into a plurality of windows, each window comprising a predetermined number of bits; generating, at said external test device, a signature for each of said plurality of windows; comparing, for each of the windows, said generated signature with an expected signature for the corresponding window to determine whether said circuitry under test functions as expected; and if said generated signature fails to match with said expected signature, storing information to an error map log, wherein further interaction with said circuitry under test is not required after determining that said generated signature fails to match said expected signature for acquiring said information for storing said information to said error map log.

23. The method of claim 22 wherein said comparing step comprises: comparing said generated signature for a first window with an expected signature for said first window.

24. The method of claim 23 wherein said storing information to an error map log further comprises: if said generated signature for said first window fails to match with said expected signature for said first window, storing information about at least said first window to said error map log.

25. The method of claim 24 wherein said information about said first window comprises: the received output data of said first window.

26. The method of claim 22 further comprising: generating said expected signature for each of the windows, wherein said generating said expected signatures comprises determining whether a first window of expected output bits is available for a given test, and when determined that the expected output bits for the first window are available, inputting the expected output bits for the first window to signature generation logic, wherein the signature generation logic generates an expected signature for the first window based on the expected output bits for the first window.

27. The method of claim 22 further comprising: receiving, at the external test device, input specifying the predetermined number of bits for at least one of the windows.

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Description

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TECHNICAL FIELD

The present invention relates in general to testing of integrated circuits, and more particularly to a system and method for testing of circuitry utilizing a signature generated external to the circuitry under test.

BACKGROUND OF THE INVENTION

During typical semiconductor manufacturing processes, a plurality of integrated circuits are formed as individual dice on a semiconductor wafer. Each semiconductor wafer generally has hundreds to thousands of individual dice formed thereon. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional and which dice are not functional. In most testing procedures, each die is probed using probe equipment while the dice are still on the wafer. This step is also known as "wafer sort."

The purpose of the wafer-level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less time and expense that is wasted on further processing of defective dice. That is, if it is determined that a detected defect cannot be repaired, the time and expense of completing a chip assembly will not be expended. After the wafer-level testing, the functional dice are then packaged, and generally the packaged part is tested again to ensure that no defects were introduced during packaging. Various techniques have been developed for performing wafer-level testing, such as those described further below, and as is known in the art similar techniques may also be used for testing a packaged device.

In typical semiconductor testing, the device under test (DUT) (which may be referred to as "circuitry under test" (CUT) and is intended to encompass a device under test on a wafer as well as a packaged device) receives a set of input stimuli from automatic test equipment (ATE) arranged external to the DUT, after which the ATE observes the DUT outputs. In general, the correct expected outputs of the DUT are stored in the ATE memory, and the ATE compares all of the output bits received from the DUT against the stored expected bit values to determine whether the DUT is functioning properly (e.g., whether the DUT is generating the expected output values responsive to the input values). Thus, a DUT (e.g., a device on a wafer or a packaged device) may be communicatively coupled to an external ATE, and such ATE may input test stimuli thereto and receive and analyze responses therefrom. As described further below, circuitry may be included on the DUT, which may, for example, generate a signature corresponding to the DUT's response to the input stimuli, and such signature may be output to the ATE. While much of the testing techniques described herein are described as testing a DUT that is on a wafer (i.e., wafer-level testing), it should be recognized that similar techniques may typically also be used for testing a packaged device.

In the case of wafer-level testing, a probe may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe is typically communicatively coupled to an external ATE that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly. Dice on a wafer may be tested serially (e.g., by contacting each die with the probe in series) or in parallel.

Traditional testing techniques of the existing art require an undesirably large amount of memory on the ATE utilized for the testing, which undesirably increases the cost of the ATE and the resulting product. For instance, sufficient data storage that is communicatively coupled to the ATE is generally required for storage of at least the following information for a testing technique: 1) input vector data, 2) output vector data, and 3) mask vector data. In general, the input vector data stored at the ATE comprises the data that is used as stimuli for inputs to the DUT (e.g., test pattern data), and the output vector data comprises the expected output data of the DUT given the input vector data, which is used for comparison with the actual output data of the DUT responsive to the input vector data to determine whether the DUT is functioning properly. Generally, the mask vector data comprises data designating which of the bits of the expected output data actually need to be compared to the received outputs of the DUT, e.g., the mask vector data maps the expected output data to the actual output data received from the DUT, as in certain configurations all of the output bits of the DUT may not be compared with expected output data (e.g., certain non-deterministic bits, or "don't care/unknown bits", may exist, the value of which is not relevant to the correct functioning of the DUT).

Such input vector data, output vector data, and mask vector data for a testing technique may consume an undesirably large amount of data storage space on the ATE. Further, as the comprehensiveness of a testing technique is increased and/or as the complexity of the device to be tested increases, the amount of data storage space consumed on the ATE for this vector data is likely also increased. For example, traditional testing techniques of the existing art commonly use approximately 400 to 800 bits per gate of the DUT being tested. Of course, depending on the complexity of the DUT and/or the comprehensiveness of the testing technique implemented (e.g., the number of flip-flops on the DUT being tested and/or the number of input test patterns utilized), the size of the input vector data, output vector data, and/or mask vector data may vary from testing technique to testing technique (but, in current ATE architectures, for each output bit a mask bit is required such that mask vector memory is equal to the output vector memory). Embodiments of the present invention breaks this barrier, thus enabling reduction in the amount of data storage required on an ATE for a test.

In general, it is desirable to minimize the amount of data storage required on the ATE for implementing a testing technique. Several solutions have been proposed in the existing art for reducing the ATE's data storage requirements for implementing a testing technique, and more particularly, for reducing the ATE's storage requirements for storing the output vector data for a testing technique. The most pervasive techniques for minimizing the amount of data storage required on an ATE for storing output vector data are vector set truncation techniques and on-chip signature analysis techniques, which are described further below.

One popular technique for minimizing the amount of data storage required on an ATE for storing output vector data is truncation. In general, truncation involves dropping a portion of the test, i.e., a portion of the output data, mask data, and/or input data (i.e., not using this test portion in determining whether the DUT is functioning properly). As a result, the amount of data stored on the ATE may be reduced. However, truncation of vector sets (e.g., input, output, and mask vector sets), for example, also results in a reduction of test coverage, and as a consequence, may result in reduction of product quality (i.e., truncation reduces the comprehensiveness of the testing of a DUT, which may result in an improperly functioning DUT passing the test). This reduction in product quality is often not acceptable. Sometimes this technique is used in combination with vector set reordering based on the likelihood of a vector actually detecting a defect for each vector, after which the tail of the vector data is truncated. This way, the impact on test coverage can be minimized. However, in most cases there is still a significant impact on the test coverage.

One of the most attractive output compression schemes is based on signature analysis. Signature analysis is a well-known technique for compressing a sequence of logic values output from a circuit under test into a relatively small number of bits of data (signature) that, when compared to stored data (e.g., an expected signature), will indicate the presence or absence of faults in the circuit. In general, a signature of a group of output bits compresses such group of output bits and uniquely identifies such group of output bits such that it may be determined whether the group of output bits are as expected. It should be noted that there is generally a slight possibility of obtaining a correct signature for incorrect output bits (aliasing). While a signature may be used to discern whether the group of output bits is as expected, if the signature is not as expected it generally cannot be discerned from the signature which one(s) of the group of output bits had unexpected values. Thus, diagnosis of errors or error debug is generally limited (e.g., unavailable) when on-chip signature generation is used. In general, error diagnosis refers to a process for identifying an error in a DUT, such as determining the situation(s) under which the DUT has an error and/or determining the bit(s) that are incorrect as a result of the error. Error debug generally refers to a process for determining the cause of an error.

Various techniques for generating a signature for output data are well known in the art. For example, one technique comprises feeding the complete output vector data through a linear feedback shift register with different exclusive OR (XOR) feedback loops, which results in a very short signature in the shift register that depends on all output vector data. When the feedback loops, i.e. the polynomials, of the shift register are selected carefully, no significant aliasing will occur. On-chip techniques for generating a signature of the chip's output data during testing have been proposed in the existing art using circuitry called a SISR (Single Input Signature Register) or (in the case of multiple XORed inputs) a MISR (Multiple Input Signature Register). Such SISR and MISR circuitry for generating signatures on-chip are well-known in the art, and therefore are not described in greater detail herein. Examples of test schemes that use signature analysis (e.g., via a MISR) are described in the following patents: 1) U.S. Pat. No. 6,442,722 entitled "METHOD AND APPARATUS FOR TESTING CIRCUITS WITH MULTIPLE CLOCKS", issued to Nadeau-Dostie et al.; 2) U.S. Pat. No. 6,393,594 entitled "METHOD AND SYSTEM FOR PERFORMING PSEUDO-RANDOM TESTING OF AN INTEGRATED CIRCUIT", issued to Anderson et al.; 3) U.S. Pat. No. 6,374,370 entitled "METHOD AND SYSTEM FOR FLEXIBLE CONTROL OF BIST REGISTERS BASED UPON ON-CHIP EVENTS", issued to Bockhaus et al.; 4) U.S. Pat. No. 6,363,506 entitled "METHOD FOR SELF-TESTING INTEGRATED CIRCUITS", issued to Karri et al.; 5) U.S. Pat. No. 6,327,685 entitled "LOGIC BUILT-IN SELF TEST", issued to Koprowski et al.; 6) U.S. Pat. No. 6,240,537 entitled "SIGNATURE COMPRESSION CIRCUIT AND METHOD", issued to Sim; 7) U.S. Pat. No. 6,158,033 entitled "MULTIPLE INPUT SIGNATURE TESTING & DIAGNOSIS FOR EMBEDDED BLOCKS IN INTEGRATED CIRCUITS", issued to Wagner et al.; 8) 5,978,946 entitled "METHODS AND APPARATUS FOR SYSTEM TESTING OF PROCESSORS AND COMPUTERS USING SIGNATURE ANALYSIS", issued to Needham; 9) U.S. Pat. No. 5,960,008 entitled "TEST CIRCUIT", issued to Osawa et al.; and 10) U.S. Pat. No. 5,938,784 entitled "LINEAR FEEDBACK SHIFT REGISTER, MULTIPLE INPUT SIGNATURE REGISTER, AND BUILT-IN SELF TEST CIRCUIT USING SUCH REGISTERS", issued to Kim, the disclosures of which are hereby incorporated herein by reference. A further example of a test scheme that uses signature analysis (e.g., via a MISR) is described in U.S. Published patent application No. 20,020,073,374 entitled "METHOD, SYSTEM AND PROGRAM PRODUCT FOR TESTING AND/OR DIAGNOSING CIRCUITS USING EMBEDDED TEST CONTROLLER ACCESS DATA", the disclosure of which is hereby incorporated herein by reference.

It should be recognized that because a signature is a compressed identification of the output bits, the amount of storage space required on an ATE for storing the output vector data (expected signatures) may be reduced well below that required for storing all of the actual expected output bits. Further, because a signature may identify an entire set of output bits (within the bounds of aliasing) desired to be analyzed (e.g., the entire output vector), test coverage is not reduced, as in the case of truncation.

However, on-chip signature analysis techniques of the existing art have several disadvantages. First, such techniques include circuitry on-chip for generating a signature of the chip's output data during testing. Such signature generation circuitry consumes area on the chip, thus increasing the overall size of the chip (or decreasing the amount of circuitry that may otherwise be included in the chip) and potentially hindering the chip's performance (e.g., because of the increased distance that signals may be required to travel given the increased size of the chip). Also, implementing the signature generation circuitry on-chip may require design modifications to be made to the circuitry under test in order to enable such signature generation circuitry to be implemented therewith. Further, the signature generation circuitry is typically utilized only during testing of the circuitry. That is, the signature generation circuitry is typically not utilized during normal operation of the circuitry in the target application. Thus, implementing the signature generation circuitry on-chip is disadvantageous in that it consumes area on the chip (thus increasing the overall size of the chip) and is useful only during-testing of the chip. Further, as mentioned above, on-chip signature generation is generally disadvantageous because it does not allow for error diagnosis (i.e., a determination as to which one(s) of a group of output bits that have incorrect outputs cannot be made from the signature of such output bits) or error debug. Further still, on-chip signature generation circuitry may itself have defects.

Additionally, since the signature depends on all output vector data, it also depends on the output vector data bits that have a non-deterministic behavior. This non-deterministic behavior can, for example, occur when a partial scan approach is used, e.g., only a subset of flip-flops on a DUT is scanned. In certain designs, some flip-flops cannot be scanned due to design constraints. Other sources of non-deterministic (unknown) output states include having multiple clock domains and tri-state buses. As a consequence, the values of these non-deterministic bits cannot be controlled without additional design modifications. However, these design modifications result in area overhead and potential performance degradation. The presence of unknown/non-deterministic output signals can corrupt the signature, making the signature and the test almost always useless. The design modifications impact on area, flow, and design performance can be a substantial disadvantage, and not acceptable for some designs.

In addition, in the on-chip signature generation techniques that do not provide on-chip masking capability, the user sometimes desires to perform only a part of the test or suppress certain non-deterministic outputs from the circuitry under test, e.g., during the debugging phase or when certain expected outputs turn out to be simulated incorrectly. In that case, depending on the number of masked outputs, signature analysis techniques of the existing art cannot be used. That is, because the signature generation techniques of the existing art comprise on-chip circuitry that is fixed for generating a signature for a certain set of output values, none of such output values can be masked out during the testing process. One could provide on-chip masking capability, however, in general extra channels/bandwidth are required to supply the masking data.

Moreover, it is very computationally intensive, and sometimes impossible, to reverse the signature analysis process. In other words, by using signature analysis techniques of the existing art, it is possible to determine a discrepancy between the actual output vector data and the expected output vector data. However, it is typically not possible to determine which received bits of the output vector data are wrong. This seriously limits the error diagnosis/debugging capability of signature-based testing methodologies of the existing art and typically requires a bypass mode for performing error diagnosis/debugging, which adds more circuitry and more inputs/outputs.

Proposals have been made for a tester that generates a signature off-chip. For example, "Low-Cost Testing of High-Density Logic Components", IEEE Design & Test of Computers, 0740 7475 (April, 1990) proposes a tester that includes signature generation logic that receives output from a DUT and generates a signature for such received output. However, such proposed tester has several shortcomings. For instance, the proposed tester does not allow for concurrent testing and error diagnosis/debugging. Further, the proposed tester does not allow for masking out of unknown states (e.g., masking of non-deterministic output bits) in generating a signature. We are aware of no commercially available ATEs that implement the technique proposed by the "Low-Cost Testing of High-Density Logic Components" article. Further, if an ATE were implemented in accordance with such proposal, it would not allow for masking of unknown states, and if such masking were implemented it would require a substantial amount of mask data stored at the ATE (as no compression of the mask data is proposed).

Because of the above-described disadvantages, the use of signature analysis techniques to reduce the ATE memory requirements is not wide spread.

BRIEF SUMMARY OF THE INVENTION

In view of the above, a desire exists for a system and method for testing circuitry that preferably conserves data storage requirements (e.g., ATE storage requirements) for implementing such testing technique. Further, a desire exists for a system and method that enables testing of circuitry that preferably minimizes the amount of on-chip circuitry required for implementing such testing technique. Further still, a desire exists for a system and method that enables testing of circuitry in a manner that allows for diagnosis/debug of detected errors to, for example, determine the specific output bit(s) from a device under test that are incorrect without requiring huge vector memory. Further, concurrent error diagnosis/debug and testing of the circuitry is desired. That is, a desire exists for concurrent error evaluation (e.g., diagnosis and/or debug) and testing of the circuitry. The term "error evaluation" is used broadly herein and is intended to encompass error diagnosis and error debug. Error evaluation further encompasses yield learning. That is, either error diagnosis, error debug, or yield learning may be considered an error evaluation. Additionally, a desire exists for such a system and method that further allow for masking of unknown states (e.g., non-deterministic bits) in generating a signature. A desire exists for a system and method that compresses at least the output data and mask data that are used for implementing a testing technique for testing of circuitry.

The present invention is directed to a system and method which enable testing of circuitry using an externally generated signature. In a preferred embodiment, an external tester is provided that is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. As described further herein, various advantages are recognized by generating a signature for output data external to the DUT. The external tester may then compare the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data may be written to an error map log. For instance, if the generated signature fails to match an expected signature, then at least a portion of the actual received output data (for which the generated signature was generated) may be written to an error map log. In a preferred embodiment, further interaction with the DUT is, depending on the error evaluation goals, not required after detecting an error (e.g., after detecting that a generated signature fails to match an expected signature) in order to perform such error evaluation (e.g., storing the actual received output data corresponding to an error to an error map log). Thus, error evaluation (e.g., diagnosis and/or debugging) may be performed concurrently with testing of the DUT. Accordingly, in a preferred embodiment, error evaluation may be performed concurrently with testing of a DUT to the extent supported by conventional ATEs. Thus, separate testing and debug modes are not required. That is, once testing is performed on the DUT, further interaction with the DUT is not required to perform error evaluation.

Further, a preferred embodiment of the present invention may be implemented in combination with mask vector compression and/or input vector compression techniques for a test for further conservation of data storage required for implementing the test. For instance, not only may a signature analysis be implemented for compressing the output vector data, but also input vector and/or mask vector compression techniques may also be implemented in combination therewith for minimizing the amount of data storage required at the ATE for implementing a given test.

In certain embodiments, the received output data is divided into a plurality of windows, wherein each window is a predetermined number of bits. The external tester generates a signature for each window, and compares the generated signature for each window with an expected signature for such window. If an error is detected (i.e., a generated signature for a window fails to match the expected signature for such window), then information relating at least to the failed window may be written to an error map log. For instance, the actual received output data for a failed window may be written to an error map log.

According to one embodiment of the present invention, an off-chip test system comprises a means for inputting test data to a chip under test, and a means for receiving output data from the chip under test responsive to the input test data. The off-chip test system further comprises means for generating a signature for at least a portion of the received output data, and a means for comparing the generated signature with an expected signature. The off-chip test system further comprises a means for storing information, to an error map log if the generated signature fails to match with the expected signature.

According to another embodiment of the present invention, a system for testing circuitry comprises an automated test equipment external to the circuitry that is at least temporarily communicatively coupled to such circuitry. The automated test equipment comprises a communicative interface for inputting test data to the circuitry, a communicative interface for receiving output data from the circuitry responsive to the input test data, and logic operable to generate a signature for at least a portion of the received output data. The automated test equipment further comprises compare logic for comparing a generated signature with an expected signature, and logic for storing information to an error map log if a generated signature fails to match an expected signature.

According to another embodiment of the present invention, a method for testing circuitry comprises inputting test data to circuitry under test, and receiving, at an external test device, output data from the circuitry under test responsive to the input test data. The method further comprises generating, at the external test device, a signature for at least a portion of the received output data, and comparing the generated signature with an expected signature to determine whether the circuitry under test functions as expected. If the generated signature fails to match with the expected signature, information is stored to an error map log, wherein further interaction with the circuitry under test is not required after determining that the generated signature fails to match the expected signature for acquiring the information for storing such information to the error map log.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

FIG. 1A shows a block diagram of a traditional testing system;

FIG. 1B shows an example operational flow of the traditional test system of FIG. 1A;

FIG. 2 shows an example block diagram of a prior art test system that utilizes signature analysis;

FIG. 3A shows an example block diagram of a test system of a preferred embodiment of the present invention;

FIG. 3B shows an example operational flow of a test system of a preferred embodiment of the present invention;

FIG. 4 shows an example flow chart that illustrates how expected window signatures are created in a preferred embodiment of the present invention;

FIG. 5 shows an example flow chart that illustrates an operational flow of a testing technique in accordance with a preferred embodiment of the present invention;

FIG. 6 shows an example operational-flow diagram of one embodiment of the present invention in which capturing of error information starts after detection of a predetermined target number of failed windows for a device under test;

FIG. 7 shows an example computer system that may be used for generating expected signatures to be used by a tester; and

FIG. 8 shows a block diagram of an exemplary tester which may be adapted to implement embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

As described above, in typical semiconductor testing, the device under test (DUT) (or "circuitry under test" (CUT)) receives a set of input stimuli from automatic test equipment (ATE) arranged external to the DUT, after which the ATE observes the DUT outputs. In general, the correct expected outputs of the DUT are stored in the ATE memory, and the ATE compares all of the output bits received from the DUT against the stored expected bit values to determine whether the DUT is functioning properly (e.g., whether the DUT is generating the expected output values responsive to the input values).

In the case of wafer-level testing, a probe may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe is typically communicatively coupled to an external ATE that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly.

An example of this traditional approach is illustrated in FIGS. 1A 1B. FIG. 1A shows a block diagram of traditional testing system 100 that comprises ATE 101, which is communicatively coupled to probe 111. As described further below, probe 111 may be used to communicate input data to one or more DUTs, such as DUT 113 on wafer 112, and receive output data from such DUTs. As shown, data storage 106 is communicatively coupled to ATE 101 and stores information needed for performing the testing of DUT 113, such as input vector data 109, output vector data (or "expected raw data") 107, and mask vector data 110 for the test. Further, error map data 108 may be stored within data storage 106, as described further below. Data storage 106 is typically implemented as internal memory of ATE 101, but may, in certain implementations, be implemented as an external data storage medium that is communicatively coupled to ATE 101. As further shown, ATE 101 comprises logic 102 for generating input test data (e.g., input test pattern(s)) to be input to DUT 113, logic 103 for receiving raw output data from DUT 113 responsive to the input test data, logic 114 for masking non-deterministic bits of the received raw output data, logic 104 operable to compare the received, non-masked raw output data with expected raw data 107, and logic 105 for generating error map 108 for failed tests. Each of logic 102, 103, 114, 104, and 105 of ATE 101 may comprise software and/or hardware for performing their respective tasks.

In operation, probe 111 is typically brought into contact with the appropriate access pads for testing one or more DUTs, such as DUT 113. For instance, probe 111 is brought into contact with the appropriate pads for inputting test signals to DUT 113 and receiving output signals from DUT 113. Logic 102 of ATE 101 is then used to communicate input test data to DUT 113. For instance, such input test data may comprise a pattern of input signals designed to test the responsiveness of DUT 113 to various different input stimuli. Thereafter, logic 103 of ATE 101 receives the output data generated by DUT 113 responsive to the test input data. Logic 114 is used to mask the non-deterministic bits of the received raw output data, and logic 104 is used to compare the non-masked, raw output data received from DUT 113 to the expected raw data 107 stored in data storage 106. Thus, it is determined whether the output data generated by DUT 113 responsive to the input data is as expected. If it is determined that the output data received from DUT 113 is not as was expected responsive to the input data (i.e., the received non-masked, output data does not match the expected output data 107), then logic 105 may generate information in error map 108 about this failed test. Such error map information may comprise an error log of the expected output and actual output received, for example. This process may repeat for any number of input test patterns that are generated for testing DUT 113.

FIG. 1B shows an example operational flow of the traditional test system 100 of FIG. 1A. As shown, in operational block 121, it is determined whether a next output bit is available from DUT 113 responsive to particular input test data. That is, input test stimuli (e.g., a test pattern) is input to DUT 113 and it is determined whether all of the output bits from DUT 113 responsive to such input test stimuli are received at ATE 101. If no further output bits are expected from DUT 113, then it is determined at block 122 that the testing is complete. However, if it is determined that an output bit has been received from DUT 113 responsive to a given input test pattern, then operation advances in the ATE 101 to operational block 123 whereat a "don't care" bit (or "non-deterministic" bit) may be masked. For example, certain output bits may have a non-deterministic behavior (e.g., may not indicate whether DUT 113 is functioning properly responsive to the input pattern), and such bits whose value the test doesn't care about may be masked (or filtered) from the received output data. Thus, the received bit may be masked in operational block 123.

Thereafter, if the received output bit is not masked in block 123, then in operational block 124 the ATE 101 compares the received output bit with the expected output bit 107 to determine whether such output bit matches with the expected bit 107. If the received output bit matches the expected output bit 107, then it is determined that DUT 113 passes this test in block 125, and operation may return to block 121 to perform further testing (e.g., receive further output bits from DUT 113). However, if the received output bit does not match the expected output bit 107, then it is determined that DUT 113 fails this test and information about such failure (e.g., the address and/or received output data from DUT 113) may be stored to error map 108, which may be later used in debugging of DUT 113 to determine the reason that it failed this test.

In view of the above, traditional testing techniques generally store all of the expected output bits for various different input test patterns as the output vector data 107 in data storage 106 for ATE 101. Storing all of such expected output bits results in extremely high ATE memory requirements. Further, as technology progresses the required output vector data volume is expected to grow steeply with the scaling of semiconductor technology. Hence, in the future, the problem is expected to become even worse.

As a consequence, certain solutions have been proposed in the existing art for trying to reduce the ATE memory requirements for storing such output vector data. As mentioned above, one proposed solution truncates a portion of the output vector data simply because the ATE is unable to meet the high memory demands. As described above, such truncation results in a reduction of test coverage, which may result in lower product quality.

Another solution is to utilize signature analysis in order to compress the output data vector. As described above, signature analysis is a well-known technique for compressing a sequence of logic values output from a circuit under test into a relatively small number of bits of data (signature). Various techniques for generating a signature for output data are well known in the art. Typically, well-known SISR (Single Input Signature Register) or MISR (Multiple Input Signature Register) circuitry is implemented on-chip in order to generate a signature for the chip's output values responsive to an input test pattern. In certain implementations, well-known Cellular Automata circuitry may be implemented on-chip in order to generate a signature for the chip's output values responsive to an input test pattern. Because various implementations of Cellular Automata circuitry for generating a signature are well-known in the art, such Cellular Automata is not described further herein.

Turning to FIG. 2, an example block diagram of a prior art test system 200 that utilizes signature analysis is shown. Testing system 200 comprises ATE 201, which is communicatively coupled to probe 211. As described further below, probe 211 may be used to communicate input data to one or more DUTs, such as DUT 213 on wafer 212, and receive output data from such DUTs. In this test solution, signature generating circuitry 214 (e.g., a SISR, MISR, or Cellular Automata) is included within DUT 213, which is operable to generate a signature of output values that are generated by DUT 213 responsive to input test values. As shown, data storage 206 is communicatively coupled to ATE 201 and stores information needed for performing the testing of DUT 213, such as input vector data 208 and expected signatures 207. As further shown, ATE 201 comprises logic 202 for generating input test data to be input to DUT 213, logic 203 for receiving a signature (generated by circuitry 214) from DUT 213 responsive to the input test data, and logic 204 operable to compare the received signature with expected signature 207.

In operation, probe 211 is typically brought into contact with the appropriate access pads for testing one or more DUTs, such as DUT 213. For instance, probe 211 is brought into contact with the appropriate pads for inputting test signals to DUT 213 and receiving output signals from DUT 213. Logic 202 of ATE 201 is then used to communicate input test data to DUT 213. For instance, such input test data may comprise a pattern of input signals designed to test the responsiveness of DUT 213 to various different input stimuli. Thereafter, signature generating logic 214 of DUT 213 generates a signature for the output values of DUT 213 responsive to the input test signals. Logic 203 of ATE 201 receives the generated signature from DUT 213, and logic 204 is used to compare the received signature to the expected signature 207 stored in data storage 206. Thus, it is determined whether the generated signature received from DUT 213 responsive to the input test data is as expected. This process may repeat for any number of input test patterns that are generated for testing DUT 213.

It should be recognized that because a signature is a compressed identification of the output bits, the amount of storage space required on ATE 201 for storing the output vector data (expected signatures 207) may be reduced well below that required for storing all of the actual expected output bits (as in the traditional system 100 of FIG. 1A). Thus, expected signatures 207 may consume less storage space within data storage 206 for implementing a given testing technique than would be consumed by traditional test solutions in which all expected bits are stored (such as expected raw data 107 in the example of FIG. 1A). Further, because a signature may uniquely identify an entire set of output bits desired to be analyzed (e.g., the entire output vector), test coverage is not reduced, as in the case of truncation.

However, as described above, signature analysis techniques of the existing art have several disadvantages. For example, such techniques include circuitry on-chip (e.g., circuitry 214) for generating a signature of the chip's output data during testing. Such signature generation circuitry consumes area on the chip, thus increasing the overall size of the chip (or decreasing the amount of circuitry that may otherwise be included in the chip) and potentially hindering the chip's performance. Further, such on-chip signature generation techniques typically do not allow for diagnosis of errors (e.g., determination of the specific output bit(s) that are incorrect) at the ATE. Thus, it should be recognized that an error map is not constructed in this example, as was constructed in the example of FIG. 1A. Various other disadvantages associated with signature analysis techniques of the existing art are described herein above, and because of such disadvantages, the use of signature analysis techniques to reduce the ATE memory requirements is not wide spread. As the complexity of the DUTs and/or the comprehensiveness of the test coverage have increased, the desirability to conserve the amount of data storage required on an ATE for implementing a test has increased. Accordingly, a desire for an improved testing technique that conserves the amount of data storage required for implementing such testing technique (e.g., through use of signature analysis) but not having the disadvantages mentioned above has arisen.

As described above, proposals have also been made for a tester that generates a signature off-chip. For example, "Low-Cost Testing of High-Density Logic Components", IEEE Design & Test of Computers, 0740 7475 (April, 1990) proposes a tester that includes signature generation logic that receives output from a DUT and generates a signature for such received output. However, such proposed tester has several shortcomings. For instance, the proposed tester does not allow for simultaneous testing and error diagnosis. Further, the proposed tester does not allow for masking out of unknown states (e.g., masking of non-deterministic output bits) in generating a signature. Also, we are aware of no commercially available ATEs that implement the technique proposed by the "Low-Cost Testing of High-Density Logic Components" article. Further, if an ATE were implemented in accordance with such proposal, it would not allow for masking of unknown states, and if such masking were implemented it would require a substantial amount of mask data stored at the ATE (as no compression of the mask data is proposed).

Embodiments of the present invention provide a test solution that conserves the amount of data storage required at a tester (e.g., ATE) and also preferably minimizes the amount of on-chip circuitry required for such test solution. More specifically, embodiments of the present invention use signature analysis to achieve compression of the expected output data. Further, embodiments of the present invention use logic (e.g., software and/or hardware) arranged off the device under test (e.g., off a device on a wafer or a packaged device that is being tested) to generate a signature of the output of such device. For instance, in a preferred embodiment, logic is included within an ATE to receive raw output data from a DUT and generate a signature for at least a portion of the received raw output data (e.g., a portion of the received raw output data may, in certain implementations, be masked such that it is not utilized in generating the signature). Most preferably, the received raw output data is divided into a plurality of "windows," wherein each window is a predetermined number of bits, and a signature is generated in the ATE for each window and compared against an expected signature for such window to determine if the device is functioning as expected.

In a preferred embodiment, the data storage required at the ATE may be conserved in that expected signatures for the test solution may be stored thereto, as opposed to storing all of the actual expected output bits for such test solution. Further, in a preferred embodiment, circuitry for generating a signature of the DUT's output is not included on the DUT, thus minimizing the area required on the DUT for implementing the test solution. A further advantage of a preferred embodiment of the present invention is that it enables concurrent (or "single-pass") error evaluation (e.g., diagnosis/debugging). Thus, if an error is detected during testing, a second pass of inputting data to the DUT and receiving output data therefrom is not required for error evaluation (e.g., diagnosing the error for determining the specific output bit(s) that have an incorrect value). Further, a preferred embodiment of the present invention enables masking of received output data for generating a signature. Thus, non-deterministic bits of the received output data may be masked in accordance with mask data stored on the ATE that identifies the output bit(s) to be masked (or filtered) for the test. In accordance with certain embodiments of the present invention, compression techniques may be used for the mask data to further reduce the data storage requirements at the ATE. Various other advantages of embodiments of the present invention are described further below.

Various embodiments of the present invention are now described with reference to FIGS. 3A 3B and 4 8, wherein like reference numerals represent like part