Title: TCP/IP offload device with reduced sequential processing
Abstract: A TCP Offload Engine (TOE) device includes a state machine that performs TCP/IP protocol processing operations in parallel. In a first aspect, the state machine includes a first memory, a second memory, and combinatorial logic. The first memory stores and simultaneously outputs multiple TCP state variables. The second memory stores and simultaneously outputs multiple header values. In contrast to a sequential processor technique, the combinatorial logic generates a flush detect signal from the TCP state variables and header values without performing sequential processor instructions or sequential memory accesses. In a second aspect, a TOE includes a state machine that performs an update of multiple TCP state variables in a TCB buffer all simultaneously, thereby avoiding multiple sequential writes to the TCB buffer memory. In a third aspect, a TOE involves a state machine that sets up a DMA move in a single state machine clock cycle.
Patent Number: 6,996,070 Issued on 02/07/2006 to Starr, et al.
| Inventors:
|
Starr; Daryl D. (Milpitas, CA);
Philbrick; Clive M. (San Jose, CA)
|
| Assignee:
|
Alacritech, Inc. (San Jose, CA)
|
| Appl. No.:
|
729111 |
| Filed:
|
December 5, 2003 |
| Current U.S. Class: |
370/252; 714/15; 714/21 |
| Current Intern'l Class: |
G01R 31/08 (20060101) |
| Field of Search: |
709/231,250
710/30
370/252
714/15,21
|
References Cited [Referenced By]
U.S. Patent Documents
| 4366538 | Dec., 1982 | Johnson et al.
| |
| 4589063 | May., 1986 | Shah et al.
| |
| 4991133 | Feb., 1991 | Davis et al.
| |
| 5056058 | Oct., 1991 | Hirata et al.
| |
| 5058110 | Oct., 1991 | Beach et al.
| |
| 5097442 | Mar., 1992 | Ward et al.
| |
| 5163131 | Nov., 1992 | Row et al.
| |
| 5212778 | May., 1993 | Dally et al.
| |
| 5280477 | Jan., 1994 | Trapp.
| |
| 5289580 | Feb., 1994 | Latif et al.
| |
| 5303344 | Apr., 1994 | Yokoyama et al.
| |
| 5412782 | May., 1995 | Hausman et al.
| |
| 5448566 | Sep., 1995 | Richter et al.
| |
| 5485579 | Jan., 1996 | Hitz et al.
| |
| 5506966 | Apr., 1996 | Ban.
| |
| 5511169 | Apr., 1996 | Suda.
| |
| 5524250 | Jun., 1996 | Chesson et al.
| |
| 5548730 | Aug., 1996 | Young et al.
| |
| 5566170 | Oct., 1996 | Bakke et al.
| |
| 5588121 | Dec., 1996 | Reddin et al.
| |
| 5590328 | Dec., 1996 | Seno et al.
| |
| 5592622 | Jan., 1997 | Isfeld et al.
| |
| 5598410 | Jan., 1997 | Stone.
| |
| 5619650 | Apr., 1997 | Bach et al.
| |
| 5629933 | May., 1997 | Delp et al.
| |
| 5634099 | May., 1997 | Andrews et al.
| |
| 5634127 | May., 1997 | Cloud et al.
| |
| 5642482 | Jun., 1997 | Pardillos.
| |
| 5664114 | Sep., 1997 | Krech, Jr. et al.
| |
| 5671355 | Sep., 1997 | Collins.
| |
| 5678060 | Oct., 1997 | Yokoyama et al.
| |
| 5692130 | Nov., 1997 | Shobu et al.
| |
| 5699317 | Dec., 1997 | Sartore et al.
| |
| 5701434 | Dec., 1997 | Nakagawa.
| |
| 5701516 | Dec., 1997 | Cheng et al.
| |
| 5727142 | Mar., 1998 | Chen.
| |
| 5749095 | May., 1998 | Hagersten.
| |
| 5751715 | May., 1998 | Chan et al.
| |
| 5752078 | May., 1998 | Delp et al.
| |
| 5758084 | May., 1998 | Silverstein et al.
| |
| 5758089 | May., 1998 | Gentry et al.
| |
| 5758186 | May., 1998 | Hamilton et al.
| |
| 5758194 | May., 1998 | Kuzma.
| |
| 5771349 | Jun., 1998 | Picazo, Jr. et al.
| |
| 5778013 | Jul., 1998 | Jedwab.
| |
| 5790804 | Aug., 1998 | Osborne.
| |
| 5794061 | Aug., 1998 | Hansen et al.
| |
| 5802258 | Sep., 1998 | Chen.
| |
| 5802580 | Sep., 1998 | McAlpice.
| |
| 5809328 | Sep., 1998 | Nogales et al.
| |
| 5812775 | Sep., 1998 | Van Seters et al.
| |
| 5815646 | Sep., 1998 | Purcell et al.
| |
| 5878225 | Mar., 1999 | Bilansky et al.
| |
| 5898713 | Apr., 1999 | Melzer et al.
| |
| 5913028 | Jun., 1999 | Wang et al.
| |
| 5930830 | Jul., 1999 | Mendelson et al.
| |
| 5931918 | Aug., 1999 | Row et al.
| |
| 5935205 | Aug., 1999 | Murayama et al.
| |
| 5937169 | Aug., 1999 | Connery et al.
| |
| 5941969 | Aug., 1999 | Ram et al.
| |
| 5941972 | Aug., 1999 | Hoese et al.
| |
| 5950203 | Sep., 1999 | Stakuis et al.
| |
| 5970804 | Oct., 1999 | Robbat, Jr.
| |
| 5991299 | Nov., 1999 | Radogna et al.
| |
| 5996024 | Nov., 1999 | Blumenau.
| |
| 6005849 | Dec., 1999 | Roach et al.
| |
| 6009478 | Dec., 1999 | Panner et al.
| |
| 6016513 | Jan., 2000 | Lowe.
| |
| 6021446 | Feb., 2000 | Gentry et al.
| |
| 6021507 | Feb., 2000 | Chen.
| |
| 6026452 | Feb., 2000 | Pitts.
| |
| 6034963 | Mar., 2000 | Minami et al.
| |
| 6038562 | Mar., 2000 | Anjur et al.
| |
| 6044438 | Mar., 2000 | Olnowich.
| |
| 6047323 | Apr., 2000 | Krause.
| |
| 6047356 | Apr., 2000 | Anderson et al.
| |
| 6057863 | May., 2000 | Olarig.
| |
| 6061368 | May., 2000 | Hitzelberger.
| |
| 6065096 | May., 2000 | Day et al.
| |
| 6070200 | May., 2000 | Gates et al.
| |
| 6101555 | Aug., 2000 | Goshey et al.
| |
| 6141705 | Oct., 2000 | Anand et al.
| |
| 6145017 | Nov., 2000 | Ghaffari.
| |
| 6157955 | Dec., 2000 | Narad et al.
| |
| 6172980 | Jan., 2001 | Flanders et al.
| |
| 6173333 | Jan., 2001 | Jolitz et al.
| |
| 6202105 | Mar., 2001 | Gates et al.
| |
| 6226680 | May., 2001 | Boucher et al.
| |
| 6246683 | Jun., 2001 | Connery et al.
| |
| 6247060 | Jun., 2001 | Boucher et al.
| |
| 6279051 | Aug., 2001 | Gates et al.
| |
| 6298403 | Oct., 2001 | Suri et al.
| |
| 6334153 | Dec., 2001 | Boucher et al.
| |
| 6345301 | Feb., 2002 | Burns et al.
| |
| 6356951 | Mar., 2002 | Gentry, Jr.
| |
| 6389468 | May., 2002 | Muller et al.
| |
| 6389479 | May., 2002 | Boucher.
| |
| 6421742 | Jul., 2002 | Tillier.
| |
| 6427169 | Jul., 2002 | Elzur.
| |
| 6434651 | Aug., 2002 | Gentry, Jr.
| |
| 6449656 | Sep., 2002 | Elzur et al.
| |
| 6453360 | Sep., 2002 | Muller et al.
| |
| 6480489 | Nov., 2002 | Muller et al.
| |
| 6526446 | Feb., 2003 | Yang et al.
| |
| 2001/0004354 | Jun., 2001 | Jolitz.
| |
| 2001/0013059 | Aug., 2001 | Dawson et al.
| |
| 2001/0014892 | Aug., 2001 | Gaither et al.
| |
| 2001/0014954 | Aug., 2001 | Purcell et al.
| |
| 2001/0025315 | Sep., 2001 | Jolitz.
| |
| 2001/0048681 | Dec., 2001 | Bilic et al.
| |
| 2001/0053148 | Dec., 2001 | Bilic et al.
| |
| 2003/0066011 | Apr., 2003 | Oren.
| |
| 2003/0165160 | Sep., 2003 | Minami et al.
| |
| 2004/0042464 | Mar., 2004 | Elzur et al.
| |
| 2004/0125751 | Jul., 2004 | Vangal et al.
| |
| 2004/0193733 | Sep., 2004 | Vangal et al.
| |
| 2004/0249998 | Dec., 2004 | Rajagopalan et al.
| |
| Foreign Patent Documents |
| WO 98/5085/2 | Nov., 1998 | WO.
| |
| WO 99/0434/3 | Jan., 1999 | WO.
| |
| WO 99/6521/9 | Dec., 1999 | WO.
| |
| WO 00-1309/1 | Mar., 2000 | WO.
| |
| WO 01/0477/0 | Jan., 2001 | WO.
| |
| WO 01/0510/7 | Jan., 2001 | WO.
| |
| WO 01/0511/6 | Jan., 2001 | WO.
| |
| WO 01/0512/3 | Jan., 2001 | WO.
| |
| WO 01/4096/0 | Jun., 2001 | WO.
| |
Other References
EE Times article entitled "Ethernet Interconnect Outpacing Infiniband At Intel",
by Rick Merritt, 3 pages, Sep. 12, 2002.
Internet pages entitled "Hardware Assisted Protocol Processing", (which Eugene
Feinber is working on), 1 page, printed Nov. 25, 1998.
Zilog product Brief entitled "Z85C30 CMOS SCC Serial Communication Controller",
Zilog Inc., 3 pages, 1997.
Internet pages of Xpoint Technologies, Inc. entitled "Smart LAN Work Requests",
5 pages, printed Dec. 19, 1997.
Internet pages entitled: Asante and 100 BASE-T Fast Ethernet. 7 pages, printed
May 27, 1997.
Internet pages entitled: A Guide to the Paragon XP/S-A7 Supercomputer at Indiana
University. 13 pages, printed Dec. 21, 1998.
Richard Stevens, "TCP/IP Illustrated, vol. 1, The Protocols", pp. 325-326 (1994).
Internet pages entitled: Northridge/Southbridge vs. Intel Hub Architecture, 4
pages, printed Feb. 19, 2001.
Gigabit Ethernet Technical Brief, Achieving End-to-End Performance. Alteon Networks,
Inc., First Edition, Sep. 1996, 15 pages.
Internet pages directed to Technical Brief on Alteon Ethernet Gigabit NIC technology,
www.alteon.com, 14 pages, printed Mar. 15, 1997.
VIA Technologies, Inc. article entitled "VT8501 Apollo MVP4", pp. i-iv, 1-11,
cover and copyright page, revision 1.3, Feb. 1, 2000.
iReady News Archives article entitled "iReady Rounding Out Management Team with
Two Key Executives", http://www.ireadyco.com/archives/keyexec.html, 2 pages, printed
Nov. 28, 1998.
"Toshiba Delivers First Chips to Make Consumer Devices Internet-Ready Based On
iReady's Design," Press Release Oct., 1998, 3 pages, printed Nov. 28, 1998.
Internet pages from iReady Products, web sitehttp://www.ireadyco.com/products,html,
2 pages, downloaded Nov. 25, 1998.
iReady News Archives, Toshiba, iReady shipping internet chip, 1 page, printed
Nov. 25, 1998.
Interprophet article entitled "Technology", http://www.interprophet.com/technology.html,
17 pages, printed Mar. 1, 2000.
iReady Corporation, article entitled "The I-1000 Internet Tuner", 2 pages, date unknown.
iReady article entitled "About Us Introduction", Internet pages fromhttp://www.iReadyco.com/about.html,
3 pages, printed Nov. 25, 1998.
iReady News Archive article entitled "Revolutionary Approach to Consumer Electronics
Internet Connectivity Funded", San Jose, CA, Nov. 20, 1997, 2 pages, printed Nov.
2, 1998.
iReady News Archive article entitled "Seiko Instruments Inc. (SII) Introduces
World's First Internet-Ready Intelligent LCD Modules Based on iReady Technology,"
Santa Clara, CA and Chiba, Japan, Oct. 26, 1998. 2 pages, printed Nov. 2, 1998.
NEWSwatch Article entitled "iReady internet Tuner to Web Enable Devices", Tuesday,
Nov. 5, 1996, printed Nov. 2, 1998, 2 pages.
EETimes article entitled "Tuner for Toshiba, Toshiba Taps iReady for Internet
Tuner", by David Lammers, 2 pages, printed Nov. 2, 1998.
"Comparison of Novell Netware and TCP/IP Protocol Architectures", by J.S. Carbone,
19 pages, printed Apr. 10, 1998.
Adaptec article entitled "AEA-7100C-a DuraSAN product", 11 pages, printed Oct.
1, 2001.
iSCSI HBA article entitled "iSCSI and 2Gigabit fibre Channel Host Bus Adapters
from Emulex, QLogic, Adaptec, JNI", 8 pages, printed Oct. 1, 2001.
iSCSI HBA article entitled "FCE-3210/6410 32 and 64-bit PCI-to-Fibre Channel
HBA", 6 pages, printed Oct. 1, 2001.
ISCSI.com article entitled "iSCSI Storage", 2 pages, printed Oct. 1, 2001.
"Two-Way TCP Traffic Over Rate Controlled Channels: Effects and Analysis", by
Kalampoukas et al., IEEE Transactions on Networking, vol. 6, No. 6, Dec. 1998,
17 pages.
JReady News article entitled "Toshiba Delivers First Chips to Make Consumer Devices
Internet-Ready Based on iReady Design", Santa Clara, CA, and Tokyo, Japan, Oct.
14, 1998, printed Nov. 2, 1998, 3 pages.
Internet pages of InterProphet entitled "Frequently Asked Questions", by Lynne
Jolitz, printed Jun. 14, 2000, 4 pages.
"File System Design For An NFS File Server Appliance", Article by D. Hitz, et
al., 13 pages.
Adaptec Press Release article entitled "Adaptec Announces EtherStorage Technology",
2 pages, May 4, 2000, printed Jun. 14, 2000.
Adaptec article entitled "EtherStorage Frequently Asked Questions", 5 pages,
printed Jul. 19, 2000.
Adaptec article entitled "EtherStorage White Paper", 7 pages, printed Jul. 19, 2000.
CIBC World Markets article entitled "Computers; Storage", by J. Berlino et al.,
9 pages, dated Aug. 7, 2000.
Merrill Lynch article entitled "Storage Futures", by S. Milunovich, 22 pages,
dated May 10, 2000.
CBS Market Watch article entitled "Montreal Start-Up Battles Data Storage Bottleneck",
by S. Taylor, dated Mar. 5, 2000, 2 pages, printed Mar. 7, 2000.
Internet-draft article entitled "SCSI/TCP (SCSI over TCP)", by J. Satran et al.,
38 pages, dated Feb. 2000, printed May 19, 2000.
Internet pages entitled Technical White Paper-Xpoint's Disk to LAN Acceleration
Solution for Windows NT Server, printed Jun. 5, 1997, 15 pages.
Jato Technologies article entitled Network Accelerator Chip Architecture, twelve-slide
presentation, printed Aug. 19, 1998, 13 pages.
EETimes article entitled Enterprise System Uses Flexible Spec, dated Aug. 10,
1998, printed Nov. 25, 1998, 3 pages.
Internet pages entitled "Smart Ethernet Network Interface Cards", which Berend
Ozceri is developing, printed Nov. 25, 1998.
Internet pages of Xaqti corporation entitled "GigaPower Protocol Processor Product
Review," printed Nov. 25, 1999, 4 pages.
Internet pages entitled "DART: Fast Application Level Networking via Data-Copy
Avoidance," by Robert J. Walsh, printed Jun. 3, 1999, 25 pages.
Schwaderer et al., IEEE Computer Society Press publication entitled "XTP in VLSI
Protocol Decomposition for ASIC Implementation", from 15th Conference
on Local Computer Networks, 5 pages, Sep. 30-Oct. 3, 1990.
Beach, Bob, IEEE Computer Society Press publication entitled, "UltraNet: An Architecture
for Gigabit Networking", from 15th Conference on Local Computer Networks,
18 pages, Sep. 30-Oct. 3, 1990.
Chesson et al., IEEE Symposium Record entitled, "The Protocol Engine Chipset",
from Hot Chips III, 16 pages, Aug. 26-27, 1991.
Maclean et al., IEEE Global Telecommunications Conference, Globecom '91, presentation
entitled "An Outboard Processor for High Performance Implementation of Transport
Layer Protocols", 7 pages, Dec. 2-5, 1991.
Ross et al., IEEE article entitled "FX1000: A high performance single chip Gigabit
Ethernet NIC", from Compcon '97 Proceedings, 7 pages, Feb. 23-26, 1997.
Strayer et al., "Ch. 9: The Protocol Engine" from XTP: The Transfer Protocol,
12 pages, Jul. 1992.
Publication entitled "Protocol Engine Handbook", 44 pages, Oct. 1990.
Koufopavlou et al., IEEE Global Telecommunications Conference, Globecom '92,
presentation entitled, "Parallel TCP for High Performance Communication Subsystems",
7 pages, Dec. 6-9, 1992.
Lillienkamp et al., Publication entitled "Proposed Host-Front End Protocol",
56 pages, Dec. 1984.
|
Primary Examiner: Phunkulh; Bob
Assistant Examiner: Wilson; Robert W.
Attorney, Agent or Firm: Silicon Edge Law Group, LLP, Lauer; Mark A., Wallace; T. Lester
Claims
What is claimed is:
1. A TCP offload engine (TOE) capable of offloading, from a host, TCP protocol
processing tasks that are associated with a TCP connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
combinatorial logic that receives said at least two TCP state values and said
at least two packet header values and generates therefrom a flush detect signal
indicative of whether an error condition has occurred, the two TCP state values
and the two packet header values all being supplied to the combinatorial logic simultaneously.
2. A TCP offload engine (TOE) capable of offloading, from a host, TCP protocol
processing tasks that are associated with a TCP connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
combinatorial logic that receives said at least two TCP state values and said
at least two packet header values and generates therefrom a flush detect signal
indicative of whether an error condition has occurred, the two TCP state values
and the two packet header values all being supplied to the combinatorial logic
simultaneously, wherein the TOE transfers the receive packet sequence limit, the
expected receive packet sequence number, the transmit sequence limit, the transmit
acknowledge number, and the transmit sequence number to the host if the flush detect
signal is indicative of the error condition.
3. The TOE of claim 2, wherein the combinatorial logic is part of a state machine,
the state machine being clocked by a clock signal, wherein the combinatorial logic
generates said flush detect signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock signal.
4. The TOE of claim 3, wherein the state machine does not fetch instructions,
decode the instructions, and execute the instructions.
5. The TOE of claim 4, wherein the state machine causes the expected packet receive
sequence number and the receive packet sequence limit values in the first memory
to be updated in a single period of the clock signal.
6. The TOE of claim 2, wherein the TCP connection was set up by a stack executing
on the host, and wherein control of the TCP connection was then passed from the
host to the TOE.
7. A TCP offload engine (TOE) capable of offloading, from a host, TCP protocol
processing tasks that are associated with a TCP connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
combinatorial logic that receives said at least two TCP state values and said
at least two packet header values and generates therefrom a flush detect signal
indicative of whether an error condition has occurred, the two TCP state values
and the two packet header values all being supplied to the combinatorial logic
simultaneously, wherein the TOE can control a plurality of TCP connections, each
of said TCP connections being associated with a TCB identifier, and wherein the
first memory comprises a plurality of transaction control blocks (TCB), wherein
the first memory can be addressed by a TCB identifier to access a TCB that contains
TCP state information for a TCP connection associated with the TCB identifier.
8. The TOE of claim 7, wherein more than two values of the group of TCP state
values are supplied simultaneously to the combinatorial logic, and wherein more
than two values of the group of TCP state values are used to generate the flush
detect signal.
9. The TOE of claim 7, wherein more than two values of the group of packet header
values are supplied simultaneously to the combinatorial logic, and wherein more
than two values of the group of packet header values are used to generate the flush
detect signal.
10. A TCP offload engine (TOE) capable of offloading, from a host, TCP protocol
processing tasks that are associated with a TCP connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive racket sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
combinatorial logic that receives said at least two TCP state values and said
at least two packet header values and generates therefrom a flush detect signal
indicative of whether an error condition has occurred, the two TCP state values
and the two packet header values all being supplied to the combinatorial logic
simultaneously, wherein the combinatorial logic is part of a state machine, the
state machine being clocked by a clock signal, wherein the combinatorial logic
generates said flush detect signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock
signal, wherein the state machine does not fetch instructions, decode the instructions,
and execute the instructions, and
wherein a packet having a payload is received onto the TOE, the TOE further comprising:
a DMA controller that moves the payload from the TOE to the host using a source
address value, a size value indicating an amount of information to move, and a
destination address value, wherein the state machine causes the source address
value, the size value, and the destination address value to be supplied to the
DMA controller in a single state of the state machine.
11. A TCP offload engine (TOE) capable of offloading TCP protocol processing
tasks from a host, the TCP protocol processing tasks being associated with a TCP
connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
a hardware state machine that receives said at least two TCP state values and
said at least two packet header values and generates therefrom a signal indicative
of whether an exception condition has occurred, the two TCP state values and the
two packet header values all being supplied to the hardware state machine simultaneously,
wherein the hardware state machine is clocked by a clock signal, wherein the hardware
state machine generates said signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock signal.
12. A TCP offload engine (TOE) capable of offloading TCP protocol processing
tasks from a host, the TCP protocol processing tasks being associated with a TCP
connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
a hardware state machine that receives said at least two TCP state values and
said at least two packet header values and generates therefrom a signal indicative
of whether an exception condition has occurred, the two TCP state values and the
two packet header values all being supplied to the hardware state machine simultaneously,
wherein the hardware state machine is clocked by a clock signal, wherein the hardware
state machine generates said signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock
signal, wherein the hardware state machine causes the expected packet receive sequence
number and the receive packet sequence limit values in the first memory to be updated
in a single period of the clock signal.
13. The TOE of claim 12, wherein the expected packet receive sequence number
and the receive packet sequence limit values are updated by simultaneously writing
the expected packet receive sequence number value and the receive packet sequence
limit value into the first memory.
14. The TOE of claim 12, wherein the exception condition is a condition which
results in control of the TCP connection being passed from the TOE to the host.
15. A TCP offload engine (TOE) capable of offloading TCP protocol processing
tasks from a host, the TCP protocol processing tasks being associated with a TCP
connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
a hardware state machine that receives said at least two TCP state values and
said at least two packet header values and generates therefrom a signal indicative
of whether an exception condition has occurred, the two TCP state values and the
two packet header values all being supplied to the hardware state machine simultaneously,
wherein the hardware state machine is clocked by a clock signal, wherein the hardware
state machine generates said signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock
signal, wherein the first memory is a dual-port memory that has a first interface
and a second interface, the hardware state machine reading from and writing to
the first memory via the first interface, and wherein information passes from the
host and into the first memory via the second interface.
16. The TOE of claim 15, wherein the first memory comprises a plurality of TCB
buffers, wherein one of the TCB buffers is associated with the TCP connection,
and wherein a memory descriptor list entry associated with said TCP connection
is stored in said TCB buffer associated with said TCP connection.
17. A TCP offload engine (TOE) capable of offloading TCP protocol processing
tasks from a host, the TCP protocol processing tasks being associated with a TCP
connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value;
a hardware state machine that receives said at least two TCP state values and
said at least two packet header values and generates therefrom a signal indicative
of whether an exception condition has occurred, the two TCP state values and the
two packet header values all being supplied to the hardware state machine simultaneously,
wherein the hardware state machine is clocked by a clock signal, wherein the hardware
state machine generates said signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock
signal; and
a third memory that stores a plurality of socket descriptors, wherein one of
the socket descriptors is associated with the TCP connection.
18. A TCP offload engine (TOE) capable of offloading TCP protocol processing
tasks from a host, the TCP protocol processing tasks being associated with a TCP
connection, the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value;
a hardware state machine that receives said at least two TCP state values and
said at least two packet header values and generates therefrom a signal indicative
of whether an exception condition has occurred, the two TCP state values and the
two packet header values all being supplied to the hardware state machine simultaneously,
wherein the hardware state machine is clocked by a clock signal, wherein the hardware
state machine generates said signal from said at least two TCP state values and
said at least two packet header values within approximately one period of the clock
signal, wherein the second memory outputs a parse value along with said at least
two packet header values, said parse value being indicative of whether the transport
and network layer protocols of an associated packet are the TCP and IP protocols.
19. A TCP offload engine (TOE) capable of performing TCP protocol processing
tasks, the TCP protocol processing tasks being associated with a TCP connection,
the TOE comprising:
a first memory that stores and simultaneously outputs at least two TCP state
values associated with the TCP connection, wherein the at least two TCP state values
are taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number;
a second memory that stores and simultaneously outputs at least two packet header
values of a packet communicated over the TCP connection, wherein the at least two
packet header values are taken from the group consisting of: a receive packet sequence
number, a packet payload size, a packet acknowledge number, and a packet transmit
window value; and
a state machine that includes an amount of combinatorial logic, wherein the combinatorial
logic receives said at least two TCP state values and said at least two packet
header values and generates therefrom a signal indicative of whether an exception
condition has occurred, the two TCP state values and the two packet header values
all being supplied to the combinatorial logic simultaneously, and wherein the state
machine causes the expected packet receive sequence number value and the receive
packet sequence limit value in the first memory to be updated simultaneously.
20. The TOE of claim 19, wherein the TOE is capable of offloading the protocol
processing tasks from a host processor, wherein the host processor performs exception
protocol processing associated with the TCP connection if the exception condition
has occurred.
21. The TOE of claim 20, wherein the first memory, the second memory and the
state machine are all parts of a single integrated circuit.
22. The TOE of claim 21,
wherein the first memory simultaneously outputs at least three TCP state values
taken from the group consisting of: a receive packet sequence limit, an expected
receive packet sequence number, a transmit sequence limit, a transmit acknowledge
number, and a transmit sequence number,
wherein the second memory simultaneously outputs at least three packet header
values taken from the group consisting of: a rece
